REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA 14-12-16 4 A REV 5 6 7 8 9 10 11 12 13 14 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, DIGITAL-LINEAR, DUAL, 12 BIT, DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON APPROVED BY CHARLES F. SAFFLE SIZE AMSC N/A 3 CODE IDENT. NO. DWG NO. V62/14633 16236 PAGE 1 OF 14 5962-V013-15 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual, 12 bit digital to analog converter (DAC) microcircuit, with an operating temperature range of -55C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/14633 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function AD5623R-EP Dual, 12 bit digital to analog converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 10 JEDEC PUB 95 Package style MO-187-BA Plastic small outline package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 2 1.3 Absolute maximum ratings. 1/ VDD to GND ............................................................................................................... -0.3 V to +7 V VOUTx to GND ........................................................................................................... -0.3 V to VDD + 0.3 V VREFIN / VREFOUT to GND ........................................................................................ -0.3 V to VDD + 0.3 V Digital input voltage to GND ....................................................................................... -0.3 V to VDD + 0.3 V Storage temperature range (TSTG) ............................................................................. -65C to +150C Junction temperature range (TJ) ................................................................................ +150C Power dissipation (PD) equation ................................................................................ ( TJ max – TA ) / JA Thermal impedance, junction to ambient (JC) .......................................................... 43.7C/W Thermal impedance, junction to ambient (JA) .......................................................... 142C/W Reflow soldering peak temperature lead (Pb) free ..................................................... 260 (+0/-5) C 1.4 Recommended operating conditions. 2/ Operating free-air temperature range (TA) ................................................................. -55C to +105C 1/ 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC Solid State Technology Association JEDEC PUB 95 – Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Serial write operation waveforms. The serial write operation waveforms shall be as shown in figure 3. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Static performance INL -55C to +105C 01 -55C to +105C 01 DNL Zero scale error Bits 1.5 LSB Guaranteed monotonic by design -55C to +105C 01 1 LSB All 0s loaded to DAC register -55C to +105C 01 +12 mV +2 typical +25C Offset error -55C to +105C 01 All 1s loaded to DAC register -55C to +105C 01 -55C to +105C Zero scale error drift mV 1 % of -0.1 typical +25C Gain error 12 1 typical +25C Full scale error 12 1 typical +25C Differential nonlinearity Max 3/ 4/ Resolution Relative accuracy Unit 01 FSR 1.5 % of FSR +25C 2 typical V/C Gain temperature coefficient Of FSR/C +25C 2.5 typical ppm DC power supply rejection ratio DAC code = midscale, VDD = 5 V 10% +25C -100 typical dB Due to full scale output change, RL = 2 k to GND or VDD +25C 10 typical V Due to load current change +25C 10 typical V/mA Due to powering down (per channel) +25C 5 typical V Due to full scale output change, RL = 2 k to GND or VDD +25C 25 typical V Due to load current change +25C 20 typical V/mA Due to powering down (per channel) +25C 10 typical V DC crosstalk External reference Internal reference 01 01 See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Output characteristics Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max 0 VDD 5/ Output voltage range Capacitive load stability RL = -55C to +105C 01 +25C 01 V 2 typical nF 10 typical RL =2 k DC output impedance +25C 01 0.5 typical Short circuit current VDD = 5 V +25C 01 30 typical mA Power up time Coming out of power down mode, VDD = 5 V +25C 01 4 typical s VREFIN / VREFOUT = VDD = 5.5 V -55C to +105C 01 Reference inputs Reference current 170 typical +25C Reference input range A 200 01 +25C 01 -55C to +105C 01 Reference 5/ temperature coefficient +25C 01 10 typical ppm/ C Output impedance +25C 01 7.5 typical k All digital inputs -55C to +105C 01 2 A 0.8 V Reference input impedance 0.75 V -55C to +105C VDD 26 typical k Reference output Output voltage At ambient 2.495 2.505 V Logic inputs 5/ Input current Input low voltage VINL VDD = 5 V -55C to +105C 01 Input high voltage VINH VDD = 5 V -55C to +105C 01 +25C 01 Pin capacitance DIN, SCLK, and SYNC 2 V 3 typical pF 19 typical LDAC and CLR See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Unit Min Max 4.5 5.5 V 0.45 mA Power requirements Power supply input VDD Power supply current (normal mode) 6/ IDD Internal reference off -55C to +105C 01 -55C to +105C 01 VINH = VDD and VINL = GND VDD = 4.5 V to 5.5 V 0.25 typical +25C Internal reference on -55C to +105C VDD = 4.5 V to 5.5 V 01 IDD AC characteristics 4/ 5/ Slew rate SR -55C to +105C VDD = 4.5 V to 5.5 V, 01 A 1 0.48 typical +25C VINH = VDD and VINL = GND mA 0.8 typical +25C Power supply 7/ current (all power down modes) 1 +25C 01 1.8 typical V/s +25C 01 0.1 typical nVsec +25C 01 -90 typical dB +25C 01 0.1 typical nVsec +25C 01 1 typical nVsec Feedthrough Digital feedthrough Reference feedthrough VREFIN / VREFOUT = 2 V 0.1 VP-P, frequency 10 Hz to 20 MHz Crosstalk Digital crosstalk Analog crosstalk External reference Internal reference DAC to DAC crosstalk 4 typical External reference +25C 01 Internal reference Multiplying bandwidth 1 typical nVsec 4 typical VREFIN / VREFOUT = 2 V 0.1 VP-P, +25C 01 340 typical kHz See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max AC characteristics – continued. 4/ 5/ Total harmonic distortion VREFIN / VREFOUT = 2 V 0.1 VP-P, frequency = 10 kHz +25C 01 -80 typical dB Digital to analog glitch impulse 1 LSB change around major carry +25C 01 10 typical nVsec Output voltage settling time 1/4 to 3/4 scale settling to 0.5 LSB -55C to +105C 01 Output characteristics 3 typical +25C Output noise spectral density DAC code = midscale, 1 kHz +25C 01 DAC code = midscale, 10 kHz Output noise s 4.5 120 typical nV / Hz 100 typical 0.1 Hz to 10 Hz +25C 01 Vp-p 15typical Timing characteristics. 5/ 8/ See figure 3. SCLK cycle time 9/ t1 -55C to +105C 01 20 ns SCLK high time t2 -55C to +105C 01 9 ns SCLK low time t3 -55C to +105C 01 9 ns SYNC to SCLK falling edge setup time t4 -55C to +105C 01 13 ns Data setup time t5 -55C to +105C 01 5 ns Data hold time t6 -55C to +105C 01 5 ns SCLK falling edge to t7 -55C to +105C 01 0 ns Minimum SYNC high time t8 -55C to +105C 01 15 ns SYNC rising edge to SCLK fall ignore t9 -55C to +105C 01 13 ns SCLK falling edge to t10 -55C to +105C 01 0 ns SYNC rising edge SYNC fall ignore See footnotes at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits Min Unit Max Timing characteristics – continued. 5/ 8/ See figure 3. LDAC pulse width low t11 -55C to +105C 01 10 ns SCLK falling edge to t12 -55C to +105C 01 15 ns CLR pulse width low t13 -55C to +105C 01 5 ns SCLK falling edge to t14 -55C to +105C 01 0 ns t15 -55C to +105C 01 LDAC rising edge LDAC falling edge CLR pulse activation time 300 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, VDD = 4.5 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, VREFIN / VREFOUT = VDD, all specifications at -55C to +105C and typical at +25C. 3/ Linearity calculated using a reduced code range: code 32 to code 4064. Output unloaded. 4/ See terminology section in the manufacturer’s data sheet. 5/ Guaranteed by design and characterization, but not production tested. 6/ Interface inactive. All DACs active. DAC outputs unloaded. 7/ Both DACs powered down. 8/ All input signals are specified, with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH) / 2. Unless otherwise specified, VDD = 4.5 V to 5.5 V and all specifications at -55C to +105C. 9/ Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 9 Case X FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 10 Case X - continued Dimensions Inches Symbol Millimeters Minimum Medium Maximum Minimum Medium Maximum A --- --- 0.043 --- --- 1.10 A1 0.0019 --- 0.0059 0.05 --- 0.15 A2 0.029 0.033 0.037 0.75 0.85 0.95 b 0.0059 --- 0.012 0.15 --- 0.33 c 0.0051 --- 0.009 0.13 --- 0.23 D 0.114 0.118 0.122 2.90 3.00 3.10 E 0.114 0.118 0.122 2.90 3.00 3.10 E1 0.183 0.192 0.202 4.65 4.90 5.15 e L 0.019 BSC 0.015 0.021 0.050 BSC 0.027 0.40 0.55 0.70 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Falls within reference to JEDEC MO-187-BA. FIGURE 1. Case outline - Continued. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 11 Device type 01 Case outline X Terminal number Terminal symbol Description 1 VOUTA Analog output voltage from DAC A. The output amplifier has rail to rail operation. 2 VOUTB Analog output voltage from DAC B. The output amplifier has rail to rail operation. 3 GND Ground. Reference point for all circuitry on the device. 4 LDAC Load DAC. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively., this pin can be tied permanently low. 5 CLR Asynchronous clear input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The device exits clear code mode on the 24th falling edge of the next write to the device. If CLR is activated during a write sequence, the write is aborted. 6 SYNC Level triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC act as an interrupt and the write sequence is ignored by the DAC. 7 SCLK Serial clock input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 8 DIN Serial data input. This device has a 24 bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 VDD Power supply input. This device can be operated from 4.5 V to 5.5 V. Decouple the supply with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. 10 VREFIN / Common reference input/reference output. When the internal reference is selected, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input. VREFOUT FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 12 NOTES: 1. Asynchronous LDAC update mode. 2. Synchronous LDAC update mode. FIGURE 3. Serial write operation waveforms. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 13 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Top side marking Vendor part number V62/14633-01XE 24355 DN9 AD5623RSRMZ-EP-5R7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices Route 1 Industrial Park P.O. Box 9106 Norwood, MA 02062 Point of contact: Raheen Business Park Limerick, Ireland SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14633 PAGE 14