PDF Data Sheet Rev. A

14-Bit, 2400 MSPS RF DAC
with 4-Channel Signal Processing
AD9789
The on-chip rate converter supports a wide range of baud rates
with a fixed DAC clock. The digital upconverter can place the
channels from 0 to 0.5 × fDAC. This permits four contiguous
channels to be synthesized and placed anywhere from dc to fDAC/2.
FEATURES
DOCSIS 3.0 performance: 4 QAM carriers
ACLR over full band (47 MHz to 1 GHz)
−75 dBc @ fOUT = 200 MHz
−72 dBc @ fOUT = 800 MHz (noise)
−67 dBc @ fOUT = 800 MHz (harmonics)
Unequalized MER = 42 dB
On chip and bypassable
4 QAM encoders with SRRC filters, 16× to 512× interpolation,
rate converters, and modulators
Flexible data interface: 4, 8, 16, or 32 bits wide with parity
Power: 1.6 W (IFS = 20 mA, fDAC = 2.4 GHz, LVDS interface)
Direct to RF synthesis support with fS mix mode
Built-in self-test (BIST) support
Input connectivity check
Internal random number generator
The AD9789 includes a serial peripheral interface (SPI) for
device configuration and status register readback. The flexible
digital interface can be configured for data bus widths of 4, 8,
16, and 32 bits. It can accept real or complex data.
The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for
a total power consumption of 1.6 W. It is supplied in a 164-ball
chip scale package ball grid array for lower thermal impedance
and reduced package parasitics. No special power sequencing
is required. The clock receiver powers up muted to prevent
start-up noise.
PRODUCT HIGHLIGHTS
APPLICATIONS
1.
Broadband communications systems
CMTS/DVB
Cellular infrastructure
Point-to-point wireless
2.
3.
GENERAL DESCRIPTION
4.
The AD9789 is a flexible QAM encoder/interpolator/upconverter
combined with a high performance, 2400 MSPS, 14-bit RF digitalto-analog converter (DAC). The flexible digital interface can
accept up to four channels of complex data. The QAM encoder
supports constellation sizes of 16, 32, 64, 128, and 256 with
SRRC filter coefficients for all standards.
5.
Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to
four DOCSIS- or DVB-C-compatible channels in a block.
Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz.
Flexible data interface supports LVDS for improved SFDR
or CMOS input data for less demanding applications.
Interface is configurable from 4-bit nibbles to 32-bit words
and can run at up to 150 MHz CMOS or 150 MHz LVDS
double data rate (DDR).
Manufactured on a CMOS process, the AD9789 uses a
proprietary switching technique that enhances dynamic
performance.
FUNCTIONAL BLOCK DIAGRAM
DCO
FS
RETIMER
DATA FORMATTER/
ASSEMBLER
150MHz
LVDS/CMOS
CMOS
16 TO 31
LVDS
FALL
DATA
QAM/
FILTER/
NCO
DATA
QAM/
FILTER/
NCO
DATA
QAM/
FILTER/
NCO
DATA
QAM/
FILTER/
NCO
16×
INTERPOLATOR
AND BPF
+ SCALARS
14-BIT
2.4GSPS
DAC
SPI
IRQ
RS
07852-001
32 INPUT
PINS
AND
2 PARITY
PINS
CMOS
0 TO 15
LVDS
RISE
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009-2011 Analog Devices, Inc. All rights reserved.
AD9789
TABLE OF CONTENTS
Features .............................................................................................. 1 SPI Register Descriptions.......................................................... 29 Applications....................................................................................... 1 Theory of Operation ...................................................................... 39 General Description ......................................................................... 1 Datapath Signal Processing....................................................... 39 Product Highlights ........................................................................... 1 Digital Block Upconverter ........................................................ 43 Functional Block Diagram .............................................................. 1 Digital Interface Modes ............................................................. 45 Revision History ............................................................................... 2 Analog Modes of Operation ..................................................... 54 Detailed Functional Block Diagrams............................................. 3 Analog Control Registers .......................................................... 55 Specifications..................................................................................... 4 Voltage Reference ....................................................................... 56 DC Specifications ......................................................................... 4 DAC Output Stages .................................................................... 56 Digital Specifications ................................................................... 5 Clocking the AD9789 ................................................................ 57 AC Specifications.......................................................................... 6 Mu Delay Controller.................................................................. 58 Absolute Maximum Ratings............................................................ 8 Interrupt Requests...................................................................... 61 Thermal Resistance ...................................................................... 8 Recommended Start-Up Sequence .......................................... 62 ESD Caution.................................................................................. 8 Customer BIST Modes................................................................... 63 Pin Configurations and Function Descriptions ........................... 9 Using the Internal PRN Generator to Test QAM Output AC
Performance................................................................................ 63 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 22 Serial Control Port.......................................................................... 23 Serial Control Port Pin Descriptions ....................................... 23 General Operation of Serial Control Port............................... 23 Instruction Word (16 Bits) ........................................................ 24 MSB/LSB First Transfers............................................................ 24 Using the Internal Built-In Self-Test (BIST) to Test for Digital
Data Input Connectivity............................................................. 63 QAM Constellation Maps ............................................................. 65 Channelizer Mode Pin Mapping for CMOS and LVDS............ 68 Outline Dimensions ....................................................................... 74 Ordering Guide .......................................................................... 74 SPI Register Map............................................................................. 27 REVISION HISTORY
7/11—Rev. 0 to Rev. A
Changes to Table 2, DAC Clock Input (CLKP, CLKN): Added
DAC Clock Rate Parameter............................................................. 5
Changes to Table 3, Dynamic Performance, DAC Update Rate
Parameter; Added Adjusted DAC Update Rate Parameter......... 6
Changes to Captions for Figure 42, Figure 44, Figure 46,
Figure 49 .......................................................................................... 18
Changes to Digital 16x Tunable Band-Pass Filter Section, Third
Paragraph......................................................................................... 44
Changes to Retimer and Latency Look-Up Tables Section,
Second Paragraph ........................................................................... 50
Changes to Captions for Figure 122, Figure 124, Figure 125.... 65
4/09—Revision 0: Initial Version
Rev. A | Page 2 of 76
AD9789
DETAILED FUNCTIONAL BLOCK DIAGRAMS
32 INPUT
PINS
4 TO
RETIMER 32 BITS
LVDS/CMOS
CMOS
16 TO 31
LVDS
FALL
DATA FORMATTER/
ASSEMBLER
DATAPATH
0
UP TO
32 BITS
DATAPATH
1
UP TO
32 BITS
P0
P1
FS
DCO
UP TO
32 BITS
UP TO
32 BITS
CLK
CTL
DATAPATH
2
16×
INTERPOLATOR
BPF
fC = 0 TO
fDAC/2
SUM
SCALE
BPF
DATAPATH
3
fC
Figure 2. Digital Signal Processing Functional Block Diagram
24-BIT NCO
0 TO fDAC /16
QAM
MAPPER
SRRC
2N
(N = 0 TO 5)
INPUT
SCALE
BYPASS
QAM
BYPASS
SRRC
RATE
CONVERTER
P/Q 24-BIT
(P/Q = 0.5 TO 1)
CH GAIN
0× TO 2×
Figure 3. Channel 0 Through Channel 3 Datapath Block Detail (I and Q Paths Are Identical So Only One Is Shown)
Rev. A | Page 3 of 76
07852-003
2
07852-002
CMOS
0 TO 15
LVDS
RISE
AD9789
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
DAC RESOLUTION
ANALOG OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current (Monotonicity Guaranteed)
Output Compliance Range
Output Resistance
Output Capacitance
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance 1
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
DVDD15
SUPPLY CURRENTS AND POWER DISSIPATION
fDAC = 2.4 GSPS, fOUT = 930 MHz, IFS = 25 mA, Four Channels Enabled
IAVDD33
IDVDD18
ICVDD18
IDVDD33
CMOS Interface
LVDS Interface
IDVDD15
fDAC = 2.0 GSPS, fOUT = 70 MHz, IFS = 20 mA, CMOS Interface
IAVDD33
IDVDD18
ICVDD18
IDVDD33
IDVDD15 (Four Channels Enabled, All Signal Processing Enabled)
IDVDD15 (One Channel Enabled, 16× Interpolation Only)
Power Dissipation
fDAC = 2.4 GSPS, fOUT = 930 MHz, IFS = 25 mA, Four Channels Enabled
CMOS Interface
LVDS Interface
1
Min
8.66
−1.0
Typ
14
6.5
3.5
20.2
Max
Unit
Bits
70
1
% FSR
% FSR
mA
V
Ω
pF
135
25
ppm/°C
ppm/°C
1.2
5
V
kΩ
31.66
+1.0
3.14
1.71
3.3
1.8
3.47
1.89
V
V
3.14
1.71
1.43
3.3
1.8
1.5
3.47
1.89
1.58
V
V
V
Use an external amplifier to drive any external load.
Rev. A | Page 4 of 76
45
72
180
mA
mA
mA
42
16
640
mA
mA
mA
37.4
67.3
155.4
40.3
517
365
1.7
1.63
38.5
70.5
180
50.7
556
391
mA
mA
mA
mA
mA
mA
W
W
AD9789
DIGITAL SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, LVDS drivers and receivers
are compliant with the IEEE Std 1596.3-1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
CMOS DATA INPUTS (D[31:0], P0, P1)
Input Voltage High, VIH
Input Voltage Low, VIL
Input Current High, IIH
Input Current Low, IIL
Input Capacitance
Setup Time, CMOS Data Input to CMOS_DCO 1
Hold Time, CMOS Data Input to CMOS_DCO1
CMOS OUTPUTS (CMOS_FS, CMOS_DCO)
Output Voltage High, VOH
Output Voltage Low, VOL
Output Current High, IOH
Output Current Low, IOL
Maximum Clock Rate (CMOS_DCO)
CMOS_DCO to CMOS_FS Delay
LVDS DATA INPUTS (D[15:0]P, D[15:0]N, PARP, PARN)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH, VIDTHL
Input Differential Input Impedance, RIN
Maximum LVDS Input Rate
Setup Time, LVDS Differential Input Data to Differential DCOx 2
Hold Time, LVDS Differential Input Data to Differential DCOx2
LVDS OUTPUTS (DCOP, DCON, FSP, FSN)
DCOP, FSP = VOA; DCON, FSN = VOB; 100 Ω Termination
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single Ended, RO
RO Mismatch Between A and B, ∆RO
Change in |VOD| Between 0 and 1, |∆VOD|
Change in VOS Between 0 and 1, ∆VOS
Output Current—Driver Shorted to Ground, ISA, ISB
Output Current—Drivers Shorted Together, ISAB
Power-Off Output Leakage, |IXA|, |IXB|
Maximum Clock Rate (DCOP, DCON)
DCOx to FSx Delay
DAC CLOCK INPUT (CLKP, CLKN) 3
Differential Peak Voltage
Common-Mode Voltage
DAC Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (fSCLK, 1/tSCLK)
Minimum Pulse Width High, tPWH
Minimum Pulse Width Low, tPWL
Minimum SDIO and CS to SCLK Setup, tDS
Min
Typ
2.0
3.3
0
−10
−10
Max
0.8
+10
+10
2
5.3
−1.4
2.4
0
3.3
0.4
12
12
150
0.28
0.85
825
−100
1575
+100
25
80
150
1.41
0.24
120
1375
1025
150
1150
40
200
150
0.12
1.4
Rev. A | Page 5 of 76
V
V
mA
mA
MHz
ns
mV
mV
mV
Ω
MSPS
ns
ns
0.37
2400
V
mV
MHz
250
1250
140
10
25
25
20
4
10
25
10
V
V
μA
μA
pF
ns
ns
mV
mV
mV
mV
Ω
%
mV
mV
mA
mA
mA
MHz
ns
1.8
900
20
20
Unit
MHz
ns
ns
ns
AD9789
Parameter
Minimum SCLK to SDIO Hold, tDH
Maximum SCLK to Valid SDIO and SDO, tDV
Minimum SCLK to Invalid SDIO and SDO, tDNV
INPUTS (SDIO, SCLK, CS)
Input Voltage High, VIH
Input Voltage Low, VIL
Input Current High, IIH
Input Current Low, IIL
OUTPUTS (SDO, SDIO)
Output Voltage High, VOH
Output Voltage Low, VOL
Output Current High, IOH
Output Current Low, IOL
1
2
3
Min
Typ
5
20
5
2.0
3.3
0
Max
−10
−10
0.8
+10
+10
2.4
0
3.6
0.4
Unit
ns
ns
ns
V
V
μA
μA
V
V
mA
mA
4
4
See the CMOS Interface Timing section for more information.
See the LVDS Interface Timing section for more information.
See the Clock Phase Noise Effects on AC Performance section for more information.
AC SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, fDAC = 2.4 GHz, IFS = 20 mA, digital scale = 0 dBFS, unless
otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
DAC Update Rate
Adjusted DAC Update Rate 1
Output Settling Time (tST)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 2000 MSPS
fOUT = 100 MHz
fOUT = 316 MHz
fOUT = 550 MHz
fDAC = 2400 MSPS
fOUT = 100 MHz
fOUT = 316 MHz
fOUT = 550 MHz
fOUT = 850 MHz
TWO-TONE INTERMODULATION DISTORTION
(IMD)
fDAC = 2000 MSPS
fOUT = 100 MHz
fOUT = 316 MHz
fOUT = 550 MHz
fDAC = 2400 MSPS
fOUT = 100 MHz
fOUT = 316 MHz
fOUT = 550 MHz
fOUT = 850 MHz
NOISE SPECTRAL DENSITY (NSD)
1-Channel QAM
fOUT = 100 MHz
fOUT = 316 MHz
fOUT = 550 MHz
fOUT = 850 MHz
Test Conditions/Comments
To 0.025%
Min
Typ
Max
Unit
2400
150
13
MSPS
MSPS
ns
70
63
58
dBc
dBc
dBc
70
70
60
60
dBc
dBc
dBc
dBc
86
73
62
dBc
dBc
dBc
86
74
66
66
dBc
dBc
dBc
dBc
−167
−166.5
−166.5
−166.5
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
fOUT2 = fOUT1 + 1.25 MHz
fDAC = 2400 MSPS
POUT = −14.5 dBm
POUT = −15.5 dBm
POUT = −18 dBm
POUT = −18.5 dBm
Rev. A | Page 6 of 76
AD9789
Parameter
ADJACENT CHANNEL LEAKAGE RATIO (ACLR)
1-Channel QAM
fOUT = 200 MHz (Harmonics)
fOUT = 200 MHz (Noise Floor)
fOUT = 500 MHz (Harmonics)
fOUT = 500 MHz (Noise Floor)
fOUT = 800 MHz (Harmonics)
fOUT = 800 MHz (Noise Floor)
2-Channel QAM
fOUT = 200 MHz (Harmonics)
fOUT = 200 MHz (Noise Floor)
fOUT = 500 MHz (Harmonics)
fOUT = 500 MHz (Noise Floor)
fOUT = 800 MHz (Harmonics)
fOUT = 800 MHz (Noise Floor)
4-Channel QAM
fOUT = 200 MHz (Harmonics)
fOUT = 200 MHz (Noise Floor)
fOUT = 500 MHz (Harmonics)
fOUT = 500 MHz (Noise Floor)
fOUT = 800 MHz (Harmonics)
fOUT = 800 MHz (Noise Floor)
WCDMA ACLR
Single Carrier
First Adjacent Channel
Second Alternate Channel
Third Alternate Channel
Single Carrier
First Adjacent Channel
Second Alternate Channel
Third Alternate Channel
Four Carrier
First Adjacent Channel
Second Alternate Channel
Third Alternate Channel
1
Test Conditions/Comments
fDAC = 2293.76 MSPS measured in 6 MHz
channels
Min
Typ
Max
Unit
−76
−82
−74.5
−78
−69
−78
dBc
dBc
dBc
dBc
dBc
dBc
−77.5
−81
−68
−76
−66
−76
dBc
dBc
dBc
dBc
dBc
dBc
−75
−76
−69
−72
−67
−72
dBc
dBc
dBc
dBc
dBc
dBc
−70
−72.5
−74
dBc
dBc
dBc
−68
−70.4
−72.7
dBc
dBc
dBc
−63.5
−65.1
−66.9
dBc
dBc
dBc
fDAC = 2304 MSPS, mix mode second
Nyquist zone
fOUT = 1850 MHz
fOUT = 2100 MHz
fOUT = 2100 MHz
Adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9789, the minimum interpolation factor is 16. Thus,
with fDAC = 2400 MSPS, FDACadj = 2400 MSPS/16 = 150 MSPS.
Rev. A | Page 7 of 76
AD9789
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
AVDD33 to AVSS
DVDD18 to DVSS
DVDD33 to DVSS
DVDD15 to DVSS
CVDD18 to AVSS
AVSS to DVSS
CLKP, CLKN to AVSS
FS, DCO to DVSS
CMOS and LVDS Data Inputs
to DVSS
IOUTN, IOUTP to AVSS
I120, VREF, IPTAT to AVSS
IRQ, CS, SCLK, SDO, SDIO, RESET
to DVSS
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +1.98 V
−0.3 V to +0.3 V
−0.3 V to CVDD18 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
−1.0 V to AVDD33 + 0.3 V
−0.3 V to AVDD33 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
ESD CAUTION
Table 5. Thermal Resistance
Package
Type
164-Ball
CSP_BGA
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 8 of 76
θJA
25.5
24.4
19.0
17.2
θJB
14.4
θJC
6.8
Unit
°C/W
°C/W
°C/W
°C/W
Notes
4-layer board, no vias
4-layer board, 4 PCB vias
8-layer board, 4 PCB vias
8-layer board, 16 PCB vias
AD9789
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CVDD18
1
2
3
IOUTN
4
5
A
+
+
B
+
6
IOUTP
7
8
–
+
9
AVDD33
10 11
12 13 14
1
2
3
4
+
+
+
+
X
5
6
7
8
+
+
9
10 11
12 13 14
A
X
X
NC
B
+
X
X
I120
C
CLKN C
N
+
+
X
X
VREF
D
CLKP D
P
+
+
X
X
IPTAT
E
E
F
F
G
DVDD18
G
+
+
+
+
X
X
X
X
H
H
J
J
K
K
CS L
X
X
X
SB
NC
NC
L
SCLK M
CK
NC
NC
M
SDO N
DO
R
NC
NC
N
SDIO P
IO
I
NC
NC
AVSS
DVDD18
RESET
Figure 4. Clock and Analog Pins (Top View)
1
2
3
4
5
6
7
8
9
10 11
1
12 13 14
A
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
PARP
J
K
PARN
K
P1
31 27 23 19 15
M
P0
11
7
DVSS
+ DVDD15
X DVDD33
Figure 6. Digital Supply and SPI Pins (Top View)
B
L
IRQ
NC NO CONNECT
07852-006
X AVDD33
2
3
4
5
6
7
8
9
10 11
12 13 14
FSP
3
BU
CMOS_BUS
L
P+
15 13
11
9
P–
15 13
7
5
3
1
FS
FSN
6
2
CT
CMOS_CTRL
M
11
9
7
5
3
1
FS
DCOP
29 25 21 17 13
9
5
1
FS
CMOS_FS
N
14 12 10
8
6
4
2
0
DC
DCON
P
28 24 20 16 12
8
4
0
DC
CMOS_DCO
P
14 12 10
8
6
4
2
0
DC
D[31:0] CMOS DATA INPUTS
PARITY AND CONTROL INPUTS
07852-005
30 26 22 18 14 10
N
Figure 5. CMOS Mode Data Input Pins (Top View)
14 +LVDS
14 –LVDS
Figure 7. LVDS Mode Data Input Pins (Top View)
Rev. A | Page 9 of 76
07852-007
+ CVDD18
07852-004
P
AD9789
Table 6. Pin Function Descriptions
Pin No.
A1, A2, A3, A6, A9, A10, A11,
B1, B2, B3, B6, B7, B8, B9,
B10, B11, C2, C3, C6, C7, C8,
C9, C10, C11, D2, D3, D6, D7,
D8, D9, D10, D11, E1, E2, E3,
E4, E13, E14, F1, F2, F3, F4,
F11, F12, F13, F14
A4, A5, B4, B5, C4, C5, D4, D5
A7
A8
A12, A13, B12, B13, C12, C13,
D12, D13
A14
B14
C1
C14
Mnemonic
AVSS
Description
Analog Supply Ground.
CVDD18
IOUTN
IOUTP
AVDD33
1.8 V Clock Supply.
DAC Negative Output Current.
DAC Positive Output Current.
3.3 V Analog Supply.
NC
I120
CLKN
VREF
DVDD18
DVDD15
No Connect. Leave floating.
Tie this pin to analog ground with a 10 kΩ resistor to generate a 120 μA reference current.
Negative DAC Clock Input (DACCLK).
Band Gap Voltage Reference I/O. Decouple to analog ground with a 1 nF capacitor.
Output impedance is approximately 5 kΩ.
Positive DAC Clock Input (DACCLK).
Factory Test Pin. Output current, proportional to absolute temperature, is
approximately 10 μA at 25°C with a slope of approximately 20 nA/°C.
1.8 V Digital Supply.
1.5 V Digital Supply.
D1
D14
CLKP
IPTAT
E11, E12
G1, G2, G3, G4, G7, G8, G11,
G12, G13, G14
H1, H2, H3, H4, H7, H8, H11,
H12, H13, H14, J1, J2, J3, J4,
J11, J12, J13, J14
K1, K2, K3, K4, K11, K12, K13,
K14
L1
L2, L3, M2, M3, N3, N4, P3, P4
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
DVSS
Digital Supply Ground.
DVDD33
3.3 V Digital Supply.
CS
NC
P1/PARP
D31/D15P
D27/D13P
D23/D11P
D19/D9P
D15/D7P
D11/D5P
D7/D3P
D3/D1P
FSP
CMOS_BUS
Active Low Chip Select for SPI.
Not Used. Leave unconnected.
CMOS/LVDS Parity Bit.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
Positive LVDS Frame Sync (FSP) for Data Bus.
Active High Input. Configures data bus for CMOS inputs. Low input configures data bus
to accept LVDS inputs.
Qualifying Clock for SPI.
CMOS/LVDS Parity Bit.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
Negative LVDS Frame Sync (FSN) for Data Bus.
M1
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
SCLK
P0/PARN
D30/D15N
D26/D13N
D22/D11N
D18/D9N
D14/D7N
D10/D5N
D6/D3N
D2/D1N
FSN
Rev. A | Page 10 of 76
AD9789
Pin No.
M14
Mnemonic
CMOS_CTRL
N1
N2
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
SDO
RESET
D29/D14P
D25/D12P
D21/D10P
D17/D8P
D13/D6P
D9/D4P
D5/D2P
D1/D0P
DCOP
CMOS_FS
SDIO
IRQ
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
D28/D14N
D24/D12N
D20/D10N
D16/D8N
D12/D6N
D8/D4N
D4/D2N
D0/D0N
DCON
CMOS_DCO
Description
Active High Input. Enables CMOS_DCO and CMOS_FS signals and disables DCOP/DCON
and FSP/FSN signals. Low input disables CMOS_DCO and CMOS_FS signals and enables
DCOP/DCON and FSP/FSN signals.
Serial Data Output for SPI.
Active High Input. Resets the AD9789.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
Positive LVDS Data Clock Output (DCOP) for Data Bus.
CMOS Frame Sync for Data Bus.
Serial Data Input/Output for SPI.
Active Low, Open-Drain Interrupt Request Output. Pull up to DVDD33 with a 10 kΩ
resistor.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
CMOS/LVDS Data Input.
Negative LVDS Data Clock Output (DCON) for Data Bus.
CMOS Data Clock Output for Data Bus.
Rev. A | Page 11 of 76
AD9789
–40
–45
–45
–50
–50
–55
–55
–60
–60
SFDR (dBc)
–40
–65
–70
0
200
400
600
fOUT (MHz)
800
1000
–85
1200
–90
–45
–50
–50
HARMONIC LEVEL (dBc)
–45
–55
–60
–65
–70
–75
0dBFS
–3dBFS
–6dBFS
–12dBFS
0
200
400
600
fOUT (MHz)
800
1000
1200
1000
1200
–55
–60
–65
–70
–75
–90
0dBFS
–3dBFS
–6dBFS
–12dBFS
0
200
400
600
800
1000
1200
fOUT (MHz)
Figure 12. Third-Order Harmonic vs. fOUT over Digital Full Scale,
fDAC = 2.4 GHz, Full-Scale Current = 20 mA, Temperature = 25°C
–50
–45
–55
–50
–60
–55
–65
–60
–70
SFDR (dBc)
–40
–65
–70
–75
–75
–80
–85
32mA
20mA
8mA
–80
–85
0
200
400
600
800
1000
+85°C
+25°C
–40°C
–90
–95
1200
fOUT (MHz)
07852-011
SFDR (dBc)
800
–85
Figure 9. Second-Order Harmonic vs. fOUT over Digital Full Scale,
fDAC = 2.4 GHz, Full-Scale Current = 20 mA, Temperature = 25°C
–90
600
–80
07852-009
HARMONIC LEVEL (dBc)
–40
–90
400
Figure 11. SFDR vs. fOUT over Digital Full Scale, fDAC = 2.4 GHz,
Full-Scale Current = 20 mA, Temperature = 25°C
–40
–85
200
fOUT (MHz)
Figure 8. SFDR vs. fOUT over fDAC, Full-Scale Current = 20 mA,
Digital Scale = 0 dBFS, Temperature = 25°C
–80
0
Figure 10. SFDR vs. fOUT over Full-Scale Current, fDAC = 2.4 GHz,
Digital Scale = 0 dBFS, Temperature = 25°C
–100
0
200
400
600
800
1000
1200
fOUT (MHz)
Figure 13. SFDR vs. fOUT over Temperature, fDAC = 2.4 GHz,
Full-Scale Current = 20 mA, Digital Scale = 0 dBFS
Rev. A | Page 12 of 76
07852-008
–90
0dBFS
–3dBFS
–6dBFS
–12dBFS
–80
07852-010
–85
–70
–75
2.4GHz
2.2GHz
2GHz
1.6GHz
1GHz
–80
–65
07852-012
–75
07852-013
SFDR (dBc)
TYPICAL PERFORMANCE CHARACTERISTICS
AD9789
90
100
80
90
80
70
IMD (dBc)
60
50
0
100
200
300
400
500
600 700
fOUT (MHz)
800
900 1000 1100
30
100
90
90
80
200
300
400
500
600
700
800
900 1000 1100
70
70
IMD (dBc)
60
60
50
50
32mA
20mA
8mA
0
100
200
300
400
500
600 700
fOUT (MHz)
800
+85°C
+25°C
–40°C
40
900 1000 1100
30
07852-038
40
Figure 15. Third-Order IMD vs. fOUT over Full-Scale Current, fDAC = 2.4 GHz,
Digital Scale = 0 dBFS, Temperature = 25°C
0
–157
–159
–159
–161
–161
NSD (dBm/Hz)
–157
–167
–169
400
500
600
700
800
900 1000 1100
–163
–165
–167
–169
2.4GHz
2.0GHz
1.6GHz
–173
0
200
400
600
fOUT (MHz)
800
1000
+85°C
+25°C
–40°C
–171
–173
1200
–175
07852-016
–171
–175
300
Figure 18. Third-Order IMD vs. fOUT over Temperature, fDAC = 2.4 GHz,
Full-Scale Current = 20 mA, Digital Scale = 0 dBFS
–155
–165
200
fOUT (MHz)
–155
–163
100
07852-041
IMD (dBc)
100
Figure 17. Third-Order IMD vs. fOUT over Digital Full Scale, fDAC = 2.4 GHz,
Full-Scale Current = 20 mA, Temperature = 25°C
80
NSD (dBm/Hz)
0
fOUT (MHz)
Figure 14. Third-Order IMD vs. fOUT over fDAC, Full-Scale Current = 20 mA,
Digital Scale = 0 dBFS, Temperature = 25°C
30
0dBFS
–3dBFS
–6dBFS
–12dBFS
40
07852-034
40
30
50
2.4GHz
2.0GHz
1.6GHz
1.0GHz
07852-037
60
Figure 16. NSD vs. fOUT over fDAC, 1-Channel QAM, Full-Scale Current = 20 mA
0
200
400
600
fOUT (MHz)
800
1000
1200
07852-019
IMD (dBc)
70
Figure 19. NSD vs. fOUT over Temperature, 1-Channel QAM, fDAC = 2.4 GHz,
Full-Scale Current = 20 mA
Rev. A | Page 13 of 76
AD9789
–5
DOCSIS3
–40°C
0°C
+25°C
+85°C
ACLR (dBc)
–25
–35
–45
–45
–55
–65
–65
–75
–75
–85
50
250
450
650
FREQUENCY (MHz)
850
–85
50
Figure 20. ACLR Performance over Temperature, 1-Channel QAM,
fDAC = 2.3 GHz, Full-Scale Current = 20 mA, fOUT = 200 MHz, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc)
–55
–60
–60
HARMONIC LEVEL (dBc)
–55
–65
–70
–75
DOCSIS3
25°C
65°C
85°C
–80
–85
0
100
200
300
400
500 600
fOUT (MHz)
700
800
900
250
350
450 550
650
FREQUENCY (MHz)
750
1000
850
950
–65
–70
–75
DOCSIS3
25°C
65°C
85°C
–80
Figure 21. Second-Order Harmonic Performance vs. fOUT over Temperature,
1-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc)
–85
0
100
200
300
400
500
600
700
800
900
fOUT (MHz)
1000
Figure 24. Third-Order Harmonic Performance vs. fOUT over Temperature,
1-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc)
–55
–5
DOCSIS3
25°C
65°C
85°C
–60
150
Figure 23. ACLR Performance over Temperature, 1-Channel QAM,
fDAC = 2.3 GHz, Full-Scale Current = 20 mA, fOUT = 800 MHz, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc)
07852-014
HARMONIC LEVEL (dBc)
–35
–55
07852-015
ACLR (dBc)
–25
DOCSIS3
–40°C
0°C
+25°C
+85°C
–15
07852-017
–15
07852-018
–5
–15
DOCSIS3
2.3GHz
2.2GHz
2.4GHz
–25
ACLR (dBc)
ACLR (dBc)
–65
–70
–35
–45
–55
–75
–65
–80
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
–85
50
Figure 22. Noise Floor vs. fOUT over Temperature (ACLR Measured Beyond 30 MHz),
1-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc)
250
450
650
FREQUENCY (MHz)
850
1050
07852-039
0
07852-031
–85
–75
Figure 25. ACLR Performance over fDAC, 1-Channel QAM, fOUT = 850 MHz,
Full-Scale Current = 20 mA, Temperature = 25°C, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc)
Rev. A | Page 14 of 76
AD9789
0
–5
DOCSIS3
CMOS
LVDS
–10
–20
DOCSIS3
25°C
65°C
85°C
–15
–25
ACLR (dBc)
–40
–50
–65
–70
100
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
1000
Figure 26. ACLR Performance for CMOS and LVDS Interfaces, 1-Channel QAM,
fOUT = 840 MHz, fDAC = 2.4 GHz, Full-Scale Current = 20 mA, Sum Scale = 48
(DOCSIS SPEC Is −73 dBc)
450
650
FREQUENCY (MHz)
850
1050
Figure 29. ACLR Performance over Temperature, 2-Channel QAM,
fOUT = 200 MHz, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32
(DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc)
DOCSIS3
25°C
65°C
85°C
–60
HARMONIC LEVEL (dBc)
–25
–35
–45
–55
–65
–65
–70
–75
DOCSIS3
25°C
65°C
85°C
–80
–75
250
450
650
FREQUENCY (MHz)
850
–85
07852-042
–85
50
1050
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 27. ACLR Performance over Temperature, 2-Channel QAM,
fOUT = 800 MHz, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32
(DOCSIS SPEC Is −70 dBc)
07852-045
–15
Figure 30. Second Harmonic Performance vs. fOUT over Temperature,
2-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32
(DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc)
–55
–55
–60
–65
–65
ACLR (dBc)
–60
–70
–75
DOCSIS3
25°C
65°C
85°C
–70
–75
DOCSIS3
25°C
65°C
85°C
0
100
200
300
400
500
600
fOUT (MHz)
700
800
900
1000
–80
–85
07852-043
–80
–85
250
–55
–5
ACLR (dBc)
–85
50
07852-040
0
07852-044
–75
–80
HARMONIC LEVEL (dBc)
–45
–55
–60
–90
–35
Figure 28. Third-Order Harmonic Performance vs. fOUT over Temperature,
2-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32
(DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc)
0
100
200
300
400
500
600
fOUT (MHz)
700
800
900
1000
07852-046
ACLR (dBc)
–30
Figure 31. Noise Floor vs. fOUT over Temperature (ACLR Measured Beyond 30 MHz),
2-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32
(DOCSIS SPEC Is −70 dBc)
Rev. A | Page 15 of 76
AD9789
0
0
–10
DOCSIS3
–40°C
0°C
+25°C
+85°C
ACLR (dBc)
–40
–50
–40
–50
–60
–60
–70
–70
–80
50
250
450
650
FREQUENCY (MHz)
850
1050
–80
50
Figure 32. ACLR Performance over Temperature, 4-Channel QAM,
fOUT = 200 MHz, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
(DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc)
–55
–60
–60
HARMONIC LEVEL (dBc)
–55
–65
–70
–75
DOCSIS3
25°C
65°C
85°C
–80
0
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
1050
–65
–70
–75
–85
DOCSIS3
25°C
65°C
85°C
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 36. Third-Order Harmonic Performance vs. fOUT over Temperature,
4-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
(DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc)
0
–55
–10
–60
–20
ACLR (dBc)
–65
ACLR (dBc)
850
–80
Figure 33. Second-Order Harmonic Performance vs. fOUT over Temperature,
4-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
(DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc)
–70
–75
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
–30
–40
–50
–70
–80
50
07852-028
0
DOCSIS3
2.3GHz
2.2GHz
2.4GHz
–60
DOCSIS3
25°C
65°C
85°C
–80
–85
450
650
FREQUENCY (MHz)
Figure 34. Noise Floor vs. fOUT over Temperature (ACLR Measured Beyond 30 MHz),
4-Channel QAM, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
(DOCSIS SPEC Is −67 dBc)
250
450
650
FREQUENCY (MHz)
850
1050
07852-047
–85
250
Figure 35. ACLR Performance over Temperature, 4-Channel QAM,
fOUT = 800 MHz, fDAC = 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
(DOCSIS SPEC Is −67 dBc)
07852-026
HARMONIC LEVEL (dBc)
–30
07852-029
–30
DOCSIS3
–40°C
0°C
+25°C
+85°C
–20
07852-027
ACLR (dBc)
–20
07852-030
–10
Figure 37. ACLR Performance over fDAC, 4-Channel QAM, fOUT = 850 MHz,
Full-Scale Current = 25 mA, Temperature = 25°C, Sum Scale = 20
(DOCSIS SPEC Is −67 dBc)
Rev. A | Page 16 of 76
AD9789
RMS RESULTS
CARRIER POWER
–18.10dBm/
6.00000MHz
VBW 560kHz
FREQ.
OFFSET
3.375MHz
6.375MHz
12.00MHz
18.00MHz
REF BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
SPAN 42MHz
SWEEP 39.12ms (601 PTS)
LOWER
dBc
dBm
–65.57 –83.66
–75.01 –93.11
–76.83 –94.92
–77.17 –95.26
UPPER
dBc
dBm
–68.98 –87.07
–74.62 –92.71
–76.46 –94.55
–76.56 –94.66
CENTER 840.00MHz
RES BW 30kHz
Figure 38. 1-Channel QAM ACLR, fOUT = 840 MHz, Temperature = 25°C,
Sum Scale = 48, Full-Scale Current = 20 mA, Span = 42 MHz
CENTER 840.00MHz
RES BW 30kHz
RMS RESULTS
CARRIER POWER
–21.75dBm/
6.00000MHz
VBW 300kHz
FREQ.
OFFSET
3.375MHz
6.375MHz
12.00MHz
18.00MHz
REF BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
SPAN 18MHz
SWEEP 58.4ms (601 PTS)
Figure 40. 1-Channel QAM ACLR, fOUT = 840 MHz, Temperature = 25°C,
Sum Scale = 48, Full-Scale Current = 20 mA, Span = 18 MHz
REF –35.91dBm
SPAN 42MHz
SWEEP 136.2ms (601 PTS)
LOWER
UPPER
dBc
dBm
dBc
dBm
–71.64 –93.39 –72.50 –94.25
–73.71 –95.47 –66.72 –88.47
–73.58 –95.33
0.50 –21.10
–73.70 –95.45 –66.72 –88.48
VBW 300kHz
FREQ.
LOWER
UPPER
OFFSET REF BW
dBc
dBm
dBc
dBm
RMS RESULTS
CARRIER POWER 3.375MHz 750.0kHz –73.99 –91.97 –74.93 –92.91
6.375MHz 5.250MHz –74.94 –92.92 –75.35 –93.33
–17.98dBm/
6.00000MHz
ATTEN 2dB
START 831.00MHz
RES BW 30kHz
07852-061
REF –35.91dBm
ATTEN 2dB
RMS RESULTS
CARRIER POWER
–21.29dBm/
6.00000MHz
Figure 39. 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32,
Full-Scale Current = 25 mA, Span = 42 MHz, Channel 1
ATTEN 2dB
VBW 300kHz
FREQ.
OFFSET
3.375MHz
6.375MHz
12.00MHz
18.00MHz
STOP 873MHz
SWEEP 136.2ms (601 PTS)
LOWER
REF BW
dBc
dBm
750.0kHz –70.07 –92.16
5.250MHz –69.05 –90.34
6.000MHz –0.49 –21.78
6.000MHz –66.61 –87.90
UPPER
dBc
dBm
–73.20 –94.49
–73.87 –95.16
–73.29 –94.58
–73.98 –95.27
Figure 41. 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32,
Full-Scale Current = 25 mA, Span = 42 MHz, Channel 2
Rev. A | Page 17 of 76
07852-066
CENTER 840.00MHz
RES BW 56kHz
REF –32.76dBm
07852-023
ATTEN 2dB
07852-020
REF –32.76dBm
AD9789
VBW 300kHz
SPAN 18MHz
SWEEP 58.4ms (601 PTS)
FREQ.
LOWER
UPPER
OFFSET REF BW
dBc
dBm
dBc
dBm
RMS RESULTS
CARRIER POWER 3.375MHz 750.0kHz –75.37 –96.93 –75.56 –97. 11
–21.56dBm/
6.375MHz 5.250MHz –73.85 –95.41 –72.54 –94.10
6.00000MHz
CENTER 852.00MHz
RES BW 30kHz
Figure 42. Zoomed 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32,
Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1
CENTER 834.00MHz
RES BW 30kHz
VBW 300kHz
RMS RESULTS
CARRIER POWER
–23.63dBm/
6.00000MHz
FREQ.
OFFSET
3.375MHz
6.375MHz
12.00MHz
18.00MHz
REF BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
SPAN 42MHz
SWEEP 136.2ms (601 PTS)
ATTEN 2dB
CENTER 852.00MHz
VBW 300kHz
RES BW 30kHz
Figure 43. 4-Channel QAM ACLR, fOUT = 840 MHz, Temperature = 25°C,
Sum Scale = 20, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 1
SPAN 18MHz
SWEEP 58.4ms (601 PTS)
Figure 44. Zoomed 2-Channel QAM ACLR, fOUT = 840 MHz, Sum Scale = 32,
Full-Scale Current = 25 mA, Span = 18 MHz, Channel 2
REF –35.96dBm
LOWER
UPPER
dBc
dBm
dBc
dBm
–70.33 –93.96 –11.07 –34.70
–69.04 –92.67 –0.49 –24.12
–70.38 –94.01
0.00 –23.63
–71.02 –94.65
0.43 –23.20
VBW 300kHz
FREQ.
LOWER
UPPER
OFFSET REF BW
dBc
dBm
dBc
dBm
RMS RESULTS
CARRIER POWER 3.375MHz 750.0kHz –75.51 –96.54 –75.17 –96.20
–21.03dBm/
6.375MHz 5.250MHz –72.55 –93.58 –73.90 –94.93
6.00000MHz
ATTEN 2dB
07852-021
REF –35.96dBm
ATTEN 2dB
RMS RESULTS
CARRIER POWER
–23.23dBm/
6.00000MHz
FREQ.
OFFSET
3.375MHz
6.375MHz
12.00MHz
18.00MHz
REF BW
750.0kHz
5.250MHz
6.000MHz
6.000MHz
SPAN 42MHz
SWEEP 136.2ms (601 PTS)
LOWER
dBc
dBm
–11.10 –34.32
–0.75 –23.98
–0.59 –23.81
–0.35 –23.58
UPPER
dBc
dBm
–72.19 –95.42
–68.97 –92.20
–70.32 –93.55
–70.70 –93.93
07852-022
CENTER 840.00MHz
RES BW 30kHz
REF –35.91dBm
07852-067
ATTEN 2dB
07852-065
REF –35.91dBm
Figure 45. 4-Channel QAM ACLR, fOUT = 840 MHz, Temperature = 25°C,
Sum Scale = 20, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 4
Rev. A | Page 18 of 76
AD9789
CENTER 834.00MHz
RES BW 30kHz
VBW 300kHz
REF –35.96dBm
SPAN 18MHz
SWEEP 58.4ms (601 PTS)
CENTER 852.00MHz
RES BW 30kHz
FREQ.
LOWER
UPPER
OFFSET REF BW
dBc
dBm
dBc
dBm
RMS RESULTS
CARRIER POWER 3.375MHz 750.0kHz –72.95 –96.56 –10.86 –34.48
6.375MHz 5.250MHz –69.38 –92.99 –0.51 –24.13
–23.62dBm/
6.00000MHz
Figure 49. Zoomed 4-Channel QAM ACLR, fOUT = 840 MHz, Temperature =
25°C, Sum Scale = 20, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 4
50
50
48
48
46
46
44
44
42
42
40
38
38
36
+25°C
+85°C
–40°C
32
150
250
350
450
550 650
fOUT (MHz)
750
850
950
+25°C
+85°C
–40°C
34
32
30
50
07852-032
34
150
250
350
450
550
650
750
850
950
fOUT (MHz)
Figure 47. Modulation Error Ratio, Equalized, 1-Channel 256-QAM,
fDAC = 2.29376 GHz, Full-Scale Current = 20 mA, Sum Scale = 48
(Equalization Filter from Demodulation Toolbox on Spectrum Analyzer Used)
Figure 50. Modulation Error Ratio, Equalized, 4-Channel 256-QAM,
fDAC = 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
(Equalization Filter from Demodulation Toolbox on Spectrum Analyzer Used)
50
50
48
48
46
46
44
44
42
42
MER (dB)
40
38
36
40
38
36
+25°C
+85°C
–40°C
32
150
250
350
450
550 650
fOUT (MHz)
750
850
950
+25°C
+85°C
–40°C
34
32
30
50
07852-033
34
150
250
350
450
550
fOUT (MHz)
Figure 48. Modulation Error Ratio, Unequalized, 1-Channel 256-QAM,
fDAC = 2.29376 GHz, Full-Scale Current = 20 mA, Sum Scale = 48
650
750
850
950
07852-036
MER (dB)
40
07852-035
36
30
50
SPAN 18MHz
SWEEP 58.4ms (601 PTS)
VBW 300kHz
FREQ.
LOWER
UPPER
OFFSET REF BW
dBc
dBm
dBc
dBm
RMS RESULTS
CARRIER POWER 3.375MHz 750.0kHz –11.20 –34.40 –74.44 –97.64
6.375MHz 5.250MHz –0.77 –23.96 –69.07 –92.26
–23.20dBm/
6.00000MHz
MER (dB)
MER (dB)
Figure 46. Zoomed 4-Channel QAM ACLR, fOUT = 840 MHz, Temperature =
25°C, Sum Scale = 20, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1
30
50
ATTEN 2dB
07852-025
ATTEN 2dB
07852-024
REF –35.96dBm
Figure 51. Modulation Error Ratio, Unequalized, 4-Channel 256-QAM,
fDAC = 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20
Rev. A | Page 19 of 76
AD9789
REF –32.62dBm
80
ATTEN 0dB
75
70
65
60
SFDR (dBc)
55
50
45
40
35
30
25
20
CENTER 2.100GHz
RES BW 30kHz
Figure 52. SFDR vs. fOUT in Mix Mode, fDAC = 2.4 GHz, Full-Scale Current = 20 mA
(Second Nyquist Zone Performance)
90
RMS RESULTS
CARRIER POWER
–19.95dBm/
3.84000MHz
85
VBW 300kHz
FREQ.
OFFSET
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
SPAN 53.84MHz
SWEEP 174.6ms (601 PTS)
LOWER
dBc
dBm
–68.93 –88.88
–71.31 –91.26
–73.43 –93.37
–75.12 –95.07
–75.60 –95.55
UPPER
dBc
dBm
–67.99 –87.94
–70.42 –90.37
–72.68 –92.63
–74.89 –94.84
–76.51 –96.46
07852-092
10
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
fOUT (MHz)
07852-068
15
Figure 55. One-Carrier WCDMA ACLR in Mix Mode, fOUT = 2.1 GHz,
fDAC = 2304 MHz, Full-Scale Current = 20 mA
80
75
IMD (dBc)
70
REF –38.62dBm
65
ATTEN 2dB
60
55
50
45
40
30
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
fOUT (MHz)
07852-076
35
Figure 53. IMD vs. fOUT in Mix Mode, fDAC = 2.4 GHz, Full-Scale Current = 20 mA
(Second Nyquist Zone Performance)
–45
–50
CENTER 2.102 50GHz
RES BW 30kHz
VBW 300kHz
FIRST ADJACENT CHANNE L
SECOND ADJACENT CHANNE L
THIRD ADJACENT CHANNE L
FIFTH ADJACENT CHANNE L
RMS RESULTS
CARRIER POWER
–26.06dBm/
3.84000MHz
ACLR (dBc)
–55
–60
–65
REF BW
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
LOWER
dBc
dBm
–0.25 –26.31
–0.42 –26.48
–64.07 –90.13
–65.36 –91.42
–66.86 –92.92
–67.83 –93.89
UPPER
dBc
dBm
–0.42 –26.47
–63.50 –89.56
–65.13 –91.18
–66.97 –93.03
–68.70 –94.76
–68.64 –94.70
Figure 56. Four-Carrier WCDMA ACLR in Mix Mode, fOUT = 2.1 GHz,
fDAC = 2304 MHz, Full-Scale Current = 20 mA
–70
–75
07852-075
–80
–85
1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250
fOUT (MHz)
FREQ.
OFFSET
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
30.00MHz
SPAN 63.84MHz
SWEEP 207ms (601 PTS)
Figure 54. ACLR vs. fOUT in Mix Mode with One-Carrier WCDMA, fDAC = 2304 MHz,
Full-Scale Current = 20 mA (Second Nyquist Zone Performance)
Rev. A | Page 20 of 76
07852-093
–40
AD9789
1100
2000
AVDD33
DVDD33 (LVDS)
DVDD33 (CMOS)
DVDD18
DVDD15
CVDD18
1600
700
600
500
400
300
1000
800
600
100
200
1.2
1.4
1.6
1.8
fDAC (GHz)
2.0
2.2
2.4
0
1.0
500
1200
POWER DISSIPATION (mW)
600
400
300
200
1.6
1.8
2.0
2.2
2.4
TOTAL (CMOS)
TOTAL (LVDS)
1000
800
600
400
200
1.2
1.4
1.6
1.8
2.0
2.2
2.4
fDAC (GHz)
0
1.0
07852-095
0
1.0
180
160
140
AVDD33
120
100
80
60
40
14
16 18 20 22 24 26
FULL-SCALE CURRENT (mA)
28
30
32
07852-098
20
12
1.6
1.8
2.0
2.2
2.4
Figure 61. Total Power Dissipation vs. fDAC, 16× Interpolation,
One Channel Enabled, fOUT = 70 MHz, Full-Scale Current = 20 mA
200
10
1.4
fDAC (GHz)
Figure 58. Power Dissipation by Supply vs. fDAC, 16× Interpolation,
One Channel Enabled, fOUT = 70 MHz, Full-Scale Current = 20 mA
8
1.2
Figure 59. AVDD33 Power Dissipation vs. Full-Scale Current
Rev. A | Page 21 of 76
07852-097
100
0
1.4
Figure 60. Total Power Dissipation vs. fDAC, 4-Channel DOCSIS, fOUT = 915 MHz,
Full-Scale Current = 25 mA (Datapath Configuration: QAM Encoder On,
SRRC Filter On, Four 2× Interpolation Filters On)
1400
AVDD33
DVDD33 (LVDS)
DVDD33 (CMOS)
DVDD18
DVDD15
CVDD18
1.2
fDAC (GHz)
700
POWER DISSIPATION (mW)
1200
400
Figure 57. Power Dissipation by Supply vs. fDAC, 4-Channel DOCSIS, fOUT = 915 MHz,
Full-Scale Current = 25 mA (Datapath Configuration: QAM Encoder On,
SRRC Filter On, Four 2× Interpolation Filters On)
POWER DISSIPATION (mW)
1400
200
0
1.0
TOTAL (CMOS)
TOTAL (LVDS)
07852-096
800
07852-094
POWER DISSIPATION (mW)
900
1800
POWER DISSIPATION (mW)
1000
AD9789
TERMINOLOGY
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0. For IOUTP, 0 mA output is expected when all inputs are
set to 0. For IOUTN, 0 mA output is expected when all inputs
are set to 1.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in dB, between the peak amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Noise Spectral Density (NSD)
NSD is the converter noise power per unit of bandwidth. NSD
is usually specified in dBm/Hz in the presence of a 0 dBm fullscale signal.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the output when all inputs
are set to 1s minus the output when all inputs are set to 0s.
Adjacent Channel Leakage Ratio (ACLR)
The adjacent channel leakage (power) ratio is the ratio, in dBc,
between the measured power within a channel relative to its
adjacent channels.
Temperature Drift
Modulation Error Ratio (MER)
Modulated signals create a discrete set of output values referred
to as a constellation. Each symbol creates an output signal corresponding to one point on the constellation. MER is a measure
of the discrepancy between the average output symbol magnitude
and the rms error magnitude of the individual symbol.
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset,
gain, and reference drift, the drift is reported in ppm per °C.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from nominal to minimum and maximum
specified voltages.
Output Compliance Range
The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits may cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Intermodulation Distortion (IMD)
IMD is the result of two or more signals at different frequencies
mixing together. Many products are created according to the
formula af1 ± bf2, where a and b are integer values.
Rev. A | Page 22 of 76
AD9789
SERIAL CONTROL PORT
The AD9789 serial control port is a flexible, synchronous serial
communications port that allows an easy interface to many
industry-standard microcontrollers and microprocessors. The
AD9789 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI® and Intel® SSR
protocols. The serial control port allows read/write access to all
registers that configure the AD9789. Single- or multiple-byte
transfers are supported, as well as MSB first or LSB first transfer
formats. The AD9789 serial control port can be configured for a
single bidirectional I/O pin (SDIO only) or for two unidirectional
I/O pins (SDIO/SDO). By default, the AD9789 is in unidirectional
long instruction mode (long instruction mode is the only
instruction mode supported).
SERIAL CONTROL PORT PIN DESCRIPTIONS
The SCLK (serial clock) pin is the serial shift clock. This pin is
an input. SCLK is used to synchronize serial control port reads
and writes. Write data bits are registered on the rising edge of
this clock, and read data bits are registered on the falling edge.
This pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin that acts
as an input only (unidirectional mode) or as both an input and
an output (bidirectional mode). The AD9789 defaults to the
unidirectional I/O mode (Register 0x00[7] = 0).
The SDO (serial data output) pin is used only in the unidirectional
I/O mode as a separate output pin for reading back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to DVDD33.
M1
CS
L1
SDO
N1
SDIO
P1
AD9789
SERIAL
CONTROL
PORT
07852-048
SCLK
Figure 62. Serial Control Port
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or read operation to the AD9789 is initiated by pulling
CS low. CS stall high is supported in modes where three or
fewer bytes of data (plus the instruction data) are transferred
(see Table 7). In these modes, CS can temporarily return high
on any byte boundary, allowing time for the system controller
to process the next byte. CS can go high on byte boundaries
only and can go high during either part (instruction or data)
of the transfer.
During CS stall high mode, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort the transfer before all of the data is sent, the
state machine must be reset by either completing the remaining
transfers or by returning CS low for at least one complete SCLK
cycle (but less than eight SCLK cycles). Raising CS on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 7), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending streaming mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9789.
In the first part, a 16-bit instruction word is written to the
AD9789, coincident with the first 16 SCLK rising edges. The
instruction word provides the AD9789 serial control port with
information regarding the data transfer, which is the second
part of the communication cycle. The instruction word defines
whether the upcoming data transfer is a read or a write, the
number of bytes in the data transfer, and the starting register
address for the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
of the communication cycle is the transfer of data into the serial
control port buffer of the AD9789. Data bits are registered on
the rising edge of SCLK.
The length of the transfer (one, two, or three bytes or streaming
mode) is indicated by two bits (N1 and N0) in the instruction byte.
When the transfer is one, two, or three bytes (but not streaming
mode), CS can be raised after each sequence of eight bits to stall
the bus, except after the last byte, where it ends the cycle. When
the bus is stalled, the serial transfer resumes when CS is lowered.
Raising CS on a nonbyte boundary resets the serial control port.
During a write, streaming mode does not skip reserved or blank
registers; therefore, the user must know what bit pattern to write
to the reserved registers to preserve proper operation of the
part. It does not matter what data is written to blank registers.
Most writes to the control registers immediately reconfigure the
device. However, Register 0x16 through Register 0x1D do not
directly control device operation. They provide data to internal
logic that must perform additional operations on the data before
it is downloaded and the device configuration is changed. For
any updates to Register 0x16 through Register 0x1D to take
effect, the FREQNEW bit (Register 0x1E[7]) must be set to 1
(this bit is self-clearing). Any number of bytes of data can be
changed before updating registers. Setting the FREQNEW bit
simultaneously updates Register 0x16 through Register 0x1D.
In a similar fashion, any changes to Register 0x22 and Register
0x23 require PARMNEW (Register 0x24[7]) to be toggled from
a low state to a high state before the new values take effect.
Unlike the FREQNEW bit, PARMNEW is not self-clearing.
Rev. A | Page 23 of 76
AD9789
Read
If the instruction word is for a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by Bits[N1:N0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling edge
of SCLK.
The default mode of the AD9789 serial control port is the unidirectional mode. In unidirectional mode, the readback data
appears on the SDO pin. It is also possible to set the AD9789 to
bidirectional mode using the SDIO_DIR bit (Register 0x00[7]).
In bidirectional mode, both the sent data and the readback data
appear on the SDIO pin.
A readback request reads the data that is in the serial control port
buffer area or the data in the active registers (see Figure 63).
The AD9789 supports only the long instruction mode; therefore,
Register 0x00[4:3] reads 11 (this register uses mirrored bits).
Long instruction mode is the default at power-up or reset, and
writing to these bits has no effect.
SDO
CS
SERIAL
CONTROL
PORT
FREQNEW
WRITE REGISTER 0x1E = 0x10
TO UPDATE REGISTERS
07852-049
SDIO
ACTIVE REGISTERS
SCLK
BUFFER REGISTERS
The AD9789 uses Register Address 0x00 to Register Address 0x55.
Figure 63. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9789
INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
N1 and N0, indicate the length of the transfer in bytes. The final
13 bits (Bits[A12:A0]) are the address at which to begin the read
or write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[N1:N0] (see Table 7).
Table 7. Byte Transfer Count
N1
0
0
1
1
N0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communication cycle. Only Bits[A6:A0] are needed to cover the
range of the 0x55 registers used by the AD9789. Bits[A12:A7]
must always be 0. For multibyte transfers, this address is the
starting byte address. In MSB first mode, subsequent bytes
increment the address.
MSB/LSB FIRST TRANSFERS
The AD9789 instruction word and byte data can be MSB first or
LSB first. Any data written to Register 0x00 must be mirrored,
the upper four bits (Bits[7:4]) with the lower four bits (Bits [3:0]).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, the default setting for
Register 0x00[7:0] is 0x18, which mirrors Bit 4 and Bit 3. These
bits set the long instruction mode (the default and the only
mode supported). The default for the AD9789 is MSB first.
When LSB first is set by Register 0x00[1] and Register 0x00[6],
it takes effect immediately. In multibyte transfers, subsequent
bytes reflect any changes in the serial port configuration.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the low
address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte transfer cycle.
When LSB first mode is active, the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The internal byte address generator of the
serial control port increments for each byte of the multibyte
transfer cycle.
The AD9789 serial control port register address decrements
from the register address just written toward 0x00 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x55 for
multibyte I/O operations.
Streaming mode always terminates when it reaches Address 0x2F.
Note that unused addresses are not skipped during multibyte I/O
operations.
Table 8. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB First
MSB First
Rev. A | Page 24 of 76
Address Direction
Increment
Decrement
Stop Sequence
0x02D, 0x02E, 0x02F, stop
0x001, 0x000, 0x02F, stop
AD9789
Table 9. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
N1
N0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
SDIO DON'T CARE
R/W N1 N0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
DON'T CARE
REGISTER (N – 1) DATA
07852-050
DON'T CARE
Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
CS
SCLK
DON'T CARE
SDIO
DON'T CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
07852-051
SDO
DON'T CARE
R/W N1 N0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
tDS
tHI
tS
tDH
CS
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
N1
R/W
N0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
07852-052
SCLK
tC
tCLK
tLO
Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
tDV
SDIO
SDO
DATA BIT N
DATA BIT N – 1
07852-053
SCLK
Figure 67. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
A0 A1 A2 A3 A4
A5 A6 A7 A8 A9 A10 A11 A12 N0 N1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
D1 D2 D3 D4 D5 D6 D7
REGISTER (N + 1) DATA
Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
Rev. A | Page 25 of 76
DON'T CARE
07852-054
SDIO DON'T CARE
DON'T CARE
AD9789
tS
tC
CS
tCLK
tHI
SCLK
tLO
tDS
SDIO
BIT N
BIT N + 1
Figure 69. Serial Control Port Timing—Write
Table 10. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHI
tLO
tDV
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 67)
Rev. A | Page 26 of 76
07852-055
tDH
AD9789
SPI REGISTER MAP
Do not write to the following registers unless instructed otherwise: Register 0x34, Register 0x35, Register 0x37, Register 0x3B, Register 0x3F,
or Register 0x40 through Register 0x55.
Table 11. Register Map
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
Register Name
SPI control
Saturation
counter
Parity counter
Interrupt enable
Interrupt
status/clear
Channel enable
Bypass
QAM/SRRC
configuration
Summing node
scalar
Input scalar
NCO 0 frequency
tuning word
Bit 7
SDIO_DIR
Bit 6
LSBFIRST
Bit 5
RESET
PARERR
PARERR
BISTDONE
BISTDONE
PARMSET
PARMSET
QAM
SRRC
Reserved
PARCNT[7:0]
PARMCLR
LOCKACQ
PARMCLR
LOCKACQ
Reserved
Reserved
ALPHA[1:0]
Reserved
Bit 2
Bit 1
Bit 0
LOCKLOST
LOCKLOST
SATERR
SATERR
Reserved
Reserved
CHANEN[3:0]
INT[4:0]
MAPPING[2:0]
NCO 3 frequency
tuning word
Rate converter
denominator (Q)
Rate converter
numerator (P)
Interpolating BPF
center frequency
FREQNEW
CMOS_BUS
BIN
Reserved
PARMNEW
Reserved
CMOS_CTRL
Reserved
BUSWDTH[1:0]
DCODIV[2:0]
DSCPHZ[3:0]
DCO_INV
IF_MODE
DATWDTH
CMPLX
Reserved
CHAN0GAIN[7:0]
CHAN1GAIN[7:0]
CHAN2GAIN[7:0]
CHAN3GAIN[7:0]
Reserved
Rev. A | Page 27 of 76
0x00
0x00
0x00
0x0D
INSCALE[7:0]
FTW0[7:0]
FTW0[15:8]
FTW0[23:16]
FTW1[7:0]
FTW1[15:8]
FTW1[23:16]
FTW2[7:0]
FTW2[15:8]
FTW2[23:16]
FTW3[7:0]
FTW3[15:8]
FTW3[23:16]
Q[7:0]
Q[15:8]
Q[23:16]
P[7:0]
P[15:8]
P[23:16]
FC[7:0]
FC[15:8]
Reserved
NCO 2 frequency
tuning word
Default
0x18
0x00
0x00
0x00
0x01
SUMSCALE[7:0]
NCO 1 frequency
tuning word
Frequency update
Hardware version
Interface
configuration
Data control
DCO frequency
Internal clock
phase adjust
Parameter update
Channel 0 gain
Channel 1 gain
Channel 2 gain
Channel 3 gain
Spectrum shaping
Bit 4
Bit 3
LNG_INST
SATCNT[7:0]
VER[3:0]
CHANPRI
PAR[1:0]
LTNCY[2:0]
ONES[3:0]
SNCPHZ[3:0]
0x20
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x00
0x00
0x80
0x00
0x00
0x00
0x03
0xC8
0x61
0x1F
0x85
SPEC_INV
0x00
0x80
0x80
0x80
0x80
0x00
AD9789
Addr
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x50
0x51
0x52
0x53
0x54
0x55
Register Name
Mu Delay
Control 1
Mu control duty
cycle
Clock Receiver 1
Clock Receiver 2
Mu Delay
Control 2
Reserved
Reserved
DAC bias
Reserved
DAC decoder
Mu Delay
Control 3
Mu Delay
Control 4
Reserved
Full-Scale
Current 1
Full-Scale
Current 2
Phase detector
control
Reserved
BIST control
BIST status
BIST zero
padding length
Bit 7
SEARCH_
TOL
Duty cycle
correct
enable
CLK_DIS
MU_CLKDIS
Bit 6
SEARCH_ERR
Bit 5
TRACK_
ERR
BIST Signature 1
Bit 2
Bit 1
GUARDBAND[4:0]
Bit 0
MANUAL_ADJ[5:0]
(Factory test only)
CLKN_CML[3:0]
Reserved
PSIGN
SLOPE
MODE[1:0]
NSIGN
MU_EN
MSEL[1:0]
DAC decoder mode
SEARCH_DIR[1:0]
MUPHZ[4:0]
Reserved
CMP_BST
CLKSHDN
BDONE
INPUTSEL
Reserved
S0ENABL
S1ENABL
BCLKDIV[3:0]
S0RDEN
S0PRNG
S0CLKDIV[3:0]
S1RDEN
S1PRNG
S1CLKDIV[3:0]
0xF0
0x3F
0x42
0x00
0xCA
0x03
0x00
0x00
0x40
MUDLY[8:1]
0x00
Reserved
FSC[7:0]
0x00
0x00
Reserved
PHZ_PD
Default
0x0B
0x40
Reserved
CLKP_CML[3:0]
MUSAMP
GAIN[1:0]
Reserved
Reserved
Reserved
Reserved
Reserved
BIST vector
length
BIST clock adjust
Sign 0 control
Sign 0 clock
adjust
Sign 1 control
Sign 1 clock
adjust
RegFnl0Freq
RegFnl1Freq
BIST Signature 0
Bit 3
INC_DEC
(Factory)
PDBIAS
MUDLY[0]
Bit 4
FSC[9:8]
AUTO_CAL
PHZ_DET_BIAS[3:0]
Reserved
BENABLE
BSTATUS[6:0]
PADLEN[7:0]
PADLEN[15:8]
VECTLEN[7:0]
VECTLEN[15:8]
VECTLEN[23:16]
S0ZERO
S0NEG
S1ZERO
S1NEG
Final Rate/Offset Control 0 [7:0]
Final Rate/Offset Control 1 [7:0]
SGN0[7:0]
SGN0[15:8]
SGN0[23:16]
SGN1[7:0]
SGN1[15:8]
SGN1[23:16]
Rev. A | Page 28 of 76
0x02
0x18
BCLKPHZ[3:0]
S0FNLCH
S0SEL[1:0]
S0CLKPHZ[3:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
S1FNLCH
S1SEL[1:0]
S1CLKPHZ[3:0]
0x00
0x00
BMODE[3:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9789
SPI REGISTER DESCRIPTIONS
Table 12. SPI Control Register (Address 0x00)
Bit
7
Bit Name
SDIO_DIR
6
LSBFIRST
5
RESET
4
[3:0]
LNG_INST
Description
This bit configures the SDIO pin as an input-only pin or as a bidirectional input/output pin. Both choices conform
to the SPI standard.
0 = input only.
1 = bidirectional (input/output).
This bit configures the SPI interface for MSB first or LSB first mode. Both choices conform to the SPI standard.
0 = MSB first.
1 = LSB first.
When set to 1, this bit resets the part. After the part is reset, 0 is written to this bit on the next cycle.
0 = no reset.
1 = software reset.
This bit sets the SPI to long instruction mode; 1 is the only valid value.
These bits should mirror Bits[7:4]. Bit 3 should mirror Bit 4, Bit 2 should mirror Bit 5, Bit 1 should mirror Bit 6, and
Bit 0 should mirror Bit 7.
Table 13. Saturation Counter Register (Address 0x01)
Bit
[7:0]
Bit Name
SATCNT[7:0]
Description
This read-only register contains the saturation counter. This register reflects the number of samples at the output of
the SUMSCALE gain block that overrange the datapath and are digitally clipped. The count is cleared by writing
a 1 to Register 0x04, Bit 1.
Table 14. Parity Counter Register (Address 0x02)
Bit
[7:0]
Bit Name
PARCNT[7:0]
Description
This read-only register contains the input data parity error counter. The count is cleared by writing a 1 to
Register 0x04, Bit 7.
Table 15. Interrupt Enable Register (Address 0x03)
Bit
7
Name
PARERR
6
BISTDONE
5
PARMSET
4
PARMCLR
3
LOCKACQ
2
LOCKLOST
1
SATERR
0
Reserved
Description
Setting this bit to 1 enables a PARERR flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 7 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a BISTDONE flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 6 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a PARMS_SET flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 5 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a PARMS_CLR flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 4 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a LOCKACQ flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 3 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a LOCKLOST flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 2 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a SATERR (overflow into 16× interpolator) flag to generate an interrupt request.
Generating an interrupt request results in Interrupt Bit 1 being set in Register 0x04 and the IRQ pin going low.
Reserved.
Rev. A | Page 29 of 76
AD9789
Table 16. Interrupt Status/Clear Register (Address 0x04)
Bit
7
6
5
Name
PARERR
BISTDONE
PARMSET
4
PARMCLR
3
2
LOCKACQ
LOCKLOST
1
SATERR
0
Reserved
Description
If this bit is set to 1, one or more parity errors has occurred. Writing a 1 to this bit clears the interrupt.
If this bit is set to 1, the BIST has reached the terminal state. Writing a 1 to this bit clears the interrupt.
If this bit is set to 1, the parameter update register (Address 0x24) has been updated. Writing a 1 to this bit clears
the interrupt.
If this bit is set to 1, the parameter update register (Address 0x24) has been cleared. Writing a 1 to this bit clears
the interrupt.
If this bit is set to 1, proper data handoff between the digital engine and the DAC core is occurring.
If this bit is set to 1, proper data handoff between the digital engine and the DAC core has been lost. Writing a 1
to this bit clears the interrupt.
If this bit is set to 1, one or more saturation errors (overflow into 16× interpolator) has occurred. Writing a 1 to
this bit clears the interrupt.
Reserved.
Table 17. Channel Enable Register (Address 0x05)
Bit
[7:4]
[3:0]
Bit Name
Reserved
CHANEN[3:0]
Description
Reserved.
A Logic 1 in any bit position enables the corresponding channel; 0000 means that all channels are disabled.
Setting
Channels Enabled
0000
All channels disabled.
0001
Channel 0 enabled.
0010
Channel 1 enabled.
0011
Channel 0 and Channel 1 enabled.
…
…
1110
Channel 1, Channel 2, and Channel 3 enabled.
1111
All channels enabled.
Table 18. Bypass Register (Address 0x06)
Bit
7
6
5
[4:0]
Bit Name
QAM
SRRC
Reserved
INT[4:0]
Description
If this bit is set to 1, the QAM mappers are bypassed.
If this bit is set to 1, the square root raised cosine (SRRC) filters are bypassed.
Reserved.
A Logic 1 in any bit position bypasses the corresponding interpolation filter. The preferred order for bypassing
interpolation filters is to first bypass Filter 0, then Filter 1, and so on.
Setting
Interpolation Filters Bypassed
00000
All interpolation filters enabled.
00001
Interpolation Filter 0 bypassed.
00010
Interpolation Filter 1 bypassed.
00011
Interpolation Filter 0 and Interpolation Filter 1 bypassed.
…
…
01111
Interpolation Filter 0, Interpolation Filter 1, Interpolation Filter 2, and Interpolation Filter 3
bypassed.
…
…
11111
All interpolation filters bypassed.
Rev. A | Page 30 of 76
AD9789
Table 19. QAM/SRRC Configuration Register (Address 0x07)
Bit
[7:6]
[5:4]
Bit Name
Reserved
ALPHA[1:0]
3
[2:0]
Reserved
MAPPING[2:0]
Description
Reserved.
These bits set the SRRC filter alpha.
Setting
Alpha Filter
00
0.12
01
0.18
10
0.15
11
0.13
Reserved.
These bits set the QAM encoding.
Setting
QAM Encoding
000
DOCSIS 64-QAM
001
DOCSIS 256-QAM
010
DVB-C 16-QAM
011
DVB-C 32-QAM
100
DVB-C 64-QAM
101
DVB-C 128-QAM
110
DVB-C 256-QAM
111
Unused
Table 20. Summing Node Scalar Register (Address 0x08)
Bit
[7:0]
Bit Name
SUMSCALE[7:0]
Description
This register sets the value of the 2.6 multiplier that is applied to the output of the channel summing node.
Setting
2.6 Multiplier
00000000
0
00000001
0.015625
00000010
0.03125
…
…
00001101
0.203125 (default)
…
…
11111110
3.96875
11111111
3.984375
Table 21. Input Scalar Register (Address 0x09)
Bit
[7:0]
Bit Name
INSCALE[7:0]
Description
This register sets the value of the 3.5 multiplier that is applied to the input data. This scaling block is in parallel
with the QAM encoder block and is used when the QAM encoder block is bypassed.
Setting
3.5 Multiplier
00000000
0
00000001
0.03125
00000010
0.0625
…
…
00100000
1 (default)
…
…
11111110
7.9375
11111111
7.96875
Rev. A | Page 31 of 76
AD9789
The three NCO 0 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 0. For more information
about programming these registers, see the Baseband Digital Upconverter section.
Table 22. NCO 0 Frequency Tuning Word Registers (Address 0x0A to Address 0x0C)
Address
0x0A
0x0B
0x0C
Bit Name
FTW0[7:0]
FTW0[15:8]
FTW0[23:16]
Description
Frequency tuning word for NCO 0, Bits[7:0]
Frequency tuning word for NCO 0, Bits[15:8]
Frequency tuning word for NCO 0, Bits[23:16]
The three NCO 1 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 1. For more information
about programming these registers, see the Baseband Digital Upconverter section.
Table 23. NCO 1 Frequency Tuning Word Registers (Address 0x0D to Address 0x0F)
Address
0x0D
0x0E
0x0F
Bit Name
FTW1[7:0]
FTW1[15:8]
FTW1[23:16]
Description
Frequency tuning word for NCO 1, Bits[7:0]
Frequency tuning word for NCO 1, Bits[15:8]
Frequency tuning word for NCO 1, Bits[23:16]
The three NCO 2 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 2. For more information
about programming these registers, see the Baseband Digital Upconverter section.
Table 24. NCO 2 Frequency Tuning Word Registers (Address 0x10 to Address 0x12)
Address
0x10
0x11
0x12
Bit Name
FTW2[7:0]
FTW2[15:8]
FTW2[23:16]
Description
Frequency tuning word for NCO 2, Bits[7:0]
Frequency tuning word for NCO 2, Bits[15:8]
Frequency tuning word for NCO 2, Bits[23:16]
The three NCO 3 frequency tuning word registers together compose the 24-bit frequency tuning word for NCO 3. For more information
about programming these registers, see the Baseband Digital Upconverter section.
Table 25. NCO 3 Frequency Tuning Word Registers (Address 0x13 to Address 0x15)
Address
0x13
0x14
0x15
Bit Name
FTW3[7:0]
FTW3[15:8]
FTW3[23:16]
Description
Frequency tuning word for NCO 3, Bits[7:0]
Frequency tuning word for NCO 3, Bits[15:8]
Frequency tuning word for NCO 3, Bits[23:16]
The three rate converter denominator (Q) registers together compose the 24-bit denominator for the rate converter decimation ratio. For
more information about programming these registers, see the Sample Rate Converter section.
Table 26. Rate Converter Denominator (Q) Registers (Address 0x16 to Address 0x18)
Address
0x16
0x17
0x18
Bit Name
Q[7:0]
Q[15:8]
Q[23:16]
Description
Rate converter denominator, Bits[7:0]
Rate converter denominator, Bits[15:8]
Rate converter denominator, Bits[23:16]
The three rate converter numerator (P) registers together compose the 24-bit numerator for the rate converter decimation ratio. For more
information about programming these registers, see the Sample Rate Converter section.
Table 27. Rate Converter Numerator (P) Registers (Address 0x19 to Address 0x1B)
Address
0x19
0x1A
0x1B
Bit Name
P[7:0]
P[15:8]
P[23:16]
Description
Rate converter numerator, Bits[7:0]
Rate converter numerator, Bits[15:8]
Rate converter numerator, Bits[23:16]
Rev. A | Page 32 of 76
AD9789
The two interpolating BPF center frequency registers together compose the 16-bit center frequency of the 16× band-pass interpolation
filter. For more information about programming these registers, see the Digital 16× Tunable Band-Pass Filter section.
Table 28. Interpolating BPF Center Frequency Registers (Address 0x1C and Address 0x1D)
Address
0x1C
0x1D
Bit Name
FC[7:0]
FC[15:8]
Description
Center frequency, Bits[7:0]
Center frequency, Bits[15:8]
Table 29. Frequency Update Register (Address 0x1E)
Bit
7
Name
FREQNEW
[6:0]
Reserved
Description
Setting this bit to 1 updates the derived registers in the AD9789. This bit must be set for changes to Register 0x16
through Register 0x1D to take effect. This self-clearing bit is reset to 0 after the derived registers are updated.
Reserved.
Table 30. Hardware Version Register (Address 0x1F)
Bit
[7:4]
[3:0]
Name
Reserved
VER[3:0]
Description
Reserved.
This read-only register indicates the version of the chip (0011).
Table 31. Interface Configuration Register (Address 0x20)
Bit
7
6
5
4
3
Bit Name
CMOS_BUS
CMOS_CTRL
Reserved
DCO_INV
IF_MODE
2
CHANPRI
[1:0]
PAR[1:0]
Description
This bit reflects the state of the CMOS_BUS pin (L14).
This bit reflects the state of the CMOS_CTRL pin (M14).
Reserved.
When set to 1, the DCO pin is inverted.
This bit sets the data interface mode.
0 = channelizer mode. Supports all available interface widths and 8- and 16-bit word widths. Supports maximum
fBAUD of fDAC/48.
1 = quadrature digital upconverter (QDUC) mode. Supports 32-bit interface, 16-bit word mode only. Supports
maximum fBAUD of fDAC/16.
This bit selects the channel prioritization value (used in channelizer mode only).
0 = device expects input samples only for those channels that are enabled.
1 = device expects data for all four channels. Data for disabled channels is expected and must be sent, but this
data is discarded by the AD9789.
These bits set the parity checking. For more information, see the Parity section.
Setting
Parity Checking
00
Parity checking deactivated
01
IQ parity (a value of 0 is expected on the I channel and a value of 1 is expected on the
Q channel)
10
Even parity
11
Odd parity
Rev. A | Page 33 of 76
AD9789
Table 32. Data Control Register (Address 0x21)
Bit
7
Bit Name
BIN
[6:5]
BUSWDTH[1:0]
4
DATWDTH
3
CMPLX
[2:0]
LTNCY[2:0]
Description
This bit selects the coding for the device.
0 = twos complement coding.
1 = straight binary coding.
These bits set the input data bus width for the device.
Setting
Input Bus Width
00
4 bits
01
8 bits
10
16 bits
11
32 bits
This bit sets the data-word width that is sent to the datapaths.
0 = 8-bit data-word.
1 = 16-bit data-word.
This bit configures the datapath for real or complex data.
0 = real data.
1 = complex data.
These bits set the turnaround latency from the FS pulse to the internal data sampling time. For more information,
see the Latency Register section.
Setting
Latency
000
Input data begins to be sampled at approximately the first rising edge of DCO after FS
goes low.
001
Input data begins to be sampled at approximately the second rising edge of DCO after
FS goes low.
…
…
111
Input data begins to be sampled at approximately the eighth rising edge of DCO after
FS goes low.
Table 33. DCO Frequency Register (Address 0x22)
Bit
7
[6:4]
Bit Name
Reserved
DCODIV[2:0]
[3:0]
ONES[3:0]
Description
Reserved.
These bits configure the data clock output (DCO) frequency.
Setting
DCO Clock Frequency
000
DCO clock disabled
001
fDACCLK/16
010
fDACCLK/32
011
Invalid
100
fDACCLK/64
101
Invalid
11x
Invalid
These bits always read back 1111.
Rev. A | Page 34 of 76
AD9789
Table 34. Internal Clock Phase Adjust Register (Address 0x23)
Bit
[7:4]
Bit Name
DSCPHZ[3:0]
[3:0]
SNCPHZ[3:0]
Description
The data sampling clock (DSC) is an internal clock that is used to sample the input data. This clock can occur on
1 of 16 phases to optimize the setup and hold timing of the data interface.
Setting
Selected Phase
0000
Earliest clock phase
0001
Second earliest clock phase that occurs 1/16 of a DSC cycle later
…
…
1111
Last available clock phase
The synchronization clock (SNC) is an internal clock that is used to synchronize the digital datapath clock with
the DAC clock. This clock can occur on 1 of 16 phases to optimize the DAC-to-datapath timing.
Setting
Selected Phase
0000
Earliest clock phase
0001
Second earliest clock phase that occurs 1/16 of a DSC cycle later
…
…
1111
Last available clock phase
Table 35. Parameter Update Register (Address 0x24)
Bit
7
Name
PARMNEW
[6:0]
Reserved
Description
This bit must transition from 0 to 1 for changes to Register 0x22 and Register 0x23 to take effect. Assuming that
this bit was previously set to 0, writing a 1 to this bit causes the readback value of the bit to reflect the state of
the chip. (The state of the chip is updated very quickly; for this reason, users with slow SPI implementations may
never read back a 0 after an update.)
0 = values have not been updated.
1 = values have been updated.
Reserved.
Table 36. Channel Gain Registers (Address 0x25 to Address 0x28)
Address
0x25
0x26
0x27
0x28
Register Name
Channel 0 gain
Channel 1 gain
Channel 2 gain
Channel 3 gain
Bit Name
CHAN0GAIN[7:0]
CHAN1GAIN[7:0]
CHAN2GAIN[7:0]
CHAN3GAIN[7:0]
Description
These registers configure a value for the 1.7 multiplier applied to each individual
channel just prior to the SUMSCALE block. The range of the channel gain is 0 to
1.9921875 with a step size of 0.0078125. To mute an individual channel, set the
scale factor to 0.
Setting
Channel Gain
00000000
0
00000001
0.0078125
…
…
11111111
1.9921875
Table 37. Spectrum Shaping Register (Address 0x29)
Bit
[7:1]
0
Name
Reserved
SPEC_INV
Description
Reserved.
Setting this bit to 1 spectrally inverts the signal, effectively multiplying the Q data by −1.
Rev. A | Page 35 of 76
AD9789
Table 38. Mu Delay Control 1 Register (Address 0x2F)
Bit
7
Bit Name
SEARCH_TOL
6
SEARCH_ERR
5
TRACK_ERR
[4:0]
GUARDBAND[4:0]
Description
This bit specifies the accuracy of the phase search. The optimal value for this bit is 1.
0 = not exact: the search can find a phase within two values of the desired phase.
1 = exact: the search finds the exact phase specified.
This bit configures the search behavior when an error is encountered.
0 = stop on error.
1 = retry on error.
This bit configures the track behavior if the controller does not find the desired phase. The optimal value for
this bit is 0.
0 = continue on error.
1 = reset on error.
These bits set the guard band value. The guard band is defined as follows:
GUARDBAND[4:0] × 8 = number of mu delay codes of guard band from the endpoints
If the search mode is alternating, the search proceeds in both directions until the guard band is reached in one
direction. When the guard band is reached, the search continues only in the opposite direction. If the desired
phase is not found before the guard band is reached in the second direction, the search reverts to the alternating
mode and continues looking within the guard band. The search fails if the mu delay reaches the endpoints.
For more information, see the Mu Delay Controller section.
Setting
Guard Band
00000
0
…
…
01011
11 (default)
…
…
11111
31
Table 39. Mu Control Duty Cycle Register (Address 0x30)
Bit
7
Bit Name
Duty cycle
correct enable
6
[5:0]
INC_DEC
MANUAL_ADJ[5:0]
Description
Setting this bit to 1 turns on the mu control duty cycle correction circuitry. Turn on this function before
enabling the mu controller. Along with the phase comparator boost (enabled in Register 0x3E[5]), this
function allows for more robust operation of the mu controller over the entire operating speed of the part.
Reserved (factory use only).
Reserved (factory use only).
Table 40. Clock Receiver 1 Register (Address 0x31)
Bit
[7:4]
Bit Name
CLKN_CML[3:0]
[3:0]
Reserved
Description
These bits adjust the common-mode level at the CLKN pin. The recommended value for these bits and the
CLKP_CML[3:0] bits is 0xF. For more information, see the Optimizing the Clock Common-Mode Voltage section.
Reserved.
Table 41. Clock Receiver 2 Register (Address 0x32)
Bit
7
Bit Name
CLK_DIS
6
5
Reserved
PSIGN
[4:1]
CLKP_CML[3:0]
0
NSIGN
Description
This bit disables or enables the clock receiver. When the AD9789 powers up, this bit is set to 0 to prevent
severe output noise that occurs on power-up with no clock. When the DAC clock is stable, set this bit to 1.
0 = disabled.
1 = enabled.
Reserved (factory use only; leave at default value).
This bit specifies the sign for the CLKP_CML bits.
0 = negative (recommended).
1 = positive.
These bits adjust the common-mode level at the CLKP pin. The recommended value for these bits and the
CLKN_CML[3:0] bits is 0xF. For more information, see the Optimizing the Clock Common-Mode Voltage section.
This bit specifies the sign for the CLKN_CML bits.
0 = negative (recommended).
1 = positive.
Rev. A | Page 36 of 76
AD9789
Table 42. Mu Delay Control 2 Register (Address 0x33)
Bit
7
Bit Name
MU_CLKDIS
6
SLOPE
[5:4]
MODE[1:0]
3
MUSAMP
[2:1]
GAIN[1:0]
0
MU_EN
Description
This bit disables or enables the clock to the mu delay controller.
0 = enabled.
1 = disabled.
This bit configures the desired slope for the phase measurement of the mu delay. When the desired phase is
measured, the slope of the phase measurement is calculated and compared to the value of this bit. For optimal
ac performance, the best setting for the search is a positive slope and a phase value of 14.
0 = negative.
1 = positive.
These bits configure the mode of operation for the mu controller.
00 = search and track (recommended).
01 = track only.
10 = search only.
11 = invalid.
Transitioning this bit from 0 to 1 enables the user to read back the mu delay value that the controller locked to
(the MUDLY bits in Register 0x39 and Register 0x3A), as well as the phase that it locked to (the MUPHZ bits in
Register 0x39).
0 = no action.
1 = transition from 0 to 1 captures the readback of the mu controller phase and delay.
These bits set the tracking rate of the mu controller.
00 = slowest tracking.
01 = nominal tracking (recommended).
10 = fastest tracking.
11 = invalid (do not use).
This bit enables or disables the mu controller. Before enabling the mu controller, turn on both the phase
comparator boost (Register 0x3E[5]) and the mu control duty cycle correction circuitry (Register 0x30[7]). Both
of these functions allow for more robust operation of the mu controller over the entire operating speed of the
part.
0 = mu controller off (manual mode).
1 = mu controller on (auto mode).
Table 43. DAC Bias Register (Address 0x36)
Bit
7
[6:2]
[1:0]
Bit Name
PDBIAS
Reserved
MSEL[1:0]
Description
Setting this bit to 1 powers down the DAC circuitry.
Reserved.
These bits set the mirror roll-off frequency control, which can be used to adjust the noise contribution of the
internal current mirror to optimize the 1/f noise.
00 = bypass the mirror roll-off frequency control.
01 = narrowest bandwidth.
10 = medium bandwidth.
11 = widest bandwidth.
Table 44. DAC Decoder Register (Address 0x38)
Bit
[7:2]
[1:0]
Bit Name
Reserved
DAC decoder
mode
Description
Reserved.
These bits set the decoder mode for the DAC. It is recommended that normal mode (the default) be used.
00 = normal mode.
01 = return to zero mode.
10 = mix mode.
11 = invalid.
Rev. A | Page 37 of 76
AD9789
Table 45. Mu Delay Control 3 Register (Address 0x39)
Bit
7
Bit Name
MUDLY[0]
[6:5]
SEARCH_DIR[1:0]
[4:0]
MUPHZ[4:0]
Description
This bit is the LSB of the mu delay value. Along with Bits[7:0] in Register 0x3A, this bit configures the
programmable mu delay; the search algorithm begins at this specified mu delay value. In manual mode, the
MUDLY bits can be written to. In tracking mode, the sampled MUDLY value can be read back. Even though
there are 9 bits of resolution for this delay line value, the maximum allowable mu delay is 431 (0x1AF). The
optimal point to begin the search is in the middle of the delay line, or approximately 216 (0xD8).
These bits configure the search direction, starting at the selected mu delay value.
00 = search down.
01 = search up.
10 = search up and down (optimal).
11 = invalid.
These bits specify the phase to be measured with the maximum allowable phase being 16 (10000). If a value
larger than 16 is loaded, the controller will not lock. When the desired phase is measured, the slope of the
phase measurement is calculated and compared to the configured slope, which is specified by the SLOPE bit
in Register 0x33[6]. For optimal ac performance, the best setting for the search is for a positive slope and a
phase value of 14 (01110).
Table 46. Mu Delay Control 4 Register (Address 0x3A)
Bit
[7:0]
Bit Name
MUDLY[8:1]
Description
Along with Bit 7 in Register 0x39, these bits configure the programmable mu delay; the search algorithm
begins at this specified mu delay value. In manual mode, the MUDLY bits can be written to. In tracking mode,
the sampled MUDLY value can be read back. Even though there are 9 bits of resolution for this delay line
value, the maximum allowable mu delay is 431 (0x1AF). The optimal point to begin the search is in the
middle of the delay line, or approximately 216 (0xD8).
Table 47. Full-Scale Current 1 Register (Address 0x3C)
Bit
[7:0]
Bit Name
FSC[7:0]
Description
Along with Bits[1:0] in Register 0x3D, this register sets the full-scale current for the DAC. For more information,
see the Voltage Reference section.
Setting (Includes Register 0x3D[1:0])
Full-Scale Current (mA)
0000000000
8.6
…
…
1000000000
20 (default)
…
…
1011010000
25
…
…
1111111111
32.1
Table 48. Full-Scale Current 2 Register (Address 0x3D)
Bit
[7:2]
[1:0]
Bit Name
Reserved
FSC[9:8]
Description
Reserved.
Along with the FSC[7:0] bits in Register 0x3C, these bits set the full-scale current for the DAC. For more information, see Table 47 and the Voltage Reference section.
Table 49. Phase Detector Control Register (Address 0x3E)
Bit
7
6
5
4
[3:0]
Bit Name
PHZ_PD
Reserved
CMP_BST
AUTO_CAL
PHZ_DET_BIAS[3:0]
Description
Powers down the phase detector. This bit is for factory use only; this bit should be set to 0.
Reserved.
Comparator boost. This bit is for factory use only; this bit should always be set to 1.
This bit is for factory use only; this bit should always be set to 1.
These bits display the binary weighted current. Do not write to these bits (factory use only).
Rev. A | Page 38 of 76
AD9789
THEORY OF OPERATION
QAM Encoder
The QAM encoder supports seven different standards-compliant
mappings. (For illustrations of the supported mappings, see the
QAM Constellation Maps section.) The QAM encoder receives
input data-words of 8 bits in width and maps them into 16, 32,
64, 128, or 256 point constellations. It outputs 5-bit complex
QAM modulated samples. The mode in which the QAM
encoder runs is selected via the QAM/SRRC configuration
register (Register 0x07[2:0]).
5
FROM INPUT
INTERFACE
CMOS
16 TO 31
LVDS
FALL
FS
16×
INTERPOLATOR
AND BPF
+ SCALARS
QAM/
DATA FILTER/
NCO
QAM/
DATA FILTER/
NCO
SPI
5
I
Q
Table 50 lists the available QAM mapper modes along with the
corresponding input bits and output range. The operation of the
QAM encoder when configured in DOCSIS 64-QAM mode is
described in this section. The operation of the QAM encoder in
the other modes is conceptually the same; only the input data
bit encoding and scale factors are different.
QAM/
DATA FILTER/
NCO
QAM/
DATA FILTER/
NCO
QAM
ENCODER
Figure 72. QAM Encoder I/O
14-BIT
2.4GSPS
DAC
IRQ RS
The DOCSIS 64-QAM constellation diagram is shown in
Figure 73. The constellation diagram shows how the QAM
encoder input is mapped into the QAM constellation. For
example, an input data-word of 111111 maps to the constellation
point in the upper right corner of the 64-QAM constellation.
07852-099
DCO
CMOS
0 TO 15
LVDS
RISE
RETIMER
DATA FORMATTER/ASSEMBLER
32 INPUT
PINS
AND
2 PARITY
PINS
150MHz LVDS/CMOS
Control of the AD9789 functions is via a serial peripheral
interface (SPI).
8
07852-056
The AD9789 is a flexible digital signal processing (DSP) engine
combined with a high performance, 2400 MSPS, 14-bit DAC
(Figure 70). The DSP blocks include a QAM encoder, a 2×
upsampling square root raised cosine (SRRC) filter, selectable
interpolation from 16× to 512×, a rate converter, and a complex
modulator. The digital interface can accept up to four channels
of complex data. The QAM encoder supports constellation sizes
of 16, 32, 64, 128, and 256. The on-chip rate converter allows
fine resolution of baud rates with a fixed DAC sampling clock.
The digital upconverters can place the input signals from dc to
0.5 × fDAC. An analog mix mode extends the output spectrum
into the second and third DAC Nyquist zones.
Figure 70. Top Level Functional Block Diagram
DATAPATH SIGNAL PROCESSING
The DSP blocks included on the AD9789 can be grouped into
two sections. The first is the datapath signal processing. Four
identical datapaths, or channels, can be used. A block diagram
of a single channel is shown in Figure 71. Enabling and disabling
each DSP block within the datapath takes effect on all channels.
There is independent control of the scaling and the frequency
placement of each channel.
SRRC
110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111
110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010
100,111 101,011 000,111 001,011 000,101 001,111 010,101 011,111
100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010
2
2N
(N = 0 TO 5)
INSCALE
C5 C4 C3, C2 C1 C0
24-BIT NCO
0 TO fDAC /16
RATE
CONVERTER
P/Q 24-BIT
I
010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101
(P/Q = 0.5 TO 1)
BYPASS
QAM
BYPASS
SRRC
CH GAIN
0× TO 2×
07852-129
QAM
MAPPER
Q
Figure 71. Datapath Block Diagram
010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110
110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101
The following sections describe each of the DSP blocks
included in the datapath.
07852-057
110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110
Figure 73. DOCSIS 64-QAM Constellation
Rev. A | Page 39 of 76
AD9789
Table 50. QAM Mapper Input and Output Range vs. Mode
ITU-T J.83
Annex
B
B
A
A
A and C
A and C
A and C
Bit Range
at Output
−14 to +14
−15 to +15
−15 to +15
−15 to +15
−14 to +14
−11 to +11
−15 to +15
Input Bits
B7 B6 B5 B4 B3 B2 B1 B01
X X C5 C4 C3 C2 C1 C0
C7 C6 C5 C4 C3 C2 C1 C0
X X X X C3 C2 C1 C0
X X X C4 C3 C2 C1 C0
X X C5 C4 C3 C2 C1 C0
X C6 C5 C4 C3 C2 C1 C0
C7 C6 C5 C4 C3 C2 C1 C0
X = don’t care.
Each constellation point corresponds to an I and Q coordinate
pair, as shown in Figure 74. In the figure, two symbols are highlighted in a 64-QAM constellation: I = 14, Q = 14 (Pair 1) and
I = 6, Q = −10 (Pair 2).
To represent the I and Q coordinate points, 5-bit, twos complement numbers are used. For example, an input of 011101
into the QAM encoder maps to the I = 6, Q = −10 position of
the QAM-64 constellation and results in output samples of
I = 00110, Q = 10110.
SYMBOL I = 14, Q = 14
I = 01110, Q = 01110
Q
14
Input Scalar
The input scalar block is active only when the QAM mapper
is bypassed. The value of INSCALE[7:0] is programmed in
Register 0x09[7:0]. The scale factor applied to the input data
is calculated as follows:
ScaleFactor 
INSCALE[7:0]
32
This factor provides a scaling range of the input data from 0 to
7.96875 in steps of 0.03125. The default value of 0x20 provides a
scale factor of 1. As shown in Figure 76, the output of the input
scalar block is rounded to the nearest 16-bit value. If the output
exceeds the maximum or minimum value, it is clipped to either
positive or negative full scale (0x7FFF or 0x8000).
10
ROUND
SATURATE
6
8
INSCALE
2
–14
–10
–6
–2
2
6
10
14
Figure 76. Input Scalar Block Diagram
I
–2
SRRC Filter
The square root raised cosine (SRRC) filter performs a 2×
interpolation and filtering operation on the input data. The
SRRC filter has a pass band, transition band, and stop band
requirement as per the DOCSIS, Euro-DOCSIS, and DVB-C
standards.
–6
–10
07852-058
–14
SYMBOL I = 6, Q = –10
I = 00110, Q = 10110
Figure 74. I and Q Symbol Mapping
8
16
QAM
MAPPER
X
5
The SRRC filter accepts only five bits at its input and can be
bypassed (Register 0x06[6]). If the SRRC filter is the first block
enabled in the datapath, these five bits are the five MSBs of the
8-bit data-word.
SRRC
5
16
16
16
2
To cover all the standards, the value of alpha can be set to 0.12,
0.13, 0.15, or 0.18. This value is programmed in Register 0x07[5:4].
The frequency, fN, is determined by the input data baud rate.
The response of the SRRC filter is illustrated in Figure 77.
BYPASS
QAM
BYPASS
SRRC
07852-059
16
INSCALE
07852-100
1
SPI Register 0x07,
MAPPING[2:0] Bits
000
001
010
011
100
101
110
111
Description
DOCSIS 64-QAM
DOCSIS 256-QAM
DVB-C 16-QAM
DVB-C 32-QAM
DVB-C 64-QAM
DVB-C 128-QAM
DVB-C 256-QAM
Unused
Figure 75. QAM Mapper and SRRC Filter Detail
(I and Q Paths Are Identical So Only One Is Shown)
Rev. A | Page 40 of 76
AD9789
10
0
–10
<0.4dB
FREQUENCY
–20
MAGNITUDE (dB)
<0.4dB
–3.01dB
<–43dB
–50
–60
(1 +α) fN
–80
–90
Figure 77. SRRC Filter Characteristics
–100
–2.0
If the SRRC filter is used, at least four of the 2× interpolation
filters must be enabled. The reason for this is that the SRRC
filter requires a minimum of 12 clock cycles at the fDAC/16 rate
per sample to function properly.
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY × fINPUT (Hz)
1.5
2.0
07852-103
fN
Figure 80. 2× Half-Band Interpolation Filter 1 Response
10
Half-Band Interpolation Filters
0
–10
–20
MAGNITUDE (dB)
The AD9789 can provide from 1× to 32× interpolation through
the datapath using five bypassable half-band interpolation filters.
The half-band interpolation filters are controlled via Register
0x06[4:0]. The preferred order in terms of power savings for
bypassing these filters is to bypass Filter 0 first, then Filter 1,
and so on. The frequency response of the low-pass filters is
shown in Figure 79 through Figure 82. All of the filters have a
pass band of 0.8 × fINPUT, where fINPUT is the data rate at the input
of each filter. The pass band is flat to within 0.01 dB for all
filters. The stop-band attenuation exceeds 85 dB in Filter 0,
Filter 1, and Filter 2, and 75 dB in Filter 3 and Filter 4.
2
–40
–70
07852-060
(1 –α) fN
–30
–30
–40
–50
–60
–70
–80
–90
–100
–2.0
–1.5
–1.0
0
–0.5
0
0.5
1.0
FREQUENCY × fINPUT (Hz)
1.5
2.0
07852-104
0dB
Figure 81. 2× Half-Band Interpolation Filter 2 Response
1
07852-101
10
BYPASS
REGISTER 0x06[4:0]
0
–10
Figure 78. Conceptual Block Diagram of 2× Half-Band Interpolation Filters
0
–10
–20
–30
–40
–50
–60
–80
–50
–100
–1.875
–70
–80
–1.250
–0.625
0
0.625
FREQUENCY × fINPUT (Hz)
1.250
1.875
07852-105
–90
–60
Figure 82. 2× Half-Band Interpolation Filter 3 and Filter 4 Response
–90
–100
–2.0
–30
–70
–40
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY × fINPUT (Hz)
1.5
2.0
07852-102
MAGNITUDE (dB)
–20
MAGNITUDE (dB)
10
Figure 79. 2× Half-Band Interpolation Filter 0 Response
Rev. A | Page 41 of 76
AD9789
Sample Rate Converter
Example
The purpose of the sample rate converter (SRC) is to provide
increased flexibility in the ratio of the input baud rate to the
DAC update rate. Each of the four channelization datapaths
contains a sample rate converter (SRC) that provides a data rate
conversion in the range of 0.5 to 1.0 inclusive. The rate conversion
factor is set by the ratio of two 24-bit values, P and Q. Figure 83
is a conceptual block diagram of the SRC. It can be thought of
as an interpolation block, followed by filtering and decimation
blocks.
A DOCSIS application has a master system clock that runs at a
frequency of fMASTER. Several channel baud rates are supported,
all of which are fractions of the master clock and can be
represented by the following equation:
Q
24
P
24
Q
07852-106
P
f BAUD =
f DAC = 224 × f MASTER = 2293.76 MHz
The values of P and Q are set by programming the P[23:0] and
Q[23:0] registers at Address 0x16 through Address 0x1B.
Denominator (Q)
Register 0x18
Register 0x17
Register 0x16
224 × f MASTER = I ×
P
× 16 × f BAUD
Q
(1)
P N 7
= ×
Q M 16
f BAUD =
P
≤ 1.0
Q
Q[23] = 1
(7)
401
× 10.24 MHz = 5.0569 MHz
812
(8)
P and Q can then be calculated from the numerator and
denominator of Equation 9.
P 812 7 5684 0 x1634
=
× =
=
Q 401 16 6416 0 x1910
The values of P and Q must be selected within the following
constraints:
0.5 ≤
(6)
Recall that N and M are given by the required baud rate. For
example, assume a baud rate of 5.0569 MHz, which results from
M = 401 and N = 812.
where I is the total interpolation ratio of the SRRC filter and the
five half-band interpolation filters.
If Equation 1 is satisfied, the long-term baud rate, fBAUD, is
exactly maintained. No residual frequency offset errors are
introduced by the rate conversion process.
P
M
× 16 × × f MASTER
Q
N
Enabling the SRRC filter and four of the half-band interpolation
filters would result in the total interpolation factor, I, being equal
to 32. Substituting 32 for I and simplifying Equation 6 results in
Equation 7.
The values of P and Q should be selected to satisfy the following
equation for the desired baud rate (fBAUD) and DAC clock frequency (fDAC).
f DAC = I ×
(5)
Inserting Equation 4 and Equation 5 into Equation 1 results in
Equation 6.
Table 51. Register Locations for Sample Rate Converter
Numerator (P)
Register 0x1B
Register 0x1A
Register 0x19
(4)
Equation 1 must be satisfied for fBAUD to be exactly maintained.
To facilitate this, the DAC sampling frequency is selected to be a
multiple of fMASTER that satisfies the signal bandwidth and output
frequency requirements. For fMASTER = 10.24 MHz, a signal bandwidth requirement of 32 MHz or greater, and a supported output
frequency band of up to 1 GHz, the following DAC sampling
frequency can be selected:
Figure 83. Conceptual Block Diagram of the Sample Rate Converter
Bits
[23:16] (Byte 2)
[15:8] (Byte 1)
[7:0] (Byte 0)
M
× f MASTER
N
(2)
(3)
Equation 3 states that the value of Q must be shifted so that the
MSB of Q is set.
In most systems, the baud rate is a given, and the DAC sample
rate is selected so that it is high enough to support the signal
bandwidth and output frequency requirements. In many cases,
it is desirable to set the DAC clock rate to a multiple of a system
clock rate. The following example shows how P and Q can be
selected in such a system.
(9)
Because the value of Q must be MSB justified, both numbers
can be shifted by 11 bits, resulting in the final P and Q values
of 0xB1A000 and 0xC80000, respectively.
Baseband Digital Upconverter
The digital upconverter enables each baseband channel to be
placed anywhere from dc to fDAC/16. The center frequency for
each of the four channels is register programmable through the
24-bit frequency tuning words, FTW 0 through FTW 3. For the
desired center frequency of each individual channel, the FTW
can be calculated as follows:
Rev. A | Page 42 of 76
FTW =
f CENTER
× (2 24 − 1)
⎛ f DAC ⎞
⎜
⎟
⎝ 16 ⎠
AD9789
Channel 0
Reg. 0x0C
Reg. 0x0B
Reg 0x0A
Channel 1
Reg. 0x0F
Reg. 0x0E
Reg 0x0D
Channel 2
Reg. 0x12
Reg. 0x11
Reg 0x10
Channel 3
Reg. 0x15
Reg. 0x14
Reg 0x13
DATAPATH
0
The FTW sets the frequency of the sine and cosine signals
generated by the numerically controlled oscillator (NCO).
The complex output from the NCO is multiplied by the input
datapath signal to modulate the signal to the desired output
frequency. A conceptual block diagram of the baseband digital
upconverter is shown in Figure 84.
Individual Channel Scalar
The last block in the datapath is an 8-bit scalar (Register 0x25 to
Register 0x28) intended for compensating out any sampling and
hardware roll-offs that may be encountered. The scale factor
applied to each channel is calculated as follows:
CHANxGAIN[7 :0]
128
The range of the channel gain is 0 to 1.9921875 with a step size
of 0.0078125. An individual channel can be easily and quickly
muted, if desired, by setting the scale factor to 0.
Table 53. Register Locations for Channel Gain Scalar
CHANxGAIN
[7:0]
Channel 0
Reg. 0x25
Channel 1
Reg. 0x26
DATAPATH
3
Channel 2
Reg. 0x27
Channel 3
Reg. 0x28
ScaleFactor =
fC
SUMSCALE[7 :0]
64
This factor provides a scaling range of the input data from 0 to
3.984375 with a step size of 0.015625. The default value of 0x0D
provides a scale factor of 0.203125. Note that when the channels
are summed, they are clipped at the output of the summing
junction scalar block if the value exceeds the maximum or
minimum full-scale value (0x7FFF or 0x8000). If the full 16-bit
range of each individual channel is used, the sum scalar should
be set to 0x10 (0.25) to avoid the possibility of clipping.
TO SATURATION COUNTER
SATERR
REGISTER 0x03[1]
ROUND
SATURATE
8
ROUND
SATURATE
SUMSCALE
REGISTER 0x08
07852-108
CHANxGAIN[7:0]
BPF
The summing junction scalar block operates on the sum of the
four channels. The value of SUMSCALE[7:0] is programmed in
Register 0x08. The scale factor applied to the data is calculated
as follows:
The default value of the channel gain provides a scale factor of
1. As shown in Figure 85, the output of the input scalar block is
rounded to the nearest 16-bit value. If the output exceeds the
maximum or minimum value, it is clipped to either positive or
negative full scale (0x7FFF or 0x8000).
8
SUM
SCALE
BPF
fC = 0 TO
fDAC/2
Summing Junction Scalar
Figure 84. Conceptual Block Diagram of the Baseband Digital Upconverter
ScaleFactor =
DATAPATH
2
Each block of the digital block upconverter is described in more
detail in the following sections.
07852-107
FTW NCO FREQUENCY
TUNING WORD
DATAPATH
1
Figure 86. Functional Block Diagram of the Digital Block Upconverter
SIN
COS
24
DIGITAL BLOCK
UPCONVERTER
Figure 85. Individual Channel Gain Control
07852-110
FTW
[23:16]
[15:8]
[7:0]
The second half of the DSP engine on the AD9789 combines the
outputs of the four datapaths into one block, scales the block of
channels, interpolates by 16× to the full DAC rate, and performs
a band-pass filter operation allowing the block of channels to be
placed anywhere in the Nyquist bandwidth of the DAC.
07852-109
Table 52. Register Locations of FTWs for Each Channel
DIGITAL BLOCK UPCONVERTER
16×
INTERPOLATOR
The calculated FTW for each channel should be entered into
the register locations listed in Table 52.
Figure 87. Block Diagram of the Summing Junction Scalar
In practice, the signal-to-noise ratio (SNR) of the channel can
be improved by increasing the sum scale factor and permitting
a small amount of clipping. The larger signal amplitude can
improve the SNR if the clipping is brief and infrequent.
Rev. A | Page 43 of 76
AD9789
should be taken to appropriately filter the desired signal with
the interpolation filters prior to the input of the BPF..
0
–20
MAGNITUDE (dB)
Table 54 shows recommended sum scale values for each QAM
mapper mode. The criteria used to determine the recommended
sum scale values were MER/EVM measurements and spectral
purity. Because clipping results in impulsive noise, it can be
observed in the output spectrum as a transient increase in the
output noise floor. These sum scale values were chosen such
that the transient increases in the noise floor were minimal.
These tests were completed for one, two, three, and four carrier
outputs at approximately 850 MHz. Because clipping can occur
in the RF chain following the DAC, further verification of these
values should be performed at the system level by adding BER
tests to the sum scale selection criteria.
–40
–60
–80
Table 54. Recommended Sum Scale Values for all QAM
Mapper Modes and Channel Count
54
34
26
20
54
34
26
20
80
50
38
30
54
34
26
20
54
34
26
20
54
34
26
20
0.5
1.0
1.5
FREQUENCY (GHz)
07852-062
1 Channel
48
0
2.0
Figure 89. Band-Pass Filter Response at 200 MHz, fDAC = 2.4 GHz
0
–20
MAGNITUDE (dB)
–40
–60
–80
Digital 16× Tunable Band-Pass Filter
–100
The digital band-pass filter works in conjunction with a fixed
16× interpolator (see Figure 88). The 16× interpolation filter
creates 16 images of the baseband signal in the Nyquist band
of the DAC. The digital band-pass filter must then be tuned to
reject the 15 undesired images. The center frequency of the
band-pass filter can be placed anywhere from dc to fDAC/2. The
tuning word for the band-pass filter center frequency can be
calculated as follows:


f CENTER
 216  1
f DAC
The resulting tuning word is a 16-bit value where the most
significant byte is written to Register 0x1D[7:0] and the least
significant byte is written to Register 0x1C[7:0].
0.5
1.0
1.5
FREQUENCY (GHz)
2.0
Figure 90. Band-Pass Filter Response at 1 GHz, fDAC = 2.4 GHz
0
–2
MAGNITUDE (dB)
BPF _ Center _ Freq 
0
07852-063
QAM
Mode
DVB-C
16-QAM
DVB-C
32-QAM
DVB-C
64-QAM
DVB-C
128-QAM
DVB-C
256-QAM
DOCSIS
64-QAM
DOCSIS
256-QAM
–100
Sum Scale Value (Decimal)
2 Channels
3 Channels
4 Channels
28
22
16
–4
–6
–8
–10
fC
0
07852-111
16
20
40
FREQUENCY (MHz)
60
80
Figure 91. Band-Pass Filter Pass-Band Detail, fDAC = 2.4 GHz
Figure 88. Conceptual Block Diagram of 16× Tunable Band-Pass Filter
The width of the filter’s stop band is fixed at approximately
fDAC/64. The effective FLAT pass band is fDAC/64. As can be
inferred from Figure 89 to Figure 91, mistuning of the BPF
center frequency can result in unwanted images appearing. Care
Rev. A | Page 44 of 76
07852-064
16
AD9789
fDAC
DIGITAL INTERFACE MODES
In QDUC mode (Register 0x20[3] = 1), the interface is fixed at
a 32-bit bus width and one channel of complex data. The available
signal processing methods are interpolation (16× to 512×), rate
conversion (0.5 to 1.0), and complex modulation. The maximum
baud rate supported in QDUC mode is fDAC/16.
In both channelizer and QDUC modes, the input data bus
can be configured to accept LVDS or CMOS data via the
CMOS_BUS pin (L14). If CMOS_BUS is pulled to 3.3 V, the
data bus is configured to accept CMOS inputs (D[31:0], P0,
and P1). If CMOS_BUS is pulled to 0 V, the bus is configured
to accept LVDS inputs (D[15:0]P, D[15:0]N, PARP, and PARN).
Two output signals are used to source data into the AD9789.
The first is the data clock output signal (DCO), which is
provided to clock data from the digital data source. DCO is a
divided-down version of DACCLK. The second is the frame sync
signal (FS), which is provided to request a new data-word. The
average frequency of the FS signal is equal to the symbol rate or
baud rate of the data. As with the input data bus, the DCO and
FS signals can be configured as LVDS or CMOS outputs via the
CMOS_CTRL pin (M14). If CMOS_CTRL is pulled to 3.3 V,
DCO and FS are output as CMOS signals on the P14 and N14
pins (CMOS_DCO and CMOS_FS), respectively. If CMOS_CTRL
is pulled to 0 V, DCO and FS are output as LVDS signals on the
N13, P13, L13, and M13 pins (DCOP, DCON, FSP, and FSN),
respectively.
Channelizer Mode
In channelizer mode, the digital interface has programmable
bus width, data width, and data format. The bus width, which is
the physical width of the digital data bus at the input of the
AD9789, can be set to a 4-, 8-, 16-, or 32-bit wide interface. The
data width, which is the internal width of the data at the input
to the digital datapath, can be set to an 8-bit or 16-bit word. The
data format can be programmed for real or complex data. A list
of supported interface modes is shown in Table 55.
FS
DCO
CLK
CTL
DATAUP TO
32 BITS PATH
2
UP TO DATA32 BITS PATH
3
fDAC
fDAC
DATAUP TO
32 BITS PATH
1
16
32
SUM
SCALE
16×
INTERPOLATOR
CMOS
16 TO 31
LVDS
FALL
DATAUP TO PATH
32 BITS
0
BPF
fC = 0 TO
fDAC/2
BPF
fC
Figure 92. Channelizer Mode
Table 55. Interface Configurations Supported
in Channelizer Mode
First Input
Block Enabled
QAM Encoder
SRRC Filter
Interpolation
Filter
Bus Width
Reg. 0x21[6:5]
32 bits
16 bits
8 bits
4 bits
32 bits
16 bits
8 bits
4 bits
32 bits
16 bits
8 bits
Data Width
Reg. 0x21[4]
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
16 bits
16 bits
16 bits
Data Format
Reg. 0x21[3]
Real
Real
Real
Real
Complex
Complex
Complex
Complex
Complex
Complex
Complex
If the QAM encoder is the first block enabled in the datapath,
the data width should be set to an 8-bit word and real data
format. If the SRRC filter is the first block enabled in the
datapath, the data width should be set to an 8-bit word and
complex data format. If both the QAM encoder and the SRRC
filters are bypassed, the data width should be set to a 16-bit
word and complex data format.
Pin Mapping in Channelizer Mode
In CMOS mode (CMOS_BUS and CMOS_CTRL pins = 3.3 V),
the various interface width options are mapped to the AD9789
input pins as shown in Table 56.
Table 56. CMOS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
Rev. A | Page 45 of 76
Pin Assignments
D[3:0]
D[7:0]
D[15:0]
D[31:0]
BUSWDTH[1:0]
00
01
10
11
07852-112
P0
P1
RETIMER
In channelizer mode (Register 0x20[3] = 0), the interface can be
configured for 4- to 32-bit bus widths and can accept up to four
channels of complex data. Any of the signal processing blocks in
the digital datapath can be used. The maximum baud rate
supported in channelizer mode is fDAC/48.
LVDS/CMOS
Channelizer mode
Quadrature digital upconverter (QDUC ) mode
32 INPUT
PINS
•
•
CMOS
0 TO 15
LVDS
RISE
PROGRAMMABLE DATA
FORMATTER/ASSEMBLER
The AD9789 can be configured for two main digital interface
modes of operation:
4 TO 32 BITS
16 TO 1024
AD9789
In LVDS mode, the various interface width options are mapped
to the AD9789 input pins as shown in Table 57. When the interface width is set to 32 bits in LVDS mode, the interface becomes
double data rate (DDR). In DDR mode, the first 16 bits are
sampled on the rising edge of the data sampling clock (DSC,
which is synchronous to DCO), and the second 16 bits are
sampled on the falling edge of DSC. All other interface widths
are single data rate (SDR), where the input data is sampled on
the falling edge of DSC.
Table 57. LVDS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
Pin Assignments
D[3:0]P, D[3:0]N
D[7:0]P, D[7:0]N
D[15:0]P, D[15:0]N
D[15:0]P, D[15:0]N rising
edge and falling edge
BUSWDTH[1:0]
00
01
10
11
In nibble or byte loading, the most significant nibble or byte
should be loaded first. Data for Channel 0 should be loaded first
followed by Channel 1, Channel 2, and Channel 3. In complex
data format, the in-phase part should be loaded before the
quadrature part of the data-word. The data bus is LSB justified
when the data for each channel is assembled internally. A few
examples of how the interface maps for different configurations
follow. For more information on how a particular configuration
is mapped, see the Channelizer Mode Pin Mapping for CMOS
and LVDS section.
Example 1
For a CMOS interface with a 32-bit bus width, 8-bit data width,
real data format, and four channels enabled, the data in Table 58
is expected on the input port after data is requested.
Table 58. CMOS Pin Mapping for Bus Width = 32 Bits,
Data Width = 8 Bits, Data Format = Real, Four Channels1
DCO
1
1
D[31:24]
R3
D[23:16]
R2
D[15:8]
R1
D[7:0]
R0
R represents the real data loaded to a given channel; the channel number
follows R.
Example 2
For a CMOS interface with a 32-bit bus width, 8-bit data width,
complex data format, and four channels enabled, the data in
Table 59 is expected on the input port after data is requested.
Table 59. CMOS Pin Mapping for Bus Width = 32 Bits,
Data Width = 8 Bits, Data Format = Complex, Four Channels1
DCO
1
2
1
D[31:24]
Q1
Q3
D[23:16]
I1
I3
D[15:8]
Q0
Q2
D[7:0]
I0
I2
I represents the in-phase term and Q represents the quadrature term of the
complex data loaded to a given channel; the channel number follows I or Q.
Example 3
For an LVDS interface with a 16-bit bus width, 8-bit data width,
complex data format, and four channels enabled, the data in
Table 60 is expected on the input port after data is requested.
Table 60. LVDS Pin Mapping for Bus Width = 16 Bits,
Data Width = 8 Bits, Data Format = Complex, Four Channels1
DCO
1
2
3
4
1
D[15:8]P, D[15:8]N
Q0
Q1
Q2
Q3
D[7:0]P, D[7:0]N
I0
I1
I2
I3
I represents the in-phase term and Q represents the quadrature term of the
complex data loaded to a given channel; the channel number follows I or Q.
Example 4
For an LVDS interface with a 32-bit bus width, 8-bit data width,
complex data format, and four channels enabled, the data in
Table 61 is expected on the input port after data is requested.
Table 61. LVDS Pin Mapping for Bus Width = 32 Bits,
Data Width = 8 Bits, Data Format = Complex, Four Channels1
DCO2
1 rise
1 fall
2 rise
2 fall
D[15:8]P, D[15:8]N
Q0
Q1
Q2
Q3
D[7:0]P, D[7:0]N
I0
I1
I2
I3
1
I represents the in-phase term and Q represents the quadrature term of the
complex data loaded to a given channel; the channel number follows I or Q.
2
“Rise” means that the data is sourced on the rising edge of DCOx; “fall” means
that the data is sourced on the falling edge of DCOx.
DCO and FS Rates in Channelizer Mode
The DCO signal is a data clock output provided to clock data
from the digital data source. The DCO is a divided version of
the DAC clock. The FS signal is an output provided to request a
new data-word. The average frequency of the FS signal (fFS) is
exactly equal to the symbol rate or baud rate (fBAUD) of the data.
FS is intended as a request line; timing should be taken from the
DCO. The frequencies of the DCO signal (fDCO), the baud rate
(fBAUD), and the DAC clock (fDAC) are related as shown by the
following two equations:
f DAC = I ×
P
× 16 × f BAUD
Q
fDCO = fDAC /(16 × N)
(1)
(2)
where:
I is the interpolation factor, which can range from 1 to 64.
P/Q is the rate conversion factor (0.5 to 1.0, inclusive).
N is a programmable DCO divide factor set using the
DCODIV[2:0] bits in Register 0x22[6:4].
Set DCODIV[2:0] to 1, 2, or 4. A value of 0 disables the DCO.
A DCODIV value of 3 is not functional. The frequency of the
DSC signal is always equal to DCO.
Rev. A | Page 46 of 76
AD9789
Before choosing an interface configuration, divide the frequency
of DCO by the highest frequency baud rate that will be used in
the system and truncate it. The result is the number of available
DCO cycles (cyclesAVAIL) between FS pulses.
⎞
⎟
⎟
⎠
An example of channel prioritization set to 0 is shown in Table 62.
In this example, the data interface is configured for CMOS with
32-bit bus width, 8-bit data width, and real data format.
Each interface configuration requires a particular number of
DCO cycles between FS pulses to successfully load data into all
channels. This number can be calculated using the following
formula:
DW
BW
where:
N is the number of channels enabled (1 to 4). N is always equal
to 4 if channel prioritization is set to 1 (see the Channel
Prioritization section).
F represents the data format. If the data format is real, F = 1;
if the data format is complex, F = 2.
DW is the data width in number of bits (8 or 16).
BW is the bus width in number of bits (4, 8, 16, or 32).
For a successful interface design, the number of DCO cycles
between FS pulses must be greater than the number of DCO
cycles required by the interface.
Design Example
In this example, a system has the baud rate fFS = 6.4 MHz. If a
4-bit-wide interface is desired for four channels with real data
format and a data width of 8 bits, the selected fDCO should be at
least 8 × fFS. First, using Equation 1 and Equation 2, evaluate the
interface speed with N = 1, P/Q = 0.7, and I = 32.
Channels
4 Channels
Enabled
Channel 0
Disabled
Channel 0,
Channel 2
Disabled
[D31:D24]
Channel 3
CMOS Bit Mapping
[D23:D16]
[D15:D8]
Channel 2
Channel 1
[D7:D0]
Channel 0
Channel 3
Channel 2
Channel 1
Channel 3
Channel 1
The same example behaves differently when channel prioritization
is set to 1, as shown in Table 63.
Table 63. Input Mapping vs. Enabled Channels,
Channel Prioritization = 1
Channels
4 Channels
Enabled
Channel 0
Disabled
Channel 0,
Channel 2
Disabled
[D31:D24]
Channel 3
CMOS Bit Mapping
[D23:D16]
[D15:D8]
Channel 2
Channel 1
Channel 3
Channel 2
[D7:D0]
Channel 0
Channel 1
Channel 3
Channel 1
Quadrature Digital Upconverter (QDUC) Mode
fDAC = 32 × 0.7 × 16 × 6.4 MHz = 2293.76 MHz
fDCO = 2293.76 MHz/(16 × 1) = 143.36 MHz
The fDCO/fBAUD ratio = 22.4. If a value of N = 2 is selected, the
number of available DCO cycles is reduced to 11; this option
may not be feasible when the latency values are taken into
account. See the Latency Effects on Channelizer Mode section
for more information about latency.
In QDUC mode (Register 0x20[3] = 1), the data interface is fixed
at a 32-bit bus width, 16-bit data width, and complex data format.
In QDUC mode, only one channel should be enabled. If more
than one channel is enabled, identical I and Q data is sent to
each enabled channel. Within the datapath, the QAM mapper
and the SRRC filter must be bypassed (Register 0x06[7:6] = 11).
Channel Prioritization
32
INPUT
PINS
P0
P1
FS
DCO
Rev. A | Page 47 of 76
LVDS/CMOS
When channels are enabled and disabled, the input interface
mapping can be affected. If channel prioritization (Register
0x20[2]) is set to 0, the device expects input samples for only
the channels that are enabled. In this configuration, the physical
channel mapping at the DUT input can move around based on
the number of channels enabled, where Channel 0 has highest
priority (it never moves location when enabled). If channel
prioritization is set to 1, data is expected for all four channels
but the data is ignored internally if the channel is disabled.
This method is recommended because enabling and disabling
channels does not shift the input data bus.
CMOS
0 TO 15
LVDS
RISE
I
CMOS
16 TO 31 Q
LVDS
FALL
I AND Q
16 BITS
ON
I AND Q
16 BITS
OFF
I AND Q
16 BITS
OFF
I AND Q
16 BITS
OFF
BPF
fC =
0 TO
fDAC /2
BPF
Figure 93. QDUC Mode
fC
07852-069
cycles INTERFACE = N × F ×
Table 62. Input Mapping vs. Enabled Channels,
Channel Prioritization = 0
16×
INTERPOLATOR
⎛ f DCO
cycles AVAIL = floor ⎜⎜
⎝ max f BAUD
If the number of channels enabled is always less than four and
the user does not plan to enable and disable channels dynamically,
setting channel prioritization to 0 is the best choice because
fewer clocks and/or pins are required to transfer the input data.
AD9789
Pin Mapping in QDUC Mode
1
2
3
4
5
6
7
8
9
10 11
12 13 14
A
In CMOS mode, the AD9789 input pins are mapped as shown
in Table 64.
B
C
Table 64. Pin Mapping in QDUC Mode for CMOS Interface
D
Data Bit
D31
D16
D15
D0
P1
P0
E
2
3
4
5
6
7
8
9
10 11
Pin No.
L5
P8
L9
P12
L4
M4
F
G
H
PARP
J
PARN
K
12 13 14
A
FSP
L
P+
15 13
11
9
7
5
3
1
FS
FSN
M
P–
15 13
11
9
7
5
3
1
FS
DCOP
N
14 12 10
8
6
4
2
0
DC
DCON
P
14 12 10
8
6
4
2
0
DC
B
14 +LVDS
C
Figure 95. LVDS Data Input Pin Mapping
D
DCO and FS Rates in QDUC Mode
E
In QDUC mode, DCODIV should always be set to 1 (Register
0x22[6:4] = 001). The clock period of DCO is equal to 16 DAC
clock periods. When only 16× interpolation is required and the
rate converter is not used, the data rate of the interface is equal
to fDCO.
F
G
H
J
K
L
P1
31 27 23 19 15
11
7
3
BU
CMOS_BUS
M
P0
30 26 22 18 14 10
6
2
CT
CMOS_CTRL
N
29 25 21 17 13
9
5
1
FS
CMOS_FS
P
28 24 20 16 12
8
4
0
DC
CMOS_DCO
If further interpolation or rate conversion is enabled in the
datapath, the data rate of the interface is fBAUD. The average rate
of FS, fFS, is equal to the baud rate, fBAUD. The baud rate can be
specified by the following equation:
07852-113
D[31:0] CMOS DATA INPUTS
PARITY AND CONTROL INPUTS
f BAUD =
Figure 94. CMOS Data Input Pin Mapping
In LVDS mode, the AD9789 input pins are mapped as shown in
Table 65.
Table 65. Pin Mapping in QDUC Mode for LVDS Interface1
Data Bit
D15P, D15N rising
D0P, D0N rising
D15P, D15N falling
D0P, D0N falling
PARP, PARN rising
PARP, PARN falling
1
14 –LVDS
07852-114
1
Description
MSB of I data
LSB of I data
MSB of Q data
LSB of Q data
Parity for D[31:16]
Parity for D[15:0]
Description
MSB of I data
LSB of I data
MSB of Q data
LSB of Q data
Parity for D[15:0]P, D[15:0]N
rising
Parity for D[15:0]P, D[15:0]N
falling
Pin No.
L5, M5
N12, P12
L5, M5
N12, P12
L4, M4
f DCO
P
2 ×
Q
N
where:
N is the number of 2× interpolation filters enabled.
P/Q is the rate converter ratio.
The FS signal becomes a request for data that effectively gates the
DCO clock and ensures that data is sent at the correct baud rate.
If P/Q = 1 and N = 0, DCO occurs at the baud rate and FS is not
required. In this case, FS is inactive (always high). The DCO
signal can be used as a constant rate clock to request samples
from the data source.
L4, M4
“Rising” means that the data is sourced on the rising edge of DCOx; “falling”
means that the data is sourced on the falling edge of DCOx.
Rev. A | Page 48 of 76
AD9789
DCO
7 DCO CYCLES
FS
6 DCO CYCLES
tPD
7 DCO CYCLES
tPD
tPD
SAMPLE
0
SAMPLE
1
SAMPLE
2
07852-115
D[31:0]
DSC
Figure 96. QDUC Mode Interface Timing Diagram for Design Example When FS Is Active
Design Example
LVDS
DATA
In this example, a system has a DAC rate of 1600 MHz and a
baud rate of 15 MHz. Because fDCO = fDAC/16 = 100 MHz, the
ratio of fDCO/fFS = 6.667. To satisfy the requirement that P/Q be
between 0.5 and 1.0, an additional interpolation factor of 8×
must be applied, so N = 3. Solving for P/Q results in 5/6.
Retimer Operation
The AD9789 uses a three-register retimer. The first two registers
are clocked from any one of 16 phases derived from the DAC
clock. The clock for the last register is fixed to Phase 15. The
programmable register clocks are the digital sample clock (DSC)
and the synchronizer clock (SNC). By choosing different
phases, fine adjustment of the sampling time can be made to
adjust for delays in the data source. Register 0x23[7:4] sets the
DSC phase (DSCPHZ) and Register 0x23[3:0] sets the SNC
phase (SNCPHZ) to any one of the 16 phases. The last register
in the chain is always clocked from Phase 15.
The parity counters can aid in identifying the edges of the data
valid windows. Operation in CMOS mode is quite similar to operation in LVDS mode, as can be seen in Figure 97 and Figure 98.
CMOS
DATA
32
32
Q
D
CLK
32
Q
D
CLK
Q
D
CLK
BITS
0 TO 31
DSC
Φ 0 TO 15
07852-070
SNC
Φ 0 TO 13
PHZ
Φ 15
Figure 97. CMOS Retiming Registers
Q
D
CLK
16
Q
D
CLK
16
Q
D
CLK
16
Q
D
CLK
Q
D
CLK
BITS
0 TO 15
Q
D
CLK
BITS
16 TO 31
16
Q
D
CLK
DSC
Φ 0 TO 15
SNC
Φ 0 TO 13
07852-071
Therefore, three out of every 20 DCO clock edges should
result in data samples being loaded into the device (the ratio
of fFS/fDCO = 3/20). Figure 96 shows a timing diagram that
illustrates the operation of the interface in this example. In the
timing diagram, tPD corresponds to the propagation delay
between the rising edge of FS and when the first sample in a
given transmission is sampled into the AD9789. Note that tPD
can vary by more than 1 DCO cycle.
16
16
PHZ
Φ 15
Figure 98. LVDS Rearranges the DSC Register
Register 0x23 and Register 0x21[2:0] can provide timing adjustments with very low jitter penalty, but they can also be set to the
following recommended safe values:
•
•
In LVDS mode, DSCPHZ = 0, SNCPHZ = 3, LTNCY = 0
(see the Latency Register section)
In CMOS mode, DSCPHZ = 0, SNCPHZ = 7, LTNCY = 0
(see the Latency Register section)
Timing adjustments can then be made in an FPGA or other
data source.
Note that selecting Phase 14 or Phase 15 for SNCPHZ results in
a timing violation. In CMOS mode, setting DSCPHZ one step
behind or at SNCPHZ also results in a timing violation.
Latency Register
A latency register, controlled via Register 0x21[2:0], follows the
three-register retimer and can delay the data up to seven DCO
clocks in steps of one DCO clock. The critical retiming is
already done in the first three registers, so an incorrect latency
value does not result in a timing violation. The latency value
determines which data sample is the first sample in a transmission and routes that sample to the appropriate channel.
Latency is affected by the round-trip delay from when FS goes
high to when the first data sample is output from the retimer. If
the latency value programmed into the part is incorrect, the
input data samples will not be assembled properly.
Rev. A | Page 49 of 76
AD9789
0123 4 56 7 8
16
24
32
40
48
56
64
72
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
DCO
FS
LVDS DDR
SAMPLE
SAMPLE
LVDS SDR
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
CMOS
SAMPLE
SAMPLE
SAMPLE
SAMPLE
07852-116
SAMPLE
Figure 99. Sampling Points at Delay = 0
Retimer and Latency Look-Up Tables
For LVDS DDR,
In practice, the retimer and latency parameters can be reduced
to a single verified and guaranteed table that provides delays at
optimum sample points from 0 to over 100 DAC clocks. The
sampling points for LVDS DDR, LVDS SDR, and CMOS interface modes are given in Figure 99 for delay = 0. The number
scale above the DCO signal in Figure 99 corresponds to the
delay value in DAC clock cycles in Table 66 and Table 67.
The delay of the pins should be taken into account. This delay is
800 ps for the output delay and 800 ps for the input delay, for a
total of 1.6 ns. This delay is included in the following formulas.
See Table 66 for a complete set of recommended retimer settings
for all delay values. Note: for LVDS DDR, zero (0) measured delay
results in a retimer setting of 20, while for .LVDS SDR or CMOS,
the zero(0) delay corresponds to a retimer setting of 12 at fDAC =
2.4 GHz.
To use Table 66 and Table 67, probe the FS, DCO, and data
input signals at the AD9789. While viewing these signals on an
oscilloscope, measure the delay between the rising edge of FS
and the start of the first data sample and add 1.6 ns from the
delay of the pins to this value. Normalize this total delay to one
DAC clock period. The optimum sampling point in number of
DAC clock cycles, which corresponds to the delay number in
Table 66 and Table 67, can be found from this measured value
for each interface mode.
Delay OPTIMAL =
Delay MEASURED + 1.6 ns
t DCO / 16
+ 16
For LVDS SDR,
Delay OPTIMAL =
Delay MEASURED + 1.6 ns
t DCO / 16
+8
For CMOS,
Delay OPTIMAL =
Delay MEASURED + 1.6 ns
t DCO / 16
+8
For a maximum valid sampling window, the sampling point
should be fine-tuned based on the data input setup and hold
times. If the setup and hold times are symmetric about the
DCO edge, choosing a sampling point at the center of the data
window results in the maximum valid sampling window. For
more information on the input data setup and hold times, refer
to the CMOS Interface Timing section or the LVDS Interface
Timing section.
The LAT, SNC, and DSC values for the optimal sampling point in
Table 66 or Table 67 should be written to the LTNCY[2:0] bits in
Register 0x21[2:0], the SNCPHZ[3:0] bits in Register 0x23[3:0],
and the DSCPHZ[3:0] bits in Register 0x23[7:4], respectively.
Rev. A | Page 50 of 76
AD9789
Table 66. Recommended Retimer Settings for All Delay
Values, LVDS Mode
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
0
0
7
8
8
1
3
0
16
1
7
8
24
2
3
0
32
2
7
8
40
3
3
0
48
3
7
8
56
4
3
0
64
4
7
8
72
5
3
0
80
5
7
8
88
6
3
0
1
0
8
9
9
1
4
1
17
1
8
9
25
2
4
1
33
2
8
9
41
3
4
1
49
3
8
9
57
4
4
1
65
4
8
9
73
5
4
1
81
5
8
9
89
6
4
1
2
0
9
10
10
1
4
2
18
1
9
10
26
2
4
2
34
2
9
10
42
3
4
2
50
3
9
10
58
4
4
2
66
4
9
10
74
5
4
2
82
5
9
10
90
6
4
2
3
0
9
11
11
1
5
3
19
1
9
11
27
2
5
3
35
2
9
11
43
3
5
3
51
3
9
11
59
4
5
3
67
4
9
11
75
5
5
3
83
5
9
11
91
6
5
3
4
0
10
12
12
1
5
4
20
1
10
12
28
2
5
4
36
2
10
12
44
3
5
4
52
3
10
12
60
4
5
4
68
4
10
12
76
5
5
4
84
5
10
12
92
6
5
4
5
0
10
13
13
1
6
5
21
1
10
13
29
2
6
5
37
2
10
13
45
3
6
5
53
3
10
13
61
4
6
5
69
4
10
13
77
5
6
5
85
5
10
13
93
6
6
5
6
1
2
14
14
1
6
6
22
2
2
14
30
2
6
6
38
3
2
14
46
3
6
6
54
4
2
14
62
4
6
6
70
5
2
14
78
5
6
6
86
6
2
14
94
6
6
6
7
1
3
15
15
1
7
7
23
2
3
15
31
2
7
7
39
3
3
15
47
3
7
7
55
4
3
15
63
4
7
7
71
5
3
15
79
5
7
7
87
6
3
15
95
6
7
7
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
96
6
7
8
104
7
3
0
112
7
7
8
97
6
8
9
105
7
4
1
113
7
8
9
98
6
9
10
106
7
4
2
114
7
9
10
99
6
9
11
107
7
5
3
115
7
9
11
100
6
10
12
108
7
5
4
116
7
10
12
101
6
10
13
109
7
6
5
117
7
10
13
102
7
2
14
110
7
6
6
X
X
X
X
103
7
3
15
111
7
7
7
X
X
X
X
Table 67. Recommended Retimer Settings for All Delay
Values, CMOS Mode
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Rev. A | Page 51 of 76
0
0
7
0
8
1
3
8
16
1
7
0
24
2
3
8
32
2
7
0
40
3
3
8
48
3
7
0
56
4
3
8
64
4
7
0
1
0
8
1
9
1
4
9
17
1
8
1
25
2
4
9
33
2
8
1
41
3
4
9
49
3
8
1
57
4
4
9
65
4
8
1
2
0
8
2
10
1
4
10
18
1
8
2
26
2
4
10
34
2
8
2
42
3
4
10
50
3
8
2
58
4
4
10
66
4
8
2
3
0
9
3
11
1
5
11
19
1
9
3
27
2
5
11
35
2
9
3
43
3
5
11
51
3
9
3
59
4
5
11
67
4
9
3
4
0
9
4
12
1
5
12
20
1
9
4
28
2
5
12
36
2
9
4
44
3
5
12
52
3
9
4
60
4
5
12
68
4
9
4
5
0
2
5
13
1
6
13
21
1
2
5
29
2
6
13
37
2
2
5
45
3
6
13
53
3
2
5
61
4
6
13
69
4
2
5
6
1
2
6
14
1
6
14
22
2
2
6
30
2
6
14
38
3
2
6
46
3
6
14
54
4
2
6
62
4
6
14
70
5
2
6
7
1
3
7
15
1
7
15
23
2
3
7
31
2
7
15
39
3
3
7
47
3
7
15
55
4
3
7
63
4
7
15
71
5
3
7
AD9789
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
72
5
3
8
80
5
7
0
88
6
3
8
96
6
7
0
104
7
3
8
112
7
7
0
73
5
4
9
81
5
8
1
89
6
4
9
97
6
8
1
105
7
4
9
113
7
8
1
74
5
4
10
82
5
8
2
90
6
4
10
98
6
8
2
106
7
4
10
114
7
8
2
75
5
5
11
83
5
9
3
91
6
5
11
99
6
9
3
107
7
5
11
115
7
9
3
76
5
5
12
84
5
9
4
92
6
5
12
100
6
9
4
108
7
5
12
116
7
9
4
77
5
6
13
85
5
2
5
93
6
6
13
101
6
2
5
109
7
6
13
117
7
2
5
78
5
6
14
86
6
2
6
94
6
6
14
102
7
2
6
110
7
6
14
X
X
X
X
79
5
7
15
87
6
3
7
95
6
7
15
103
7
3
7
111
7
7
15
X
X
X
X
The timing of the input data is referenced to DCO for a given
phase of DSC. The CMOS data input timing over temperature is
shown in Table 68 for DCO_INV = 0 (Register 0x20[4]),
DSCPHZ = 0 (Register 0x23[7:4]), and DCODIV = 1 (Register
0x22[6:4]). Table 68 also shows the data valid window (DVW).
The data valid window is the sum of the setup and hold times of
the interface. DVW is the minimum amount of time that valid
data must be presented to the device to ensure proper sampling.
Table 68. CMOS Data Input Timing with Respect to DCO
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
Min tS (ns)
4.9
5.1
5.3
5.3
Min DVW (ns)
3.5
3.5
3.6
3.9
For any value of DSCPHZ greater than 0, the setup and hold
times shift by increments of tDCO/16, where tDCO is the period of
the data clock.
tS = 5.3 ns − ((tDCO/16) × DSCPHZ)
tH = 0.24 ns + ((tDCO/16) × DSCPHZ)
DCO
tS
Latency Effects on Channelizer Mode
Min tH (ns)
−1.4
−1.6
−1.7
−1.4
tH
When selecting an interface configuration in channelizer mode,
the number of DCO cycles between FS pulses (cyclesAVAIL) must
be greater than the number of DCO cycles required by the interface configuration (cyclesINTERFACE). Latency consumes some of
these available DCO cycles between FS. This decrease in available
DCO cycles is a result of the round-trip propagation delay from
the FS output of the AD9789 to the respective data sample at the
input of the AD9789 (LTNCY[2:0]) in addition to the internal
latency of the device.
For a successful interface design, the following condition must
be met:
07852-117
INPUT
DATA
DSC
Figure 100. CMOS Input Timing
In some interface modes, the delay from the rising edge of DCO
to the rising edge of FS needs to be known. This delay is summarized over temperature in Table 69.
DCO
tD
FS
07852-118
cyclesAVAIL ≥ cyclesINTERFACE + LTNCY[2:0] + 2
DSC
CMOS Interface Timing
When the AD9789 is configured with a CMOS interface
(CMOS_CTRL = CMOS_BUS = 3.3 V), a CMOS data clock
output signal, DCO, is provided to drive data from the data
source. The output signal operates at the input data rate, which
is equal to fDAC/16 when DCODIV = 1. CMOS data on the bus is
sampled on the rising edge of an internal sampling clock (DSC).
Note that the frequency of DCO is equal to the frequency of
DSC and the phase relationship between DCO and DSC is
determined by DSCPHZ (Register 0x23[7:4]).
Figure 101. CMOS_DCO to CMOS_FS Delay
Table 69. Timing Delay Between CMOS_DCO and CMOS_FS
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
Rev. A | Page 52 of 76
tD, MAX DCO to FS (ns)
0.64
0.71
0.85
0.85
tD, MIN DCO to FS (ns)
0.28
0.4
0.49
0.28
AD9789
When the AD9789 is configured with an LVDS interface
(CMOS_CTRL = CMOS_BUS = 0 V), an LVDS data clock output signal, DCO, is provided to drive data from the data source.
The LVDS interface may be single data rate (SDR) or double
data rate (DDR) depending on the bus width configuration. In
SDR, data is sampled into the part only on the falling edge of
the internal sampling clock (DSC). Note that the frequency of
DCO is equal to the frequency of DSC, so the effective data rate
is equal to the DCO frequency. The phase relationship between
DCO and DSC is determined by DSCPHZ (Register 0x23[7:4]).
In DDR, data is sampled into the part on both the rising and falling
edges of DSC, so the effective data rate is equal to twice the DCO
frequency. The interface is DDR only when the bus width is equal to
32 bits. The DCO frequency is equal to fDAC/16 when DCODIV = 1.
The timing of the input data is referenced to DCO for a given phase
of DSC. The LVDS input data timing over temperature is shown
in Table 70 for DCO_INV = 0 (Register 0x20[4]), DSCPHZ = 0
(Register 0x23[7:4]), and DCODIV = 1 (Register 0x22[6:4]).
Table 70. LVDS Data Input Timing with Respect to DCO
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
Min tS (ns)
1.04
1.23
1.41
1.41
Min tH (ns)
0.24
0.16
0.03
0.24
Min DVW (ns)
1.28
1.39
1.44
1.65
In DDR mode, these setup and hold times must be applied to
both edges of DCO. In SDR mode, these setup and hold times
must be applied to the falling edge of DCO.
DCO
tD
FS
DSC
Figure 103. LVDS DCO to FS Delay
Table 71. Timing Delay Between LVDS DCO and FS
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
The AD9789 supports parity checking on the input data bus.
There are three parity checking modes: even parity, odd parity,
and IQ parity. In IQ parity mode, a value of 0 is always expected
on the I channel and a value of 1 is always expected on the Q
channel. Note that IQ parity mode is generally useful only when
the LVDS interface is used. These modes are controlled via
Register 0x20[1:0].
SINGLE DATA RATE (SDR)
DCO
tH
INPUT
DATA
Recall that the LVDS interface can be single data rate (SDR) or
double data rate (DDR), depending on the bus width configuration. The interface is DDR only when the bus width is equal
to 32 bits.
DSC
DOUBLE DATA RATE (DDR)
DCO
tS
tH
tS
tH
07852-119
INPUT
DATA
DSC
Register 0x20[1:0]
00
01
10
11
If parity checking is used, each data-word that is transferred
into the AD9789 should have a parity bit accompanying it,
regardless of FS. In other words, parity must be valid for every
DCO edge. The parity bits are located at Pin L4 and Pin M4.
When operating the interface in CMOS mode, the input parity
bits are referred to as P1 and P0, respectively. When operating
the interface in LVDS mode, the input parity bits are referred
to as PARP and PARN, respectively.
tH = 0.24 ns + ((tDCO/16) × DSCPHZ)
tH
tD, MIN DCO to FS (ns)
0.21
0.16
0.12
0.12
Parity
Parity Mode
Deactivates Parity Checking
IQ Parity
Even Parity
Odd Parity
tS = 1.41 ns − ((tDCO/16) × DSCPHZ)
tS
tD, MAX DCO to FS (ns)
0.37
0.35
0.32
0.37
Table 72. Parity Mode SPI Settings
For any value of DSCPHZ greater than 0, the setup and hold
times shift by increments of tDCO/16, where tDCO is the period
of the data clock.
tS
In some interface modes, the delay from the rising edge of
DCO to the rising edge of FS needs to be known. This delay
is summarized over temperature in Table 71.
07852-120
LVDS Interface Timing
Figure 102. LVDS Input Timing, SDR vs. DDR
Rev. A | Page 53 of 76
AD9789
In QDUC mode, where the interface is fixed at a 32-bit bus
width, the parity behavior is straightforward (see Table 73).
If a parity error occurs, the parity counter (Register 0x02[7:0])
is incremented. The parity counter continues to accumulate
until it is cleared or until it reaches a maximum value of 255.
The count can be cleared by writing a 1 to Register 0x04[7].
Table 73. Parity Behavior in QDUC Mode
Interface
CMOS
Bus
Width
32 bits
LVDS1
(DDR)
32 bits
1
Even/Odd Parity
P1 checks D[31:16]
P0 checks D[15:0]
[PARP, PARN] rising checks
D[15:0]P, D[15:0]N rising
[PARP, PARN] falling checks
D[15:0]P, D[15:0]N falling
IQ Parity
P1 = 0
P0 = 1
PARP rising = 0
PARN rising = 1
PARP falling = 1
PARN falling = 0
“Rising” corresponds to the data sampled on the rising edge of DSC; “falling”
corresponds to the data sampled on the falling edge of DSC.
An IRQ can be enabled to trigger when a parity error occurs by
writing a 1 to Register 0x03[7]. The status of IRQ can be measured via Register 0x04[7] or by using the IRQ pin (Pin P2). If
using the IRQ pin and more than one IRQ is enabled, the user
must check Register 0x04 when an IRQ event occurs to determine
whether the IRQ was caused by a parity error. The IRQ can also
be cleared by writing a 1 to Register 0x04[7].
ANALOG MODES OF OPERATION
In channelizer mode, where the interface is configurable for
different bus widths, data widths, and data formats, the parity
bits check the data-word on the bus.
The AD9789 uses a quad-switch architecture that can be configured to operate in one of three modes via the serial peripheral
interface: normal mode, RZ mode, and mix mode.
For example, consider a configuration in channelizer mode where
the bus width is 4, the data width is 8, and the data format is
real. In this case, eight clock cycles are required to transfer all of
the baud rate data to represent four channels. In the even parity
or odd parity mode, one parity bit and four data bits are sent on
each clock; the parity bit checks the four data bits to verify that
all of the data was sent over the interface.
The quad-switch architecture masks the code-dependent glitches
that occur in a conventional two-switch DAC. Figure 104 shows
the waveforms for a conventional DAC and the quad-switch DAC.
In the two-switch architecture with D1 and D2 in different states,
a switch transition results in a glitch. However, if D1 and D2 are
at the same state, the switch does not create a glitch. This codedependent glitching causes an increased amount of distortion in
the DAC. In the quad-switch architecture, two switches are
always transitioning at each half clock cycle, regardless of the
code; therefore, code-dependent glitches are eliminated, but a
constant glitch at 2 × fDAC is created.
Table 74. Parity Behavior in Channelizer Mode
Interface
CMOS
Bus
Width
4 bits
CMOS
8 bits
CMOS
16 bits
CMOS
32 bits
LVDS
(SDR)1
LVDS
(SDR)1
LVDS
(SDR)1
LVDS
(DDR)1
4 bits
1
8 bits
16 bits
32 bits
Even/Odd Parity
P1 ignored
P0 checks D[3:0]
P1 ignored
P0 checks D[7:0]
P1 ignored
P0 checks D[15:0]
P1 checks D[31:16]
P0 checks D[15:0]
[PARP, PARN] falling checks
D[3:0]P, D[3:0]N falling
[PARP, PARN] falling checks
D[7:0]P, D[7:0]N falling
[PARP, PARN] falling checks
D[15:0]P, D[15:0]N falling
[PARP, PARN] rising checks
D[15:0]P, D[15:0]N rising
[PARP, PARN] falling checks
D[15:0]P, D[15:0]N falling
IQ Parity
P1 = 0
P0 = 1
P1 = 0
P0 = 1
P1 = 0
P0 = 1
P1 = 0
P0 = 1
Not supported
Not supported
INPUT DATA
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D6
D7
D8
D9
D10
DACCLK
2-SWITCH
DAC OUTPUT
4-SWITCH
DAC OUTPUT
(NORMAL MODE)
t
D6
D1
D2
D3
D4
D7
D8
D9
D10
t
D5
Not supported
Figure 104. Two-Switch and Quad-Switch DAC Waveforms
PARP rising = 0
PARN rising = 1
PARP falling = 1
PARN falling = 0
“Rising” corresponds to the data sampled on the rising edge of DSC; “falling”
corresponds to the data sampled on the falling edge of DSC.
The quad-switch architecture can also be easily configured to
perform an analog mix or return-to-zero (RZ) function. In mix
mode, the output is effectively chopped at the DAC sample rate.
The RZ mode is similar to mix mode, except that the intermediate data samples are replaced with midscale values instead
of inverting values. Figure 105 shows the DAC waveforms for
both mix mode and RZ mode.
Rev. A | Page 54 of 76
07852-072
Table 74 summarizes the behavior of the two parity pins and
how they interact with the data in all interface modes.
AD9789
INPUT DATA
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
ANALOG CONTROL REGISTERS
DACCLK
D2
4-SWITCH
DAC OUTPUT
(fS MIX MODE)
–D7
D4
D1
D5
–D9
–D10
–D6
t
–D1
–D5 D6
–D2
–D4
D8
D3
D4
D7
D8
D9
D10
t
D5
–110
07852-073
D2
Using the MSEL[1:0] bits (Register 0x36[1:0]), the user can
adjust the noise contribution of the internal current mirror to
optimize the 1/f noise. Figure 107 shows MSEL vs. the 1/f noise
with 20 mA full-scale current into a 50 Ω resistor.
D9
D7
D6
D1
Mirror Roll-Off Frequency Control
D10
–D3
4-SWITCH
DAC OUTPUT
(RETURN-TOZERO MODE)
The AD9789 includes registers for optimizing its analog
performance. These registers include noise reduction in the
output current mirror and output current mirror headroom
adjustments.
–D8
D3
–115
Switching between analog modes reshapes the sinc roll-off
inherent at the DAC output. The performance and maximum
amplitude in all three Nyquist zones is affected by this sinc
roll-off depending on where the carrier is placed, as shown in
Figure 106.
FIRST
NYQUIST ZONE
SECOND
NYQUIST ZONE
0
NOISE (dBm/Hz)
Figure 105. Mix Mode and RZ Mode DAC Waveforms
THIRD
NYQUIST ZONE
MSEL = 11
–125
MSEL = 10
–130
MSEL = 00
–140
1
10
FREQUENCY (kHz)
Figure 107. 1/f Noise with Respect to MSEL Bits
–15
NORMAL
MODE
–20
–25
0
0.5
1.0
1.5
2.0
FREQUENCY (Hz)
2.5
3.0
07852-074
–30
Figure 106. Sinc Roll-Off for Each Analog Operating Mode (fS = 2 × DACCLK)
The RZ mode, with its lower but flat response, can be quite
useful for quick checks of system frequency response.
Rev. A | Page 55 of 76
100
07852-083
MIX MODE
–10
AMPLITUDE (dBm)
MSEL = 01
–135
–5 RZ MODE
–35
–120
AD9789
VOLTAGE REFERENCE
The AD9789 output current is set by a combination of digital
control bits and the I120 reference current, as shown in
Figure 108.
AD9789
FSC[9:0]
VBG
1.2V
VREF
CURRENT
SCALING
+
FULL-SCALE
CURRENT
07852-084
10kΩ
AVSS
IPTAT (Pin D14) is used for factory testing and can simply be
left floating. IPTAT is an output current that is proportional to
absolute temperature. At 25°C, the output current is approximately 10 μA and follows a slope of approximately 20 nA/°C.
–
I120
1nF
DAC
I120
VREF (Pin C14) must be bypassed to ground with a 1 nF
capacitor. The band gap voltage is present on this pin and can
be buffered for use in external circuitry. The typical output
impedance is near 5 kΩ. If desired, an external reference can be
used to overdrive the internal reference by connecting it to the
VREF pin.
For optimal DOCSIS 3.0 ACLR performance, the full-scale
output current settings provided in Table 75 are recommended.
Figure 108. Voltage Reference Circuit
The reference current is obtained by forcing the band gap
voltage across an external 10 kΩ resistor from I120 (Pin B14) to
ground. The 1.2 V nominal band gap voltage, VREF (Pin C14),
generates a 120 μA reference current in the 10 kΩ resistor. This
current is adjusted digitally by FSC[7:0] (Register 0x3C[7:0])
and FSC[9:8] (Register 0x3D[1:0]) to set the output full-scale
current, IFS, in milliamperes.
IFS = 0.023 × FSC[9:0] + 8.58
The full-scale output current range is approximately 8.6 mA to
32.1 mA for register values from 0x000 to 0x3FF. The default
value of 0x200 generates 20 mA full scale. The typical range is
shown in Figure 109.
35
Table 75. Recommended Full-Scale Current Settings vs.
Number of QAM Channels
Number of
QAM Channels
1
2
3
4
Recommended IFS (mA)
20
25
25
25
FSC[9:0]
512
720
720
720
DAC OUTPUT STAGES
To properly evaluate the AD9789 in the lab, three distinct
output coupling circuits were used.
Figure 110 shows the optimal output network when measuring
traditional DAC performance specifications such as SFDR and
IMD performance with sine waves.
30
IOUTP
90Ω
JTX-2-10T
90Ω
07852-121
70Ω
20
IOUTN
15
Figure 110. Recommended Transformer Output Stage
for Single-Tone/Multitone Measurements
10
0
0
200
400
600
800
DAC GAIN CODE
1000
07852-085
5
Figure 111 shows the optimal output network when measuring
signals in mix mode (second or third Nyquist zone). The bandwidth of the center tap transformer is not sufficient to support
mix mode outputs, so the best solution is to use a wideband
balun by itself.
Figure 109. Full-Scale Current vs. DAC Gain Code
90Ω
IOUTP
Always connect a 10 kΩ resistor from the I120 pin to ground
and use the digital controls to adjust the full-scale current. The
AD9789 is not a multiplying DAC. Applying an analog signal to
I120 is not supported.
70Ω
IOUTN
MABACT0039
90Ω
07852-122
IFS (mA)
25
Figure 111. Recommended Transformer Output Stage for Mix Mode
Rev. A | Page 56 of 76
AD9789
Finally, when measuring performance for CMTS and other
digital TV applications, it is advantageous to insert a 1 dB,
1.2 GHz Chebyshev low-pass filter between the DAC and the
transformer to better control the impedance seen at the DAC
core. This helps to decrease the folded back harmonics for
higher frequency outputs. The optimal transformer for CMTS
measurements is the JTX-2-10T, which consists of a balun and
center-tapped transformer in a single package. This output stage
is shown in Figure 112.
VCC
5.6nH
IOUTP
90Ω
90Ω
VREF
JTX-2-10T
2.2pF
50Ω
07852-123
IOUTN
4.7pF
Traces from the DAC to the transformer should be 50 Ω impedance to ground each in Figure 110 and Figure 112 and 25 Ω to
ground each in Figure 111 to avoid unnecessary parasitics.
CLOCKING THE AD9789
To provide the required signal swing for the internal clock
receiver of the AD9789, it is necessary to use an external clock
buffer chip to drive the CLKP and CLKN inputs. These high
level, high slew rate signals should not be routed any distance
on a PCB. The recommended clock buffer for this application
is the ADCLK914. This ultrafast clock buffer is capable of
providing 1.9 V out of each side into a 50 Ω load terminated
to VCC (3.3 V) for a total differential swing of 3.8 V.
GND
2 3 4 5
C82
0.01µF
GND
R15
49.9Ω
GND
VEE
VCC
1
2
3
4
VT
VREF
GND
D
D
NC
NC
5 6 7 8
Q
D
VEE
Figure 113. ADCLK914 Functional Block Diagram
The internal 50 Ω resistors shown at the ADCLK914 inputs are
rated to carry currents from PECL or CML drivers. The VT pin
can be connected to VCC, a PECL current sink, or the internal
VREF, or it can be left floating depending on the source. The
common-mode input range of the ADCLK914 does not include
LVDS voltage levels, so ac coupling is required in that case.
VCC33
R13
49.9Ω
R14
49.9Ω
U3
ADCLK914
C99
2400pF
C0803H50
CLKP
R17
100Ω
R0402
C102
2400pF
C0803H50
12
Q
11
Q
NC 10
NC 9
CLKN
ADCLK914 SUPPLY DECOUPLING
NC
NC
VEE
VCC
1
C81
0.01µF
50Ω
Q
VCC33
C83
0.01µF
16 15 14 13
50Ω
50Ω
D
Figure 112. Recommended Transformer Output Stage
for CMTS Measurements
J3
PSTRNKPE4117
ADCLK914
VT
5.6nH
07852-124
70Ω
VCC33
VCC33
GND
C31
0.1µF
C0402
C32
0.01µF
C0402
C33
0.1µF
C0402
C34
0.01µF
C0402
GND
GND
GND
GND
Figure 114. ADCLK914/AD9789 Interface Circuit for Use with a Lab Generator
Rev. A | Page 57 of 76
07852-125
4.7pF
The buffer, in turn, can be easily driven from lower level signals
such as CML or attenuated PECL that might be encountered on
a PCB. This buffer also provides very low, 100 fs added random
jitter, which is important to obtain the optimal ac performance
from the AD9789. A functional block diagram of the ADCLK914
is shown in Figure 113. Figure 114 shows the recommended
schematic for the ADCLK914/AD9789 interface. Refer to the
ADCLK914 data sheet for more information. Any time that the
noise floor from the DAC cannot meet the specifications in this
data sheet, the clock should be examined.
AD9789
Optimizing the Clock Common-Mode Voltage
In addition to the system that optimizes the handoff timing, an
additional system sets the common-mode voltage of the clock.
This system can be used to properly align the crossing point of
the CLKP and CLKN signals to ensure that the duty cycle of the
clock is set properly. Figure 115 shows how the common-mode
voltage of CLKP and CLKN is set. There are eight switches
controlled by the CLKP_CML bits (Register 0x32[4:1]) and the
CLKN_CML bits (Register 0x31[7:4]) for both the CLKP and
CLKN signals. The direction of the adjustment is determined by
the PSIGN and NSIGN bits (Register 0x32, Bit 5 and Bit 0). If
PSIGN and NSIGN are low, the common-mode voltage decreases
with CLKP_CML/CLKN_CML values. If PSIGN and NSIGN are
high, the common-mode voltage increases with CLKP_CML/
CLKN_CML values, as shown in Figure 116. With both
CLKP_CML and CLKN_CML set to 0, the feedback path forces
the common-mode voltage to be set to approximately 0.9 V. The
optimal ac performance occurs at a setting of −15 on both the
CLKP and CLKN offset bits.
Table 76. Four-Carrier DOCSIS Close-In ACLR Performance
at 900 MHz for Various Phase Noise Profiles
Band
750 kHz
to 6 MHz
6 MHz to
12 MHz
12 MHz to
18 MHz
CLKx_CML
SIGN = 1
−70.9
−70.3
−67
−63.8
−63
−71
−70.8
−70.8
−70.8
−65
Table 77. Phase Noise Summary for Each Profile
Phase Noise (dBc/Hz)
Offset1
2 kHz
20 kHz
200 kHz
2 MHz
20 MHz
Profile 1
−114.8
−117.8
−128.3
−148.5
−152.5
Profile 2
−112.8
−115.5
−118.9
−127.9
−149.9
Profile 3
−111.7
−114.6
−118.3
−122.2
−148
Profile 4
−111.2
−113.8
−116.8
−117.9
−145.7
At offsets less than 500 kHz, the measurement instrument dominates the
phase noise performance.
MU DELAY CONTROLLER
07852-081
The mu delay adjusts timing between the digital and analog
blocks. The mu delay controller receives phase relational
information between the digital and analog clock domains. The
control system continuously adjusts the mu delay to maintain
the desired phase relationship between the digital and analog
sections. A top level diagram of the mu delay within the DAC is
shown in Figure 117.
CVDD18
Figure 115. Clock Common-Mode Control
1.10
CLKN
1.05
1.00
16-BIT
DATA
0.95
16
DIGITAL
CIRCUITRY
14
14-BIT
2.4GSPS
DAC
0.90
DAC
CLOCK
0.85
MU
DELAY
MU
Φ DET
MU Φ
CONTROL
0.80
0.75
5
7
9
11 13 15
Figure 117. Mu Delay Controller Block Diagram
07852-082
0.70
–15 –13 –11 –9 –7 –5 –3 –1 1 3
OFFSET CODE
07852-077
COMMON-MODE VOLTAGE (V)
Spec
−60
To meet the close-in ACLR requirements for four-carrier
DOCSIS, the phase noise found in Profile 3 is the minimum
requirement necessary.
CLKP/CLKN
CLKP
Phase Noise (dBc)
Profile 2
Profile 3
Profile 4
−67.2
−62.4
−59.1
Table 77 shows the phase noise at various offsets for each
profile. (All phase noise numbers are specified in dBc/Hz.)
1
CLKx_CML
SIGN = 0
Profile 1
−71
Figure 116. Common-Mode Voltage with Respect to CLKP_CML/CLKN_CML
and PSIGN/NSIGN
Clock Phase Noise Effects on AC Performance
The quality of the clock source driving the ADCLK914 determines the achievable ACLR performance of the AD9789.
Table 76 summarizes the close-in ACLR for a four-carrier
DOCSIS signal at 900 MHz with respect to various phase
noise profiles. (All ACLR values are specified in dBc.)
The mu controller has two modes of operation: initial phase
search and phase tracking. In the phase search mode, the controller looks for the initial mu delay value to use before going
into tracking mode. In tracking mode, the controller makes
adjustments to the initial mu delay value to keep the phase at
the desired value. The initial phase search is required because
multiple mu delay settings may result in the desired phase, but
the device may not operate correctly at all of those mu delay values.
Rev. A | Page 58 of 76
AD9789
The mu controller is enabled via Register 0x33[0]. Enabling the
controller sets in motion the phase search mode. Before enabling
the controller, it is important to turn on both the phase comparator
boost (Register 0x3E[5]) and the mu control duty cycle correction
circuitry (Register 0x30[7]). Both of these functions allow for more
robust operation of the mu controller over the entire operating
speed of the part. The three modes of operation for the mu controller are specified by the MODE[1:0] bits in Register 0x33[5:4]
as follows:
Not exact (0): can find a phase within two values of the
desired phase
Exact (1): finds the exact phase specified (optimal setting)
Figure 118 shows a typical plot of mu phase vs. mu delay line
value at 2.4 GSPS. Starting at the selected mu delay value, the
search direction can be specified via the SEARCH_DIR[1:0]
bits in Register 0x39[6:5]. The three possible choices for the
search are as follows:
•
•
•
18
DESIRED
PHASE
AND
SLOPE
16
14
GUARD
BAND
12 GUARD
BAND
10
8
6
4
2
0
SEARCH STARTING
LOCATION
0
40
80
120
160
200 240 280
MU DELAY
320
360
400
440
Figure 118. Typical Mu Phase Characteristics @ 2.4 GSPS
To determine whether the search is on the correct slope, the
controller measures the slope by first incrementing and then
decrementing the mu delay value until any of the following
events happens:
•
•
•
•
•
The phase changes by 2.
The phase is equal to 16 (the maximum value).
The phase is equal to 0 (the minimum value).
The mu delay is 431 (the maximum value).
The mu delay is 0 (the minimum value).
After incrementing and then decrementing the mu delay value,
the values of the measured phases are compared to determine
whether the slope matches the desired slope. To consider the
slope valid, the positive direction phase and the negative
direction phase must be on opposite sides of the desired phase.
Examples of valid and invalid phase choices are shown in
Figure 119 and Figure 120.
15
14
Down only (00)
Up only (01)
Alternating up and down (10) (optimal setting)
9
8
13
7
12
DESIRED
If the search direction is alternating, the search proceeds in both
directions until a programmable guard band is reached in one
of the directions, specified by the GUARDBAND[4:0] bits in
Register 0x2F[4:0]. When the guard band is reached, the search
continues only in the opposite direction. If the desired phase is
not found before the guard band is reached in the second direction, the search reverts to the alternating mode and continues
looking within the guard band.
11
10
POSITIVE SLOPE
Rev. A | Page 59 of 76
DESIRED
6
5
4
NEGATIVE SLOPE
Figure 119. Valid Positive and Negative Slope Phase Examples
07852-079
•
Continue (0): continues to search (optimal setting)
Reset (1)
Search and track (00) (optimal setting)
Track only (01)
Search only (10)
The search algorithm begins at a specified mu delay value set using
the MUDLY[8:0] bits, where the LSB is located in Register 0x39[7]
and the MSBs are located in Register 0x3A[7:0]. Even though
there are nine bits of resolution for this delay line value, the
maximum allowable mu delay is 431 (decimal). The optimal
point to begin the search is in the middle of the delay line, or
approximately 216. The initial search algorithm works by sweeping through different mu delay values until the desired phase is
measured; this phase is specified using the MUPHZ[4:0] bits in
Register 0x39[4:0], with the maximum allowable phase being 16.
If values larger than 16 are loaded, the controller will not lock.
When the desired phase is measured, the slope of the phase
measurement is calculated and compared to the desired slope,
which is specified by the SLOPE bit in Register 0x33[6]. For
optimal ac performance, the best setting for the search is a
positive slope and a phase value of 14. If the phase and slope
match the configured values, the search algorithm is finished.
The SEARCH_TOL bit (Register 0x2F[7]) can be used to
specify the accuracy of the search as follows:
•
•
•
MU PHASE
•
•
•
The search fails if the mu delay reaches the endpoints. If the
controller does not find the desired phase during the search, the
TRACK_ERR bit (Register 0x2F[5]) determines the corrective
action as follows:
07852-078
Operating the Mu Controller in Auto Mode
AD9789
13
12
DESIRED
3
3
14
13
2
2
DESIRED
1
07852-080
14
4
15
15
1
Figure 120. Invalid Slope Phase Examples
Table 78 lists register writes and reads to lock to the controller.
The program assumes that the clock receiver is already enabled
and that a clean lock is provided. The typical locking time for
the mu controller is approximately 180,000 DAC cycles (at
2 GSPS, ~75 μs).
Table 78. AD9789 Mu Delay Controller Routine
When the initial mu delay value has been found by the search
algorithm, the tracking mode is enabled. In tracking mode, a
simple control loop is used to increment by 1, decrement by 1,
or not change the mu delay value depending on the measured
phase. The control loop uses the desired slope to determine
whether the mu delay should be incremented or decremented.
No attempt is made to determine whether the actual slope has
changed or is still valid.
Address
0x30
0x31
Data
0x80
0xF0
R/W
Write
Write
0x32
0x9E
Write
Two status bits, LOCKACQ (Register 0x04[3]) and LOCKLOST
(Register 0x04[2]) are available to signal proper operation of the
control loop. If the current phase is more than five steps away
from the desired phase and the LOCKACQ bit was previously
set, the LOCKACQ bit is cleared and the LOCKLOST interrupt
bit is set. Furthermore, if lock is lost, the controller can remain
in the tracking loop, or it can be reset to start the search again.
0x3E
0x38
Write
0x24
0x24
0x2F
0x00
0x80
0xCE
Write
Write
Write
0x33
0x39
0x42
0x4E
Write
Write
0x3A
0x6C
Write
0x03
0x04
0x03
0x33
0x00
0xFE
0x0C
0x43
Write
Write
Write
Write
0x33
0x33
0x04
0x4B
0x43
Write
Write
Read
By setting the MUSAMP bit high (Register 0x33[3]) from a low
state, the user can read back the mu delay value that the controller
locked to by reading the MUDLY bits (Register 0x39[7] and
Register 0x3A[7:0]), as well as the phase it locked to by reading
back the MUPHZ[4:0] bits (Register 0x39[4:0]). These bits will
no longer read back the value that the search started at or the
desired phase, but instead will read back the mu delay line value
and phase that the controller is locked to.
0x39
Rev. A | Page 60 of 76
Read
Description
Enable duty cycle correction.
Set common-mode level of CLKN:
CLKN_CML = 0xF.
Set common-mode level of CLKP:
CLKP_CML = 0xF.
Set direction of CLKP_CML and
CLKN_CML: PSIGN = 0; NSIGN = 0.
Enable clock receiver: CLK_DIS = 1.
Set phase comparator boost
(AUTO_CAL must be set to its
default value, 1).
Enable digital clocks.
Search for exact phase with a guard
band of 98 codes from endpoints.
Set search slope to positive.
Set search phase to 14,
search up and down.
Set start point of search to midpoint of mu delay line (Code 216).
Disable lock and lock lost indicators.
Clear lock and lock lost indicators.
Enable lock and lock lost indicators.
Enable mu delay controller and
start search/track routine.
Set mu phase read bit high.
Set mu phase read bit low.
Check lock and lock lost bits:
LOCKACQ should be on.
LOCKLOST should be off.
Check phase readback (should be
equal to 14).
AD9789
Operating the Mu Controller in Manual Mode
INTERRUPT REQUESTS
In manual mode, the user must sweep through all the mu delay
values and record the phase value at each value of MUDLY as
shown in Figure 118. Every time that the MUDLY value is
stepped, the MUSAMP bit must be toggled from low to high
to read the corresponding phase for the specified mu delay line
value. It is not possible to keep read high and continuously read
back the phase value. As with auto mode, the optimal ac performance occurs at a positive slope and a phase of 14; therefore,
when the curve is complete, choose the MUDLY value that
corresponds to this condition and write that value to the
MUDLY[8:0] bits (Register 0x39[7] and Register 0x3A).
The following interrupt (IRQ) requests can be used for additional
information and verification of the status of various functional
blocks:
•
Calculating Mu Delay Line Step Size
•
Stepping through all of the mu delay line values and plotting
mu phase vs. mu delay not only allows the user to find the
optimal mu delay value, but can also allow the user to determine
the mu delay line step size. To calculate the step size, take one
full cycle of the mu phase curve and divide the period of the
DAC clock by this delta. From Figure 118, the two transition
points are approximately 56 and 270, providing a delta of approximately 214 steps. Therefore, the mu delay line step size would
be approximately 2 ps/step, as shown in the following equation:
⎛
⎞
1
⎜
⎟
⎜ 2.4 GHz ⎟
⎝
⎠ = 1.95 ps
214
If the mu controller is enabled, this value allows the user to
calculate (in picoseconds) how much drift is in their system
with respect to the DAC clock period over temperature.
•
•
•
•
PARERR—triggered when one or more parity errors
occurs on the data bus
PARMSET—triggered when PARMNEW is set and
internally registered
PARMCLR—triggered when PARMNEW is cleared and
internally registered
LOCKACQ—triggered when the mu controller is locked to
the user-defined phase
LOCKLOST—triggered when the mu controller loses lock
(if the LOCKACQ bit was previously set)
SATERR—triggered when one or more saturation errors
occurs
Each IRQ is enabled using the enable bits in the interrupt
enable register, Register 0x03. The status of the IRQ can be
measured in one of the following ways: via the SPI bits found in
the interrupt status/clear register (Register 0x04) or using the
IRQ pin (Pin P2).
If the pin is used to determine that an interrupt has occurred,
it is necessary to check Register 0x04 to determine which bit
caused the interrupt because the pin indicates only that an
interrupt has occurred. To clear an IRQ, it is necessary to write
a 1 to the bit in Register 0x04 that corresponds to the interrupt.
Rev. A | Page 61 of 76
AD9789
RECOMMENDED START-UP SEQUENCE
The steps necessary to optimize the performance of the part and generate an output waveform are listed in Table 79.
Table 79. Recommended System Start-Up Sequence
Step
0
0
1
1
2
3
4
4
4
4
5
6
7
8
9
9
9
9
9
9
9
10
11
12
13
14
15
1
Description
Power up the AD9789.
Apply the clock.
Enable the clock receiver and set the clock CML.
Enable duty cycle correction.
Enable digital clocks.
Set up mu controller.
Disable all interrupts.
Clear all interrupts.
Enable mu control interrupts.
Enable mu delay controller.
Set up digital datapath.
Set up rate converter.
Set up BPF center frequency.
Set up interface.
Set up channel gains.
Set up spectral invert.
Set up full-scale current.
Wait until mu delay controller is locked (SPI read) 1 .
Update rate converter and BPF.
Update interface clocks.
Enable channels.
Enable other interrupts if desired.
Register
Data
0x32
0x30
0x24
0x24
0x2F
0x33
0x39
0x3A
0x03
0x04
0x03
0x33
0x06 to 0x15
0x16 to 0x1B
0x1C to 0x1D
0x20 to 0x23
0x25 to 0x28
0x29
0x3C to 0x3D
0x04
0x1E
0x24
0x24
0x05
0x03
0x9E
0x80
0x00
0x80
0xCE
0x42
0x4E
0x6C
0x00
0xFE
0x0C
0x43
Typical lock time of the mu controller is approximately 180,000 DAC cycles (at 2 GSPS, ~75 μs).
Rev. A | Page 62 of 76
0x08
0x80
0x00
0x80
AD9789
CUSTOMER BIST MODES
USING THE INTERNAL PRN GENERATOR TO TEST
QAM OUTPUT AC PERFORMANCE
The AD9789 can be configured to enable an on-chip pseudorandom number (PRN) generator. The PRN output is connected
to the front end of the datapath and disconnects the datapath
from the input pins. In this way, the PRN generator can be used
in conjunction with the on-chip QAM encoder to generate a
QAM output. The PRN generator allows the user to measure
the ac performance of a QAM signal at the DAC output without
an external data source. To enable the internal PRN generator
via the serial port, follow these steps.
1.
Ensure that the clock is enabled and that the clock
common-mode level is set to its optimal value by setting
the registers in Table 80 to the values shown in the table.
After the PRN generator is started, users can freely configure
the datapath for their desired test configuration as long as
Register 0x40 to Register 0x55 are not modified.
To disable the PRN generator, write 0x00 to Register 0x40.
USING THE INTERNAL BUILT-IN SELF-TEST (BIST)
TO TEST FOR DIGITAL DATA INPUT CONNECTIVITY
The AD9789 includes an internal built-in self-test (BIST) engine
that processes incoming data and creates a signature that can be
read back via the serial port. This BIST feature can be configured
to observe the static state of the digital data input pins (L4 to
L12, M4 to M12, N5 to N12, and P5 to P12) and to reflect the
state of these pins via the signature registers (Register 0x50 to
Register 0x55). In this way, the user can verify digital data input
connectivity.
Table 80. Register Settings to Configure the Clock
Testing Connectivity for LVDS Interface Mode
Register
0x30
0x31
Data
0x80
0xF0
To test the connectivity of the digital data input pins in LVDS
interface mode, follow these steps.
0x32
0x9E
2.
Description
Enable duty cycle correction.
Set the common-mode level of CLKN:
CLKN_CML = 0xF.
Set the common-mode level of CLKP:
CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.
Enable clock receiver (CLK_DIS = 1).
Configure BIST mode for PRN generation and disconnect
the inputs by setting the registers in Table 81 to the values
shown in the table.
1.
Ensure that the clock is enabled and that the clock
common-mode level is set to its optimal value by setting
the registers in Table 83 to the values shown in the table.
Table 83. Register Settings to Configure the Clock
Register
0x30
0x31
Data
0x80
0xF0
0x32
0x9E
Table 81. Register Settings to Configure PRN Generation
Register
0x42
0x43
0x44
0x45
0x46
0x47
0x49
0x4B
0x4C
0x4D
0x05
3.
4.
Setting
0x10
0x00
0x10
0x00
0x00
0x10
0x16
0x17
0x4E
0x1F
0x0F
2.
3.
Cycle the PARMNEW bit to ensure that the digital clocks
are active by first setting Register 0x24 to 0x00, and then
setting Register 0x24 to 0x80.
Configure the LVDS interface for high speed, 16-bit bus
width, 16-bit data width operation by setting the registers
in Table 84 to the values shown in the table.
Table 84. Register Settings for LVDS Interface
Cycle the PARMNEW bit to ensure that the digital clocks
are active by first setting Register 0x24 to 0x00, and then
setting Register 0x24 to 0x80.
Start PRN generation by setting the registers in Table 82 to
the values shown in the table.
Register
0x20
0x21
0x22
0x23
Table 82. Register Settings to Start PRN Generation
Register
0x48
0x4A
0x40
Description
Enable duty cycle correction.
Set the common-mode level of CLKN:
CLKN_CML = 0xF.
Set the common-mode level of CLKP:
CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.
Enable clock receiver (CLK_DIS = 1).
Setting
0xAB
0xAB
0x56
Rev. A | Page 63 of 76
Setting
0x08
0x41
0x1F
0x87
AD9789
4.
Configure pin mode by setting the registers in Table 85 to
the values shown in the table.
Table 85. Register Settings to Configure Pin Modes
Register
0x42
0x43
0x44
0x45
0x46
0x47
0x49
0x4B
0x4C
0x4D
5.
6.
7.
3.
Setting
0x00
0x08
0x00
0x08
0x00
0x10
0x1C
0x1C
0x00
0x00
Register
0x20
0x21
0x22
0x23
4.
Table 86. Register Settings for BIST Pin Test
8.
Setting
0x80
0x80
0x55
Read back the signature registers (Register 0x50 to
Register 0x55) to determine the pin states (see Table 87).
5.
Ensure that the clock is enabled and that the clock
common-mode level is set to its optimal value by setting
the registers in Table 88 to the values shown in the table.
Table 88. Register Settings to Configure the Clock
Data
0x80
0xF0
0x32
0x9E
Cycle the PARMNEW bit to ensure that the interface
configuration was updated by first setting Register 0x24
to 0x00, and then setting Register 0x24 to 0x80.
Apply static CMOS data to the input ports.
Enable the BIST pin test by setting the registers in Table 91
to the values shown in the table.
Register
0x48
0x4A
0x40
To test the connectivity of the digital data input pins in CMOS
interface mode, follow these steps.
Register
0x30
0x31
Setting
0x00
0x08
0x00
0x08
0x00
0x10
0x1C
0x1C
0x00
0x00
Table 91. Register Settings for BIST Pin Test
Testing Connectivity for CMOS Interface Mode
1.
Configure pin mode by setting the registers in Table 90 to
the values shown in the table.
Register
0x42
0x43
0x44
0x45
0x46
0x47
0x49
0x4B
0x4C
0x4D
6.
7.
Associated LVDS Pairs
Data bits D[7:0]
Data bits D[15:8]
Parity PAR
Data bits D[7:0] (repeated)
Data bits D[15:8] (repeated)
Parity PAR (repeated)
Setting
0x08
0x61
0x1F
0x87
Table 90. Register Settings to Configure Pin Modes
Table 87. Signature Register Settings
Register
0x50
0x51
0x52
0x53
0x54
0x55
Cycle the PARMNEW bit to ensure that the digital clocks
are active by first setting Register 0x24 to 0x00, and then
setting Register 0x24 to 0x80.
Configure the CMOS interface for high speed, 32-bit bus
width, 16-bit data width operation by setting the registers
in Table 89 to the values shown in the table.
Table 89. Register Settings for CMOS Interface
Cycle the PARMNEW bit to ensure that the interface
configuration was updated by first setting Register 0x24
to 0x00, and then setting Register 0x24 to 0x80.
Apply static LVDS data to the input ports.
Enable the BIST pin test by setting the registers in Table 86
to the values shown in the table.
Register
0x48
0x4A
0x40
2.
Description
Enable duty cycle correction.
Set the common-mode level of CLKN:
CLKN_CML = 0xF.
Set the common-mode level of CLKP:
CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.
Enable clock receiver (CLK_DIS = 1).
8.
Setting
0x80
0x80
0x55
Read back the signature registers (Register 0x50 to Register
0x55) to determine the pin states (see Table 92).
Table 92. Signature Register Settings
Register
0x50
0x51
0x52
0x53
0x54
0x55
Rev. A | Page 64 of 76
Associated CMOS Pairs
Data bits D[23:16]
Data bits D[31:24]
Parity P1
Data bits D[7:0]
Data bits [D15:8]
Parity P0
AD9789
QAM CONSTELLATION MAPS
Q
IKQK = 10
Q
1001
0010
0011
1010
1000
0000
0001
1101
1100
0100
0110
1111
1110
0101
0111
IKQK = 11
10011
00110
00010
10010
10101
10001
00100
00101
00111
10110
10100
10000
00000
00001
00011
I
11011
11001
11000
01000
01100
01110
IKQK = 01
11111
11101
11100
01001
01101
01010
IKQK ARE THE TWO MSBs IN EACH QUADRANT.
11010
11110
01011
01111
IKQK = 11
I
IKQK = 01
07852-087
1011
IKQK = 00
10111
IKQK = 00
07852-086
IKQK = 10
IKQK ARE THE TWO MSBs IN EACH QUADRANT.
Figure 121. DVB-C 16-QAM Constellation
Figure 123. DVB-C 32-QAM Constellation
11
Q
IKQK = 10
101100 101110 100110 100100
001000 001001 001101 001100
101101 101111 100111 100101
001010 001011 001111 001110
101001 101011 100011 100001
9
IKQK = 00
IKQK = 10
7
π/2 ROTATION
000010 000011 000111 000110
11010
11011
01011
01010
11000
11001
01001
01000
10000
10001
10101
10100
11100
11101
10010
10011
10111
10110
11110
11111
00010
00011
00111
00110
01110
01111
00000
00001
00101
00100
01100
01101
1
3
5
7
9
11
IKQK = 00
101000 101010 100010 100000
000000 000001 000101 000100
110100 110101 110001 110000
010000 010010 011010 011000
110110 110111 110011 110010
010001 010011 011011 011001
111110 111111 111011 111010
010101 010111 011111 011101
111100 111101 111001 111000
010100 010110 011110 011100
3
I
1
IKQK = 01
IKQK ARE THE TWO MSBs IN EACH QUADRANT.
IKQK = 11
IKQK = 01
π ROTATION
3π/2 ROTATION
07852-088
IKQK = 11
IKQK ARE THE TWO MSBs IN EACH QUADRANT.
Figure 124. DVB -C128-QAM Constellation3
Figure 122. DVB-C 64-QAM Constellation
Rev. A | Page 65 of 76
07852-089
5
AD9789
13
IKQK = 10
π/2 ROTATION
11
9
7
5
3
1
0000
0001
0101
0100
0100
0101
0001
0000
0010
0011
0111
0110
0110
0111
0011
0010
1011
1111
1110
1110
1111
1011
1010
1010
10
11
1101
1001
1000
1000
1001
1101
1100
1100
1101
1001
1000
1010
1011
1111
1110
1110
1111
1011
1010
0010
0011
0111
0110
0110
0111
0011
0010
0101
0001
0000
11
13
15
10
1000 1001 1101 1100 11 1100
00
00
IKQK = 00
01
0000
0001 0101 0100 01 0100
1
3
5
7
9
IKQK = 11
IKQK = 01
π ROTATION
3π/2 ROTATION
07852-090
15
IKQK ARE THE TWO MSBs IN EACH QUADRANT.
Figure 125. DVB-C 256-QAM Constellation
Q
C5 C4 C3, C2 C1 C0
110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111
110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010
100,111 101,011 000,111 001,011 000,101 001,111 010,101 011,111
100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010
I
010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101
010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110
110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101
07852-091
110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110
Figure 126. DOCSIS 64-QAM Constellation
Rev. A | Page 66 of 76
AD9789
Q
1110, 1111, 1110, 1111, 1110, 1111, 1110, 1111, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1111 1101 1011 1001 0111 0101 0011 0001 1111 1111 1111 1111 1111 1111 1111 1111
C7 C6 C5 C4,
C3 C2 C1 C0
1100, 1101, 1100, 1101, 1100, 1101, 1100, 1101, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1110 1100 1010 1000 0110 0100 0010 0000 1100 1100 1100 1100 1100 1100 1100 1100
1010, 1011, 1010, 1011, 1010, 1011, 1010, 1011, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1111 1101 1011 1001 0111 0101 0011 0001 1011 1011 1011 1011 1011 1011 1011 1011
1000, 1001, 1000, 1001, 1000, 1001, 1000, 1001, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1110 1100 1010 1000 0110 0100 0010 0000 1000 1000 1000 1000 1000 1000 1000 1000
0110, 0111, 0110, 0111, 0110, 0111, 0110, 0111, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1111 1101 1011 1001 0111 0101 0011 0001 0111 0111 0111 0111 0111 0111 0111 0111
0100, 0101, 0100, 0101, 0100, 0101, 0100, 0101, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1110 1100 1010 1000 0110 0100 0010 0000 0100 0100 0100 0100 0100 0100 0100 0100
0010, 0011, 0010, 0011, 0010, 0011, 0010, 0011, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1111 1101 1011 1001 0111 0101 0011 0001 0011 0011 0011 0011 0011 0011 0011 0011
0000, 0001, 0000, 0001, 0000, 0001, 0000, 0001, 0000, 0011, 0100, 0111, 1000, 1011, 1100, 1111,
1110 1100 1010 1000 0110 0100 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0000, 0001, 0000, 0001, 0000, 0001, 0000, 0001,
0001 0001 0001 0001 0001 0001 0001 0001 0001 0011 0101 0111 1001 1011 1101 1111
I
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0010, 0011, 0010, 0011, 0010, 0011, 0010, 0011,
0010 0010 0010 0010 0010 0010 0010 0010 0000 0010 0100 0110 1000 1010 1100 1110
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0100, 0101, 0100, 0101, 0100, 0101, 0100, 0101,
0101 0101 0101 0101 0101 0101 0101 0101 0001 0011 0101 0111 1001 1011 1101 1111
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 0110, 0111, 0110, 0111, 0110, 0111, 0110, 0111,
0110 0110 0110 0110 0110 0110 0110 0110 0000 0010 0100 0110 1000 1010 1100 1110
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1000, 1001, 1000, 1001, 1000, 1001, 1000, 1001,
1001 1001 1001 1001 1001 1001 1001 1001 0001 0011 0101 0111 1001 1011 1101 1111
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1010, 1011, 1010, 1011, 1010, 1011, 1010, 1011,
1010 1010 1010 1010 1010 1010 1010 1010 0000 0010 0100 0110 1000 1010 1100 1110
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1110, 1111, 1110, 1111, 1110, 1111, 1110, 1111,
1110 1110 1110 1110 1110 1110 1110 1110 0000 0010 0100 0110 1000 1010 1100 1110
Figure 127. DOCSIS 256-QAM Constellation
Rev. A | Page 67 of 76
07852-126
1110, 1101, 1010, 1001, 0110, 0101, 0010, 0001, 1100, 1101, 1100, 1101, 1100, 1101, 1100, 1101,
1101 1101 1101 1101 1101 1101 1101 1101 0001 0011 0101 0111 1001 1011 1101 1111
AD9789
CHANNELIZER MODE PIN MAPPING FOR CMOS AND LVDS
Table 94 and Table 95, along with Figure 128 and Figure 129,
describe CMOS and LVDS data input pin mapping. CMOS
mode is always single data rate and samples on the rising edge
of DSC. LVDS mode is single data rate (SDR) for bus widths
of 4 bits through 16 bits and double data rate (DDR) for a bus
width of 32 bits.
Table 93. Data Input Configurations for Channelizer Mode
Bus Width
4
4
8
8
8
16
16
16
32
32
32
Data Width
8
8
8
8
16
8
8
16
8
8
16
Data Format
Real
Complex
Real
Complex
Complex
Real
Complex
Complex
Real
Complex
Complex
1
2
3
4
5
6
7
8
9
10 11
12 13 14
A
B
C
D
E
F
G
H
J
K
L
P1
31 27 23 19 15
11
7
3
BU
CMOS_BUS
M
P0
30 26 22 18 14 10
6
2
CT
CMOS_CTRL
N
29 25 21 17 13
9
5
1
FS
CMOS_FS
P
28 24 20 16 12
8
4
0
DC
CMOS_DCO
D[31:0] CMOS DATA INPUTS
07852-127
Table 93 lists the available combinations of data input configuration parameters when the AD9789 is in channelizer mode.
Many of these configurations require multiple clocks to load all
channels. All of these configurations are described in detail in
Table 96 and Table 97.
PARITY AND CONTROL INPUTS
Figure 128. CMOS Data Input Pin Mapping
1
2
3
4
5
6
7
8
9
10 11
12 13 14
A
B
C
D
E
F
Table 94. CMOS Pin Assignments for Various Interface Widths
Pin Assignments
D[3:0]
D[7:0]
D[15:0]
D[31:0]
BUSWDTH[1:0]
00
01
10
11
H
PARP
J
PARN
K
Table 95. LVDS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
Pin Assignments
D[3:0]P, D[3:0]N
D[7:0]P, D[7:0]N
D[15:0]P, D[15:0]N
D[15:0]P, D[15:0]N rising
edge and falling edge
BUSWDTH[1:0]
00
01
10
11
Rev. A | Page 68 of 76
FSP
L
P+
15 13
11
9
7
5
3
1
FS
FSN
M
P–
15 13
11
9
7
5
3
1
FS
DCOP
N
14 12 10
8
6
4
2
0
DC
DCON
P
14 12 10
8
6
4
2
0
DC
14 +LVDS
14 –LVDS
Figure 129. LVDS Data Input Pin Mapping
07852-128
Interface Width
4 bits
8 bits
16 bits
32 bits
G
AD9789
In Table 96, “R” represents real data loaded to a given channel, “I” represents the in-phase term, and “Q” represents the quadrature term
of complex data. The channel number follows R, I, or Q.
Table 96. Channelizer Mode Configurations and Channel Construction: CMOS Interface, Channel Prioritization = 1
Datapath Configuration
BW
DW
Format
4
8
Real
Datapath Configuration
BW
DW
Format
4
8
Complex
Datapath Configuration
BW
DW
Format
8
8
Real
Datapath Configuration
BW
DW
Format
8
8
Complex
DCO
1
2
3
4
5
6
7
8
[D31:D28]
[D27:D24]
CMOS Pin Mapping
[D23:D20] [D19:D16] [D15:D12]
[D11:D8]
[D7:D4]
[D3:D0]
R0
R0
R1
R1
R2
R2
R3
R3
[D11:D8]
[D7:D4]
[D3:D0]
I0
I0
Q0
Q0
I1
I1
Q1
Q1
I2
I2
Q2
Q2
I3
I3
Q3
Q3
[D11:D8]
[D7:D4]
DCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
[D31:D28]
[D27:D24]
CMOS Pin Mapping
[D23:D20] [D19:D16] [D15:D12]
DCO
1
2
3
4
[D31:D28]
[D27:D24]
CMOS Pin Mapping
[D23:D20] [D19:D16] [D15:D12]
DCO
1
2
3
4
5
6
7
8
[D31:D28]
[D3:D0]
R0
R1
R2
R3
[D27:D24]
CMOS Pin Mapping
[D23:D20] [D19:D16] [D15:D12]
[D11:D8]
[D7:D4]
[D3:D0]
I0
Q0
I1
Q1
I2
Q2
I3
Q3
Rev. A | Page 69 of 76
AD9789
Datapath Configuration
BW
DW
Format
8
16
Complex
Datapath Configuration
BW
DW
Format
16
8
Real
Datapath Configuration
BW
DW
Format
16
8
Complex
Datapath Configuration
BW
DW
Format
16
16
Complex
Datapath Configuration
BW
DW
Format
32
8
Real
Datapath Configuration
BW
DW
Format
32
8
Complex
Datapath Configuration
BW
DW
Format
32
16
Complex
DCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
[D31:D28]
DCO
1
2
[D31:D28]
DCO
1
2
3
4
DCO
1
2
3
4
5
6
7
8
DCO
1
DCO
1
2
DCO
1
2
3
4
[D27:D24]
CMOS Pin Mapping
[D23:D20] [D19:D16] [D15:D12]
[D11:D8]
[D7:D4]
[D3:D0]
I0
I0
Q0
Q0
I1
I1
Q1
Q1
I2
I2
Q2
Q2
I3
I3
Q3
Q3
CMOS Pin Mapping
[D23:D20] [D19:D16] [D15:D12] [D11:D8]
R1
R3
CMOS Pin Mapping
[D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8]
Q0
Q1
Q2
Q3
CMOS Pin Mapping
[D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8]
I0
Q0
I1
Q1
I2
Q2
I3
Q3
CMOS Pin Mapping
[D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8]
R3
R2
R1
CMOS Pin Mapping
[D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8]
Q1
I1
Q0
Q3
I3
Q2
CMOS Pin Mapping
[D31:D28] [D27:D24] [D23:D20] [D19:D16] [D15:D12] [D11:D8]
Q0
I0
Q1
I1
Q2
I2
Q3
I3
[D27:D24]
Rev. A | Page 70 of 76
[D7:D4]
[D3:D0]
R0
R2
[D7:D4]
[D3:D0]
I0
I1
I2
I3
[D7:D4]
[D3:D0]
[D7:D4]
[D3:D0]
R0
[D7:D4]
[D3:D0]
I0
I2
[D7:D4]
[D3:D0]
AD9789
In DDR mode, “rise” corresponds to data sampled on the rising edge of DSC; “fall” corresponds to data sampled on the falling edge of DSC.
Table 97. Channelizer Mode Configurations and Channel Construction: LVDS Interface, Channel Prioritization = 1
Datapath Configuration
BW
DW
Format
4
8
Real
Datapath Configuration
BW
DW
Format
4
8
Complex
Datapath Configuration
BW
DW
Format
8
8
Real
Datapath Configuration
BW
DW
Format
8
8
Complex
[D15:D12]
LVDS Pin Mapping
[D11:D8]
[D7:D4]
DCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
[D15:D12]
LVDS Pin Mapping
[D11:D8]
[D7:D4]
DCO
1
2
3
4
[D15:D12]
LVDS Pin Mapping
[D11:D8]
[D7:D4]
DCO
1
2
3
4
5
6
7
8
[D15:D12]
DCO
1
2
3
4
5
6
7
8
[D3:D0]
R0
R0
R1
R1
R2
R2
R3
R3
[D3:D0]
I0
I0
Q0
Q0
I1
I1
Q1
Q1
I2
I2
Q2
Q2
I3
I3
Q3
Q3
[D3:D0]
R0
R1
R2
R3
LVDS Pin Mapping
[D11:D8]
[D7:D4]
[D3:D0]
I0
Q0
I1
Q1
I2
Q2
I3
Q3
Rev. A | Page 71 of 76
AD9789
Datapath Configuration
BW
DW
Format
8
16
Complex
Datapath Configuration
BW
DW
Format
16
8
Real
Datapath Configuration
BW
DW
Format
16
8
Complex
Datapath Configuration
BW
DW
Format
16
16
Complex
Datapath Configuration
BW
DW
Format
32
8
Real
Datapath Configuration
BW
DW
Format
32
8
Complex
DCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
[D15:D12]
DCO
1
2
[D15:D12]
LVDS Pin Mapping
[D11:D8]
[D7:D4]
[D3:D0]
I0
I0
Q0
Q0
I1
I1
Q1
Q1
I2
I2
Q2
Q2
I3
I3
Q3
Q3
LVDS Pin Mapping
[D11:D8]
[D7:D4]
R1
R3
DCO
1
2
3
4
[D15:D12]
DCO
1
2
3
4
5
6
7
8
[D15:D12]
DCO
1 rise
1 fall
[D15:D12]
DCO
1 rise
1 fall
2 rise
2 fall
[D15:D12]
LVDS Pin Mapping
[D11:D8]
[D7:D4]
Q0
Q1
Q2
Q3
[D3:D0]
I0
I1
I2
I3
LVDS Pin Mapping
[D11:D8]
[D7:D4]
I0
Q0
I1
Q1
I2
Q2
I3
Q3
LVDS Pin Mapping
[D11:D8]
[D7:D4]
R1
R3
[D3:D0]
[D3:D0]
R0
R2
LVDS Pin Mapping
[D11:D8]
[D7:D4]
Q0
Q1
Q2
Q3
Rev. A | Page 72 of 76
[D3:D0]
R0
R2
[D3:D0]
I0
I1
I2
I3
AD9789
Datapath Configuration
BW
DW
Format
32
16
Complex
DCO
1 rise
1 fall
2 rise
2 fall
3 rise
3 fall
4 rise
4 fall
[D15:D12]
Rev. A | Page 73 of 76
LVDS Pin Mapping
[D11:D8]
[D7:D4]
I0
Q0
I1
Q1
I2
Q2
I3
Q3
[D3:D0]
AD9789
OUTLINE DIMENSIONS
12.00 BSC SQ
A1 BALL
CORNER
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
10.40
BSC SQ
F
G
H
J
0.80
BSC
K
L
M
N
P
*1.30
1.22
1.14
0.80
REF
BOTTOM VIEW
DETAIL A
0.65
REF
DETAIL A
0.38
0.33
0.28
0.24
REF
SEATING
PLANE
0.96
0.89
0.82
0.53
COPLANARITY
0.08
0.48
0.43
BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-219 WITH THE EXCEPTION
TO PACKAGE HEIGHT.
111808-A
TOP VIEW
Figure 130. 164-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-164-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9789BBCZ
AD9789BBCZRL
AD9789BBC
AD9789BBCRL
AD9789-EBZ
AD9789-MIX-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
164-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
164-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
164-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
164-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
Evaluation Board for CMTS and Normal Mode Evaluation
Evaluation Board for Mix Mode Evaluation
Z = RoHS Compliant Part.
Rev. A | Page 74 of 76
Package Option
BC-164-1
BC-164-1
BC-164-1
BC-164-1
AD9789
NOTES
Rev. A | Page 75 of 76
AD9789
NOTES
©2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07852-0-7/11(A)
Rev. A | Page 76 of 76