Schematic for the STK672-440BNGEVB Evaluation Board JP13 JP12 VDD (5V) R08 C03 R03 R09 R10 R01 R04 R05 R07 R06 LED JP9 ⑤ ② ③ ④ RESETB ENABLE ① A JP6 COM1 JP7 JP10 JP02 Example of the parallel connection JP03 JP8 JP04 Vcc AB JP05 B BB Vref COM2 JP11 R02 C09 C08 C10 C01 GND C04 C05 C07 C06 P.GND S.GND FAULT2 JP21 8 MOI or VrefOP 9 JP22 2相ステッピングモータ 10 JP19 A 4 11 CLOCK 13 14 Vref JP16 No ① ② ③ ④ ⑤ 1/7/2014 5 12 JP15 -4xx -6xx MODE2 MODE1 CLOCK CWD MODE3 -7xx φAB φBB φB φA N.C JP14 C02 STK672 -xxx JP17 17 1 16 2 6 19 COM1 JP20 18 AB B 3 15 JP01 7 BB COM2 P.G2 P.G1 JP18 -1- www.onsemi.com