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RT8071D
3A, 1MHz, Synchronous Step-Down Converter
General Description
Features
The RT8071D is a high efficiency synchronous, step-down
DC/DC converter. Its input voltage ranges from 2.7V to
5.5V that provides an adjustable regulated output voltage
from 0.6V to VIN while delivering up to 3A of output current.

High Efficiency : Up to 95%

The internal synchronous low On-resistance power
switches increase efficiency and eliminate the need for
an external Schottky diode. The switching frequency is
fixed internally at 1MHz. The 100% duty cycle provides
low dropout operation, hence extending battery life in
portable systems. Current mode operation with internal
compensation allows the transient response to be
optimized over a wide range of loads and output capacitors.
The RT8071D is available in the WDFN-10L 3x3 package.

High Efficiency at Light Load
Ω/49mΩ
Ω
Low RDS(ON) Power Switches : 69mΩ
Fixed Frequency : 1MHz
No Schottky Diode Required
Internal Compensation
0.6V Reference Allows Low Output Voltage
Low Dropout Operation : 100% Duty Cycle
OCP, UVP, OTP






Applications

Portable Instruments

Battery Powered Equipments
Notebook Computers
Distributed Power Systems
IP Phones
Digital Cameras

Ordering Information

RT8071D

Package Type
QW : WDFN-10L 3x3 (W-Type)

Lead Plating System
G : Green (Halogen Free and Pb free)
Marking Information
5R= : Product Code
Note :

YMDNN : Date Code
5R=YM
DNN
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
RT8071D
VIN
SW
VIN
VCC
FB
Enable
EN
VOUT
PGOOD
PGOOD
GND
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8071D-01
June 2015
is a registered trademark of Richtek Technology Corporation.
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1
RT8071D
Pin Configurations
FB
VCC
VIN
GND
GND
1
2
3
4
5
GND
(TOP VIEW)
10
9
11
8
7
6
EN
PGOOD
NC
SW
SW
WDFN-10L 3x3
Functional Pin Description
Pin No.
Pin Name
Pin Function
Feedback Input. This pin receives the feedback voltage from a resistive
voltage divider connected across the output.
Supply Voltage Input. Decouple this pin to GND with at least 1F ceramic
capacitor.
Power Input. Decouple this pin to GND with at least 10F ceramic capacitor.
1
FB
2
VCC
3
VIN
4, 5,
11 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND f or maximum power dissipation.
6, 7
SW
Switch Node. Connect this pin to the inductor.
8
NC
No Internal Connection.
9
PGOOD
Power Good Indicator. This pin is an open drain logic output. The PGOOD will
be pulled to ground when the output voltage is less than 90% of the target
output voltage.
10
EN
Enable Control Input. Pull high the EN pin to turn on the converter.
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is a registered trademark of Richtek Technology Corporation.
DS8071D-01
June 2015
RT8071D
Function Block Diagram
EN
EN
PGOOD
PGOOD
VIN
ISEN
Slope
Com
OSC
VREF
0.6V
EA
FB
OC
Limit
Output
Clamp
Driver
Int-SS
SW
Control
Logic
0.54V
NISEN
PGOOD
POR
OTP
0.2V
GND
Current Limit
UV
VCC
Operation
The RT8071D is a synchronous low voltage Buck Converter
that can support the input voltage range from 2.7V to 5.5V
and the output current can be up to 3A. The RT8071D
uses a constant frequency, current mode architecture. In
normal operation, the high-side P-MOSFET is turned on
when the Switch Controller is set by the oscillator (OSC)
and is turned off when the current comparator resets the
switch controller. High-side MOSFET peak current is
measured by internal RSENSE. The Current Signal is
where Slope Compensator works together with sensing
voltage of RSENSE. The error amplifier EA adjusts COMP
voltage by comparing the feedback signal (VFB) from the
output voltage with the internal 0.6V reference. When the
load current increases, it causes a drop in the feedback
voltage relative to the reference, the COMP voltage then
rises to allow higher inductor current to match the load
current.
UV Comparator
Oscillator (OSC)
The internal oscillator runs at nominal frequency 1MHz.
PGOOD Comparator
When the feedback voltage (VFB) is higher than threshold
voltage 0.54V, the PGOOD open drain output will be high
impedance.
Enable
There is an internal pull down 500kΩ resistor at EN pin.
When the EN pin is higher than 1.6V, the converter will be
turned on. The EN pin can be connected to VIN through a
100kΩ resistor for automatic startup.
Soft-Start (SS)
An internal current source charges an internal capacitor
to build the soft-start ramp voltage. The VFB voltage will
track the internal ramp voltage during soft-start interval.
The maximum soft-start time is 200μs.
If the feedback voltage (VFB) is lower than threshold voltage
0.2V, the UV Comparator's output will go high and the
Switch Controller will turn off the high-side MOSFET.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8071D-01
June 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8071D
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VIN, VCC ----------------------------------------------------------------------------------- −0.3V to 6.5V
SW to GND
DC ------------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
< 20ns ------------------------------------------------------------------------------------------------------------------- −2.5V to 9V
 Other Pins --------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
 Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 --------------------------------------------------------------------------------------------------------- 1.429W
 Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA --------------------------------------------------------------------------------------------------- 70°C/W
WDFN-10L 3x3, θJC --------------------------------------------------------------------------------------------------- 8.2°C/W
 Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
 Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
 Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------------------------ 2kV


Recommended Operating Conditions



(Note 4)
Supply Input Voltage, VIN, VCC ----------------------------------------------------------------------------------- 2.7V to 5.5V
Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 3.3V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Unit
0.594
0.6
0.606
V
--
0.1
0.4
A
Active , V FB = 0.7V, Not Switching
--
110
170
Shutdown
--
--
1
Output Voltage Line Regulation
V IN = 2.7V to 5.5V, IOUT = 0A
--
0.3
--
%/V
Output Voltage Load Regulation
IOUT = 0A to 3A
1
--
1
%
Switch Leakage Current
--
--
1
A
Switching Frequency
0.8
1
1.2
MHz
Feedback Reference Voltage
V REF
Feedback Leakage Current
IFB
DC Bias Current
Switch On
Resistance
High-Side
RDS(ON)_P
V IN = 5V
--
69
--
Low-Side
RDS(ON)_N
V IN = 5V
--
49
--
4.8
--
--
V CC Rising
2.2
2.4
2.6
V CC Falling
2.2
--
2.4
--
P-MOSFET Current Limit
ILIM
Under-Voltage Lockout
Threshold
V UVLO
EN Input Voltage
Test Conditions
Logic-High
V IH
2
1.6
Logic-Low
V IL
--
--
0.4
TSD
---
500
150
---
EN Pull Low Resistance
Over Temperature Protection
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A
m
A
V
V
k
C
is a registered trademark of Richtek Technology Corporation.
DS8071D-01
June 2015
RT8071D
Parameter
Over-Temperature Protection
Hysteresis
Soft-Start Time
VOUT Discharge Resistance
VOUT Under-Voltage Protection
(Latch-Off)
Symbol
Test Conditions
tSS
Measures FB, With Respect to
V REF
Power Good
Power Good Hysteresis
Min
Typ
Max
Unit
--
20
--
C
---
-100
200
--
s

--
33
40
%
85
90
--
%
--
5
--
%
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8071D-01
June 2015
is a registered trademark of Richtek Technology Corporation.
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RT8071D
Typical Application Circuit
L
1.5µH
RT8071D
3 VIN
VIN
CIN
10µF
VOUT
COUT 1.05V
22µF x 2
SW 6, 7
2 VCC
CFF
560pF
C1
1µF
R3
100k
R1
6.2k
FB 1
9
PGOOD
Enable
R2
8.2k
PGOOD
10 EN
GND
4, 5,
11 (Exposed Pad)
Table 1. Recommended Component Selection
V OUT (V)
R1 (k)
R2 (k)
CFF (pF)
L (H)
C OUT (F)
3.3
37
8.2
430
2
22 x 2
2.5
26
8.2
430
2
22 x 2
1.8
16.5
8.2
510
1.5
22 x 2
1.5
12.3
8.2
560
1.5
22 x 2
1.2
8.2
8.2
620
1.5
22 x 2
1
5.6
8.2
680
1.5
22 x 2
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is a registered trademark of Richtek Technology Corporation.
DS8071D-01
June 2015
RT8071D
Typical Operating Characteristics
Output Voltage vs. Output Current
Efficiency vs. Output Current
1.07
100
90
1.06
70
Output Voltage (V)
Efficiency (%)
80
VIN = 5V, VOUT = 3.3V
VIN = 3.3V, VOUT = 1.05V
VIN = 5V, VOUT = 1.05V
60
50
40
30
1.05
VIN = 5V
VIN = 3.3V
1.04
1.03
20
1.02
10
IOUT = 0A to 3A
VOUT = 1.05V, IOUT = 0A to 3A
1.01
0
0.001
0.01
0.1
1
0
10
0.5
1
Output Voltage vs. Output Current
2.5
3
Switching Frequency vs. Temperature
1.4
Switching Frequency (MHz)1
3.34
3.33
Output Voltage (V)
2
Output Current (A)
Output Current (A)
3.32
3.31
3.30
3.29
VIN = 5V, VOUT = 3.3V, IOUT = 0A to 3A
3.28
1.3
1.2
1.1
1.0
0.9
VIN = 3.3V
VIN = 5V
0.8
0.7
0.6
0.5
VOUT = 1.05V, IOUT = 0.6A
0.4
0
0.5
1
1.5
2
2.5
3
-50
-25
0
Switching Frequency vs. Temperature
50
75
100
125
Reference Voltage vs. Temperature
0.65
1.3
0.64
1.2
0.63
Reference Voltage (V)
1.4
1.1
1.0
0.9
0.8
0.7
0.6
0.5
25
Temperature (°C)
Output Current (A)
Switching Frequency (MHz)1
1.5
VIN = 5V, VOUT = 3.3V, IOUT = 0.6A
0.4
0.62
0.61
0.60
0.59
0.58
0.57
0.56
IOUT = 0.6A
0.55
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8071D-01
June 2015
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT8071D
EN Threshold Voltage vs. Temperature
1.5
2.7
1.4
EN Threshold Voltage (V)
UVLO Threshold (V)
UVLO Threshold vs. Temperature
2.8
2.6
2.5
Rising
2.4
2.3
2.2
Falling
2.1
2.0
1.3
1.2
Rising
1.1
1.0
Falling
0.9
0.8
0.7
1.9
1.8
0.6
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Power On from Enable Voltage
Power Off from Enable Voltage
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(1V/Div)
VPGOOD
(5V/Div)
VOUT
(1V/Div)
VPGOOD
(5V/Div)
IOUT
(5A/Div)
IOUT
(5A/Div)
VIN = 5V, VOUT = 1.05V, IOUT = 4A
VIN = 5V, VOUT = 1.05V, IOUT = 4A
Time (100μs/Div)
Time (100μs/Div)
Power On from Enable Voltage
Power Off from Enable Voltage
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(2V/Div)
VPGOOD
(5V/Div)
VOUT
(2V/Div)
VPGOOD
(5V/Div)
IOUT
(5A/Div)
IOUT
(5A/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 4A
Time (100μs/Div)
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125
VIN = 5V, VOUT = 3.3V, IOUT = 4A
Time (100μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS8071D-01
June 2015
RT8071D
Application Information
The RT8071D is a single-phase step-down converter. It
provides single feedback loop, current mode control with
fast transient response. An internal 0.6V reference allows
the output voltage to be precisely regulated for low output
voltage applications. A fixed switching frequency (1MHz)
oscillator and internal compensation are integrated to
minimize external component count. Protection features
include over current protection, under voltage protection
and over temperature protection.
Output Voltage Setting
Connect a resistive voltage divider at the FB between VOUT
and GND to adjust the output voltage. The output voltage
is set according to the following equation :
VOUT = VREF   1 R1 
 R2 
where VREF is the feedback reference voltage 0.6V (typ.).
VOUT
R1
reduce the output surge current. The internal 0.6V
reference takes over the loop control once the internal
ramping-up voltage becomes higher than 0.6V.
UVLO Protection
The RT8071D has input Under-Voltage Lockout protection
(UVLO). If the input voltage exceeds the UVLO rising
threshold voltage (2.4V typ.), the converter resets and
prepares the PWM for operation. If the input voltage falls
below the UVLO falling threshold voltage during normal
operation, the device will stop switching. The UVLO rising
and falling threshold voltage has a hysteresis to prevent
noise-caused reset. The power sequence of the VCC and
VIN need to be considered if they are powered separately.
The driver voltage of high-side MOSET comes from VIN
input and internal control circuit is powered by VCC. The
VCC has to be powered earlier than the VIN to ensure
that the high-side MOSFET has never turned on before
the internal control circuit is ready. At power off, the voltage
at the VIN has to be removed before the VCC goes below
the threshold of UVLO.
FB
R2
GND
Figure 1. Setting VOUT with a Voltage Divider
Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as shown below:
L=
Chip Enable and Disable
The EN pin allows for power sequencing between the
controller bias voltage and another voltage rail. The
RT8071D remains in shutdown if the EN pin is lower than
400mV. When the EN pin rises above the VEN trip point,
the RT8071D begins a new initialization and soft-start cycle.
Internal Soft-Start
The RT8071D provides an internal soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is enabled. During softstart, the internal soft-start capacitor becomes charged
and generates a linear ramping up voltage across the
capacitor. This voltage clamps the voltage at the FB pin,
causing PWM pulse width to increase slowly and in turn
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8071D-01
June 2015
VOUT   VIN  VOUT 
fSW  LIR  ILOAD(MAX)  VIN
where LIR is the ratio of the peak-to-peak ripple current to
the average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(IPEAK) :
IPEAK = ILOAD(MAX) +  LIR  ILOAD(MAX) 
 2

The calculation above serves as a general reference. To
further improve transient response, the output inductor
can be further reduced. This relation should be considered
along with the selection of the output capacitor.
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RT8071D
Input Capacitor Selection
High quality ceramic input decoupling capacitor, such as
X5R or X7R, with values greater than 10μF are
recommended for the input capacitor. The X5R and X7R
ceramic capacitors are usually selected for power regulator
capacitors because the dielectric material has less
capacitance variation and more temperature stability.
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Generally, selecting an
input capacitor with voltage rating 1.5 times greater than
the maximum input voltage is a conservatively safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
IIN_RMS = ILOAD 
VOUT  VOUT 
 1
VIN 
VIN 
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor bank.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
IOUT(MAX)  0.25
VIN =
CIN  fSW
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the Buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
1

VP_P = LIR  ILOAD(MAX)   ESR +
8  COUT  fSW 

When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation :
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
Power Good Output (PGOOD)
PGOOD is an open-drain type output and requires a pullup resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
PGOOD signal goes low if the output is turned off or is
10% below its nominal regulation point.
Under-Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage. When under voltage protection is enabled, both
UGATE and LGATE gate drivers will be forced low if the
output is less than 33% of its set voltage threshold. The
UVP will be ignored for at least 3ms (typ.) after start up or
a rising edge on the EN threshold. Toggle EN threshold or
cycle VIN to reset the UVP fault latch and restart the
controller.
Over-Current Protection (OCP)
The RT8071D provides over-current protection by detecting
high-side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold,
the OCP will be triggered. When OCP is tripped, the
RT8071D will keep the over current threshold level until
the over current condition is removed.
VSAG = ILOAD  ESR
For a given output voltage sag specification, the ESR value
can be determined.
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is a registered trademark of Richtek Technology Corporation.
DS8071D-01
June 2015
RT8071D
Maximum Power Dissipation (W)1
Thermal Shutdown (OTP)
The device implements an internal thermal shutdown
function when the junction temperature exceeds 150°C.
The thermal shutdown forces the device to stop switching
when the junction temperature exceeds the thermal
shutdown threshold. Once the die temperature decreases
below the hysteresis of 20°C, the device reinstates the
power up sequence.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-10L 3x3 package, the thermal resistance, θJA, is
70°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formulas :
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8071D-01
June 2015
Four-Layer PCB
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve of Maximum Power Dissipation
Layout Considerations
Layout is very important in high frequency switching
converter design. The PCB can radiate excessive noise
and contribute to converter instability with improper layout.
Certain points must be considered before starting a layout
using the RT8071D.

Make the traces of the main current paths as short and
wide as possible.

Put the input capacitor as close as possible to the device
pins (VIN and GND).

SW node encounters high frequency voltage swings so
it should be kept in a small area. Keep sensitive
components away from the SW node to prevent stray
capacitive noise pick-up.

Ensure all feedback network connections are short and
direct. Place the feedback network as close to the chip
as possible.

The GND pin and Exposed Pad should be connected to
a strong ground plane for heat sinking and noise
protection.

An example of PCB layout guide is shown in Figure 3
for reference.
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance. The derating curve in Figure 2 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
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RT8071D
SW should be connected to
inductor by wide and short trace.
Keep sensitive components away
from this trace.
GND
The voltage divider must
be connected as close to
the device as possible.
R1
VOUT
R2
FB 1
CIN2
VCC 2
VIN 3
CIN1 GND 4
GND 5
11
10
9
8
7
6
REN
EN
PGOOD
RPGOOD
NC
L
SW
SW
VOUT
COUT
GND
Input capacitor must be placed
as close to the IC as possible.
VIN
The output capacitor must
be placed near the IC.
Figure 3. PCB Layout Guide
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS8071D-01
June 2015
RT8071D
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8071D-01
June 2015
www.richtek.com
13