ADSP-BF535 EZ-KIT Lite® Evaluation System Manual Revision 3.0, January 2005 Part Number 85-000603-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, VisualDSP++, the VisualDSP++ logo, Blackfin, CROSSCORE, the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Regulatory Compliance The ADSP-BF535 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark. The ADSP-BF535 EZ-KIT Lite evaluation system had been appended to Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file. The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. CONTENTS PREFACE Purpose of This Manual ................................................................. xiv Intended Audience ......................................................................... xiv Manual Contents ............................................................................ xv What’s New in This Manual ........................................................... xvi Technical or Customer Support ...................................................... xvi Supported Processors ..................................................................... xvii Product Information ..................................................................... xvii MyAnalog.com ........................................................................ xvii Processor Product Information ................................................ xviii Related Documents ................................................................ xviii Online Technical Documentation ............................................. xix Accessing Documentation From VisualDSP++ ....................... xx Accessing Documentation From Windows ............................. xx Accessing Documentation From Web ................................... xxi Printed Manuals ....................................................................... xxi VisualDSP++ Documentation Set ......................................... xxi Hardware Tools Manuals ..................................................... xxii Processor Manuals ............................................................... xxii ADSP-BF535 EZ-KIT Lite Evaluation System Manual v CONTENTS Data Sheets ........................................................................ xxii Notation Conventions .................................................................. xxii USING EZ-KIT LITE Package Contents ......................................................................... 1-2 Default Configuration .................................................................. 1-3 Installation and Session Startup ..................................................... 1-5 Evaluation License Restrictions ..................................................... 1-6 Memory Map ............................................................................... 1-6 SDRAM Interface ......................................................................... 1-7 Flash Memory .............................................................................. 1-8 Programmable Flag Pins .............................................................. 1-10 Power Management ............................................................... 1-11 Example Programs ...................................................................... 1-12 Flash Programmer Utility ............................................................ 1-12 Background Telemetry Channel .................................................. 1-12 VisualDSP++ Interface ................................................................ 1-13 Trace Window ...................................................................... 1-13 Enabling Trace Buffer ....................................................... 1-14 Reading Trace Buffer Data ................................................ 1-14 Performance Monitor ............................................................ 1-15 Boot Load ............................................................................. 1-16 Context Switching ................................................................ 1-16 Using M3 Register ............................................................ 1-16 Using Stack Pointer .......................................................... 1-17 vi ADSP-BF535 EZ-KIT Lite Evaluation System Manual CONTENTS Hardware Breakpoints ........................................................... 1-18 Global Breakpoint Options ............................................... 1-18 Common Breakpoint Attributes ........................................ 1-18 Data Breakpoints .............................................................. 1-18 Data Breakpoint Specific Attributes ............................... 1-19 Instruction Breakpoints ..................................................... 1-19 Instruction Breakpoint Specific Attributes ...................... 1-21 Hardware Breakpoints Tips and Tricks ............................... 1-21 Latency ......................................................................... 1-21 Restrictions ................................................................... 1-22 Target Options ...................................................................... 1-22 Reset Options ................................................................... 1-22 On Emulator Exit ............................................................. 1-23 Other Options .................................................................. 1-23 Restricted Software Breakpoints ............................................. 1-23 EZ-KIT LITE HARDWARE REFERENCE System Architecture ...................................................................... 2-2 External Bus Interface .............................................................. 2-3 SPORT0 Audio Interface ......................................................... 2-3 Expansion Interface ................................................................. 2-4 JTAG Emulation Port .............................................................. 2-5 Jumper and Switch Settings ........................................................... 2-5 Audio Input Select Jumper (JP1) .............................................. 2-5 Audio Codec Disable Jumper (JP2) .......................................... 2-6 ADSP-BF535 EZ-KIT Lite Evaluation System Manual vii CONTENTS Boot Mode Select Switch (SW1) .............................................. 2-7 Processor PLL Setup Switch (SW2) .......................................... 2-7 LEDs and Push Buttons ................................................................ 2-9 Programmable Flag LEDs (LED4–1) ....................................... 2-9 USB Monitor LED (LED5) ................................................... 2-10 Power LED (LED6) .............................................................. 2-10 Reset LEDs (LED7 and LED8) ............................................. 2-10 Non-Maskable Interrupt Push Button (SW3) ......................... 2-11 Programmable Flag Push Buttons (SW7–4) ............................ 2-11 Reset Push Button (SW8) ...................................................... 2-11 Connectors ................................................................................. 2-12 Expansion Interface (P3–1) ................................................... 2-12 FlashLINK (P4) .................................................................... 2-13 Audio (P5 and P6) ................................................................ 2-13 USB (P7) .............................................................................. 2-14 JTAG (P8) ............................................................................ 2-14 SPORT0 (P9) ....................................................................... 2-15 Power Connector (P10) ......................................................... 2-15 Specifications ............................................................................. 2-15 Power Supply ........................................................................ 2-16 Board Current Measurements ................................................ 2-16 Mechanical Dimensions ........................................................ 2-17 BILL OF MATERIALS INDEX viii ADSP-BF535 EZ-KIT Lite Evaluation System Manual CONTENTS ADSP-BF535 EZ-KIT Lite Evaluation System Manual ix CONTENTS x ADSP-BF535 EZ-KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP-BF535 EZ-KIT Lite®, Analog Devices, Inc. evaluation system for Blackfin® processors. The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics towards delivering signal processing performance in a microprocessor-like environment. The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the ADSP-BF535 (formerly ADSP-21535) Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code development and debug, such as: • Create, compile, assemble, and link application programs written in C++, C and ADSP-BF535 assembly • Load, run, step, halt, and set breakpoints in application program • Read and write data and program memory • Read and write core and peripheral registers • Plot memory Access to the ADSP-BF535 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF535 processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster ADSP-BF535 EZ-KIT Lite Evaluation System Manual xi communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.com/dsp/tools/. ADSP-BF535 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board. ADSP-BF535 EZ-KIT Lite installation is part of the VisuL The alDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires: • VisualDSP++ allows a connection to the ADSP-BF535 EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed. • The linker restricts a users program to 176 KB of internal memory for code space with no restrictions for data space. Refer to the VisualDSP++ Installation Quick Reference Card for details. The board’s features include: • Analog Devices ADSP-BF535 processor D D D 300 MHz Core Clock Speed (default) Switch-Configurable Core Clock Speed Switch-Configurable Boot Mode • USB Debugging Interface L This is not the processor’s USB interface. xii ADSP-BF535 EZ-KIT Lite Evaluation System Manual Preface • Analog Devices AD1885 48 kHz AC’97 SoundMAX® Codec D D Jumper-Selectable Line-In or Mic-In 3.5 mm Stereo Jack Line-Out 3.5 mm Stereo Jack • SDRAM D 4 M x 32-bit • Flash Memory D 272 K x 16 • Interface Connectors D D D D 14-Pin Emulator Connector for JTAG Interface SPORT0 Connector FlashLINK™ Connector (for flash memory programming) Expansion Interface Connectors (not populated) • General-Purpose IO D D D 4 Push Buttons connected to Processor Programmable Flags 1 Push Button connected to Processor Non-maskable Interrupt 4 LEDs connected to Processor Programmable Flags • Real Time Clock • Analog Devices ADP3331, ADP3338, ADP3339, and ADP3088 Voltage Regulators The EZ-KIT Lite board has a flash memory device that can be used to store user-specific boot code. By configuring the boot mode switch (SW1) and by programming the flash memory, the board can run as a stand-alone unit. For information about the flash memory, see “Flash Memory” on page 1-8. ADSP-BF535 EZ-KIT Lite Evaluation System Manual xiii Purpose of This Manual interfaces with an audio codec to aid development of audio signal processing applications. SPORT0 also connects to an off-board connector for communication with other serial devices. For information about SPORT0, see “SPORT0 Audio Interface” on page 2-3. SPORT0 Additionally, the EZ-KIT Lite board provides access to most peripheral ports of the processor. Access is provided in the form of uninstalled expansion interface connectors. The processor’s USB pins are brought to the P3 connector but require additional circuitry to function as a USB port. The PCI bus of the processor is not available at any connector of the EZ-KIT Lite. For information about the expansion interface, see “Expansion Interface” on page 2-4. Purpose of This Manual The ADSP-BF535 EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes the operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF535 EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs. The product software installation is detailed in the VisualDSP++ Installation Quick Reference Card. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices xiv ADSP-BF535 EZ-KIT Lite Evaluation System Manual Preface processors can use this manual but should supplement it with other texts (such as the ADSP-BF535 Processor Hardware Reference and the Blackfin Processor Instruction Set Reference) that describe your target architecture. Programmers who are unfamiliar with VisualDSP++ should refer to the VisualDSP++ online Help and user’s or getting started guides. For the locations of these documents, see “Related Documents”. Manual Contents The manual consists of: • Chapter 1, “Using EZ-KIT Lite” on page 1-1 Describes the EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map. • Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1 Provides information on the EZ-KIT Lite hardware components. • Appendix A, “Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board. • Appendix B, “Schematics” on page B-1 Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design. This appendix is not part of the online Help. The online Help viewers should go to the PDF version of the ADSP-BF535 EZ-KIT Lite Evaluation System Manual located in the Docs\EZ-KIT Lite Manuals folder on the installation CD to see the schematics. Alternatively, the schematics can be found on the Analog Devices Web site, www.analog.com/processors. ADSP-BF535 EZ-KIT Lite Evaluation System Manual xv What’s New in This Manual What’s New in This Manual This revision of the ADSP-BF535 EZ-KIT Lite Evaluation System Manual provides an updated listing of related documents and updated licensing information. Technical or Customer Support You can reach DSP Tools Support in the following ways. • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technicalSupport • E-mail tools questions to [email protected] • E-mail processor questions to [email protected] • Phone questions to 1-800-ANALOGD • Contact your Analog Devices, Inc. local sales office or authorized distributor • Send questions by mail to: Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA xvi ADSP-BF535 EZ-KIT Lite Evaluation System Manual Preface Supported Processors This EZ-KIT Lite evaluation system supports the Analog Devices ADSP-BF535 (formerly ADSP-21535) Blackfin processors. Product Information You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals). Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. MyAnalog.com MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. Registration: Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as means for you to select the information you want to receive. If you are already a registered user, just log on. Your user name is your e-mail address. ADSP-BF535 EZ-KIT Lite Evaluation System Manual xvii Product Information Processor Product Information For information on embedded processors and DSPs, visit our Web site at www.analog.com/processors, which provides access to technical publications, data sheets, application notes, product overviews, and product announcements. You may also obtain additional information about Analog Devices and its products in any of the following ways. • E-mail questions or requests for information to [email protected] • Fax questions or requests for information to 1-781-461-3010 (North America) +49 (89) 76 903-557 (Europe) • Access the FTP Web site at ftp ftp.analog.com or ftp 137.71.23.21 ftp://ftp.analog.com Related Documents For information on product related development software, see the following publications. Table 1. Related Processor Publications xviii Title Description ADSP-BF535 Embedded Processor Datasheet General functional description, pin-out, and timing ADSP-BF535 Blackfin Processor Hardware Reference Description of internal processor architecture and all register functions Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions ADSP-BF535 EZ-KIT Lite Evaluation System Manual Preface Table 2. Related VisualDSP++ Publications Title Description VisualDSP++ User’s Guide Description of VisualDSP++ features and usage VisualDSP++ Assembler and Preprocessor Manual Description of the assembler function and commands VisualDSP++ C/C++ Complier and Library Manual for Blackfin Processors Description of the complier function and commands for Blackfin processors VisualDSP++ Linker & Utilities Manual Description of the linker function and commands VisualDSP++ Loader Manual Description of the loader/splitter function and commands you plan to use the EZ-KIT Lite board in conjunction with a L IfJTAG emulator, also refer to the documentation that accompanies the emulator. All documentation is available online. Most documentation is available in printed form. Visit the Technical Library Web site to access all processor and tools manuals and data sheets: http://www.analog.com/processors/resources/technicalLibrary . Online Technical Documentation Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary .PDF files of most manuals are provided in the Docs folder on the VisualDSP++ installation CD. ADSP-BF535 EZ-KIT Lite Evaluation System Manual xix Product Information Each documentation file type is described as follows. File Description .CHM Help system files and manuals in Help format .HTM or .HTML Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .HTML files requires a browser, such as Internet Explorer 4.0 (or higher). .PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF). Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher). If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site. Accessing Documentation From VisualDSP++ To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP++ documentation via the Start menu. To view ADSP-BF535 EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help window. Accessing Documentation From Windows In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documentation from Windows. xx ADSP-BF535 EZ-KIT Lite Evaluation System Manual Preface Help system files (.CHM) are located in the Help folder, and .PDF files are located in the Docs folder of your VisualDSP++ installation CD. The Docs folder also contains the Dinkum Abridged C++ library and the FlexLM network license manager software documentation. Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++ and the ADSP-BF535 EZ-KIT Lite evaluation system. Accessing Documentation From Web Download manuals at the following Web site: http://www.analog.com/processors/resources/technicalLibrary/manuals. Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files. Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts. VisualDSP++ Documentation Set To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit. If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir/continent.asp. ADSP-BF535 EZ-KIT Lite Evaluation System Manual xxi Notation Conventions Hardware Tools Manuals To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual. Processor Manuals Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual. Data Sheets All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site. To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site. Notation Conventions Text conventions used in this manual are identified and described as follows. conventions, which apply only to specific chapters, may L Additional appear throughout this document. xxii ADSP-BF535 EZ-KIT Lite Evaluation System Manual Preface Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu). {this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. .SECTION Commands, directives, keywords, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. L Note: For correct operation, ... A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. a Caution: Incorrect device operation may result if ... Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol. [ Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-BF535 EZ-KIT Lite Evaluation System Manual xxiii Notation Conventions xxiv ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1 USING EZ-KIT LITE This chapter provides specific information to assist you with development of programs for the ADSP-BF535 EZ-KIT Lite evaluation system. • “Package Contents” on page 1-2 Lists the items contained in your ADSP-BF535 EZ-KIT Lite package. • “Default Configuration” on page 1-3 Shows the default configuration of the ADSP-BF535 EZ-KIT Lite. • “Installation and Session Startup” on page 1-5 Instructs how to start a new or open an existing ADSP-BF535 EZ-KIT Lite session using VisualDSP++. • “Evaluation License Restrictions” on page 1-6 Describes the restrictions of the VisualDSP++ demo license shipped with the EZ-KIT Lite. • “Memory Map” on page 1-6 Defines the ADSP-BF535 EZ-KIT Lite’s memory map. • “SDRAM Interface” on page 1-7· Defines the register values to configure the on-board SDRAM. • “Flash Memory” on page 1-8 Describes how to program and use the on-board flash memory. • “Programmable Flag Pins” on page 1-10 Describes the function and use of the programmable flag pins of the EZ-KIT Lite evaluation system. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-1 Package Contents • “Example Programs” on page 1-12 Provides information about the example programs included in the ADSP-BF535 EZ-KIT Lite evaluation system. • “Flash Programmer Utility” on page 1-12 Provides information on the Flash Programmer utility included with the EZ-KIT Lite software. • “Background Telemetry Channel” on page 1-12 Highlights the advantages of the Background Telemetry Channel. • “VisualDSP++ Interface” on page 1-13 Describes the trace, performance monitoring, boot loading, context switching, hardware breakpoints, and target options of the EZ-KIT Lite system. For more detailed information about programming the ADSP-BF535 Blackfin processor, see the documents referred to as “Related Documents”. Package Contents Your ADSP-BF535 EZ-KIT Lite evaluation system package contains the following items. • ADSP-BF535 EZ-KIT Lite board • VisualDSP++ Installation Quick Reference Card • CD containing: D D D 1-2 VisualDSP++ software ADSP-BF535 EZ-KIT Lite software USB driver files ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite D D Example programs ADSP-BF535 EZ-KIT Lite Evaluation System Manual (this document) • Universal 7.5V DC power supply • USB 2.0 cable • Registration card (please fill out and return) If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc. Default Configuration The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. The ADSP-BF535 EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your computer case. When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which may damage the board components. Figure 1-1 shows the default jumper settings, switches, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before powering the board. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-3 Default Configuration Figure 1-1. EZ-KIT Lite Hardware Setup 1-4 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Installation and Session Startup correct operation, install the software and hardware in the L For order presented in the VisualDSP++ Installation Quick Reference Card. 1. Verify that the yellow USB monitor LED (LED5, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 2. From the Start menu, navigate to the VisualDSP++ environment via the Programs menu. If you are running VisualDSP++ for the first time, the New Session dialog box appears on the screen (skip the rest of the procedure and go to step 3). If you have run VisualDSP++ previously, the last opened session appears on the screen. To switch to another session, via the Session List dialog box, hold down the Ctrl key while starting VisualDSP++ (go to step 5). 3. In Debug target, select EZ-KIT Lite (ADSP-BFxxx). In Platform, select ADSP-BFxxx EZ-KIT Lite. In Processor, choose the appropriate processor, ADSP-BF535. In Session name, type a new name or accept the default. 4. Click OK to return to the Session List. 5. Highlight the session and click Activate. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-5 Evaluation License Restrictions Evaluation License Restrictions The ADSP-BF535 EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires: • VisualDSP++ allows a connection to the ADSP-BF535 EZ-KIT Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed. • The linker restricts a users program to 176 KB of internal memory for code space with no restrictions for data space. EZ-KIT Lite hardware must be connected and powered up in L The order to use VisualDSP++ with a valid temporary or demo license. Refer to the VisualDSP++ Installation Quick Reference Card for details. Memory Map The ADSP-BF535 processor has internal SRAM that can be used for instruction or data storage. The configuration of internal SRAM is detailed in the ADSP-BF535 Processor Hardware Reference. The ADSP-BF535 EZ-KIT Lite board contains 272K x 16 bits of external flash memory. This memory is connected to the processor’s ~AMS0 memory select pin. The external memory interface is also connected to 4M x 32-bit SDRAM memory. This memory is connected to the ~SMS0 pin. 1-6 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 1-1. EZ-KIT Lite Evaluation Board Memory Map Start Address External Memory End Address Content 0x0000 0000 0x00FF FFFF SDRAM Bank 0 (SDRAM) See “SDRAM Interface” on page 1-7. 0x2000 0000 0x2009 FFFF ASYNC Memory Bank 0 (FLASH) See “Flash Memory” on page 1-8. All other locations Internal Memory Not used 0xF000 0000 0xF003 FFFF L2 SRAM 256 KB 0xFF80 0000 0xFF80 3FFF Data Bank A 16 KB 0xFF90 0000 0xFF90 3FFF Data Bank B 16 KB 0xFFA0 0000 0xFFA0 3FFF Instruction SRAM 16 KB 0xFFB0 0000 0xFFB0 0FFF Scratch Pad SRAM 4 KB 0xFFC0 0000 0xFFDF FFFF System MMRs 2 MB 0xFFE0 0000 0xFFFF FFFF Core MMRs 2 MB All other locations Reserved SDRAM Interface In order to use the 4M x 32 bits (16 MB) of SDRAM memory, the three SDRAM control registers must be initialized. Table 1-2 shows the standard configuration for these registers when using the EZ-KIT Lite in the default configuration. These numbers were derived using the M48LC4M16ATG-75 with a system clock frequency of 120 MHz. If you are in an EZ-Kit Lite or emulator session, the SDRAM registers are set to the values in Table 1-2 automatically when a reset operation is performed. Clearing the Use XML reset values check box on the Target Options dialog box, which is accessible through the Settings pull-down menu, disables this feature. For more information see the Table 1-12 on page 1-24. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-7 Flash Memory Table 1-2. SDRAM Default Settings Register Value Function EBIU_SDRRC 0x0000074A RDIV = 1866 clock cycles EBIU_SDBCTL 0x00000001 Bank 0 enabled Bank 0 size = 16 MB Bank 0 column address width = 8 bits EBIU_SDGCTL 0x0091998F 32-bit data path External buffering timing disabled tWR = 2 SCLK cycles tRCD = 3 SCLK cycles tRP = 3 SCLK cycles tRAS = 6 SCLK cycles pre-fetch disabled CAS latency = 3 SCLK cycles SCLK1 disabled An example program is included in the EZ-KIT installation directory to demonstrate how to set up the SDRAM interface. Flash Memory The DSM2150 Flash/PLD chip provides a total of 272K x 16 bits of external flash memory, arranged into two independent flash arrays (boot and main). The chip also has a series of configuration registers to control IO and PLD. This chip is initially configured with the memory sectors mapped to the processor, as shown in Figure 1-2. Use PSDsoft Express™ to modify the default settings for the flash memory. The DSM project must be modified and the flash memory must be reprogrammed using FlashLINK. The default project files can be found in \…\Blackfin\EZ-KITs\ADSP-BF535\PSDConfigFiles. Analog Devices does not provide any support for setting up the DSM2150 with PSDsoft Express or programming it using FlashLINK. E-mail STMicroelectronics at [email protected] for technical assistance. 1-8 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite 0x200A 0000 Main Flash Array 0x2002 0000 Empty 0x2001 00FF Config 0x2001 0000 Empty 0x2000 8000 0x2000 0000 Boot Flash Array Figure 1-2. Flash Memory Map To program the flash memory with your boot code, you must first create a loader file from your processor code. Set up the loader in VisualDSP++, depending on how you plan to boot the flash memory. The two possibilities are to boot the processor in 16-bit external execution mode or in 8-bit boot mode. See “Boot Mode Select Switch (SW1)” on page 2-7 for the boot mode settings. Next, the loader file must be programmed into the flash memory. This can be done through the processor using the VisualDSP++ Flash Programmer utility (see “Flash Programmer Utility” on page 1-12) or by using the FlashLink programmer. The DSM2150 can be re-programmed using the FlashLINK JTAG programming cable available from STMicroelectronics (www.st.com/psd) for approximately $59. FlashLINK plugs into any PC parallel port. The software development tool, PSDsoft Express, is required to modify the DSM2150 configuration and to operate the FlashLINK cable. PSDsoft Express can be downloaded at no charge from at www.st.com/psd. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-9 Programmable Flag Pins Programmable Flag Pins The ADSP-BF535 processor has 16 asynchronous Programmable Flag (PF) IO pins. During reset, PF9-0 function as inputs to the internal PLL of the processor. They are not valid until 120 uS after reset. Table 1-3 describes how the PFs can be used after reset. Table 1-3. Programmable Flag Pin Summary Flag Connected To Description PF0 LED4 PF1 LED1 PF3-0 are connected to the LEDs. These can be used to light an LED when a routine completes. PF2 LED2 PF3 LED3 PF4 SW4 PF5 SW5 PF6 SW6 PF7 SW7 PF7-4 are connected to the push buttons on the EZ-KIT Lite board and are for user input. Your routine can monitor and execute specific code when a push button is pressed. PF8 Not used PF9 Not used PF10 Not used PF11 Not used PF12 PMGMT0 PF13 PMGMT1 PF14 PMGMT2 PF15 U7.11 1-10 These are used to change the internal voltage of the processor. Refer to “Power Management” on page 1-11 for more information. Connected to the reset of the AD1885 codec (U7). This signal must be output as a high (1) to enable the AD1885 codec. ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite After a processor reset, all of the PF pins are initialized as inputs. The direction of the PF is configured by the FIO_DIR Memory Mapped Register (MMR). The PFs are set HIGH (1) using the FIO_FLAG_S and cleared (0) using the FIO_FLAG_C MMRs. For more information on configuring the PF pins, see the ADSP-BF535 Processor Hardware Reference Manual. All of the PFs can are brought out to the expansion connector P2. The location of the PF nets can be found in “Schematics” on page B-1. Power Management The PF14–12 pins allow you to program the core voltage of the processor. The default core voltage is 1.5V. Table 1-4 gives the value of the core voltage corresponding to the state of the PFs. Table 1-4. Power Management PF Settings PF14 PF13 PF12 VDD_INT 0 0 0 0.9V 0 0 1 1.0V 0 1 0 1.1V 0 1 1 1.2V 1 0 0 1.3V 1 0 1 1.4V 11 1 0 1.5V 1 1 1 1.6V 1 Default settings When lowering the core voltage of the processor, the frequency of the processor should also be taken into consideration. As you lower the core voltage, the frequency at which the core is running must be decreased. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-11 Example Programs Example Programs Example programs are provided with the ADSP-BF535 EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in the \…\Blackfin\EZ-KITs\ADSP-BF535\Examples subdirectory of the VisualDSP++ installation directory. Please refer to the readme file provided with each example for more information. Flash Programmer Utility The ADSP-BF535 EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++. Once the utility is installed, it is accessible from the Tools pull-down menu. For more information on the Flash Programmer utility, refer to online Help. Background Telemetry Channel The ADSP-BF535 USB debug agent supports the Background Telemetry Channel (BTC), which facilitates data exchange between VisualDSP++ and the processor without interrupting processor execution. The BTC allows the user to view a variable as it is updated or changed, all while the processor continues to execute. For increased performance of the BTC, including faster reading and writing, please check out our latest line of processor emulators at www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULATORS,00.html. 1-12 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite For more information about the Background Telemetry Channel, see the VisualDSP++ User’s Guide or online Help. VisualDSP++ Interface This section provides information on the following parts of the VisualDSP++ graphical user interface: • “Trace Window” on page 1-13 • “Performance Monitor” on page 1-15 • “Boot Load” on page 1-16 • “Context Switching” on page 1-16 • “Hardware Breakpoints” on page 1-18 • “Target Options” on page 1-22 • “Restricted Software Breakpoints” on page 1-23 Trace Window Choosing the Trace command from the View-->Debug Windows menu opens the Trace window (Figure 1-3). Figure 1-3. Trace Window ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-13 VisualDSP++ Interface The trace buffer stores a history of the last 16 changes in program flow taken by the program sequencer. View the history to recreate the program sequencer’s most recent path. The trace buffer does not track changes in flow caused by zero-overhead loops or while in the reset service routine. use the trace buffer, ensure your program leaves the reset service L Toroutine. Enabling Trace Buffer To view trace history in the Trace window, first, enable the trace buffer (choose Enable Trace from the Tools->Trace menu). On each halt, the Trace window is updated with the changes that occurred since the last halt. Reading the trace buffer destroys the trace buffer’s contents and discards the information previously stored before the last run. Reading Trace Buffer Data The first column between the square brackets (in blue) indicates the line number in the Trace window. The second column between square brackets, which comes in vertical pairs, shows the trace number. For each discontinuity, the first (top position) is the source trace, and the second (bottom position) is the destination trace. The third column in between square brackets shows the addresses of the instructions. Each address is followed by the assembly instruction. The trace grows upward. In Figure 1-3 on page 1-13, trace 0 occurred before trace 1, which occurred before trace 2, and so on. 1-14 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Performance Monitor Choosing Performance Monitor from the Settings menu opens the Performance Monitor Control dialog box shown in Figure 1-4. A description of the dialog box appears in Table 1-5 on page 1-15. Figure 1-4. Performance Monitor Dialog Box The performance monitor is a 32-bit counter that allows you to track occurrences of events within the core and use these to analyze system behavior. When the counter reaches zero, it causes an exception or emulation event, as specified by the Type option. Table 1-5. Performance Monitor Options Option Description Enable Enables performance monitoring. Mode Determines the mode of operation for tracking events: Disabled disables the monitor. User tracks while in user mode. Supervisor tracks while in supervisor mode. Both tracks while in both user mode and supervisor mode. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-15 VisualDSP++ Interface Table 1-5. Performance Monitor Options (Cont’d) Option Description Type Determines the type of event occurring on a match: Exception causes an exception to occur. You can install a handler to detect and handle this exception. Emulation halts the processor. Event Specifies the tracked event. Refer to your processor’s Hardware Reference for details. Events include stalls, cache hits or misses, loop iterations, branches, interrupts, loads, stores, DMA accesses, and so on. Count Specifies the count. When the 32-bit counter reaches zero, an exception or emulation event occurs. For example, to halt on the third occurrence of an event, load the count with 0xFFFFFFFE and set Type to Emulation. The counter counts up and wraps around, causing the processor to halt as desired. Boot Load Choosing Boot Load from the Settings menu runs the processor and performs a hard reset on the board. This command saves you from having to shut down VisualDSP++, reset the EZ-KIT Lite board, and bring up VisualDSP++ again when you want to perform a hard reset. Use this feature when loading debug boot code from an external part or when you want to put the device into a known state. Context Switching The ADSP-BF535 EZ-KIT Lite evaluation system uses two methods to obtain and restore the processor’s context: by using the M3 register or by using the stack. Using M3 Register Set Use M3 register for context switching option in the Target Options dialog box, as described on page 1-22. 1-16 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite When this option is selected, VisualDSP++ uses the M3 register for context switches. This renders M3 unavailable for user code since the register will be corrupted. When cleared, VisualDSP++ uses the address pointed to by the Stack Pointer register (SP). This method is very straightforward. M3 is chosen as the register for temporary storage and is, therefore, corrupted and cannot be employed in user code. Only use this method when there may be a problem using the stack method. Using Stack Pointer If the processor is in the reset service routine at startup, it is assumed the Stack Pointer (SP) is not pointing to a valid address. In this case, the SP is initialized to point to a valid address (0xFFB00FFC), and this location is used for temporary storage. If the processor is not in the reset service routine, it is assumed the user code has already initialized the SP to a valid address, and this location is used for temporary storage. After the initial startup, the SP is assumed valid. User code can change the SP at any time after leaving the reset service routine, and the new value of the SP is used for context switches. In all cases, the stack is pushed and popped and is non-intrusive to the user code. This method is less intrusive than the M3 method but is also more prone to problems. First, this method requires at least one available location on the stack. It also assumes user code does not point the SP to an invalid memory location during debugging and that, if not in the reset service routine, the SP has been programmed correctly. Additionally, it may be possible that a user program has not yet left the reset service routine, but the SP is already initialized. In this case, at startup, the processor is detected in the reset service routine still and the user’s SP value would be overwritten. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-17 VisualDSP++ Interface Hardware Breakpoints Choosing Hardware Breakpoints from the Settings menu opens the Hardware Breakpoints dialog box. The Hardware Breakpoints dialog box contains four tabbed pages: Data 0-1, Instruction 0-1, Instruction 2-3, and Instruction 4-5. Hardware breakpoints allow you to set breaks on instructions or data transfers within a user-defined memory range. The two types of breakpoints are described in “Data Breakpoints” on page 1-18 and “Instruction Breakpoints” on page 1-19. Global Breakpoint Options Global breakpoint options apply to all hardware breakpoints regardless of type. These options are listed in Table 1-6. Table 1-6. Global Breakpoint Options Option Description Enable watchpoint unit Enables the watchpoint unit. Enable data AND instruction Specifies that the processor AND the data and instruction breakpoints to form the composite interrupt. Normally each of the group interrupts are ORed to create a composite interrupt. Common Breakpoint Attributes Each tabbed page in the Hardware Breakpoints dialog box has the following common attributes, as described in Table 1-7. Data Breakpoints Figure 1-5 on page 1-20 shows the Data 0-1 page of the Hardware Breakpoints dialog box. Two individual data breakpoints can be set. A data breakpoint is triggered by a memory access to a specified address or range. Selecting Enable Range enables the two data breakpoints. 1-18 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 1-7. Common Breakpoint Attributes Option Description Enable Enables the individual breakpoint. Ensure that Global watchpoint unit is also selected. Enable Range Each tab (Data 0-1, Instruction 0-1, Instruction 2-3, and Instruction 4-5) is considered a range. Selecting this option on a particular tabbed page specifies a search range instead of a single address. Select the inclusive or exclusive range radio button as desired, for example: WPIA0 < IA <= WPIA1 causes the processor to break for an address greater than the instruction breakpoint 0 address AND less than or equal to the instruction breakpoint 1 address. IA <= WPIA0 || IA > WPIA1 causes the processor to break for an address less than or equal to the instruction breakpoint 0 address OR greater than the instruction breakpoint 1 address. Address Each breakpoint has an associated address. For a single address, this is the address searched when Enable Range is selected. This may be the upper or lower bound address. Skip count Each individual breakpoint has an associated skip count. When this count is reached, the breakpoint triggers on the next match of this breakpoint. For example, to break on every third match, enter a skip count of 2. Data Breakpoint Specific Attributes Data breakpoints have the attributes listed in Table 1-8. Instruction Breakpoints Figure 1-6 shows the Instruction 0-1 page of the Hardware Breakpoint dialog box. Six individual instruction breakpoints can be set. An instruction breakpoint occurs when an instruction is executed or an instruction in a specified range is executed. Three ranges, each with its own page, can be specified. You must select Enable Range to set up an instruction range. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-19 VisualDSP++ Interface Figure 1-5. Data Breakpoints Dialog Box Table 1-8. Data Breakpoint Specific Attributes Attribute Description Access Specifies the type of access: Reserved (reserved). Write triggers the breakpoint on any write to the specified address. Read triggers the breakpoint on any read from the specified address. Both triggers the breakpoint on any write to or read from the specified address. Source Specifies the source of access: Reserved (reserved). DAG0 triggers the breakpoint on any access using DAG0 with the specified address. DAG1 triggers the breakpoint on any access using DAG1 with the specified address. Both triggers the breakpoint on any access using DAG0 or DAG1 with the specified address. 1-20 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Figure 1-6. Instruction Breakpoints Dialog Box Instruction Breakpoint Specific Attributes Each instruction breakpoint have a specific attribute, as described in Table 1-9. Table 1-9. Instruction Breakpoint Specific Attribute Attribute Description Type Determines the type of event that occurs on a match: Exception causes an exception to occur. You can install a handler to detect and handle this exception. Emulation halts the processor. Hardware Breakpoints Tips and Tricks Be aware of the following tips and tricks when using hardware breakpoints on Blackfin processors. Latency There are no latency cycles for hardware breakpoint matches on the ADSP-BF535 EZ-KIT Lite evaluation system. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-21 VisualDSP++ Interface Restrictions When using hardware breakpoints, do not place breaks at any address where a JUMP, CALL, or IDLE instruction is not valid. Do not attempt to place breaks in the last few instructions of a DO LOOP or in the delay slots of a delayed branch. For more information on these illegal locations, see the processor’s Hardware Reference. Target Options Choosing Target Options from the Settings menu opens the Target Options dialog box (Figure 1-7). Use target options to control certain aspects of the processor on the ADSP-BF535 EZ-KIT Lite evaluation system. Figure 1-7. Target Options Dialog Box Reset Options Reset options control how the processor behaves when a reset occurs. The reset options are described in Table 1-10. 1-22 ADSP-BF535 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 1-10. Reset Options Option Description Core reset Resets the core when the debugger executes a reset. System reset Resets the peripherals when the debugger executes a reset. On Emulator Exit This target option controls processor behavior when VisualDSP++ relinquishes processor control (for example, when exiting VisualDSP++). The option is described in Table 1-11. Table 1-11. On Emulator Exit Target Options Option Description On Emulator Exit Determines the state the processor is left in when the emulator relinquishes control of the processor. Reset DSP and Run causes the processor to reset and begin execution from its reset vector location. Run from current PC causes the processor to begin running from its current location. Stall the DSP resets the processor and then writes a JUMP 0 to the first location in internal memory so the processor is stuck in a tight loop after exiting. Other Options Table 1-12 describes other available target options. Restricted Software Breakpoints The EZ-KIT Lite development system restricts breakpoint placement when certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus architecture, pipeline depth, and ordering of the EZ-KIT Lite and its target processor. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 1-23 VisualDSP++ Interface Table 1-12. Miscellaneous Target Options Option Description Verify all writes to target memory Validates all memory writes to the processor. After each write, a read is performed and the values are checked for a matching condition. Enable this option during initial program development to locate and fix initial build problems (such as attempting to load data into non-existent memory). Clear this option to increase performance while loading executable files, since VisualDSP++ does not perform the extra reads that are required to verify each write. Reset cycle counters on run Resets the cycle count registers to zero before a Run command is issued. Select this option to count the number of cycles executed between breakpoints in a program. Use XML reset values Uses a section in the processor-specific .XML file located in the installation’s system folder. The file defines registers that are reset to certain values. The values are read at startup and subsequently used to set the registers when a reset is performed through VisualDSP++. Use M3 register for context switching Allows VisualDSP++ to use the M3 register for context switches. This leaves M3 unavailable for user code because it will be corrupted. Clear this option to specify that the M3 register and VisualDSP++ use the address pointed to by the Stack Pointer register. 1-24 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2 EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-BF535 EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 2-2 Describes the configuration of the ADSP-BF535 (formerly ADSP-21535) processor and explains how the board components interface with the processor. • “Jumper and Switch Settings” on page 2-5 Shows the location and describes the function of the configuration jumpers and switches. • “LEDs and Push Buttons” on page 2-9 Shows the location and describes the function of the LEDs and push buttons. • “Connectors” on page 2-12 Shows the location and gives the part number for all of the connectors on the board. Also, the manufacturer and part number information is given for the mating parts. • “Specifications” on page 2-15 Gives the requirements for powering the board. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-1 System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board. JTAG Header 4M X 32bit SDRAM (U5, U6) 544KB Flash (U4) External Bus Interface Unit JTAG Port EZ USB FX USB Connector SRAM SPI 1:0 UART1:0 Timer2:0 ADSP-BF535 20MHz Oscillator CLK_IN 32.768KHz Crystal RTC Power Management processor (U1) VDD_EXT SPORT0 LEDs, PBs and Clock Logic PF15:0 SPORT0 Connector 5V A5V 3.3V +7.5V Connector USB VDD_INT 3.3V Power Regulation Expansion Connectors (P1, P2, P3) SPORT1 AD1885 Codec (U7) Stereo LINEIN/ MIC and LINEOUT Connectors Figure 2-1. System Architecture The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF535 Blackfin processor. The processor has a default core voltage of 1.5V. Refer to “Power Management” on page 1-11 for more information about changing the core voltage without halting the processor. The voltage of the processor’s peripheral interface is 3.3V. A 20 MHz oscillator supplies the input clock to the processor. The speed at which the core and peripherals operate is determined by the configuration of the multiplier select switch (SW2) at reset. (See “Processor PLL 2-2 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Setup Switch (SW2)” on page 2-7.) By default, the processor core runs at 300 MHz and the peripheral interface runs at 120 MHz. A 32.768 kHz crystal supplies the Real Time Clock (RTC) inputs of the processor. The EZ-KIT Lite board can be configured to boot in all of the possible ADSP-BF535 boot modes. For information about configuring the boot mode, see “Boot Mode Select Switch (SW1)” on page 2-7. External Bus Interface The External Bus Interface Unit (EBIU) is connected to 4M x 32 bits of SDRAM (16 MB). This memory is connected to the synchronous memory select 0 (~SMS0) pin. Refer to “SDRAM Interface” on page 1-7 for information about configuring the SDRAM. The EBIU is also connected to 272K x 16 bits of flash memory. This memory is connected to the asynchronous memory select (~AMS0) pin. The processor can use this memory for both booting and storing information during normal operation. Refer to “Flash Memory” on page 1-8 for information about using the flash memory. All of the address, data, and control signals are available externally via the extender connectors (P3-1). The pin-out of these connectors can be found in “Schematics” on page B-1. SPORT0 Audio Interface SPORT0 is connected to the AD1885 SoundMAX codec (U7). Two 3.5mm stereo jacks (P5, P6) allow audio to be input and output. You can supply an audio input to the Codec Microphone Input Channel (MIC1) or to the stereo LINE_IN input channel. The jumper settings of JP1 determine the codec channel driven by the input jack (P5). For information about configuring JP1, see “Audio Input Select Jumper (JP1)” on page 2-5. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-3 System Architecture is also routed to an off-board connector (P9). When using the off-board connector, the codec must be held in reset, so that it does not drive any of the SPORT0 signals. The codec can be held in reset by driving PF15 low or by setting up JP2 to always hold the codec in reset (see “Audio Codec Disable Jumper (JP2)” on page 2-6). PF15 must be pulled HI (1) for the codec to function. SPORT0 [ TCLK0 and RCLK0 pins are shorted together using R114 and R118. Expansion Interface The expansion interface consists of the footprints for three connectors. Table 2-1 shows the interfaces each connector provides. For the exact pin-out of these connectors, refer to “Schematics” in Appendix B, Schematics. Analog Devices does not populate these connectors or provide any additional support for this interface. The mechanical locations of these connectors can be found in “Mechanical Dimensions” on page 2-17. Table 2-1. Connector Interfaces Connector Interfaces P1 5V, GND, Address, Data P2 3.3V, GND, EBUI control signals, PF15-0, SPI1-0, SPORT1, UART1-0, TMR2-0, NMI P3 1.5V, GND, Reset, USB, CLKOUT, SLEEP Limits to the current and to the interface speed must be taken into consideration if you use this interface. The maximum current limit is dependent on the capabilities of the regulator used. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed. Devices does not support and is not responsible for the [ Analog effects of additional circuitry. 2-4 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference JTAG Emulation Port The JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emulation port of the processor is also connected to the USB debugging interface (Note that this is not the processor’s USB interface). When an emulator is connected to the board at P8, the USB debugging interface is disabled. See “JTAG (P8)” on page 2-14 for more information about the JTAG connector. To learn more about available emulators, contact Analog Devices (see “Product Information”). Jumper and Switch Settings This section describes the function of all the jumpers and DIP switches. The following figure (Figure 2-2 on page 2-6) shows the location of all the jumpers and DIP switches. Audio Input Select Jumper (JP1) The audio input jack (P5) can be connected to the MIC1 or the LINEIN input channels of the AD1885 codec (U7). When the JP1 jumpers connect pins 1 and 3 and pins 2 and 4, P3 connects to the mono MIC1 channel. When the jumpers connect pins 3 and 5 and pins 4 and 6, P5 connects to the stereo LINE_IN channel of the AD1885 codec. These jumper settings are illustrated in Figure 2-2 on page 2-6. (The words MIC and LINE are on the board as a reference) ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-5 Jumper and Switch Settings Figure 2-2. Jumper Locations Table 2-2. Audio Input Jumper Settings (JP1) 2 1 6 5 JP1 2 1 LINE MIC JP1 Mono MIC1 LINE MIC Stereo LINE_IN (DEFAULT) 6 5 Audio Codec Disable Jumper (JP2) Placing a jumper between pins 1 and 2 of JP2 holds the AD1885 in reset, preventing it from driving signals to the serial port. When a jumper is between pins 2 and 3 of JP2, the AD1885 is held in reset until PF15 is set to an output and is asserted. These positions are labeled on the board as DIS and ENA 1885. 2-6 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Boot Mode Select Switch (SW1) The boot mode select switch determines how the processor boots. Table 2-3 shows the switch settings for the boot modes. L SPI ROM is not available on the EZ-KIT Lite. Table 2-3. Boot Mode Select Switch BMODE0 Pin 1 BMODE1 Pin 2 BMODE2 Pin 3 Description On On On Execute from 16 bit external memory (no boot). Off1 On On Boot from 8-bit EPROM On Off On Boot from SPI0 ROM (8-bit addresses) Off Off On Boot from SPI0 ROM (16-bit addresses) – – Off All others reserved 1 Default settings Processor PLL Setup Switch (SW2) The processor’s Phase Lock Loop (PLL) multiplies the 20 MHz input clock by a multiplication factor to set the core clock speed of the processor. Internal to the processor the Programmable Flag pins, PF9-0, are multiplexed with the PLL setup signals, SSEL6-0, DF, and MSEL1-0. During reset, the function of the pins is to setup the PLL. At this time, the signals are attached to the SW2 switch and determine the core and external clock speeds of the processor. The SW2 switch drives the processor pins during reset and, for approximately 120mS, after reset. Once this time has elapsed, the PFs are no longer connected to the SW2 but are connected to the general-purpose IO (LEDs, push buttons) on the board. This is done with an external 2-to-1 multiplexer and is provided for flexibility when using the EZ-KIT Lite. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-7 Jumper and Switch Settings The following table shows the switch position that corresponds to a processor pin. Table 2-4. PLL Setup Switch (SW2) Functions Processor Pin Switch Position Processor Pin Switch Position MSEL0 1 MSEL6 7 MSEL1 2 DF 8 MSEL2 3 SSEL0 9 MSEL3 4 SSEL1 10 MSEL4 5 None 11 MSEL5 6 Bypass 12 Figure 2-3 shows the default setting for SW2. The setting produces a 300 MHz core clock speed and a 120 MHz peripheral interface speed. For more information about setting up the multiplication factors, refer to the Managing DSP Clocks section of the ADSP-BF535 Processor Hardware Reference. ON 1 2 3 4 5 6 7 8 9 10 11 12 Figure 2-3. Default PLL Setup Switch Settings (SW2) A switch setting of L processor pin. 2-8 ON supplies a logic low (0) on the corresponding ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference LEDs and Push Buttons This section describes the functionality of the LEDs and push buttons. Figure 2-4 shows the locations of the LEDs and push buttons. Figure 2-4. LED and Push Button Locations Programmable Flag LEDs (LED4–1) Four LEDs are connected to four of the processor’s Programmable Flag (PF) pins, PF3-0. These LEDs are active HIGH and are lit by an output of “1” from the processor. Refer to “Programmable Flag Pins” on page 1-10 for more information about using of the PFs when programming the processor. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-9 LEDs and Push Buttons Table 2-5. Programmable Flag LEDs LED Reference Designator Processor Programmable Flag Pin LED4 PF0 LED1 PF1 LED2 PF2 LED3 PF3 USB Monitor LED (LED5) The USB Monitor LED (LED5) indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP++ EZ-KIT Lite session. This should take approximately 15 seconds. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver (see the VisualDSP++ Installation Quick Reference Card). VisualDSP++ is communicating actively with the EZ-KIT L When Lite target board, the LED can flicker, indicating communications handshake. Power LED (LED6) When LED6 is lit (green), it indicates that power is being properly supplied to the board. Reset LEDs (LED7 and LED8) When LED8 is lit, it indicates that master reset for all the major ICs is active. When LED7 is lit, the USB interface chip (U11) is being reset. The USB chips only reset on power-up, or if USB communication has not been initialized. 2-10 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Non-Maskable Interrupt Push Button (SW3) The SW3 button is connected to the Non-maskable Interrupt (NMI) pin of the processor. When pressed, the processor vectors to the NMI interrupt vector. Programmable Flag Push Buttons (SW7–4) Four push buttons are provided for general-purpose user input. SW7-4 connect to the processor’s Programmable Flag (PF) pins, PF7-4. The push buttons are active HIGH and, when pressed, send a High (1) to the processor. Refer to “Programmable Flag Pins” on page 1-10 for more information about the use of the PFs when programming the processor. Table 2-6 shows the PF signal and the switch it is connected to. Table 2-6. Programmable Flag Switches Push Button Reference Designator Processor Programmable Flag Pin SW4 PF4 SW5 PF5 SW6 PF6 SW7 PF7 Reset Push Button (SW8) The RESET push button resets all of the ICs on the board. This reset does not affect the USB interface chip (U11) unless communication has not been initialized with a PC. After USB communication has been initialized, the only way to reset the USB is by powering down the board. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-11 Connectors Connectors This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown in Figure 2-5. Figure 2-5. Connector Locations Expansion Interface (P3–1) Three board-to-board connector footprints provide signals for most of the processor peripheral interfaces. Analog Devices does not populate these connectors or provide any additional support for this interface. For more information on the expansion interface, see “Expansion Interface” on page 2-4. Contact Samtec for the availability and pricing of the connectors. 2-12 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Part Description Manufacturer Part Number 90 Position 0.05" Spacing (P1, P2, P3) Samtec SFM-145-01-S-D Mating Connector 90 Position 0.05" Spacing (Through Hole) Samtec TFM-145-x1 Series 90 Position 0.05" Spacing (Surface Mount) Samtec TFM-145-x2 Series 90 Position 0.05" Spacing (Low Cost) Samtec TFC-145 Series FlashLINK (P4) The FlashLINK connector allows you to configure and program the STMicroelectronics DSM2150 flash/PLD chip. See “Flash Memory” on page 1-8 for more information about using the FlashLINK connector. Part Description Manufacturer Part Number Right-angle 7X2 Shrouded 0.1 Spacing TYCO 2-767004-2 Mating Assembly FlashLINK JTAG Programmer ST Micro L-101B Audio (P5 and P6) There are two 3.5 mm stereo audio jacks: one input and one output. Part Description Manufacturer Part Number 3.5 mm stereo jack (P5, P6) Shogyo SJ-0359AM-5 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-13 Connectors Part Description Manufacturer Part Number Mating Cable 3.5 mm stereo plug to 3.5 mm stereo cable Radio Shack 42-2387A USB (P7) The USB connector is a standard Type B USB receptacle. This connector is used to debug the processor and is not connected to the processor’s USB interface. Part Description Manufacturer Part Number Type B USB receptacle (P7) Mill-Max 897-30-004-90-000 Digi-Key ED90003-ND Mating Connector USB cable (provided with kit) Assmann AK672-5 Digi-Key AK672-5ND JTAG (P8) The JTAG header is the connecting point for a JTAG in-circuit emulator pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled. 3 is missing to provide keying. Pin 3 in the mating connector L Pin should have a plug. using an emulator with the EZ-KIT Lite board, follow the L When connection instructions provided with the emulator. 2-14 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference SPORT0 (P9) is connected to a 20-pin connector. The pin-out for this connector can be found in “Schematics” on page B-1. Contact AMP for pricing and availability on these connectors. SPORT0 Part Description Manufacturer Part Number 20 position AMPMODU system 50 receptacle (P9) AMP 104069-1 Mating Connectors 20 position AMPMODU ribbon cable connector AMP 111196-4 Power Connector (P10) The power connector provides all of the power necessary to operate the EZ-KIT Lite board. Part Description Manufacturer Part Number 2.5 mm Power Jack (P10) Switchcraft RAPC712 Digi-key SC1152-ND Mating Power Supply (shipped with EZ-KIT Lite) 7.5V Power Supply GlobTek TR9CC2000LCP-Y Specifications This section provides the requirements for powering the board and the mechanical dimensions of the board. ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-15 Specifications Power Supply The power connector supplies DC power to the EZ-KIT Lite board. Table 2-7 shows the power connector pin-out. Table 2-7. Power Connectors Terminal Connection Center pin +7.5 VDC@2amps Outer Ring GND Board Current Measurements The ADSP-BF535 EZ-KIT Lite board provides eight zero-ohm resistors that may be removed to measure current draw. Table 2-8 shows the resistor number, the voltage plane, and a description of each component on the plane. Table 2-8. Current Measurement Resistors Resistor Voltage Plane Description R2 VDD_RTC Processor Real Time Clock Supply R3 VDD_EXT Processor External Interface Supply R6 VDD_INT Processor Internal Interface Supply R7 VDD_PCIEXT Processor PCI Interface Supply R8 VDD_PLL Processor Phase Lock Loop Supply R110 5V 5V Supply R111 3V 3V supply to all non processor-related components R113 3V_DSP 3V to processor-related components 2-16 ADSP-BF535 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Mechanical Dimensions Figure 2-6 shows the location of the mounting holes as well as the PIN1 of each of the expansion connectors. 5.000 4.750 3.875 P1 3.750 2.500 P2 1.400 1.300 1.125 P3 6.750 7.000 6.375 6.200 3.600 3.250 0.625 0.000 0.250 0.250 0.000 Figure 2-6. Mechanical Drawing ADSP-BF535 EZ-KIT Lite Evaluation System Manual 2-17 Specifications 2-18 ADSP-BF535 EZ-KIT Lite Evaluation System Manual A BILL OF MATERIALS The bill of materials corresponds to the board schematics on page B-1. Please check the latest schematics on the Analog Devices website, http://www.analog.com/Processors/Processors/DevelopmentTools/tec hnicalLibrary/manuals/DevToolsIndex.html#Evaluation%20Kit%20Manuals. ADSP-BF535 EZ-KIT Lite Evaluation System Manual A-1 A-2 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 74LVC14A SOIC14 HEX-INVER-SCHMITT-TRIGGER 3 1 1 1 1 1 1 1 3 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY7C4201V-15AC TQFP32 64-BYTE-FIFO SN74LV164A SOIC14 8-BIT-PARALLEL-SERIAL SN74AHC1G02 SOT23-5 SINGLE-2 INPUT-NOR CY7C1019BV33-15VC SOJ32 128K X 8 SRAM BSS123 SOT23D NMOS FET ADP3331ART SOT23-6 ADJ 200MA REGULATOR 24LC00-SN SOIC8 128 BIT SERIAL EEPROM 74LVC00AD SOIC14 MMBT4401 SOT-23 NPN TRANSISTOR 200MA CY7C64603-128 PQFP128 USB-TX/RX MICROCONTROLLER 24.576MHZ SMT OSC005 CRYSTAL IDT74FCT3244APY SSOP20 3.3V-OCTAL-BUFFER Description Ref. # U18 U17 U16 U12 M1-3 VR3 U25 U13 Q1 U11 Y2 CYPRESS CY7C4201V-15AC SN74LV164AD SN74AHC1G02DBVR TI TI CY7C1019BV33-12VC CYPRESS BSS123 ADP3331ART ANALOG DEVICES FAIRCHILD 24LC00-SN 74LVC00AD PHILIPS MICROCHIP MMBT4401 FAIRCHILD CY7C64603-128NC MA505 24.576M-C2 EPSON CYPRESS IDT74FCT3244APY 74LVC14AD Part Number IDT TI U9-10, U19 U24 Manufacturer Reference Designator 12.0MHZ THR OSC006 CRYSTAL 1 2 1 1 1 2 2 1 1 2 1 1 15 16 17 18 19 20 21 22 23 24 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 25 26 ADP3088 MSOP8 500MA-BUCK-REGULATOR ADP3339AKC-5 SOT-223 5V-1.5A REGULATOR ADP3338AKC-33 SOT-223 3.3V-1.0AMP REGULATOR AD1885JST LQFP48 AC97 STEREO CODEC ADM708SAR SOIC8 VOLTAGE-SUPERVISOR 0.1uF 50V 10% 1206 CERM 1000pF 50V 5% 1206 CERM 21535 BRD DSM2150F5V U4"" BLKFIN160.OBJ SUM 876F5F1 SN74AHC1G00 SOT23-5 SINGLE-2-INPUT-NAND 32.768kHz TH OSC007 CRYSTAL MT48LC4M16 TSOP54 4MX16-SDRAM-133MHZ Description Ref. # VR5 VR4 VR1-2 U7 U23 C8-9 C25-26 U4 U26 Y1 U5-6 Y3 Reference Designator ADP3339AKC-5-REEL ADP3088ARM-REEL ANALOG DEVICES ANALOG DEVICES ADP3338AKC-3.3 AD1885JST ANALOG DEVICES ANALOG DEVICES ADM708SAR ANALOG DEVICES 12062R104K9BB2 12065A102JAT2A AVX PHILIPS DSM2150F5V ST MICRO SN74AHC1G00DBVR EC38T ECPLITEK TI MT48LC4M16A2TG-75 300-6027-ND Part Number MICRON DIG01 Manufacturer Bill Of Materials A-3 A-4 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 6 1 1 1 23 2 5 2 33 34 35 36 37 38 39 1 30 32 1 29 1 5 28 31 ADSP-21535PKB-300 PBGA260 308KBYTES-BLACKFIN 1 27 22pF 50V 5% 805 CERM AMBER-SMT LED001 GULL-WING 220uF 10V 20% E ELEC 0.00 1/8W 5% 1206 IDC 7X2 IDC7X2SRDRA RIGHT ANGLE SHROUDED DIP3 SWT015 DIP12 SWT014 SPST-MOMENTARY SWT013 6MM .05 10X2 CON014 RA USB 4PIN CON009 USB PWR 2.5MM_JACK CON005 RA RUBBER FEET BLACK Description Ref. # C5-C6 LED1-5 CT7-8 R2-3, R6-12, R21,R63-64, R77, R97, R111-118, R127 P4 SW1 SW2 SW3-8 P9 P7 P10 MH1-5 U1 Reference Designator 70247-1401 MOLEX LN1461C-TR 08055A220JAT AVX 293D227X9010E2T PANASONIC SPRAGUE 0.0ECT-ND CKN3055-ND DIGI-KEY YAGEO CKN3063-ND EVQ-PAD04M 104069-1 DIGI-KEY PANASONIC AMP 897-30-004-90-000000 SC1152-ND12 SWITCHCRAFT MILL-MAX 517-SJ-5018BK ADSP-21535PKB-300 Part Number MOUSER ANALOG DEVICES Manufacturer 0.01uF 100V 10% 805 CERM 79 1 5 4 44 44 4 5 1 1 1 3 40 41 42 43 44 45 46 47 48 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 49 50 51 2.21K 1/8W 1% 1206 22uF 16V 10% D TANT 1.5K 100MW 5% 805 1M 100MW 5% 805 4.7K 100MW 5% 805 33 100MW 5% 805 10K 100MW 5% 805 10K 100MW 5% 805 10uF 16V 10% C TANT 0.1uF 50V 10% 805 CERM 0.22uF 25V 10% 805 CERM Description Ref. # R30, R35, R40 CT1 R43 R41 R55-56, R58, R62, R107 R4-5, R46, R119 R83-84, R87-88, R90-93, R105, R120-122, R125 R1, R13-19, R31-32, R37, R44-45, R47-54, R57, R59-61, R66, R68, R78-81 CT15-18 C3, C24, C27-29 C114 C19, C30-92, C94, C96-97, C99-109, C116 Reference Designator CR32-2211F-T PCT3226CT-ND DIG01 AVX CR21-1501F-T CR21-1004F-T AVX AVX CR21-4701F-T CR21-330JTR CRCW0805-103JRT1 AVX AVX DALE CR21-103J-T 293D106X9025C2T SPRAGUE AVX 08055C104KAT 08053C224FAT 08051C103KAT2A Part Number AVX AVX AVX Manufacturer Bill Of Materials A-5 A-6 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 8 1 2 6 6 2 3 1 1 1 58 59 60 61 62 63 64 65 66 1 55 57 5 54 3 1 53 56 10uF 16V 10% B TANT 4 52 53.6K 1/10W 1% 805 16K 1/8W5% 1206 0.47UF 20V 10% A TANT 10UF 25V +80-20% 1210 Y5V 30PF 100V 5% 1206 470PF 100V 10% 1206 CERM 1UF 16V 10% 805 X7R 270PF 50V 10% 805 0.047UF 16V 10% 1206 600 100MHZ 500MA 1206 0.70 BEAD 2A S2A_RECT DO-214AA SILICON RECTIFIER 1000 100MHZ 1.5A FER002 0.06 CHOKE 100 100MW 5% 805 1A HSM160J DO-214AA SCHOTTKY Description Ref. # MURATA C4, C22, C110-113 R95 R65 9C08052A5362FKRT/R CRCW1206-163JRT1 DALE PHILIPS T491A474K025AS GRM235Y.5V106Z025 12061A300JAT2A 12061A471JAT2A GRM40X7R105K016AL C1206C271J5GAC210 12065C473JATME 240-1019-1-ND S2A PLM250S40T1 CR21-101J-T HSM160J TAJB106K016R Part Number KEMET MURATA C93, C95, C98 CT14 AVX C17-18 AVX KEMET C11, C13 C12, C14-16, C20-21 AVX DIGIKEY GENERALSEMI C10 FER1-8 D1-3 MURATA AVX R67, R82, R85-86, R89 FER9 MICRO-SEMI AVX Manufacturer D4 CT4, CT19-21 Reference Designator 165K 1/10W 1% 805 1 1 1 1 1 1 1 3 2 5 1 6 1 1 3 7 4 1 1 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ADSP-BF535 EZ-KIT Lite Evaluation System Manual 81 82 83 84 85 20MHZ 1/2 OSC001 680 1/8W 5% 1206 4.7K 1/8W 5% 1206 270 1/8W 5% 1206 22 1/8W 5% 1206 20.0K 1/8W 1% 1206 100K 1/8W 5% 1206 10K 1/8W 5% 1206 1K 1/8W 5% 1206 10K 100MW 2% RNET16 BUSSED 39PF 50V 5% 805 NPO 10K 31MW 5% RNET8 1.00M 1/4W 1% 1210 243.0K 1/10W 1% 805 10UH 47+/-20 IND001 665K 1/10W 1% 805 332K 1/10W 1% 805 316K 1/10W 1% 805 Description Ref. # U2 CR32-681J-T EC1100HS-20.000MHZ ECLIPTEK CR32-472J-T CR32-271J-T AVX AVX R20, R22, R28-29 R74 AVX R69-73, R75-76 CRCW1206-2002FRT1 DALE CR1206-22R0JTR CR1206-1003FTR1 DALE DALE CRCW1206-1002FRT1 CR32-102J-T AVX DALE 767-161-103G ECJ-2VC1H390J PANASONIC CTS 746X101103J CTS ERJ-14NF1004U PANASONIC ECG SLF7045T-100M1R1-2 TDK 9C08052A2433FKRT/R 9C08052A6653FKRT/R PHILIPS PHILIPS 9C08052A3323FKRT/R 9C08052A3163FKRT/R PHILIPS PHILIPS 9C08052A1653FKRT/R Part Number PHILIPS Manufacturer R36, R39, R126 R104 R109 R23-27, R33 R38 RN1-5 C1-C2 RN6-8 R108 R106 L1 R100 R101 R103 R102 Reference Designator Bill Of Materials A-7 A-8 ADSP-BF535 EZ-KIT Lite Evaluation System Manual RED-SMT LED001 GULL-WING 2 1 5 5 1 1 1 3 1 2 86 87 88 89 90 91 92 93 94 95 3.5MM STEREO_JACK CON001 2.5A RESETABLE FUS001 IDC 2PIN_JUMPER 0.1 IDC 7X2 IDC7X2 IDC 3X2 IDC3X2 IDC 3X1 IDC3X1 QS3257Q QSOP16 QUICKSWITCH-257 1uF 25V 20% A TANT -55+125 GREEN-SMT LED001 GULL-WING Description Ref. # P5-6 F1 SJ1-3 P8 JP1 JP2 U14-15, U20-22 CT9-13 LED6 LED7-8 Reference Designator 54102-T08-07 BERG A/D ELECTONICS ST-323-5 RAYCHEM CORP. SMD250-2 15-38-1024 54102-T08-03 BERG MOLEX 54101-T08-03 BERG ADG774ABRQ ECS-T1EY105R PANASONIC ANALOG DEVICES LN1361C LN1261C Part Number PANASONIC PANASONIC Manufacturer A B C D 1 1 2 2 ADSP-BF535 EZ-KIT LITE 3 3 ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - TITLE Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-12-2003_15:48 D 1 of 12 A B PWR_MGT_OUT 3V_DSP C D VDD_INT VDD_RTC R2 0.00 1206 R6 0.00 1206 3.3V FOR RTC VDD_EXT 1.5V XTALI VDD_PLL R3 0.00 1206 1 R1 10K 805 R8 0.00 1206 R9 0.00 1206 XTALO Y1 XXMHZ 32.768KHZ OSC007 R10 0.00 1206 RN2 RN1 VDD_PCIEXT R4 33 805 U2 1 OE R7 0.00 1206 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 ARDY 5 OUT C2 39PF 805 CLKIN C1 39PF 805 20MHZ OSC001 PCI_RST PCI_CBE0 PCI_CBE1 PCI_CBE2 R34 DNP 1206 PCI_CBE3 0 OHM RESISTORS TO MEASURE DSP CURRENT PCI_GNT PCI_DEVSEL PCI_TRDY 16 COM 15 R15 14 R14 13 R13 12 R12 11 R11 10 R10 9 R9 PCI_SERR PCI_IRDY PCI_PERR PCI_PAR PCI_LOCK PCI_FRAME PCI_STOP PCI_INTD PCI_AD31 PCI_INTC PCI_AD28 PCI_INTB PCI_AD25 1 2 3 4 5 6 7 8 1 USB_CLK 3V_DSP 3V_DSP R1 COM R2 R15 R3 R14 R4 R13 R5 R12 R6 R11 R7 R10 R8 R9 USB_XVER_DATA 16 R11 0.00 1206 15 14 13 12 11 10 9 USB_DPLS R12 0.00 1206 PCI_AD21 PCI_AD17 USB_DMNS PCI_AD16 R77 0.00 1206 PCI_AD11 PCI_AD2 PCI_INTA PCI_CLK 10K RNET16 10K RNET16 R127 0.00 1206 PCI_IDSEL U1 U1 D[31:0] A[25:2] A2 A2 A3 B06 A4 D06 A5 2 A06 A3 A4 C06 A5 A6 A05 A7 B05 A8 A9 A10 A11 A12 A13 A6 A7 A04 A8 C05 A9 D05 A10 B04 A11 A01 A12 C04 A13 A14 D04 A15 A03 A16 B03 A14 A15 A16 A17 A02 A18 C03 A19 D03 A20 B02 A21 C02 A22 E03 A23 C01 A24 A25 A17 A18 A19 A20 A21 A22 A23 F03 A24 D02 A25 3 XTALI XTALO VDD_RTC VDD_PLL BYPASS CLKIN R10 XTALI T10 XTALO U10 VDD_RTC V11 VSS_RTC G09 VDD_PLL A10 VSS_PLL C12 BYPASS D09 CLKIN1 N02 D0 M03 D1 T01 D2 P02 D3 N03 D4 R02 D5 P03 D6 U01 D7 U02 D8 T02 D9 V02 D10 V03 D11 R04 D12 U03 D13 T03 D14 T04 D15 U04 D16 V04 D17 V05 D18 R05 D19 T05 D20 U05 D21 V06 D22 R06 D23 U06 D24 T06 D25 V07 D26 V08 D27 U07 D28 R07 D29 T07 D30 V09 D31 BMODE1 BMODE2 B14 BMODE0 A14 BMODE1 B13 BMODE2 TCK TDO TMS TRST D10 C11 D11 A12 B12 A13 EMU NMI SLEEP RESET A08 TX0 D1 RX0 TX0 D2 B08 RX1 D3 C08 TX1 D4 RX1 TX1 D5 D6 TMR0 D7 TMR1 B07 C07 D07 TMR2 D8 R01 ARDY D10 D11 AOE D12 ARE D13 AWE TMR1 TMR2 ARDY E01 AOE F01 ARE G01 AWE D14 D15 AMS0 D16 AMS1 D17 AMS2 D18 AMS3 F02 AMS0 D01 AMS1 H03 AMS2 G02 AMS3 D19 D20 ~ABE0/SDQM0 D21 ~ABE1/SDQM1 D22 ~ABE2/SDQM2 D23 ~ABE3/SDQM3 E02 R13 RSCLK0 U13 RFS0 V14 DR0 V15 TSCLK0 T14 TFS0 R14 DT0 ~ABE0/SDQM0 D26 SCAS D27 SWE ~ABE1/SDQM1 G03 ~ABE2/SDQM2 H07 ~ABE3/SDQM3 L02 SRAS L03 SCAS J03 SWE D30 SMS1 D31 SMS2 M02 SMS0 P01 SMS1 N01 SMS2 K03 SMS3 TCK SA10 TDI SCKE TDO TMS R119 33 805 TRST EMU DR0 PCI_AD2 TCLK0 PCI_AD3 TFS0 PCI_AD4 DT0 PCI_AD5 RCLK1 PCI_AD7 RFS1 PCI_AD8 DR1 PCI_AD9 TCLK1 U16 MOSI0 T16 MISO0 U17 SCK0 PCI_AD10 TFS1 PCI_AD11 DT1 PCI_AD12 MOSI0 PCI_AD14 MISO0 PCI_AD15 SCK0 PCI_AD16 PCI_AD17 T17 MOSI1 U18 MISO1 R16 SCK1 MOSI1 PCI_AD18 MISO1 PCI_AD19 SCK1 PCI_AD20 PCI_AD21 U08 MS_PF0 R08 MS_PF1 T08 MS_PF2 V10 MS_PF3 U09 MS_PF4 MSEL0/PF0 MSEL1/PF1 MSEL3/PF3 MSEL4/PF4 R09 MSEL5/PF5 T09 SMS0 PCI_AD1 PCI_AD13 MSEL6/PF6 D28 D29 RFS0 PCI_AD6 U14 RSCLK1 V16 RFS1 U15 DR1 T15 TSCLK1 R15 TFS1 V17 DT1 MSEL2/PF2 D25 PCI_AD0 B01 D24 SRAS RCLK0 TMR0 D9 SMS3 TDI BMODE0 A07 RX0 D0 U1 M01 SA10 L01 SCKE K01 SCLK0 H01 CLKOUT/SCLK1 R11 DF/PF7 T11 SSEL0/PF8 U11 SSEL1/PF9 V12 PF10 T12 PF11 R12 PF12 U12 PF13 V13 PF14 T13 PF15 MS_PF[6:0] PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 MS_PF5 PCI_AD27 MS_PF6 PCI_AD28 DF_PF7 PCI_AD29 SSEL0_PF8 PCI_AD30 SSEL1_PF9 PCI_AD31 E17 PCI_AD0 E18 PCI_AD1 G16 PCI_AD2 F17 PCI_AD3 F18 PCI_AD4 G18 PCI_AD5 G17 PCI_AD6 H18 PCI_AD7 J18 PCI_AD8 H17 PCI_AD9 K18 PCI_AD10 H16 PCI_AD11 L18 PCI_AD12 J17 PCI_AD13 M18 PCI_AD14 K17 PCI_AD15 J16 PCI_AD16 K16 PCI_AD17 N18 PCI_AD18 P18 PCI_AD19 L17 PCI_AD20 L16 PCI_AD21 R18 PCI_AD22 T18 PCI_AD23 M17 PCI_AD24 M16 PCI_AD25 N17 PCI_AD26 P17 PCI_AD27 P15 PCI_AD28 N16 PCI_AD29 R17 PCI_AD30 P16 PCI_AD31 PCI_CLK PCI_RST D14 PCI_CLK D18 F16 PCI_CBE0 F15 PCI_CBE1 E16 PCI_CBE2 D17 PCI_CBE3 RN8 PCI_CBE0 5 PCI_CBE1 10 PCI_CBE2 PCI_DEVSEL C14 PCI_INTA B15 PCI_INTB A15 PCI_INTC D13 PCI_INTD PCI_IDSEL 10K RNET8 PCI_INTA RN7 PCI_INTB 5 PCI_INTC 10 C17 PCI_PAR PCI_IRDY PCI_TRDY PF13 PF14 1 R1 2 R2 3 R3 4 R4 6 R5 7 R6 8 R7 9 R8 2 PCI_AD0 PCI_AD1 PCI_AD3 PCI_AD4 PCI_AD9 PCI_AD7 PCI_AD5 PCI_AD6 1 R1 2 R2 3 R3 4 R4 6 R5 7 R6 8 R7 9 R8 PCI_AD13 PCI_AD8 PCI_AD10 PCI_AD15 PCI_AD14 PCI_AD24 PCI_AD20 PCI_AD12 PCI_SERR 10K RNET8 PCI_PERR PCI_LOCK G07 3 RN6 PCI_STOP 5 COM1 COM2 USB_CLK A09 XVER_DATA C09 DPLS D08 DMNS B10 TXDPLS G10 TXDMNS C10 TXEN A11 SUSPEND PF12 COM2 PCI_FRAME 10 PF11 COM1 PCI_INTD C15 PCI_PAR E15 PCI_IRDY B17 PCI_TRDY B16 PCI_SERR D15 PCI_PERR A16 PCI_LOCK A17 PCI_STOP PF10 COM2 PCI_GNT C16 PCI_DEVSEL B18 PCI_IDSEL USB_CLK COM1 PCI_CBE3 D16 PCI_REQ C18 PCI_GNT PCI_FRAME 3V_DSP PCI_RST USB_XVER_DATA USB_DPLS USB_DMNS USB_TXDLPLS 1 R1 2 R2 3 R3 4 R4 6 R5 7 R6 8 R7 9 R8 PCI_AD29 PCI_AD18 PCI_AD26 PCI_AD19 PCI_AD30 PCI_AD23 PCI_AD22 PCI_AD27 USB_TXDMNS 10K RNET8 USB_TXEN USB_SUSPEND PF15 ADSP-BF535PKB-300 PBGA260 SCLK0 B11 ADSP-BF535PKB-300 PBGA260 NMI D12 R5 33 805 SLEEP B09 RESET CLKOUT ANALOG DEVICES ADSP-BF535PKB-300 PBGA260 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - DSP Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-25-2003_9:50 D 2 of 12 A B 3.3V C D 3.3V 1 1 RN3 1 PB0 2 PB1 3 PB2 4 PB3 5 PB4 6 PB5 7 PB6 8 PB7 16 COM 15 R15 14 R14 13 R13 12 R12 11 R11 10 R10 9 R9 R1 R2 R3 R4 R5 R6 R7 R8 512 KB MAIN FLASH 32KB SECONDARY FLASH RN4 1 PA0 PD0 PA1 PD1 PA2 PD3 16 COM 15 R15 14 R14 13 R13 12 R12 11 R11 10 R10 9 R9 R1 2 R2 3 R3 4 PA3 R4 5 PA4 R5 6 PA5 R6 7 PA6 R7 8 PA7 R8 ~ABE0/SDQM0 PC7 ~ABE3/SDQM3 PE6 A[21:2] A2 A3 PE7 10K RNET16 A5 A6 A7 A8 A9 A10 A11 A12 A13 3.3V A14 2 A15 A16 A17 A18 R13 10K 805 R14 10K 805 R15 10K 805 R16 10K 805 R17 10K 805 R18 10K 805 R19 10K 805 A19 A20 A21 AMS0 PC7 AOE ~ABE1/SDQM1 71 PE0/TMS 72 PE1/TCK 73 PE2/TDI 74 PE3/TDO 75 PE4/TSTAT 76 PE5/~TERR 77 PE6 78 PE7 3.3V 3 2 3 4 5 6 7 8 9 10 PE6 PE7 12 U13 U9 11 11 12 13 14 RESET 41 PC0 42 PC1 43 PC2 44 PC3 45 PC4 46 PC5 47 PC6 48 PC7 59 CNTL0/~WR 60 CNTL1/~RD 40 CNTL2 AWE P4 1 3 AD0 4 AD1 5 AD2 6 AD3 7 AD4 10 AD5 11 AD6 12 AD7 13 AD8 14 AD9 15 AD10 16 AD11 17 AD12 18 AD13 19 AD14 20 AD15 3 4 39 RESET 13 74LVC00AD SOIC14 74LVC14A SOIC14 SDRAM 4M X 16 D[31:0] U4 A4 10K RNET16 SDRAM 4M X 16 D[15:0] 31 PF0 32 PF1 33 PF2 34 PF3 35 PF4 36 PF5 37 PF6 38 PF7 21 PG0 22 PG1 23 PG2 24 PG3 25 PG4 26 PG5 27 PG6 28 PG7 51 PA0 52 PA1 53 PA2 54 PA3 55 PA4 56 PA5 57 PA6 58 PA7 61 PB0 62 PB1 63 PB2 64 PB3 65 PB4 66 PB5 67 PB6 68 PB7 D0 A[19:2] D1 U5 U6 D2 A2 23 A3 24 A4 25 A5 26 A6 29 A7 30 A8 31 A9 32 A10 33 A11 34 D3 D4 D5 D6 D7 D8 D9 D10 D11 22 D12 A13 35 D13 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D14 A19 21 A18 20 D15 PA0 16 PA1 17 PA2 18 BA1 BA0 15 PA5 39 D0 A2 23 D1 A3 24 D2 A4 25 D3 A5 26 D4 A6 29 D5 A7 30 D6 A8 31 D7 A9 32 D8 A10 33 D9 A11 34 D10 22 D11 A13 CAS RAS 35 D13 A19 21 D14 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A18 20 BA1 BA0 D15 16 19 17 37 CKE 38 CLK 18 CS 2 DQ0 4 DQ1 5 DQ2 7 DQ3 8 DQ4 10 DQ5 11 DQ6 13 DQ7 42 DQ8 44 DQ9 45 DQ10 47 DQ11 48 DQ12 50 DQ13 51 DQ14 53 DQ15 A0 D12 WE PA3 PA4 2 DQ0 4 DQ1 5 DQ2 7 DQ3 8 DQ4 10 DQ5 11 DQ6 13 DQ7 42 DQ8 44 DQ9 45 DQ10 47 DQ11 48 DQ12 50 DQ13 51 DQ14 53 DQ15 15 DQML 39 DQMH D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 2 D29 D30 D31 WE CAS CS 19 37 CKE 38 CLK RAS DQML DQMH PA6 MT48LC4M16 TSOP54 PA7 PB0 SA10 PB1 SWE PB2 SCAS PB3 SRAS PB4 ~ABE0/SDQM0 PB5 ~ABE1/SDQM1 PB6 ~ABE2/SDQM2 PB7 ~ABE3/SDQM3 MT48LC4M16 TSOP54 3 SCLK0 79 PD0 80 PD1 1 PD2 2 PD3 PD0 SCKE PD1 SMS0 SLEEP PD3 DSM2150F5V-12T6 TQFP80 7X2 IDC7X2SRDRA C3 0.1UF 805 C4 1UF 805 ANALOG DEVICES PSD JTAG HEADER 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - DSP MEMORY Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-12-2003_15:48 D 3 of 12 A B C D SJ2 SHORTING JUMPER DEFAULT=4 & 6 1 AUDIO CODEC AD1885 CT4 10UF B 1 A5V 3.3V SJ1 SHORTING JUMPER DEFAULT=3 & 5 C8 0.1UF 1206 POPULATE TO COMPLY WITH PC99 R21 0.00 1206 C114 0.22UF 805 U7 Analog Signals C11 270PF 805 ALT_VAL=1K 1 VDD1 9 VDD2 VSS1 C7 0.01UF 1206 DNP JP1 SETTINGS * Digital Signals 25 AVDD1 38 AVDD2 43 AVDD3 SJ1 SJ2 INPUT SOURCE 1&3 2&4 MIC IN 3&5 4&6 LINE IN * Denotes Default Setting 26 AVSS1 40 AVSS2 44 AVSS3 VSS2 XTAL_IN FER2 600 1206 R29 4.7K 1206 SDATA_IN 27 VREF 28 VREFOUT C112 1UF 805 C110 1UF 805 BIT_CLK 30 AFILT2 29 AFILT1 2 LINE IN/MIC 1 3 C111 1UF 805 TP1 SYNC JP1 AGND 3 2 4 C10 0.047UF 1206 C9 0.1UF 1206 DR0 DT0 R114 0.00 1206 6 C6 22PF 805 TCLK0 10 RFS0 11 C5 22PF 805 R118 0.00 1206 46 ID1 45 ID0 5 2 8 RCLK0 32 FILT_L 31 FILT_R P5 Y2 XXMHZ 24.576MHZ OSC005 2 5 SDATA_OUT RESET R22 4.7K 1206 C15 470PF 1206 7 3 XTL_OUT C13 270PF 805 AGND 4 33 RX3D 34 CX3D JS1 JS0 6 2 48 47 AGND 4 AGND 22 MIC2 21 MIC1 5 FER3 600 1206 1 R28 4.7K 1206 CON001 C14 470PF 1206 AGND D5 VC0805 40A 805 PHONE_IN C113 1UF 805 24 LINE_IN_R 23 LINE_IN_L TP2 AUX_L AUX_R TP3 36 LINE_OUT_R 35 LINE_OUT_L R20 4.7K 1206 D6 VC0805 40A 805 PC_BEEP 37 MONO_OUT 41 HP_OUT_R 39 HP_OUT_L AGND 12 13 14 R26 10K 1206 R25 10K 1206 R23 10K 1206 R24 10K 1206 15 16 VIDEO_L 17 VIDEO_R 18 CD_L 20 CD_R 19 CD_GND_REF JP2: 1885 DISABLE 1&2 DISABLE AD1885 * 2&3 NORMAL OPERATION * DENOTES DEFAULT SETTING AGND AD1885JST LQFP48 R30 2.21K 1206 SHGND JP2 1 3 CT7 220UF E FER1 600 1206 HEAD PHONE OUT P6 SJ3 3 PF15 2 3 SHORTING JUMPER DEFAULT=1 & 2 2 IDC3X1 3 W1 COPPER 4 C12 470PF 1206 5 R27 10K 1206 R32 10K 805 1 R112 0.00 1206 CON001 R31 10K 805 DNP AGND AGND AGND CT8 220UF E FER4 600 1206 AGND D7 VC0805 40A 805 C16 470PF 1206 D8 VC0805 40A 805 AGND R33 10K 1206 ANALOG DEVICES AGND 4 Approvals SHGND Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - AUDIO CODEC Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-21-2003_12:05 D 4 of 12 A B C D 3.3V RN5 1 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 BMODE0 BMODE1 BMODE2 MS0 MS1 MS2 MS3 MS4 COM R15 R14 R13 R12 R11 R10 R9 U9 16 MUL_SEL 15 MS5 14 MS6 13 MS_PF[0:6] DF 12 4 YA I0A SSEL0 11 SSEL1 10 MS_PF1 I1A 7 YB I0B BYPASS 9 MS_PF2 10K RNET16 MS_PF3 I1B 9 YC I0C I1C 12 YD 9 6 74LVC14A SOIC14 U20 MS_PF0 8 I0D I1D S 3 5 6 11 10 14 13 1 74LVC14A SOIC14 C19 0.01UF 805 PF0 MS1 PF1 MS2 PF2 MS3 PF3 MUL_SEL SW2 1 MS0 I0C YD I0D I1D S E 10 14 13 1 7 18 8 DF MS5 17 SSEL0 9 16 PF5 SSEL1 MS6 10 15 11 PF6 14 12 12 12 11 MS6 PF4 11 I1C 6 19 10 YC 5 MS5 MS4 9 I1B 9 DF_PF7 I0B 20 6 8 YB 5 7 MS_PF6 7 3 21 6 MS_PF5 I1A 2 4 5 MS4 I0A 22 4 2 YA 23 3 3 MS3 BYPASS DF 24 2 2 MS2 U21 ON 15 MS1 4 DSP_RESET_1 MS0 ADG774A QSOP16 MS_PF4 1 5 1 E 2 R65 16K 1206 U9 2 13 SWT014 DIP12 PF7 MUL_SEL 15 QS3257Q QSOP16 SW2: CLOCK MULTIPLIER SELECT SWITCH 1 2 3 4 5 6 7 8 9 10 11 12 OFF OFF OFF OFF ON ON ON ON OFF ON ON ON DEFAULT SETTINGS: Internal Clock - 15:1 - 300MHZ External Clock - 2.5:1 - 120MHZ REFER TO DSP HARDWARE REFERENCE FOR DETAILED SETTING INFOMATION U22 4 SSEL0_PF8 SW1 ON 3 YA 6 5 YB I0B I1B 9 SWT015 DIP3 I0A I1A 7 SSEL1_PF9 4 3 BMODE2 2 2 BMODE1 1 BMODE0 3 1 YC I0C I1C 12 YD I0D I1D 2 3 5 6 SSEL0 PF8 R66 10K 805 SSEL1 PF9 PF0 11 R120 10K 805 10 PF1 14 R121 10K 805 13 SW1 SETTINGS: BOOT MODE SELECTION BMODE2 ON * ON ON ON OFF * = DEFAULT BMODE1 ON ON OFF OFF - BMODE0 ON OFF ON OFF - BOOT MODE EXECUTE 16-BIT EXTERNAL 8-BITS ROM SPI0 ROM (8-BIT ADDRESS) SPI0 ROM (16-BIT ADDRESS) ALL OTHERS RESERVED S E 1 3 PF2 MUL_SEL R122 10K 805 15 PF3 QS3257Q QSOP16 ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - CONFIG Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-12-2003_15:48 D 5 of 12 A B C D 3.3V R83 10K 805 PF4 R82 100 805 R63 0.00 1206 U10 9 1 SW4 SWT013 SPST-MOMENTARY 8 PF4 3.3V 1 74LVC14A SOIC14 CT9 1UF A 3.3V USB RESET LED7 RED-SMT LED001 R90 10K 805 3.3V RESET LED8 RED-SMT LED001 3.3V 9 USB_CONFIGURED 8 USB_RESET 10 R84 10K 805 PF5 R64 0.00 1206 U10 5 SW5 SWT013 SPST-MOMENTARY U23 6 PF5 74LVC14A SOIC14 U24 1 MR 4 PFI SW8 SWT013 SPST-MOMENTARY RESET RESET 8 2 1A1 4 1A2 6 1A3 8 1A4 7 5 PFO CT10 1UF A 2 R75 270 1206 74LVC00AD SOIC14 R68 10K 805 R85 100 805 R76 270 1206 U13 RESET ADM708SAR SOIC8 PF[0:3] PF0 11 PF1 13 PF2 15 PF3 17 SOFT_RESET 18 1Y1 16 1Y2 14 1Y3 12 1Y4 DSP_RESET_1 5V 2 9 2Y1 7 2Y2 5 2Y3 3 2Y4 2A1 2A2 2A3 2A4 1 OE1 19 OE2 PF3 LED3 AMBER-SMT LED001 PF2 LED2 AMBER-SMT LED001 PF1 LED1 AMBER-SMT LED001 PF0 LED4 AMBER-SMT LED001 POWER LED6 GREEN-SMT LED001 IDT74FCT3244APY SSOP20 3.3V R69 270 1206 R70 270 1206 R71 270 1206 R72 270 1206 R74 680 1206 R88 10K 805 PF6 R89 100 805 11 3 R115 0.00 1206 U10 SW6 SWT013 SPST-MOMENTARY 10 PF6 74LVC14A SOIC14 1 CT12 1UF A U13 3 3 2 3.3V 74LVC00AD SOIC14 3.3V U9 1 2 74LVC14A SOIC14 R78 10K 805 R79 10K 805 R80 10K 805 U9 3.3V 3.3V 13 12 4 U13 U10 6 74LVC14A SOIC14 NMI R86 100 805 R116 0.00 1206 U10 13 74LVC14A SOIC14 12 R67 100 805 3 4 74LVC14A SOIC14 74LVC14A SOIC14 R117 0.00 1206 U9 11 PF7 SW3 SWT013 SPST-MOMENTARY 10 NMI 74LVC14A SOIC14 ANALOG DEVICES CT13 1UF A CT11 1UF A 4 2 R91 10K 805 R87 10K 805 SW7 SWT013 SPST-MOMENTARY U10 1 5 74LVC00AD SOIC14 PF7 R81 10K 805 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - RESET/PB/LED Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-13-2003_19:50 D 6 of 12 A B C D D[0:31] A[2:25] 3.3V 3.3V 5V 1 1.5V 1 DSP JTAG HEADER P2 2 1 4 3 P3 P1 2 ~ABE3/SDQM3 4 3 6 5 SCLK0 ~ABE0/SDQM0 A3 8 7 A2 A5 10 9 A4 A7 12 11 A6 A9 14 13 A8 A11 16 15 A10 A13 18 17 A12 A15 20 19 A14 A17 22 21 A16 A19 24 23 A18 A21 26 25 A20 A23 28 27 A22 A25 30 29 A24 32 31 2 34 33 36 35 SCKE SMS0 SMS1 SMS2 SMS3 ARDY AMS0 AMS1 AMS2 AMS3 PF5 D1 40 39 D0 D3 42 41 D2 PF7 D5 44 43 D4 D7 46 45 D6 D9 48 47 D8 D11 50 49 D10 D13 52 51 D12 D15 54 53 D14 D17 56 55 D16 57 SRAS PF3 37 58 SCAS PF1 38 D19 3 1 D18 D21 60 59 D20 D23 62 61 D22 D25 64 63 D24 D27 66 65 D26 PF9 PF11 PF13 PF15 RCLK1 RFS1 DR1 SCK0 MOSI0 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 54 53 56 55 58 57 60 MISO0 RX0 TX0 TMR1 NMI 59 62 61 64 63 66 65 68 67 D29 68 67 D28 70 69 D31 70 69 D30 72 71 72 71 74 73 74 73 76 75 78 77 78 77 80 79 80 79 82 81 82 81 84 83 84 83 86 85 86 85 88 87 87 90 89 90 1 4 3 SWE 6 5 SA10 8 7 10 9 12 11 14 13 16 15 18 17 ~ABE0/SDQM0 ~ABE1/SDQM1 PA0 ~ABE2/SDQM2 PA1 ~ABE3/SDQM3 PA2 AWE PA3 ARE PA4 AOE PA5 20 19 22 21 24 PA6 ~ABE0/SDQM0 26 PA7 ~ABE1/SDQM1 28 RESET ~ABE2/SDQM2 30 RESET 23 25 27 29 ~ABE3/SDQM3 32 31 PF0 34 33 PF2 36 35 PF4 38 37 PF6 40 39 PF8 42 41 PF10 44 43 PF12 46 45 PF14 48 47 TCLK1 50 49 TFS1 52 51 DT1 54 53 SCK1 56 55 MOSI1 58 57 MISO1 60 59 RX1 62 61 TX1 64 63 TMR0 66 65 TMR2 68 67 70 69 72 74 R57 10K 805 USB_CLK HEADER_SELECT USB_XVER_DATA USB_DPLS P8 1 2 USB_DMNS 3 4 USB_TXDLPLS 5 6 USB_TXDMNS 7 8 USB_TXEN 9 10 USB_SUSPEND 11 12 SLEEP 13 14 CLKOUT HEADER_EMU HEADER_TMS HEADER_TCK HEADER_TRST HEADER_TDI HEADER_TDO IDC7X2 2 SPORT0 P9 1 2 3 4 5 6 7 8 9 10 71 11 12 73 13 14 76 75 15 16 78 77 17 18 80 79 19 20 82 81 84 83 86 85 88 87 90 89 DT0 TFS0 TCLK0 RCLK0 3 75 76 88 2 RFS0 DR0 CON014 10X2 89 CON017 45X2 CON017 45X2 CON017 45X2 ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - CONNECTORS Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-13-2003_19:50 D 7 of 12 A B C D 1 PF14 PF13 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 PF12 VDD_INT 1 0 1 0 1 0 1 0 1.6V 1.5V 1.4V 1.3V 1.2V 1.1V 1.0V 0.9V * * = DEFAULT WAIT 100uS FOR VOLTAGE TO SETTLE AFTER CHANGING PF11-9 UNREG_IN PWR_MGT_OUT L1 10UH IND001 3V_DSP VR5 1 2 IN1 SW 2 IN2 DRV 3 GND1 GND2 4 COMP C22 1UF 805 FB R95 53.6K 805 8 C21 470PF 1206 2 7 6 R97 0.00 1206 R103 316K 805 5 ADP3088 MSOP8 R100 665K 805 R101 332K 805 R102 165K 805 R99 DNP 1206 R92 10K 805 R96 DNP 1206 C23 DNP 805 R93 10K 805 R94 DNP 805 3 R98 DNP 1206 C20 470PF 1206 3 M3 BSS123 SOT23D 3 1 M2 BSS123 SOT23D 1 M1 BSS123 SOT23D 1 PF14 2 2 2 PF13 D4 1A DO-214AA PF12 3 3 R104 20.0K 1206 R123 DNP 805 R124 DNP 805 R125 10K 805 ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - POWER 1 Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-12-2003_15:48 D 8 of 12 A B C D 1 1 5V F1 2.5A FUS001 FER9 CHOKE_COIL FER002 4 3 1 D2 2A DO-214AA UNREG_IN 3 INPUT 2 1 2 2 OUTPUT GND 1 ADP3339AKC-5 SOT-223 P10 D3 2A DO-214AA C26 1000PF 1206 R110 0.00 RC05 VR4 R109 100K 1206 CT16 10UF C C27 0.1UF 805 CT17 10UF C C28 0.1UF 805 5V A5V 3 7.5V_POWER CON005 FER6 600 1206 C25 1000PF 1206 2 2 SHGND 3.3V 5V 3V_DSP R113 0.00 1206 VR2 3 INPUT OUTPUT FER7 600 1206 5V R111 0.00 1206 VR1 2 3 INPUT GND 1 ADP3338AKC-33 SOT-223 FER8 600 1206 2 OUTPUT GND 1 ADP3338AKC-33 SOT-223 CT18 10UF C C29 0.1UF 805 CT15 10UF C D1 2A DO-214AA C24 0.1UF 805 SHGND VDD_INT 5V 3 3 1.5V R105 10K 805 MH1 MH2 MH3 MH4 MH5 VR3 2 INPUT 6 SD ERR OUTPUT R126 0.00 1206 3 1 5 FB GND 4 ADP3331ART SOT23-6 R128 34.8K 805 R106 243.0K 805 SHGND CT14 0.47UF A CT1 22UF D R108 1.00M 1210 ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - POWER 2 Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-25-2003_9:02 D 9 of 12 A B C D 3.3V 3.3V 1 C48 0.01UF 805 C47 0.01UF 805 C44 0.01UF 805 C45 0.01UF 805 C46 0.01UF 805 C50 0.01UF 805 C49 0.01UF 805 C54 0.01UF 805 C55 0.01UF 805 MT48LC4M16 (U5) C53 0.01UF 805 3.3V C52 0.01UF 805 C51 0.01UF 805 C56 0.01UF 805 C57 0.01UF 805 C102 0.01UF 805 C43 0.01UF 805 C42 0.01UF 805 1 MT48LC4M16 (U6) PSD4135 (U4) VDD_INT C93 10UF 1210 C95 10UF 1210 C98 10UF 1210 C82 0.01UF 805 C81 0.01UF 805 C78 0.01UF 805 2 VDD_EXT C79 0.01UF 805 C80 0.01UF 805 C83 0.01UF 805 C84 0.01UF 805 C85 0.01UF 805 C86 0.01UF 805 C87 0.01UF 805 C77 0.01UF 805 C76 0.01UF 805 C75 0.01UF 805 C71 0.01UF 805 C69 0.01UF 805 VDD_PLL C70 0.01UF 805 C68 0.01UF 805 C72 0.01UF 805 C73 0.01UF 805 C74 0.01UF 805 VDD_RTC C63 0.01UF 805 C64 0.01UF 805 2 ADSP-21535 INTERNAL (U1) ADSP-21535 EXTERNAL (U1) ADSP-21535 PLL (U1) ADSP-21535 RTC (U1) VDD_PCIEXT 3.3V CT21 10UF B C107 0.01UF 805 C106 0.01UF 805 C38 0.01UF 805 C32 0.01UF 805 3.3V C39 0.01UF 805 C97 0.01UF 805 C103 0.01UF 805 C104 0.01UF 805 C105 0.01UF 805 C61 0.01UF 805 CYC64603-128 (U11) 3 CT19 10UF B C40 0.01UF 805 C41 0.01UF 805 CT20 10UF B C65 0.01UF 805 C59 0.01UF 805 C60 0.01UF 805 C62 0.01UF 805 C88 0.01UF 805 C89 0.01UF 805 QS3257 (U14, U15, U20, U21, U22) C91 0.01UF 805 C90 0.01UF 805 C92 0.01UF 805 ADSP-21535 PCI (U1) 3.3V C36 0.01UF 805 C37 0.01UF 805 C108 0.01UF 805 IDT74FCT3244APY (U24) C34 0.01UF 805 C35 0.01UF 805 74LVC14A (U9, U10, U19) 3 A5V 3.3V C58 0.01UF 805 3.3V 3.3V C66 0.01UF 805 C67 0.01UF 805 C31 0.01UF 805 3.3V C30 0.01UF 805 3.3V C96 0.01UF 805 3.3V C109 0.01UF 805 3.3V C116 0.01UF 805 3.3V C94 0.01UF 805 3.3V C100 0.01UF 805 3.3V C101 0.01UF 805 3.3V C99 0.01UF 805 C33 0.01UF 805 AGND CY7C1019V33-15VC (U12) AD1885JST DIGITAL (U7) SN74LV164A (U17) SN74AHC1G02 (U16) SN74AHC1G00 (U26) CY7C4201V-15AC (U18) ADP3088 (VR5) ADM708SAR (U23) 24LC00-SN (U25) 74LVC00AD (U13) AD1885JST ANALOG (U7) ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - BYPASS CAPS Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-12-2003_15:48 D 10 of 12 A B C D 1 1 All USB interface circuitry is considered proprietary and has been omitted from this schematic 2 2 When designing your JTAG interface please refer to the Engineer to Engineer Note EE-68 which can be found at http://www.analog.com 3 3 ANALOG DEVICES 4 Approvals Date Title 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-BF535 EZ-KIT LITE - USB INTERFACE Drawn Checked Engineering A B C Size Board No. C Date Rev A0162-2000 1.6 Sheet 3-25-2003_11:11 D 11 of 12 I INDEX A C ADSP-BF535 processor core voltage, 2-2 DF pin, 2-8 internal SRAM, 1-6 MSEL0-6 pins, 2-8 peripheral interface voltage, 2-2 peripheral ports, -xiv real time clock (RTC), 2-3 SSEL1-0 pins, 2-8 ~AMS0, memory select pin, 1-6, 2-3 audio applications, xiv codec disable jumper (JP2), 2-6 input select jumper (JP1), 2-5 interface (SPORT0), 2-3 jacks (P5, P6), 2-13 codecs, xiii, 1-10, 2-3, 2-5, 2-6, A-3 connectors, 1-3, 2-12 P10 (power), 2-15 P1 (expansion), 2-4 P2 (expansion), 1-11 P3 (expansion), 2-5 P4 (FlashLINK), 2-13 P5 (audio), 2-5, 2-13 P6 (audio), 2-3, 2-13 P7 (USB), 2-14 P8 (JTAG), 2-5, 2-14 P9 (SPORT0), 2-4, 2-15 contents, EZ-KIT Lite package, 1-2 context switching, 1-16 using M3 register, 1-16 using SP, 1-17 core voltage, 1-11, 2-2 customer support, xvi B background telemetry channel (BTC), 1-12 bill of materials, A-1 boot load, 1-16 boot mode 8-bit, 1-9 external execution mode, 1-9 switch (SW1), xiii see also switch settings breakpoints, see hardware breakpoints D data breakpoints, 1-18 specific attributes, 1-19 default configuration, 1-3 DIP switches, 1-3, 2-5 E electrostatic discharge, 1-3 emulation events, 1-15 evaluation license restrictions, 1-6 ADSP-BF535 EZ-KIT Lite Evaluation System Manual I-1 INDEX example programs, 1-12 exceptions, 1-15 expansion interface, 2-3, 2-4, 2-12 see also connectors external bus interface unit (EBIU), 2-3 flash memory, see flash memory EZ-KIT Lite architecture, 2-2 configuration, 1-3 memory map, 1-6 start up, 1-5 F features, product, xii flash arrays boot & main, 1-8 flash memory, xiii, 1-7, 1-8, 2-3 FlashLINK (P4), 1-8, 2-13 PSDsoft Express, 1-8 flash programmer, 1-12 G graphical user interface (GUI), 1-13 H hard reset, 1-16 hardware breakpoints, 1-18 common attributes, 1-18 data type, 1-18 global options, 1-18 instruction type, 1-19 restrictions, 1-22 tips and tricks, 1-21 Help, online, xxi I-2 I instruction breakpoints specific attributes, 1-21 interface, see graphical user interface (GUI) internal memory, EZ-KIT Lite, 1-7 J JTAG connector (P8), 2-14 emulation port, 2-5 jumper settings, 1-3, 2-3, 2-5 codec disable (JP2), 2-4, 2-6 input select (JP1), 2-5 L latency cycles, 1-21 LEDs, 1-3, 2-9 LED1-4, 1-10, 2-10 LED5, 1-5, 2-10 LED6, 2-10 LED7, 2-10 LED8, 2-10 M M3 register, 1-16 measurements, 2-16 mechanical dimensions, 2-17 memory mapped registers (MMR), 1-11 FIO_DIR, 1-11 FIO_FLAG_C, 1-11 N non-maskable interrupt (NMI) pin, 2-11 push button (SW3), 2-11 notation conventions, xxii ADSP-BF535 EZ-KIT Lite Evaluation System Manual INDEX P package contents, 1-2 Performance Monitor Control dialog box, 1-15 peripheral interface voltage, 2-2 ports, xiv phase lock loop (PLL) setup switch (SW2), 2-7 PMGMT0-2, 1-10 power connector (P10), 2-15 LED (LED6), 2-10 management, 1-11 supply, 2-16 programmable flags (PFs), 2-7, 2-9, 2-11 PF0-3, 1-10, 2-10 PF12-14, 1-10, 1-11 PF15, 1-10, 2-4, 2-6 PF4-7, 1-10 push buttons, 2-7, 2-9 SW3, 2-11 SW4-7, 1-10, 2-11 SW8, 2-11 R registering, this product, 1-3 regulatory compliance, iii reset board, 1-16, 2-11 options, 1-22 processor, 1-10, 2-10 service routines, 1-14 resistors, 2-16 S SDRAM, 1-7, 2-3 setting hardware breakpoints, 1-18 target options, 1-22 ~SMS0, memory select pin, 1-6, 2-3 software breakpoints, 1-23 specifications, 2-15 SPORT0 (P9), xiv, 2-15 SP (stack pointer), 1-17 register, 1-17 switch settings boot mode select (SW1), 2-7 phase lock loop setup (SW2), 2-7 see also push buttons system architecture, EZ-KIT Lite board, 2-2 T target options miscellaneous, 1-23 on emulator exit, 1-23 reset, 1-22 Target Options dialog box, 1-16, 1-22 trace buffer, 1-14 destination, 1-14 instruction addresses, 1-14 number, 1-14 source, 1-14 Trace window, 1-13, 1-14 U USB cable, 1-3 connector (P7), 2-14 interface, 2-5 interface chip (U11), 2-11 monitor LED (LED5), 2-10 port, xiv V VDD_INT, core voltage, 1-11 ADSP-BF535 EZ-KIT Lite Evaluation System Manual I-3 INDEX VisualDSP++ documentation, xxi online Help, xxi starting, 1-5 voltage plane, 2-16 I-4 X XML register reset values, 1-7, 1-24 ADSP-BF535 EZ-KIT Lite Evaluation System Manual INDEX ADSP-BF535 EZ-KIT Lite Evaluation System Manual I-5