a AC’97 SoundMAX® Codec AD1885 AC’97 2.1 FEATURES Variable Sample Rate Audio Multiple Codec Configuration Options External Audio Power-Down Control ENHANCED FEATURES Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software-Enabled VREFOUT Output for Microphones and External Power Amp Split Power Supplies (3.3 V Digital/5 V Analog) Mobile Low-Power Mixer Mode Extended 6-Bit Master Volume Control Extended 6-Bit Headphone Volume Control Digital Audio Mixer Mode PHAT™ Stereo 3D Stereo Enhancement AC’97 FEATURES AC’97 2.1-Compliant Greater than 90 dB Dynamic Range Stereo Headphone Amplifier Multibit ⌺⌬ Converter Architecture for Improved S/N Ratio Greater than 90 dB 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for: LINE-IN, CD, VIDEO, and AUX Two Analog Line-Level Mono Inputs for Speakerphone and PC BEEP Mono MIC Input w/Built-In 20 dB Preamp, Switchable from Two External Sources High Quality CD Input with Ground Sense Stereo Line-Level Outputs Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Terminal LQFP Package FUNCTIONAL BLOCK DIAGRAM ID0 ID1 JS0/EAPD JS1 AD1885 JACK SENSES AND EAPD CTRL CHIP SELECT MIC1 VREF VREFOUT 0dB/ 20dB MIC2 LINE SELECTOR AUX CD VIDEO PGA 16-BIT ⌺⌬ A/D CONVERTER PGA 16-BIT ⌺⌬ A/D CONVERTER RESET PHONE_IN SYNC ⌺ HP_OUT_L LINE_OUT_L LINE_OUT_R HP_OUT_R SAMPLE RATE GENERATORS MMV HV MV MV HV G A M ⌺ ⌺ G A M G A M G A M G A M G A M AC LINK MONO_OUT POP BIT_CLK SDATA_OUT ⌺ PHAT STEREO ⌺ PHAT STEREO ⌺ ⌺ ⌺ POP A M PC_BEEP ⌺ ⌺ ⌺ ⌺ ⌺ ⌺ NC ⌺ ⌺ ⌺ G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME HV = HEADPHONE VOLUME NC G A M 16-BIT ⌺⌬ D/A CONVERTER G A M 16-BIT ⌺⌬ D/A CONVERTER ⌺ SDATA_IN ⌺ OSCILLATOR XTL_OUT XTL_IN SoundPort is a registered trademark and PHAT is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD1885–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (FS) Input Signal Analog Output Passband 25 °C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz DAC Test Conditions Calibrated –3 dB Attenuation Relative to Full Scale Input 0 dB 10 kΩ Output Load (LINE_OUT) 32 Ω Output Load (HP_OUT) ADC Test Conditions Calibrated 0 dB Gain Input –3.0 dB Relative to Full Scale ANALOG INPUT Parameter Min Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP MIC with 20 dB Gain (M20 = 1) MIC with 0 dB Gain (M20 = 0) Input Impedance* Input Capacitance* Typ Max Unit 1 2.83 0.1 0.283 1 2.83 20 5 7.5 V rms V p-p V rms V p-p V rms V p-p kΩ pF Typ Max Unit 80 dB dB dB dB dB dB dB Max Unit MASTER VOLUME Parameter Min Step Size (0 dB to –94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size (0 dB to –46.5 dB); MONO_OUT Output Attenuation Range Span* Step Size (+6 dB to –88.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental* 1.5 –94.5 1.5 –46.5 1.5 –94.5 PROGRAMMABLE GAIN AMPLIFIER—ADC Parameter Min Step Size (0 dB to 22.5 dB) PGA Gain Range Span Typ 1.5 22.5 dB dB ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS Parameter Min Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT Step Size (+12 dB to –34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC Step Size (0 dB to –45 dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP Typ Max Unit 90 90 dB dB 1.5 –46.5 3.0 –45 dB dB dB dB * Guaranteed, not tested. –2– REV. 0 AD1885 DIGITAL DECIMATION AND INTERPOLATION FILTERS* Parameter Min Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband 0 Typ 0.4 × FS 0.6 × FS –74 Max Unit 0.4 × FS ± 0.09 0.6 × FS ∞ 12/FS 0.0 Hz dB Hz Hz dB sec µs Max Unit ANALOG-TO-DIGITAL CONVERTERS Parameter Min Resolution Total Harmonic Distortion (THD Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error 84 Typ 16 –84 87 85 Bits dB dB dB –100 –90 –90 –85 ± 10 ± 0.5 ±5 dB dB % dB mV Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS Parameter Min Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT (With 10 kΩ Load) Dynamic Range LINE_OUT (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz)* 85 16 –85 –75 Bits dB dB 90 –100 ± 10 dB dB % dB ± 0.7 –80 dB dB Max Unit –40 ANALOG OUTPUT Parameter Min Full-Scale Output Voltage; LINE_OUT 1 2.83 Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance Full-Scale Output Voltage; HP_OUT (0 dB Gain) Output Capacitance* External Load Capacitance VREF VREFOUT VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output) *Guaranteed, not tested. REV. 0 Typ –3– 800 10 15 100 1 2.05 2.25 2.25 100 32 2.45 5 ±5 V rms V p-p Ω kΩ pF pF V rms pF Ω V V mA mV AD1885–SPECIFICATIONS STATIC DIGITAL SPECIFICATIONS* Parameter Min Typ High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), IOH = 2 mA Low-Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current 0.65 × DVDD Max Unit V 0.35 × DVDD V V 0.1 × DVDD V 10 µA 10 µA 0.9 × DVDD –10 –10 POWER SUPPLY Parameter Min Power Supply Range—Analog (AVDD) Power Supply Range—Digital (DVDD) Power Dissipation—5 V/3.3 V Analog Supply Current—5 V (AVDD) Digital Supply Current—3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) 4.75 3.15 Typ Max Unit 5.25 3.45 V V mW mA mA dB 355 50 21 40 CLOCK SPECIFICATIONS Parameter Min Typ Max Unit Input Clock Frequency Recommended Clock Duty Cycle 40 24.576 50 60 MHz % POWER-DOWN MODE* Parameter Set Bits DVDD (3.3 V) Typ AVDD (5 V) Typ Unit ADC DAC ADC and DAC ADC + DAC + Mixer (Analog CD On) Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Analog CD Only (AC-Link On) Analog CD Only (AC-Link Off) Standby Headphone Standby PR0 PR1 PR1, PR0 LPMIX, PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 LPMIX, PR5, PR1, PR0 LPMIX, PR1, PR0, PR4, PR5 PR5, PR4, PR3, PR2, PR1, PR0 PR6 20 20 8 8 21 19 19 8 7 0 0 21 44 41 35 26 23 18 15 10 22 12 0.1 38 mA mA mA mA mA mA mA mA mA mA mA mA NOTES *Guaranteed, not tested. Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice. –4– REV. 0 AD1885 TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter Symbol RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK NOTES *Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice. REV. 0 –5– Min Typ Max 1.0 162.8 1.3 19.5 162.8 12.288 81.4 tCLK_PERIOD tCLK_HIGH tCLK_LOW 32.56 32.56 tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF 5 5 2 2 2 2 2 2 2 2 0 15 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 750 48.84 48.84 10 10 10 10 10 10 10 10 10 25 15 50 15 Unit µs ns µs µs ns MHz ns ps ns ns kHz µs ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns AD1885 tRST_LOW tRST2CLK BIT_CLK RESET tRISECLK tFALLCLK BIT_CLK SYNC Figure 1. Cold Reset tRISESYNC tFALLSYNC SDATA_IN tRISEDIN tRST2CLK tSYNC_HIGH SYNC tFALLDIN SDATA_OUT BIT_CLK tRISEDOUT Figure 2. Warm Reset tFALLDOUT Figure 5. Signal Rise and Fall Time tCLK_LOW BIT_CLK SYNC tCLK_HIGH tCLK_PERIOD SLOT 1 SLOT 2 WRITE TO 0x26 DATA PR4 BIT_CLK tSYNC_LOW SDATA_OUT SYNC DON’T CARE tS2_PDOWN tSYNC_HIGH tSYNC_PERIOD SDATA_IN NOTE: BIT_CLK NOT TO SCALE Figure 3. Clock Timing Figure 6. AC-Link Low Power Mode Timing tSETUP RESET BIT_CLK SDATA_OUT SYNC tSETUP2RST SDATA_OUT SDATA_IN, BIT_CLK HI-Z tOFF tHOLD Figure 4. Data Setup and Hold Figure 7. ATE Test Mode –6– REV. 0 AD1885 ABSOLUTE MAXIMUM RATINGS* Parameter Power Supplies Digital (AVDD) Analog (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature ORDERING GUIDE Min –0.3 –0.3 –0.3 –0.3 0 –65 Max Unit +3.6 +6.0 ± 10 AVDD + 0.3 DVDD + 0.3 70 +150 V V mA V V °C °C Model Temperature Range Package Description Package Option* AD1885JST 0°C to 70°C 48-Lead LQFP ST-48 *ST = Thin Quad Flatpack. ENVIRONMENTAL CONDITIONS Ambient Temperature Rating TAMB = TCASE – (PD × θCA) TCASE = Case Temperature in °C PD = Power Dissipation in W θCA = Thermal Resistance (Case-to-Ambient) θJA = Thermal Resistance (Junction-to-Ambient) θJC = Thermal Resistance (Junction-to-Case) *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package JA JC CA LQFP 76.2°C/W 17°C/W 59.2°C/W CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1885 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. MONO_OUT HP_OUT_L AVDD2 NC HP_OUT_R AVSS2 ID0 AVSS3 AVDD3 ID1 JS0 (EAPD) JS1 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 DVDD1 1 XTL_IN 2 36 LINE_OUT_R PIN 1 IDENTIFIER 35 LINE_OUT_L XTL_OUT 3 DVSS1 4 34 CX3D 33 RX3D SDATA_OUT 5 32 FILT_L AD1885 BIT_CLK 6 DVSS2 7 31 FILT_R TOP VIEW (Not to Scale) SDATA_IN 8 DVDD2 9 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF SYNC 10 RESET 11 PC_BEEP 12 26 AVSS1 25 AVDD1 NC = NO CONNECT REV. 0 –7– MIC2 LINE_IN_L LINE_IN_R CD_GND_REF CD_R MIC1 VIDEO_R CD_L AUX_R VIDEO_L PHONE_IN AUX_L 13 14 15 16 17 18 19 20 21 22 23 24 WARNING! ESD SENSITIVE DEVICE AD1885–SPECIFICATIONS PIN FUNCTION DESCRIPTIONS Digital I/O Pin Name LQFP I/O Description XTL_IN XTL_OUT SDATA_OUT BIT_ CLK SDATA_IN SYNC RESET 2 3 5 6 8 10 11 I O I O/I O I I Crystal (or Clock) Input, 24.576 MHz. Crystal Output. AC-Link Serial Data Output, AD1885 Input Stream. AC-Link Bit Clock. 12.288 MHz Serial Data Clock. Daisy Chain Input Clock. AC-Link Serial Data Input. AD1885 Output Stream. AC-Link Frame Sync. AC-Link Reset. AD1885 Master H/W Reset. Pin Name LQFP Type Description ID0 ID1 45 46 I I Chip Select Input 0 (Active Low). Chip Select Input 1 (Active Low). CHIP SELECTS JACK SENSES/EAPD/GENERAL-PURPOSE DIGITAL OUTPUTS These signals can sense the presence of audio jacks in the line-out or headphones outputs, and automatically mute the other audio outputs. JS0 can also be programmed for EAPD control. Alternatively, both pins can be programmed as general-purpose digital outputs. Pin Name LQFP Type Description JS0 JS1 47 48 I/O I/O JACK Sense Input 0 (Mutes Mono Output). JACK Sense Input 1 (Mutes Line_Out and Mono Outputs, or Line_Out Only). Analog I/O These signals connect the AD1885 component to analog sources and sinks, including microphones and speakers. Pin Name LQFP I/O Description PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 39 41 I I I I I I I I I I I I I O O O O O PC Beep. PC speaker beep passthrough. Phone Input. From telephony subsystem speakerphone or handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. Video Audio Left Channel. Video Audio Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Microphone 1. Desktop microphone input. Microphone 2. Second microphone input. Line In Left Channel. Line In Right Channel. Line Out Left Channel. Line Out Right Channel. Monaural Output to Telephony Subsystem Speakerphone. Headphones Out Left Channel. Headphones Out Right Channel. –8– REV. 0 AD1885 Filter/Reference These signals are connected to resistors, capacitors, or specific voltages. Pin Name LQFP I/O Description VREF VREFOUT AFILT1 AFLIT2 FILT_R FILT_L RX3D CX3D 27 28 29 30 31 32 33 34 O O O O O O O I Voltage Reference Filter. Voltage Reference Output 5 mA Drive (Intended for Mic Bias). Antialiasing Filter Capacitor—ADC Right Channel. Antialiasing Filter Capacitor—ADC Left Channel. AC-Coupling Filter Capacitor—ADC Right Channel. AC-Coupling Filter Capacitor—ADC Left Channel. 3D PHAT Stereo Enhancement—Resistor. 3D PHAT Stereo Enhancement—Capacitor. Power and Ground Signals Pin Name LQFP Type Description DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3 1 4 7 9 25 26 38 40 43 44 I I I I I I I I I I Digital VDD 3.3 V Digital GND Digital GND Digital VDD 3.3 V Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND Pin Name LQFP Type Description NC 42 No Connects No Connect ID0 ID1 JS0/EAPD JACK SENSE AND EAPD CTRL CHIP SELECT 0dB/20dB M20 0x0E MS MIC2 1 LS/RS (0) S 0ⴛ20 LS (4) RS (4) S E LS (3) L RS (3) E LS (1) C RS (1) T LS (2) O RS (2) R LS/RS (7) LINE AUX CD VIDEO PHONE_IN STEREO MIX (L) MONO MIX STEREO MIX (R) MONO_OUT LS (5) LS/RS (6) RS (5) MV MIX 0x20 0x04 0x04 HPM LHV HP_OUT_L GA 0x0C PHV GA 0x0E MCV GA 0x10 LLV RLV GA 0x12 LCV RCV GA 0x16 LAV RAV GA 0x14 LVV RVV M 0x0C PHM M 0x0E MCM M 0x10 LM M 0x12 CM M 0x16 AM M 0x14 VM 0x02 0x02 MM LMV 0x02 0x02 MM LMV 0x04 0x04 HPM RHV LINE_OUT_R GAM 0x1C RIV IM RESET S 0x1A AD1885 D A M 0x22 PHAT DP 0x20 0x22 PHAT DP 0x20 NC GAM 0x18 LOV OM ⌺ 3D 0x20 SWITCH NC B M 0x0A PCM A 0x0A PCV G = GAIN A = ATTENUATION M = MUTE S = SELECTOR GAM 0x18 ROV OM ⌺ OSCILLATORS PC_BEEP XTL_OUT Figure 8. Block Diagram Register Map REV. 0 SYNC BIT_CLK SDATA_OUT A POP HP_OUT_R GAM 0x1C LIV IM SDATA_IN POP LINE_OUT_L VREFOUT VREF 0 AC-LINK MIC1 JS1 –9– XTL_IN AD1885 PRODUCT OVERVIEW Sample Rates and D2S The AD1885 Codec meets the Audio Codec ’97 2.1 Extensions, adding support for multiple Codecs and variable sample rates. In addition, the AD1885 SoundPort Codec is designed to meet all requirements of the Audio Codec ’97, Component Specification, Revision 1.03, © 1996, Intel Corporation, found at www.Intel.com. The AD1885 also includes other Codec enhanced features such as communicating to three Codecs on the same link, integrated headphone driver and built-in PHAT Stereo 3D enhancement. The AD1885 default mode sets the Codec to operate at 48 kHz sample rates. The converter pairs may process left and right channel data at different sample rates. The AD1885 sample rate generator allows the Codec to instantaneously change and process sample rates from 7040 Hz to 48 kHz with a resolution of 1 Hz. The in-band integrated noise and distortion artifacts introduced by rate conversions are below –90 dB. The AD1885 uses a 4-bit Σ∆ structure and D2S to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device’s quantization noise floor. The D2S process pushes noise and distortion artifacts caused by errors in the multibit DAC to frequencies beyond the auditory response of the human ear and then filters them. The AD1885 is an analog front end for high-performance PC audio, modem, or DSP applications. The AC’97 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high-quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs), mixer, and I/O. Digital-to-Analog Signal Path The analog output of the DAC may be gained or attenuated from +12 dB to –34.5 dB in 1.5 dB steps, and summed with any of the analog input signals. The summed analog signal enters the Master Volume stage where each channel of the mixer output may be attenuated from 0 dB to –94.5 dB in 1.5 dB steps or muted. The main architectural features of the AD1885 are the high quality analog mixer section, two channels of Σ∆ ADC conversion, two channels of Σ∆ DAC conversion and Data Direct Scrambling (D2S) rate generators. FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1885 and is intended as a general introduction to the capabilities of the device. Detailed reference information may be found in the descriptions of the Indexed Control Registers. Analog Outputs Analog Inputs Host-Based Echo Cancellation Support The Codec contains a stereo pair of Σ∆ ADCs. Inputs to the ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MIC1 or MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo CD ROM (CD), stereo audio from a video source (VIDEO) and post-mixed stereo or mono line output (LINE_OUT). The AD1885 supports time correlated I/O data format by presenting mic data on the left channel of the ADC and the mono summation of left and right output on the right channel. The ADC is splittable; left and right ADC data can be sampled at different rates. Analog Mixing The AD1885 contains a V.34-capable analog front end for supporting host-based and data pump modems. The modem DAC typical dynamic range is 90 dB over a 4.2 kHz analog output passband where FS = 12.8 kHz. The left channel of the ADC and DAC may be used to convert modem data at the same sample rate in the range between 7040 Hz and 48 kHz. All programmed sample rates have a resolution of 1 Hz. The AD1885 supports irrational V.34 sample rates with 8/7 and 10/7 selectable multiplier coefficients. The AD1885 offers a line output controlled by the Master Volume control and an integrated headphone driver with independent control. PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD, and VIDEO can be mixed in the analog domain with the stereo output from the DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from +12 dB to –34.5 dB in 1.5 dB steps. The summing path for the mono inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT and HP_OUT) duplicates mono channel data on both the left and right LINE_OUT and HP_OUT. Additionally, the PC attention signal (PC_BEEP) may be mixed with the line output and headphone. A switch allows the output of the DACs to bypass the PHAT Stereo 3D enhancement. Digital Audio Mode The AD1885 is designed with a Digital Audio Mode (DAM) that allows mixing of all analog inputs, independent of the DAC output signal path. Mixed analog input signals may be sent to the ADCs for processing by the DC ’97 controller or the host, and may be used during simultaneous capture and playback at different sample rates. Telephony Modem Support Power Management Modes The AD1885 is designed to meet notebook and ACPI power consumption requirements through flexible power management control of all internal resources. The following subsections may be independently controlled: Analog-to-Digital Signal Path The selector sends left and right channel information to the programmable gain amplifier (PGA). The PGA following the selector allows independent gain control for each channel entering the ADC from 0 dB to +22.5 dB in 1.5 dB steps. Each channel of the ADC is independent, and can process left and right channel data at different sample rates. –10– ADCs and Input Mux Power-Down DACs Power-Down Analog Mixer Power-Down Digital Interface Power-Down Internal Clocks Disabled ADC and DAC Power-Down VREF Standby Mode Low-Power Mixer Mode—CD Mixer Alive Only Mode Mixer Bypass Mode (Digital Audio) Headphone REV. 0 AD1885 Indexed Control Registers Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0410h 02h Master Volume MM X LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h 04h Headphones Volume HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 X X RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h 06h Master Volume Mono MMM X X X X X X X X MMV MMV MMV MMV MMV 8000h 4 3 2 1 0 X X 08h Reserved X X X X X X X X X X X X X X X X X 0Ah PC Beep Volume PCM X X X X X X X X X X PCV3 PCV2 PCV1 PCV0 X 8000h 0Ch Phone In Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 0Eh MIC Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h 10h Line In Volume LM X X LLV4 LLV3 LLV2 LLV1 LLV0 X X X RLV4 RLV3 12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCV0 X X X RCV4 14h Video Volume VM X X LVV4 LVV3 LVV2 LVV1 LVV0 X X X 16h Aux Volume AM X X LAV4 LAV3 LAV2 LAV1 LAV0 X X 18h PCM Out Volume OM X X LOV4 LOV3 LOV2 LOV1 LOV0 X 1Ah Record Select X X X X X LS1 LS0 1Ch Record Gain IM X X X LIM3 LIM2 LIM1 1Eh Reserved X X X X X X 20h General Purpose POP X 3D X X 22h 3D Control X X X X 26h Power-Down Cntrl/Stat X X PR5 28h Extended Audio ID ID1 ID0 2Ah Extended Audio Stat/Ctrl X X 2Ch/ PCM DAC Rate (SR1) SR15 PCM ADC Rate (SR0) 34h 8808h RCV3 RCV2 RCV1 RCV0 8808h RVV4 RVV3 RVV1 RVV0 8808h X RAV4 RAV3 RAV2 RAV1 RAV0 8808h X X ROV4 ROV3 ROV2 ROV1 ROV0 8808h X X X X X RS2 RS1 RS0 0000h LIM0 X X X X RIM3 RIM2 RIM1 RIM0 8000h X X X X X X X X X X X X MIX MS LPBK X X X X X X X 0000h X X X X X X X X DP3 DP2 DP1 DP0 0000h PR4 PR3 PR2 PR1 PR0 X X X X REF ANL DAC ADC 000Xh X X X X X X X X X X X X X VRA 0001h X X X X X X X X X X X X X VRA 0000h SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h Reserved X X X X X X X X X X X X X X X X X .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 72h Jack Sense/Audio JS1_OUT JS0_ JS1 JS0 JS1_ JS0 JS1 JS0 JS1 JS0_ JS1 JS0 AUD JS1 JS0 JS 0000h Interrupt/Status FUNCT OUT PUDIS PUDIS OE OE DIS DIS CLR CLR MODE MODE INT SLOT REG REG REG X X DHWR X X X 16 M2 M1 M0 DMS DLSR X RVV2 RLV1 8008h RLV0 LS2 RLV2 PHV1 PHV0 (7Ah)* 32h/ (78h)* 74h 76h Serial Configuration Miscellaneous Control DAC LPMI X Bits Z X DAM 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. *Indicates Aliased register for AD1819B backward compatibility. REV. 0 –11– ALSR MOD SRX1 SRX8 EN 0D7 D7 F0 S7 S6 S5 T0 REV7 REV6 REV5 INT X X X X X S4 REV4 X X 7000h DRSR X ARSR 0404h S3 S2 S1 S0 4144h REV3 REV2 REV1 REV0 5360h AD1885 Reset (Index 00h) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 00h X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0410h Reset Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1885 based on the following: Bit = 1 Function AD1885 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Dedicated MIC PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution 0 0 0 0 1 0 0 0 0 0 SE[4:0] Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement. Master Volume Registers (Index 02h) Reg Num Name D15 D14 D13 02h Master Volume MM MM X LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h RMV[5:0] Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of –94.5 dB. LMV[5:0] Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of –94.5 dB. MM Master Volume Mute. When this bit is set to “1,” the channel is muted. MM xMV5 . . . xMV0 Function 0 0 0 1 00 0000 01 1111 11 1111 xx xxxx 0 dB Attenuation –46.5 dB Attenuation –94.5 dB Attenuation –∞ dB Attenuation –12– REV. 0 AD1885 Headphones Volume Registers (Index 04h) Reg Num Name 04h Headphones Volume HPM X D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 X D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h RHV[5:0] Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of –88.5 dB. LHV[5:0] Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of –88.5 dB. HPM Headphone Volume Mute. When this bit is set to “1,” the channel is muted. HPM xHV5 . . . xHV0 Function 0 0 0 1 00 0000 01 1111 11 1111 xx xxxx 6 dB Gain –40.5 dB Attenuation –88.5 dB Attenuation –∞ dB Attenuation Master Volume Mono (Index 06h) Reg Num Name 06h Master Volume MMM X Mono D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X X X X X X X X MMV4 MMV3 MMV2 MMV1 MMV0 8000h MMV[4:0] Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. MMM Mono Master Volume Mute. When this bit is set to “1,” the channel is muted. PC Beep Register (Index 0Ah) Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 0Ah PC_BEEP Volume PCM X X X X X X X D7 D7 D6 D6 X X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 X PCV3 PCV2 PCV1 PCV0 X Default 8000h PCV[3:0] PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to Left and Right Line outputs even when AD1885 is in a RESET state. This is so that Power-On Self-Test (POST) codes can be heard by the user in case of a hardware problem with the PC. PCM PC Beep Mute. When this bit is set to “1,” the channel is muted. REV. 0 PCM PCV3 . . . PCV0 Function 0 0 1 0000 1111 xxxx 0 dB Attenuation –45 dB Attenuation ∞ dB Attenuation –13– AD1885 Phone Volume (Index 0Ch) Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 0Ch Phone Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHV0 8008h D3 D3 D2 D2 D1 D1 D0 D0 Default PHV[4:0] Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. PHM Phone Mute. When this bit is set to “1,” the channel is muted. MIC Volume (Index 0Eh) Reg Name Num 0Eh MIC Volume D15 D14 MCM X D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCV0 8008h MCV[4:0] MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. M20 Microphone 20 dB Gain Block 0 = Disabled; Gain = 0 dB 1 = Enabled; Gain = 20 dB. MCM MIC Mute. When this bit is set to “1,” the channel is muted. Line In Volume (Index 10h) Reg Name Num 10h D15 Line In Volume LM LM D14 D13 D12 X X D11 D10 D9 D9 D8 D8 D7 D7 LLV4 LLV3 LLV2 LLV1 LLV0 X D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X RLV4 RLV3 RLV2 RLV1 RLV0 8808h RLV[4:0] Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LLV[4:0] Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LM Line In Mute. When this bit is set to “1,” the channel is muted. CD Volume (Index 12h) Reg Name Num 12h D15 D14 CD Volume CVM X D13 D12 D11 D10 D9 D9 D8 D8 X LCV4 LCV3 LCV2 LCV1 LCV0 D7 D7 X D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X RCV4 RCV3 RCV2 RCV1 RCV0 8808h RCV[4:0] Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LCV[4:0] Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. CVM CD Volume Mute. When this bit is set to “1,” the channel is muted. –14– REV. 0 AD1885 Video Volume (Index 14h) Reg Name Num 14h D15 Video Volume VM VM D14 D13 D12 D11 D10 D9 D9 D8 D8 X X LVV4 LVV3 LVV2 LVV1 LVV0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X X RVV4 RVV3 RVV2 RVV1 RVV0 8808h RVV[4:0] Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LVV[4:0] Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. VM Video Mute. When this bit is set to “1,” the channel is muted. AUX Volume (Index 16h) Reg Name Num D15 D14 D13 D12 16h AM AM X X LAV4 LAV3 LAV2 LAV1 LAV0 Aux Volume D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X X RAV4 RAV3 RAV2 RAV1 RAV0 8808h RAV[4:0] Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LAV[4:0] Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. AM Aux Mute. When this bit is set to “1,” the channel is muted. PCM Out Volume (Index 18h) Reg Name Num 18h PCM Out Volume D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 OM OM X X LOV4 LOV3 LOV2 LOV1 LOV0 D7 D7 X D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X ROV4 ROV3 ROV2 ROV1 ROV0 8808h ROV[4:0] Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. LOV[4:0] Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled. OM PCM Out Volume Mute. When this bit is set to “1,” the channel is muted. Volume Table REV. 0 xM x4 . . . x0 Function 0 0 0 1 00000 01000 11111 xxxxx +12 dB Gain 0 dB Gain –34.5 dB Gain –∞ dB Gain –15– AD1885 Record Select Control Register (Index 1Ah) Reg Name Num 1Ah D15 Record Select X D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X X X LS2 LS1 LS0 X X X X X RS2 RS1 RS0 0000h RS[2:0] Right Record Select LS[2:0] Left Record Select. Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to MIC in. RS2 . . . RS0 Right Record Source 0 1 2 3 4 5 6 7 MIC CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN LS2 . . . LS0 Left Record Source 0 1 2 3 4 5 6 7 MIC CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN Record Gain (Index 1Ch) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 1Ch IM IM X X X LIM3 LIM2 LIM1 LIM0 X X X X RIM3 RIM2 RIM1 RIM0 8000h Record Gain RIM[3:0] Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. LIM[3:0] Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. IM Input Mute. 0 = Unmuted, 1 = Muted or –∞ dB gain. IM xIM3 . . . xIM0 Function 0 0 1 1111 0000 xxxxx +22.5 dB Gain 0 dB Gain –∞ dB Gain –16– REV. 0 AD1885 General-Purpose Register (Index 20h) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 20h POP X 3D 3D X X X MIX MS MS LPBK X X X X X X X 0000h General-Purpose Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. LPBK Loopback Control. ADC/DAC Digital Loopback Mode MS MIC Select 0 = MIC1 1 = MIC2. MIX Mono Output Select 0 = Mix 1 = MIC. 3D 3D PHAT Stereo Enhancement 0 = PHAT Stereo is off. 1 = PHAT Stereo is on. POP PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre- and post-3D PCM out paths are mutually exclusive). 0 = pre-3D 1 = post-3D. 3D Control Register (Index 22h) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 22h X X X X X X X X X X X X DP3 DP2 DP1 DP0 0000h 3D Control DP[2:0] REV. 0 Depth Control. Sets 3D “Depth” PHAT Stereo enhancement according to table below. DP3 . . . DP0 Depth 0000 0001 . . 14 15 0% 6.67% . . 93.33% 100% –17– AD1885 Subsection Ready Register (Index 26h) Reg Name Num 26h D15 D14 Power-Down Cntrl/Stat EAPD PR6 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 PR5 PR4 PR3 PR2 PR1 PR0 X D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X X REF ANL DAC ADC 000xh Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1885 subsections. If the bit is a one, then that subsection is “ready.” Ready is defined as the subsection able to perform in its nominal state. ADC ADC section ready to transmit data. DAC DAC section ready to accept data. ANL Analog gainuators, attenuators, and mixers ready. REF Voltage References, VREF and VREFOUT up to nominal level. PR[5:0] AD1885 Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR0 – Power-Down ADC PR1 – Power-Down DAC PR2 – Power-Down Analog Mixer PR3 – Power-Down VREF and VREFOUT PR4 – Power-Down AC-Link PR5 – Power-Down Internal Clock PR6 – Power-Down Headphone EAPD – External AMP Power-Down Control Signal PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can either be up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. Power-Down State EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 ADC Power-Down DAC Power-Down ADC and DAC Power-Down Mixer Power-Down ADC + Mixer Power-Down DAC + Mixer Power-Down ADC + DAC + Mixer Power-Down Standby X X X X X X X X 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 Extended Audio ID Register (Index 28h) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 28h ID1 ID0 X X X X X X X X X X X X X VRA 0001h Extended Audio ID Note: The Extended Audio ID is a read only register. VRA Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio. ID[1:0] ID1, ID0 is a 2-bit field that indicates the codec configuration: Primary is 00; Secondary is 01. –18– REV. 0 AD1885 Extended Audio Status and Control Register (Index 2Ah) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 2Ah X X X X X X X X X X X X X X X VRA 0000h Extended Audio St/Ctrl Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. VRA Variable Rate Audio. VRA = 1 enables support for Variable Rate Audio mode (sample rate control registers and SLOTREQ signaling). PCM DAC Rate Register (Index 2Ch) Reg Num Name 2Ch/(7Ah) PCM DAC Rate D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned. PCM ADC Rate Register (Index 32h) Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 32h/(78h) PCM ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned. Jack Sense/Audio Interrupt/Status Register (Index 72h) Reg Num Name 72h Jack Sense/Audio JS1_OUT/ Interrupt/Status FUNCT D15 D14 D13 D12 D11 D10 D9 D9 JS0_ OUT JS1 JS0 JS1_ JS0_ JS1 PUDIS PUDIS OE OE OE OE DIS D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 JS0 JS1 JS0 JS1 JS0 AUD DIS CLR CLR MODE MODE INT D2 D2 D1 D1 JS1 JS0 D0 D0 Default JS JS INT 0000h Note: all register bits are read/write except for AUDINT, JSINT, JS0 and JS1, which are read only. JSINT Indicates that a jack sense interrupt has been generated by JS0 or JS1. Remains set until all JS enabled interrupts are cleared. JS0 Indicates Pin JS0 state. JS1 Indicates Pin JS1 state. AUDINT Indicates the Codec has generated audio interrupt. Remains set until software clears all pending interrupts. JS0MODE Sets JS0 pin input mode, 1 = Interrupt 0 = Jack Sense. JS1MODE Sets JS1 pin input mode, 1 = Interrupt 0 = Jack Sense. JS0CLR This bit is set by the Codec when there is a pending JS0 interrupt. Software must clear this bit to clear the JS0 interrupt status bit. JS1CLR This bit is set by the Codec when there is a pending JS1 interrupt. Software must clear this bit to clear the JS1 interrupt status bit. JS0DIS If the JS0DIS bit is set, the Codec ignores Jack Sense pin JS0. JS1DIS If the JS1DIS bit is set, the Codec ignores Jack Sense pin JS1. REV. 0 –19– AD1885 JS0_OE Enables JS0 pin as a general-purpose output. JS1_OE Enables JS1 pin as a general-purpose output. JS0PUDIS Setting the JS0PUDIS bit disables the JS0 pin internal pull-up. JS1PUDIS Setting the JS1PUDIS bit disables the JS1 pin internal pull-up. JS0_OUT When enabled as GPO, the JS0 pin reflects the state of the JS0_OUT bit. JS1_OUT/FUNCT When enabled as GPO, the JS1 pin reflects the state of the JS1_OUT bit, otherwise this bit can be set to change the functionality of JS1 so that only LINE_OUT is muted when JS1 is high. Serial Configuration (Index 74h) Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 74h Serial Configuration SLOT 16 16 REGM2 REGM1 REGM0 X X DHWR X X X X X X X X X X Note: this register is not reset when the reset register (register 00h) is written. DHWR Disable Hardware Reset. REGM0 Master Codec register mask. REGM1 Slave 1 Codec register mask. REGM2 Slave 2 Codec register mask. SLOT16 Enable 16-bit slots. If your system uses only a single AD1885, you can ignore the register mask. SLOT16 makes all AC-Link slots 16 bits in length, formatted into 16 slots. Miscellaneous Control Bits (Index 76h) Reg Name Num D15 D14 D13 D12 76h DAC Z LPMI X X Misc Control Bits D11 D10 D9 D9 DAM DMS DLSR X ARSR ADC right sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DRSR DAC right sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). SRX8D7 Multiply SR1 rate by 8/7. D8 D8 D7 D7 D6 D6 D5 D5 ALSR MOD EN EN SRX10 SRX8 D7 D7 D7 D7 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default X X DRSR X ARSR 0000h SRX10D7 Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive. MODEN Modem filter enable (left channel only). Change only when DACs and ADCs are powered down. ALSR ADC left sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DLSR DAC left sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DMS Digital Mono Select. 0 = Mixer 1 = Left DAC and Right DAC. DAM Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output. LPMIX Low Power Mixer. DACZ Zero fill (vs. repeat) if DAC is starved for data. –20– REV. 0 AD1885 Sample Rate 0 (Index 78h) Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default (32h)/78h Sample Rate 0 SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR0[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results. Sample Rate 1 (Index 7Ah) Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default (2Ch)/7Ah Sample Rate 1 SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR1[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results. Vendor ID Registers (Index 7Ch–Eh) Reg Name Num D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 7Ch F7 F7 F6 F6 F5 F5 F4 F4 F3 F3 F2 F2 F1 F1 F0 F0 S7 S7 S6 S6 S5 S5 S4 S4 S3 S3 S2 S2 S1 S1 S0 S0 4144h D2 D2 D1 D1 Vendor ID1 S[7:0] This register is ASCII encoded to “S.” F[7:0] This register is ASCII encoded to “D.” Reg Name Num 7Eh D15 Vendor ID2 T7 T7 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 T6 T6 T5 T5 T4 T4 T3 T3 T2 T2 T1 T1 T0 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5360h T[7:0] This register is ASCII encoded to “S.” REV[7:0] Revision Register field contains the revision number. D6 D6 D5 D5 These bits are read-only and should be verified before accessing vendor defined features. REV. 0 –21– D4 D4 D3 D3 D0 D0 Default AD1885 APPLICATIONS CIRCUITS The AD1885 has been designed to require a minimum amount of external circuitry. The recommended applications circuits are shown in Figures 9–18. Reference designs for the AD1885 are available and may be obtained by contacting your local Analog Devices sales representative or authorized distributor. Example shell programs for establishing a communications path between the AD1885 and an ADSP-21xx or ADSP-21xxx are also available. AVDD 22pF 24.576MHz SDATA_OUT SDATA_IN SYNC RESET BIT_CLK 47pF DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP AD1885 LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1 36 35 34 33 32 31 30 29 28 27 26 25 47nF + 270pF NPO + 270pF NPO + AVDD 13 14 15 16 17 18 19 20 21 22 23 24 10k PC_BEEP 1 2 3 4 5 6 7 8 9 10 11 12 PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R + 22pF NC JS1 JSO/EAPD ID1 ID0 AVSS3 AVDD3 NC HP_OUT_R AVSS2 HO_OUT_L AVDD2 MONO_OUT 48 47 46 45 44 43 42 41 40 39 38 37 DVDD NC NC + NOTE: IF NOT USED, GROUND JACK SENSE PINS. FB 600Z NOTE: ALL “UNUSED” ANALOG INPUTS (LINE_IN_L/R, AUX_L/R, VIDEO_L/R, MIC1, MIC2, PC_BEEP, PHONE_IN AND CD_L/R/GND) MUST BE LEFT UNCONNECTED. Figure 9. Recommended One-Codec PWR/Decoupling and AC‘97 Connections –22– REV. 0 AD1885 JACK SENSE OPERATION The AD1885 features two Jack Sense pins (JS0 and JS1) that can be used to automatically mute the LINE_OUT and/or MONO_OUT audio outputs. When the Jack Sense pins are connected to the output jacks, the AD1885 can sense whether an audio plug has been inserted into a particular output jack and automatically mute the other unnecessary audio outputs. The JS1 pin should normally be connected to the HP_OUT jack to automatically mute the MONO_OUT and LINE_OUT audio signals, while the JS0 pin should normally be connected to the LINE_OUT jack to automatically mute the MONO_OUT signal. It is also possible to set the D15 bit in the Jack Sense Index Register (72h), which causes JS1 to only mute the LINE_OUT signal. This option may be desirable in certain audio configurations. Table I summarizes the Jack Sense operation. Table I. Jack Sense Operation Table HP_OUT Plug (JS1) LINE_OUT Plug (JS0) Audio Output States (REG 72h, D15 = 0) Audio Output States (REG 72h, D15 = 1) OUT OUT OUT IN IN OUT IN IN HP_OUT = ON LINE_OUT = ON MONO_OUT = ON HP_OUT = ON LINE_OUT = ON MONO_OUT = MUTE HP_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE HP_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE HP_OUT = ON LINE_OUT = ON MONO_OUT = ON HP_OUT = ON LINE_OUT = ON MONO_OUT = MUTE HP_OUT = ON LINE_OUT = MUTE MONO_OUT = ON HP_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE NOTE: PLUG IN = JACK SENSE HIGH, PLUG OUT = JACK SENSE LOW. The Jack Sense inputs are active high and their functionality is enabled by default on CODEC power-up. If necessary, the Jack Sense inputs can be individually disabled by writing to the D8 and D9 bits on the CODEC Jack Sense Index Register (72h). The Jack Sense pins contain active internal pull-ups. If the Jack Sense inputs are not being used, they should be pulled down to digital ground using 10 kΩ resistors. This prevents LINE_OUT and MONO_OUT from becoming muted while the Jack Senses are enabled. CONNECTING THE JACK SENSES TO THE OUTPUT JACKS Headphone Jack The diagram on Figure 10 shows the preferred method to connect the JS1 Jack Sense line to the HP_OUT jack. This scheme requires a stereo jack with a normally closed and isolated single switch. The switch holds the Jack Sense line low (grounded) until an audio plug is inserted, causing the switch to open and the Jack Sense line to go high due to the CODEC internal pull-up. The R2 and R3 resistors keep the electrolytic output caps properly polarized while the HP_OUT jack is not used. NOTE: LOCATE R1 CLOSE TO CODEC. JACK SENSE LINE TO CODEC JS1 (PIN 48) OPTIONAL EMC COMPONENTS FROM CODEC HP_OUT_R (PIN 41) + L1 600Z FROM CODEC HP_OUT_L (PIN 39) + L2 600Z C1 470pF C4 470pF 5 4 3 ISOLATED NC SWITCH 2 1 HEADPHONE OUT Figure 10. Jack Sense Connection to HP_OUT Jack, Using Isolated Switch Alternatively, when an audio output jack containing an isolated switch is not available, the circuit shown on Figure 11 can be used. While the audio plug is out, this circuit keeps the Jack Sense line state low, by the pull-down affect of R2 (with no audio present) or by tracking the lower peaks of the HP_OUT audio signal. Once an audio plug is inserted and the jack switch opens, the Jack Sense line switches to a high state due to the CODEC internal pull-up, which quickly charges C1 to DVDD. The R2 and R3 resistors also keep the electrolytic output caps properly polarized while the HP_OUT jack is not used. REV. 0 –23– AD1885 NOTE: LOCATE R1 AND C1 CLOSE TO CODEC. JACK SENSE D1 TO CODEC JS1 (PIN 48) MMBD914 OPTIONAL EMC COMPONENTS L1 600Z FROM CODEC HP_OUT_R (PIN 41) + C4 470pF 1 2 3 4 5 L2 600Z FROM CODEC HP_OUT_L (PIN 39) + C5 470pF J1 HEADPHONE OUT Figure 11. Jack Sense Connection to HP_OUT Jack, Using Nonisolated Switch LINE_ OUT Jack Although not shown, if a LINE_OUT jack is used and the jack sense functionality is desired, the LINE_OUT jack should be wired in a similar configuration as shown above for the HP_OUT jack (preferably Figure 10). The LINE_OUT jack should normally be connected to the JS0 input, in order to mute the MONO_OUT signal. We recommend that in this case the output coupling caps (C2, C3) be set to 2.2 µF. All other values should be kept the same. APPLICATION CIRCUITS CD-ROM CONNECTIONS Typical CD-ROM drives generate 2 V rms output and require a voltage divider for compatibility with the Codec input (1 V rms range). The recommended circuit is basically a group of divide-by-two voltage dividers as shown on Figure 12. The CD_GND_REF pin is used to cancel differential ground noise from the CD-ROM. For optimum noise cancellation, this section of the divider should have approximately half the impedance of the right and left channel section dividers. VOLTAGE DIVIDER AC-COUPLING TO CODEC CD_L INPUT HEADER FOR CD ROM AUDIO (LGGR) 1 2 3 4 TO CODEC CD_GND_REF INPUT TO CODEC CD_R INPUT Figure 12. Typical CD-ROM Audio Connections LINE_IN, AUX AND VIDEO INPUT CONNECTIONS Most of these audio sources also generate 2 V rms audio level and require a –6 dB input voltage divider to be compatible with the Codec inputs. Figure 13 shows the recommended application circuit. For applications requiring EMC compliance, the EMC components should be configured and selected to provide adequate RF immunity and emissions control. EMC COMPONENTS LINE/AUX/VIDEO INPUT J1 1 2 3 4 5 VOLTAGE DIVIDER AC-COUPLING L2 600Z TO CODEC RIGHT CHANNEL INPUT C1 470pF L1 600Z TO CODEC LEFT CHANNEL INPUT C2 470pF Figure 13. LINE_IN, AUX, and Video Input Connections –24– REV. 0 AD1885 MICROPHONE CONNECTIONS The AD1885 contains an internal microphone preamp with 20 dB gain; in most cases a direct microphone connection as shown in Figure 14 is adequate. If the microphone level is too low, an external preamp can be added as shown in Figure 15. In either case the microphone bias can be derived from the Codec’s internal reference (VREFOUT) using a 2.2 kΩ resistor. For the preamp circuit, the VREFOUT signal can also provide the midpoint bias for the amplifier. To meet the PC99 1.0A requirements, the MIC signal should be placed on the microphone jack tip and the bias on the ring. This configuration supports electret microphones with three conductor plugs, as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). Additional filtering may be required to limit the microphone response to the audio band of interest. EMC COMPONENTS J1 L1 600Z 1 2 3 4 5 AC-COUPLING C2 470pF L2 600Z TO CODEC MIC1 OR MIC2 INPUT C1 470pF MIC BIAS MIC INPUT FROM CODEC VREFOUT Figure 14. Recommended Microphone Input Connections PREAMP EMC COMPONENTS J1 L1 600Z 1 2 3 4 5 AC-COUPLING C2 470pF AVDD 4 L2 600Z C1 470pF U1 MIC INPUT MIC BIAS TO CODEC MIC1 OR MIC2 INPUT AD8531 FROM CODEC VREFOUT Figure 15. Microphone with Additional External Preamp (20 dB Gain) LINE OUTPUT CONNECTIONS The AD1885 Codec provides stereo LINE_OUT signals at a standard 1 V rms level. These signals must be ac-coupled before they can be connected to an external load. After the ac-coupling, a minimal resistive load is recommend to keep the capacitors properly biased and reduce click and pop when plugging stereo equipment into the output jack. The capacitor values should be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. To meet the PC99 specification for PCs, testing must be performed with a 10 kΩ load, therefore a 1 µF value is recommended to achieve less than –3 dB roll-off at 20 Hz. EMC COMPONENTS AC-COUPLING STEREO LINE_OUT JACK J1 L2 600Z FROM CODEC LINE_OUT_R C1 470pF L1 600Z FROM CODEC LINE_OUT_L C2 470pF NOTE: IF AN OUTPUT AMP IS USED, THE AC-COUPLING CAP VALUES WILL DEPENDEND ON THE AMP DESIGN. Figure 16. Recommended LINE_OUT Connections REV. 0 –25– AD1885 PC_BEEP INPUT CONNECTIONS The recommended PC_BEEP input circuit is shown below. Under most cases the PC_BEEP signal should be attenuated, filtered and then ac-coupled into the Codec. PC_BEEP (FROM ICH) TO CODEC PC_BEEP INPUT Figure 17. Recommended PC_BEEP Connections GROUNDING AND LAYOUT To reduce noise and emissions, Analog Devices recommends a split ground plane as shown in Figure 18. The purpose of splitting the ground plane is to create a low noise analog area that is somewhat isolated from the digital ground current noise generated by the system’s logic. All the analog circuitry should be placed on the analog ground plane area. For reference purposes, and to return power supply currents, the analog and digital ground planes must be connected at some point, ideally a small bridge under or near the Codec should be provided. A 0 Ω resistor or a ferrite bead should also be considered since these allow some flexibility in optimizing the layout to meet EMC requirements. DIGITAL GROUND PLANE CONNECT SPLIT GROUND PLANES AT OR NEAR CODEC. PIN 1 ISOLATION TRENCH AD1885 ANALOG GROUND PLANE Figure 18. Recommended Split Ground Plane ANALOG POWER SUPPLY To minimize audio noise, the Codec analog power supply (AVDD) should be well decoupled and regulated. In PC systems it is recommended that the analog supply be derived from the 12 V PC power supply using a localized linear voltage regulator. Preferably, the analog power supply should be connected to the Codec’s analog section using a ferrite bead. If a power plane layer is being used in the system design, it is recommended that the analog power plane for the Codec also be split (mirroring the analog ground plane). In this case, the analog power supply ferrite bead should bridge the isolation trench, close to the Codec location. –26– REV. 0 AD1885 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (1.45) (0.75) 0.057 0.018 (1.35) (0.45) 0.053 0.276 (7.0) BSC 0.276 (7.0) BSC 37 36 48 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15) 0.002 (0.05) 0.007 (0.18) 0.004 (0.09) 12 13 0.019685 (0.5) BSC 25 24 0.011 (0.27) 0.006 (0.17) PRINTED IN U.S.A. 0 –7 0 MIN 0.354 (9.00) BSC 0.030 (0.75) 0.018 (0.45) C00753–2.5–7/00 (rev. 0) 48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48) REV. 0 –27–