SDP User Guide UG-502 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com SDP-H1 Controller Board INTRODUCTION This user guide describes the EVAL-SDP-CH1Z system demonstration platform-high speed (SDP-H1) controller board from Analog Devices, Inc. The SDP-H1 controller board is part of the Analog Devices system demonstration platform (SDP). The SDP consists of a series of controller boards, interposer boards, and daughter boards. SDP controller boards provide a means of communicating with the PC from the system under evaluation. Interposer boards route signals between two connectors. Daughter boards are a collection of product evaluation boards and Circuits From The Lab™ (CFTL) reference circuit boards. The SDP-H1 is used as part of the evaluation system for many Analog Devices components and reference circuits. The primary audience for this user guide is a system engineer who seeks to understand how to set up the SDP-H1 board and begin USB communications to the PC. The SDP-H1 board is designed to be used in conjunction with various Analog Devices component evaluation boards and Circuits From The Lab reference circuits as part of a customer evaluation environment. The SDP-H1 provides USB connectivity through a USB 2.0 high speed connection to the computer allowing users to evaluate components on this platform from a PC application. The SDP-H1 has a Xilinx Spartan-6 FPGA and an ADSP-BF527 Blackfin processor. The Xilinx Spartan-6 FPGA connects to an FMC low pin count (LPC) connector. This connector provides power to the daughter board (see the Power section for more details) and LVDS and LVCMOS signal support. The Blackfin processor peripherals communication lines are available through an SDP 120-pin small footprint connectors. The Blackfin processor also provides the USB controller for the board and allows the user to configure the FPGA. The SDP-H1 user guide provides instructions for installing the SDP-H1 hardware (EVAL-SDP-CH1Z board) and software onto your computer. The necessary installation files are provided with the evaluation daughter board package. The Getting Started section provides software and hardware installation procedures, PC system requirements, and basic board information. The Hardware Description section provides information on the EVAL-SDP-CH1Z components. The EVAL-SDP-CH1Z schematics are provided in the Schematics section. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 32 UG-502 SDP User Guide TABLE OF CONTENTS Introduction ...................................................................................... 1 Powering Up/Powering Down the SDP .....................................4 Revision History ............................................................................... 2 Hardware Description.......................................................................5 Product Overview............................................................................. 3 LEDs ................................................................................................5 Technical or Customer Support.................................................. 3 SDP Connector Details .................................................................5 Product Information .................................................................... 3 FMC Connector Details ............................................................ 10 Regulatory Compliance ............................................................... 3 SMA Connectors ........................................................................ 15 Getting Started .................................................................................. 4 Power............................................................................................ 15 Package Contents .......................................................................... 4 Mechanical Specifications ......................................................... 15 PC Configuration ......................................................................... 4 Schematics ....................................................................................... 17 USB Installation ............................................................................ 4 REVISION HISTORY 4/13—Revision 0: Initial Version Rev. 0 | Page 2 of 32 SDP User Guide UG-502 PRODUCT OVERVIEW The SDP-H1 board features TECHNICAL OR CUSTOMER SUPPORT • • You can reach Analog Devices customer support in the following ways: • • • • • • • • • Xilinx Spartan-6 FPGA DDR2 • Micron MT47H32M16HR-25E:G – 8Mb × 16 bits × 4 Banks (512 Mb/64 MB) SRAM • ISSI IS61WV25616BLL-10BLI – 256Kb × 16 bits (4 Mb/512 Kb) 1 × 160-pin FMC-LPC connector. (For further information, see the VITA 57 specification FMC Marketing Alliance available from VITA Technologies.) • Samtec ASP-134603-01 • Up to 1,080 Mb/s LVDS • Single-ended LVCMOS • Power Analog Devices ADSP-BF527 Blackfin processor • Core performance up to 600 MHz • 208-ball CSP-BGA package • 5 Mb of internal RAM memory 24 MHz CLKIN oscillator 32 Mb flash memory • Numonyx M25P32 SDRAM memory • Micron MT48LC16M16A2P-6A − 16 Mb × 16 bits (256 Mb/32 MB) 1 × 120-pin small foot print connectors • Hirose FX8-120P-SV1(91), 120-pin header 4 × footprints for SMA connectors • 1 × pair of footprints for external differential clock • 1 × pair of footprints for external differential trigger Blackfin processor peripherals exposed • SPI • SPORT • TWI/I2C • GPIO • PPI • Asynchronous parallel • Timers For more information, go to http://www.analog.com/sdp. • • • • • Visit the SDP website at http://www.analog.com/sdp Email processor questions to • [email protected] (worldwide support) • [email protected] (Europe support) • [email protected] (China support) Phone questions to 1-800-ANALOGD Contact your Analog Devices local sales office or authorized distributor. Send questions by mail to Analog Devices, Inc. Three Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA PRODUCT INFORMATION Product information can be obtained from the Analog Devices website. Analog Devices Website The Analog Devices website, www.analog.com, provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. Note that MyAnalog.com is a free feature of the Analog Devices website that allows customization of a web page to display only the latest information about products of interest to you. You can choose to receive weekly email notifications containing updates to the web pages that meet your interests, including documentation errata against all documents. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. Visit MyAnalog.com to sign up. If you are a registered user, just log on. Your user name is your email address. REGULATORY COMPLIANCE The EVAL-SDP-CH1Z is designed to be used solely in a laboratory environment. The board is not intended for use as a consumer end product or as a portion of a consumer end product. The board is an open system design, which does not include a shielded enclosure and therefore may cause interference to other electrical devices in close proximity. This board should not be used in or near any medical equipment or RF devices. Store unused boards in the protective shipping package. Rev. 0 | Page 3 of 32 UG-502 SDP User Guide GETTING STARTED Verifying Driver Installation This section provides specific information to assist you with using the SDP-H1 board as part of your evaluation system. Before using the SDP-H1 board, verify the driver software has installed properly. The following topics are covered: • • • • Open the Windows Device Manager and verify the SDP board appears under ADI Development Tools as shown in Figure 1. Package contents PC configuration USB installation Powering up/powering down the SDP PACKAGE CONTENTS Your EVAL-SDP-CH1Z board package contains the following: • • • EVAL-SDP-CH1Z board 1 m USB Standard-A to Mini-B cable 12 V 30 W wall wart Contact the vendor where you purchased your SDP-H1 board or contact Analog Devices if anything is missing. PC CONFIGURATION For correct operation of the SDP board, your computer must have the following minimum configuration: • • Windows® XP Service Pack 2 -32 bit, Windows Vista 32-bit/64-bit, or Windows 7 32-bit/64-bit USB 2.0 port 11212-001 When removing the SDP-H1 board from the package, handle the board carefully to avoid the discharge of static electricity, which can damage some components. USB INSTALLATION Perform the following tasks to safely install the SDP-H1 board onto the computer. There are two stages in the software application installation procedure. The first stage installs the application software. The second stage installs the .NET Framework 3.5 and the necessary drivers. Figure 1. Device Manager POWERING UP/POWERING DOWN THE SDP The following sections describe how to safely power up and power down the SDP-H1. Installing the Software Powering Up the SDP-H1 Board 1. 1. 2. Run the application install provided. The first stage installs the applications GUI and the necessary support files onto the computer. Immediately following the application install, the .NET Framework 3.5 and the driver package for the SDP board is installed. If the .NET Framework 3.5 is already preinstalled on the computer in question, this stage is skipped and Step 2 will consist of a driver package installation only. Connecting the SDP-H1 Board to the PC Attach the SDP-H1 board to a USB 2.0 port on the computer via the Standard-A to Mini-B cable provided. The SDP-H1 must be powered using the enclosed wall-wart power supply. 2. 3. 4. Connect the daughter board to the SDP-H1 board through either the 120-pin mating connector or the FMC connector (whichever is applicable). Power the daughter board. (This may not be required for FMC daughter boards (mezzanine cards). See daughter board documentation for further details.) Power the SDP-H1 board with the enclosed power supply. Connect the USB port on the computer to the SDP-H1 board. Powering Down the SDP-H1 Board 1. 2. 3. 4. Rev. 0 | Page 4 of 32 Disconnect the SDP-H1 board power supply. Disconnect any daughter board power supplies. Disconnect the USB port on the computer from the SDP-H1 board. Disconnect the daughter board from the SDP-H1 board. SDP User Guide UG-502 HARDWARE DESCRIPTION LED0, LED1, and LED2 LEDs This section describes the hardware design of the EVAL-SDPCH1Z board. These red (LED0), orange (LED1), and green (LED2) LEDs are connected to the FPGA and can be used by the user for whatever purpose they see fit. The following topics are covered: LEDs—This section describes the SDP on-board LEDs. Connector Details—This section details the pin assignments on the FMC connector and the 120-pin connector. The SMA connectors are also covered. Power—This section lists power requirements of the SDP and identifies connector power inputs and output pins. Mechanical specifications—This section provides dimensional information. STATUS LED The orange status LED is an LED used as a diagnostic tool for evaluation application developers. When there are two or more identical SDP controller board and daughter board combinations connected to the PC simultaneously, the status LED flashes during the connect routine to help the user identify which board they will communicate with. LEDS SYS_POWER LED There are eight LEDs located on the SDP-H1 board (see Figure 2). This green LED indicates that the power supplies supplying power to the FPGA, DDR2, SRAM, and Blackfin are turned on. FMC_PWR_GD LED SDP CONNECTOR DETAILS This green LED indicates that the three power supplies supplying power to the FMC connector (12P0V, 3P3V, and VADJ) are turned on. The SDP-H1 board has a 120-pin SDP connector and a low pin count (LPC) female FMC connector. This section describes the SDP connector. The FMC-LPC connector is described in the FMC Connector Details section. BF_POWER LED This green LED indicates that the SDP-H1 Blackfin processor is powered. This is not an indication of USB connectivity between the SDP-H1 and the PC. POWER USB LED RESET BUTTON 120-PIN SDP CON A LED BF_POWER FMC_PWR_GD LED LED2 LED SPI SPORT I2C/TWI GPIO Asynchronous parallel PPI UART Timers In addition, included on the connector specification are input and output power pins, ground pins, and pins reserved for future use. For further details on the peripheral interfaces, including timing diagrams, see the ADSP-BF52x Blackfin Processor Hardware Reference. STATUS LED LED1 LED LED0 LED FPGA_DONE The peripherals exposed on the 120-pin SDP connector (a Hirose FX8-120P-SV1(91) 120-pin header connector) are: LED SYS_POWER FMC-LPC CON 11212-002 Connector Pin Assignments Figure 2. SDP-H1 Board LEDs FPGA_DONE LED This green LED indicates whether or not the FPGA has been configured. When it is turned off, the FPGA is unconfigured. When it is turned on, the FPGA is configured. During repeated FPGA configuring, the LED will momentarily turn off until the configuration process has completed. The connector pin assignments for the SDP connector has been defined independently of the any internal pin sharing that occurs on the Blackfin processor. This pin assignment is identical to that found on the SDP-B (EVAL-SDP-CB1Z) and the SDP-S (EVAL-SDP-CS1Z) boards. Table 1 lists the connector pins and identifies the functionality assigned to each connector pin. Rev. 0 | Page 5 of 32 UG-502 SDP User Guide Table 1. 120-Pin SDP Connector Pin Assignments Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin Name VIN NC GND GND USB_VBUS GND PAR_D23 PAR_D21 PAR_D19 PAR_D17 GND PAR_D14 PAR_D13 PAR_D11 PAR_D9 PAR_D7 GND PAR_D5 PAR_D3 PAR_D1 PAR_RD PAR_CS GND PAR_A3 PAR_A1 PAR_FS3 PAR_FS1 GND SPORT0_TDV SPORT1_TDV SPORT_DR1 SPORT_DT1 SPI_D2 SPI_D3 SPORT_INT GND SPI_SEL_B SPI_SEL_C SPI_SEL1/SPI_SS 40 41 42 43 44 45 46 47 48 49 50 51 GND SDA_1 SCL_1 GPIO0 GPIO2 GPIO4 GND GPIO6 TMR_A TMR_C NC NC Description Power to SDP Board. Requires 300 mA at 5 V. No Connect. Leave this pin unconnected. Do not ground. Connect to ground plane of board. Connect to ground plane of board. Connected directly to the USB +5 V supply. Connect to ground plane of board. Parallel Data Bus Bit 23. (No connect.) 1 Parallel Data Bus Bit 21. (No connect.)1 Parallel Data Bus Bit 19. (No connect.)1 Parallel Data Bus Bit 17. (No connect.)1 Connect to ground plane of board. Parallel Data Bus Bit 14. Parallel Data Bus Bit 13. Parallel Data Bus Bit 11. Parallel Data Bus Bit 9. Parallel Data Bus Bit 7. Connect to ground plane of board. Parallel Data Bus Bit 5. Parallel Data Bus Bit 3. Parallel Data Bus Bit 1. Asynchronous Parallel Read Strobe. Asynchronous Parallel Chip Select. Connect to ground plane of board. Parallel Address Bus Bit 3. Parallel Address Bus Bit 1. Synchronous (PPI) Parallel Frame Sync 3. Synchronous (PPI) Parallel Frame Sync 1. Connect to ground plane of board. SPORT 0 Transmit Data Valid. (No connect.)1 SPORT 1 Transmit Data Valid. (No connect.)1 SPORT Data Receive 1. Secondary SPORT data into processor. SPORT Data Transmit 1. Secondary SPORT data from processor. SPI 0 Data 2. (No connect.)1 SPI 0 Data 3. (No connect.)1 SPORT Interrupt. Used to trigger a non-periodic SPORT event. Connect to ground plane of board. SPI Chip Select B. Use this to control a second device on the SPI bus. SPI Chip Select C. Use this for a third device on the SPI bus. SPI Chip Select 1. Used to connect to SPI boot flash, if required. Also used as chip select when Blackfin processor is operating as SPI slave. Connect to ground plane of board. I2C Data 1. I2C Data 1. General-Purpose Input/Output. General-Purpose Input/Output. General-Purpose Input/Output. Connect to ground plane of board. General-Purpose Input/Output. Timer A Flag Pin. Use as first timer, if required. Timer C Flag Pin. (No connect.)1 No Connect. Leave this pin unconnected. Do not ground. No Connect. Leave this pin unconnected. Do not ground. Rev. 0 | Page 6 of 32 SDP User Guide Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin Name GND NC NC NC EEPROM_A0 RESET_OUT GND UART_RX RESET_IN BMODE1 UART_TX GND SLEEP WAKE NC NC NC GND NC CLK_OUT TMR_D TMR_B GPIO7 GND GPIO5 GPIO3 GPIO1 SCL_0 SDA_0 GND SPI_CLK SPI_MISO SPI_MOSI SPI_SEL_A GND SPORT_TSCLK SPORT_DT0 SPORT_TFS SPORT_RFS SPORT_DR0 SPORT_RSCLK GND PAR_CLK PAR_FS2 PAR_A0 PAR_A2 GND PAR_INT PAR_WR PAR_D0 PAR_D2 PAR_D4 GND UG-502 Description Connect to ground plane of board. No Connect. Leave this pin unconnected. Do not ground. No Connect. Leave this pin unconnected. Do not ground. No Connect. Leave this pin unconnected. Do not ground. EEPROM A0. Connect to A0 address line of the EEPROM. Active low reset signal from processor board. Connect to ground plane of board. UART Receive Data. Active low pin to reset controller board. Boot Mode 1. Pull up with 10 kΩ resistor to set SDP to boot from SPI Flash. Enabled on Connector A only. UART Transmit Data. Connect to ground plane of board. Active low sleep from processor board. External wake up to processor board. No Connect. Leave this pin unconnected. Do not ground. No Connect. Leave this pin unconnected. Do not ground. No Connect. Leave this pin unconnected. Do not ground. Connect to ground plane of board. No Connect. Leave this pin unconnected. Do not ground. CLK_OUT from processor. Timer D Flag Pin. Timer B Flag Pin. Use as second timer, if required. General-Purpose Input/Output. Connect to ground plane of board. General-Purpose Input/Output. General-Purpose Input/Output. General-Purpose Input/Output. I2C Clock 0. Daughter board EEPROM must be connected to this bus. I2C Data 0. Daughter board EEPROM must be connected to this bus. Connect to ground plane of board. SPI Clock. SPI Master In, Slave Out Data. SPI Master Out, Slave In Data. SPI Chip Select A. Use this to control the first device on the SPI bus. Connect to ground plane of board. SPORT Transmit Clock. SPORT Data Transmit 0. Primary SPORT data from processor. SPORT Transmit Frame Sync. SPORT Receive Frame Sync. SPORT Data Receive 0. Primary SPORT data into processor. SPORT Receive Clock. Connect to ground plane of board. Clock for Synchronous Parallel Interface (PPI). Synchronous (PPI) Parallel Frame Sync 2. Parallel Address Bus Bit 0. Parallel Address Bus Bit 2. Connect to ground plane of board. Parallel Interrupt. Used to trigger a nonperiodic parallel event. Asynchronous Parallel Write Strobe. Parallel Data Bus Bit 0. Parallel Data Bus Bit 2. Parallel Data Bus Bit 4. Connect to ground plane of board. Rev. 0 | Page 7 of 32 UG-502 Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 Pin Name PAR_D6 PAR_D8 PAR_D10 PAR_D12 GND PAR_D15 PAR_D16 PAR_D18 PAR_D20 PAR_D22 GND VIO(+3.3V) GND GND NC NC SDP User Guide Description Parallel Data Bus Bit 6. Parallel Data Bus Bit 8. Parallel Data Bus Bit 10. Parallel Data Bus Bit 12. Connect to ground plane of board. Parallel Data Bus Bit 15. Parallel Data Bus Bit 16. (No connect.)1 Parallel Data Bus Bit 18. (No connect.)1 Parallel Data Bus Bit 20. (No connect.)1 Parallel Data Bus Bit 22. (No connect.)1 Connect to ground plane of board. +3.3 V Output. 20 mA maximum current available to power IO voltage on daughter board. Connect to ground plane of board. Connect to ground plane of board. No Connect. Leave this pin unconnected. Do not ground. No Connect. Leave this pin unconnected. Do not ground. Functionality not implemented on the SDP board. Each interface provided by the SDP-H1 is available on unique pins of the SDP-H1 120-pin connector. The connector pin numbering scheme is outlined in Figure 3. Rev. 0 | Page 8 of 32 UG-502 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESET_IN BMODE1 UART_TX UART_RX GND GND SLEEP RESET_OUT SDP WAKE EEPROM_A0 STANDARD NC NC CONNECTOR NC NC NC NC GND GND NC NC CLK_OUT NC TMR_D TMR_C * TIMERS TMR_B TMR_A GPIO7 GPIO6 GND GND GENERAL GPIO5 GPIO4 INPUT/OUTPUT GPIO3 GPIO2 GPIO1 GPIO0 SCL_1 SCL_0 I2C SDA_1 SDA_0 GND GND SPI_SEL1/SPI_SS SPI_CLK SPI_MISO SPI_SEL_C SPI SPI_MOSI SPI_SEL_B SPI_SEL_A GND GND SPORT_INT SPORT_TSCLK SPI_D3 * SPORT_DT0 SPI_D2 * SPORT SPORT_TFS SPORT_DT1 SPORT_RFS SPORT_DR1 SPORT_DR0 SPORT1_TDV * SPORT_RSCLK SPORT0_TDV * GND GND PAR_CLK PAR_FS1 PAR_FS2 PAR_FS3 PAR_A0 PAR_A1 PAR_A2 PAR_A3 GND GND PAR_CS PAR_INT PAR_WR PAR_RD PAR_D0 PAR_D1 PARALLEL PAR_D2 PAR_D3 PORT PAR_D4 PAR_D5 GND GND PAR_D6 PAR_D7 PAR_D8 PAR_D9 PAR_D10 PAR_D11 PAR_D12 PAR_D13 GND PAR_D14 PAR_D15 GND * PAR_D16 PAR_D17 * * PAR_D18 PAR_D19 * * PAR_D20 PAR_D21 * * PAR_D22 PAR_D23 * GND GND VIO(+3.3V) USB_VBUS GND GND GND GND NC NC *NC ON BLACKFIN SDP VIN NC Figure 3. 120-Pin SDP Connector Outline Rev. 0 | Page 9 of 32 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 11212-003 SDP User Guide UG-502 SDP User Guide FMC CONNECTOR DETAILS This section describes the FMC-LPC connector pin assignments. For further information, see the VITA 57 specification. Table 2. FMC-LPC Connector Pin Assignments Pin No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 D5 D6 D7 D8 D9 Pin Name GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND PG_C2M GND GND No connect No connect GND GND LA01_P_CC LA01_N_CC Description Ground. No connect. No connect. Ground. Ground. No connect. No connect. Ground. Ground. User-defined signals connected to FPGA Bank 2. 1 User-defined signals connected to FPGA Bank 2.1 Ground. Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. Ground. I2C clock line for reading FMC EEPROM. I2C data line for reading FMC EEPROM. Ground. Ground. I2C geographical address 0. Must be connected to Address Pin A1 of FMC EEPROM. 12 V (1 A) power supply to daughter board. Ground. 12 V (1 A) power supply to daughter board. Ground. 3.3 V (3 A) power supply to daughter board. Ground. Active high signal indicating 12P0V, 3P3V, and VADJ power supplies are turned on. Ground. Ground. No connect. No connect. Ground. Ground. User-defined signals connected to FPGA Bank 2.1, 2 User-defined signals connected to FPGA Bank 2.1, 2 Rev. 0 | Page 10 of 32 SDP User Guide Pin No. D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 Pin Name GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N UG-502 Description Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1, 2 User-defined signals connected to FPGA Bank 2.1, 2 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. JTAG clock. JTAG data input. JTAG data output. 3.3 V (20 mA) power supply for powering only the FMC EEPROM. JTAG mode select. JTAG reset. I2C geographical Address 1. Must be connected to address pin A0 of FMC EEPROM. 3.3 V (3 A) power supply to daughter board. Ground. 3.3 V (3 A) power supply to daughter board. Ground. 3.3 V (3 A) power supply to daughter board. Ground. Positive line of differential pair for carrying clock signals from daughter board. Negative line of differential pair for carrying clock signals from daughter board. Ground. Ground. User-defined signals connected to FPGA Bank 2.1, 2 User-defined signals connected to FPGA Bank 2.1, 2 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Rev. 0 | Page 11 of 32 UG-502 Pin No. G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 SDP User Guide Pin Name GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND No connect PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N Description Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. Variable (1.2 V to 3.3 V) (2 A) power supply to daughter board. Ground. No connect. Indicates presence of daughter board. Must be tied to ground on daughter board. Ground. Positive line of differential pair for carrying clock signals from daughter board. Negative line of differential pair for carrying clock signals from daughter board. Ground. User defined signals connected to FPGA Bank 2.1 User defined signals connected to FPGA Bank 2.1 Ground. User defined signals connected to FPGA Bank 2.1 User defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. User-defined signals connected to FPGA bank 2.1 User-defined signals connected to FPGA Bank 2.1 Rev. 0 | Page 12 of 32 SDP User Guide Pin No. H36 H37 H38 H39 H40 1 2 Pin Name GND LA32_P LA32_N GND VADJ UG-502 Description Ground. User-defined signals connected to FPGA Bank 2.1 User-defined signals connected to FPGA Bank 2.1 Ground. Variable (1.2 V to 3.3 V) (2 A) power supply to daughter board. User-defined signals with P suffix can be used as the positive pin of the differential pair. User defined signals with N suffix can be used as the negative pin of the differential pair. For further information, see the VITA 57 specification. User-defined signals with CC suffix are the preferred signal lines on which to transmit clock signals from the controller board to the daughter board. They are connected to global clock lines on the FPGA but they can also be used to carry any other user-defined signal. For further information, see the VITA 57 specification. Rev. 0 | Page 13 of 32 UG-502 SDP User Guide Table 3. FMC Connector Outline 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 H No connect PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ G GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND Rev. 0 | Page 14 of 32 D PG_C2M GND GND No connect No connect GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V C GND No connect No connect GND GND No connect No connect GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND SDP User Guide UG-502 SMA CONNECTORS The SDP-H1 has the PCB footprints for four SMA connectors (Emerson 142-0701-801, Digi-Key J502-ND). J701 and J702 are, respectively, the positive and the negative of a differential pair for supplying an external clock source to the FPGA and they are connected to clock capable pins on the FPGA. J703 and J704 can be used to supply an external trigger to the FPGA but they are not connected to clock capable FPGA pins. J701, J702, J703, and J704 are connected to an FPGA bank supplied by a fixed 3.3 V supply. POWER The SDP-H1 must be powered using the enclosed 12 V 30 W wall-wart power supply. This 12 V supply is converted, using on-board dc-to-dc switching regulators, to power all on-board systems as well as supply power to any daughter board connected to the FMC connector. Table 4 outlines the voltage and currents available to daughter boards connected to the FMC connector (as required by the VITA 57 specification). Note that the maximum allowed power budget for the daughter board is 10 W (for further information, see the VITA 57 specification). The SDP-H1 board also provides 3.3 V at 20 mA on Pin 116 (VIO_+3.3V) to connected daughter boards as the VIO voltage for the daughter board. Pin 5 (USB_VBUS) is connected to an internal 5 V power supply, providing 5 V ±10% as an output of the SDP board. MECHANICAL SPECIFICATIONS The mechanical specifications of the SDP-H1 board are 4.33" × 4.17" (110 mm × 106 mm). The height of the 120-pin connectors from the bottom of the board is approximately 0.152" (3.86 mm). The height of the FMC-LPC connector from the top of the board is approximately 0.258” (6.55 mm). The tallest component on the top is the dc power input connector at approximately 0.433" (11 mm) and the tallest component on the bottom is the L9 inductor at approximately 0.157" (4 mm). (The rubber feet on the bottom of the board are 0.311” (7.9 mm) tall.) Refer to Figure 4. Table 4. FMC Connector Power Supply Capabilities Voltage Supply VADJ 3P3VAUX 3P3V 12P0V Voltage Range 1.2 V to 3.3 V 3.3 V 3.3 V 12 V Number Of Pins 2 1 4 2 Maximum Current 2A 20 mA 3A 1A Tolerance ±5% ±5% ±5% ±5% Rev. 0 | Page 15 of 32 UG-502 SDP User Guide 4.33” 110.0mm POWER INPUT USB LED 120-PIN SDP CON A RESET BUTTON BF_POWER LED FMC_PWR_GD LED STATUS LED LED1 LED LED0 LED 4.17” 106.0mm LED2 LED FPGA_DONE LED SYS_POWER FMC-LPC CON POWER INPUT 0.258”/6.55mm FMC-LPC CON 0.311”/7.9mm CON A RUBBER FOOT RUBBER FOOT FMC-LPC CON L9 11212-004 120-PIN SPD CON A 0.496”/ 0.433”/ 12.6mm 11mm Figure 4. SDP-H1 Board Mechanical Specifications Rev. 0 | Page 16 of 32 SDP User Guide UG-502 SCHEMATICS This section provides the schematic drawings for the EVAL-SDP-CH1Z board. The schematic pages include: • • • • • • • • • • • • • SDP-H1—Blackfin Power SDP-H1—Blackfin Memory SDP-H1—Blackfin Clocks_USB SDP-H1—Blackfin I/O SDP-H1—Blackfin Connector A SDP-H1—FPGA Bank 0-Blackfin SDP-H1—FPGA Bank 1-SRAM SDP-H1—FPGA Bank 2-FMC SDP-H1—FPGA Bank 3-SDRAM SDP-H1—FPGA Power SDP-H1—Power Supply Part 1 SDP-H1—Power Supply Part 2 SDP-H1—Power Supply Part 3 Rev. 0 | Page 17 of 32 UG-502 SDP User Guide 11212-005 Figure 5. SDP-H1—Blackfin Power Rev. 0 | Page 18 of 32 SDP User Guide UG-502 11212-006 Figure 6. SDP-H1—Blackfin Memory Rev. 0 | Page 19 of 32 UG-502 SDP User Guide 11212-007 Figure 7. SDP-H1—Blackfin Clocks_USB Rev. 0 | Page 20 of 32 SDP User Guide UG-502 11212-008 Figure 8. SDP-H1—Blackfin I/O Rev. 0 | Page 21 of 32 UG-502 SDP User Guide 11212-009 Figure 9. SDP-H1—Blackfin Connector A Rev. 0 | Page 22 of 32 SDP User Guide UG-502 11212-010 Figure 10. SDP-H1—FPGA Bank 0-Blackfin Rev. 0 | Page 23 of 32 UG-502 SDP User Guide 11212-011 Figure 11. SDP-H1—FPGA Bank 1-SRAM Rev. 0 | Page 24 of 32 SDP User Guide UG-502 11212-012 Figure 12. SDP-H1—FPGA Bank 2-FMC Rev. 0 | Page 25 of 32 UG-502 SDP User Guide 11212-013 Figure 13. SDP-H1—FPGA Bank 3-SDRAM Rev. 0 | Page 26 of 32 SDP User Guide UG-502 11212-014 Figure 14. SDP-H1—FPGA Power Rev. 0 | Page 27 of 32 UG-502 SDP User Guide 11212-015 Figure 15. SDP-H1—Power Supply Part 1 Rev. 0 | Page 28 of 32 SDP User Guide UG-502 11212-016 Figure 16. SDP-H1—Power Supply Part 2 Rev. 0 | Page 29 of 32 UG-502 SDP User Guide 11212-017 Figure 17. SDP-H1—Power Supply Part 3 Rev. 0 | Page 30 of 32 SDP User Guide UG-502 NOTES Rev. 0 | Page 31 of 32 UG-502 SDP User Guide NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11212-0-4/13(0) Rev. 0 | Page 32 of 32