ADSP-TS201S EZ-KIT Lite® Evaluation System Manual Revision 3.1, April 2007 Part Number 82-000770-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information ©2007 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices icon bar and logo, TigerSHARC, TigerSHARC logo, VisualDSP++, the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Regulatory Compliance The ADSP-TS201S EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark. The ADSP-TS201S EZ-KIT Lite evaluation system had been appended to Analog Devices Development Tools Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file. The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. CONTENTS PREFACE Purpose of This Manual ................................................................. xii Intended Audience ......................................................................... xii Manual Contents ........................................................................... xii What’s New in This Manual .......................................................... xiii Technical or Customer Support ...................................................... xiv Supported Processors ...................................................................... xiv Product Information ....................................................................... xv MyAnalog.com .......................................................................... xv Processor Product Information ................................................... xv Related Documents .................................................................. xvi Online Technical Documentation ............................................ xvii Accessing Documentation From VisualDSP++ .................... xviii Accessing Documentation From Windows .......................... xviii Accessing Documentation From Web ................................... xix Printed Manuals ....................................................................... xix VisualDSP++ Documentation Set ......................................... xix Hardware Tools Manuals ...................................................... xix Processor Manuals ................................................................. xx ADSP-TS201S EZ-KIT Lite Evaluation System Manual v CONTENTS Data Sheets .......................................................................... xx Notation Conventions ................................................................... xxi USING ADSP-TS201S EZ-KIT LITE Package Contents ......................................................................... 1-2 Default Configuration .................................................................. 1-3 Installation and Session Startup ..................................................... 1-5 Evaluation License Restrictions ..................................................... 1-7 Memory Map ............................................................................... 1-7 SDRAM Interface ......................................................................... 1-8 Flash Memory .............................................................................. 1-9 Programmable FLAG Pins .......................................................... 1-10 Interrupt Pins ............................................................................. 1-11 Audio Interface ........................................................................... 1-12 Processor Link Ports ................................................................... 1-12 Example Programs ...................................................................... 1-13 Flash Programmer Utility ............................................................ 1-14 ADSP-TS201S EZ-KIT LITE HARDWARE REFERENCE System Architecture ...................................................................... 2-2 External Port ........................................................................... 2-3 Expansion Interface ................................................................. 2-3 JTAG Emulation Port ............................................................. 2-4 Switch Settings ............................................................................. 2-5 Audio Amplification Selection (SW1) ...................................... 2-5 vi ADSP-TS201S EZ-KIT Lite Evaluation System Manual CONTENTS Processor Mode Selections (SW2) ............................................ 2-6 Processor Boot Strap Settings .............................................. 2-7 SYSCON/SDRCON Mode Settings .................................... 2-7 Interrupt Enable Settings .................................................... 2-8 Link Port Width Settings .................................................... 2-8 FLAGs and IRQs Switch Settings (SW10) ................................ 2-9 Configuration Resistors ............................................................... 2-10 Processor ID Settings ............................................................. 2-10 Clock Mode Settings ............................................................. 2-12 Control Impedance Selection ................................................. 2-14 Drive Strength Selection ........................................................ 2-15 LEDs and Push Buttons .............................................................. 2-16 Power LED (LED1) ............................................................... 2-16 Reset LED (LED8) ................................................................ 2-16 FLAG LEDs (LED3–6) ......................................................... 2-17 USB Monitor LED (ZLED3) ................................................. 2-18 Programmable FLAG Push Buttons (SW6–9) ......................... 2-18 Interrupt Push Buttons (SW4 and SW5) ................................ 2-19 Reset Push Button (SW3) ...................................................... 2-19 Connectors ................................................................................. 2-20 Audio (J9 and J10) ................................................................ 2-21 Power (J8) ............................................................................. 2-21 JTAG (ZP4) .......................................................................... 2-21 USB (ZJ1) ............................................................................. 2-22 ADSP-TS201S EZ-KIT Lite Evaluation System Manual vii CONTENTS Expansion Interface (J1–3) .................................................... 2-22 Link Ports (J4–7) .................................................................. 2-23 Power Supply Specifications ........................................................ 2-23 ADSP-TS201 EZ-KIT LITE BILL OF MATERIALS ADSP-TS201S EZ-KIT LITE SCHEMATIC Title Page ..................................................................................... B-1 Processor A ................................................................................... B-2 Processor B ................................................................................... B-3 Processor Link Ports ..................................................................... B-4 Processor Power ............................................................................ B-5 Configuration ............................................................................... B-6 Memory ....................................................................................... B-7 Audio In ....................................................................................... B-8 Audio Out .................................................................................... B-9 Reset/PB/LED ............................................................................ B-10 Expansion Interface .................................................................... B-11 JTAG/CPLD For Audio .............................................................. B-12 Power Page 1 .............................................................................. B-13 Power Page 2 .............................................................................. B-14 Processor Bypass Caps ................................................................. B-15 INDEX viii ADSP-TS201S EZ-KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP-TS201S EZ-KIT Lite®, Analog Devices (ADI) evaluation system for TigerSHARC® floating-point embedded processors. The TigerSHARC processor is a static super scalar (SSS) architecture targeted at software-defined radio applications. In these wireless infrastructure applications, the TigerSHARC processor is replacing field-programmable gate arrays (FPGAs) in the chip rate processing applications for third generation cellular. The performance, flexibility, multiprocessing and IO capabilities of the TigerSHARC processor makes it superior to FPGA implementations. The evaluation board is designed to be used in conjunction with the VisualDSP++® development environment to test the capabilities of the ADSP-TS201S TigerSHARC processor. The VisualDSP++ development environment gives you the ability to perform advanced application code development and debug, such as: • Create, compile, assemble, and link application programs written in C++, C, and ADSP-TS201S assembly • Load, run, step-in, step-out, step-over, halt, and set breakpoints in application program • Read and write data and program memory • Read and write core and peripheral registers • Plot memory ADSP-TS201S EZ-KIT Lite Evaluation System Manual ix Access to the ADSP-TS201S processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-TS201S processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.com/dsp/tools/. The ADSP-TS201S EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board. ADSP-TS201S EZ-KIT Lite installation is part of the VisuL The alDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. For details about evaluation license restrictions after the 90 days, refer to “Evaluation License Restrictions” on page 1-7. Refer to the VisualDSP++ Installation Quick Reference Card for details. The board features: • Two Analog Devices ADSP-TS201S processors D D 500 MHz core clock speed Configurable core clock mode • Analog Devices AD1871 96 kHz analog-to-digital converter D Line-in 3.5 mm stereo jack • Analog Devices AD1854 96 kHz digital-to-analog converter D Line-out 3.5 mm stereo jack • SDRAM memory D x 32 MB (4 MB x 64) ADSP-TS201S EZ-KIT Lite Evaluation System Manual Preface • Flash memory D 512K main flash memory • USB debugging interface • Interface connectors D D D 14-pin emulator connector for JTAG interface Low Voltage Differential Signaling (LVDS) link ports via RJ-45 connectors Expansion interface connectors • General-purpose IO D D D 4 push button flags (two for each processor) 2 push button interrupts (one for each processor) 4 LED FLAG outputs (two for each processor) • Analog Devices ADP3331, ADP3336, ADP1864, ADP1821, and ADP1823 voltage regulators The EZ-KIT Lite board contains two external memories: flash memory and SDRAM. The flash memory can be used to store user-specific boot code. By configuring the boot mode switch (SW2) and programming the flash memory, the board can run as a stand-alone unit. The SDRAM is shared by both processors and can be used to store data external to the processors. For more information, see “Memory Map” on page 1-7. The EZ-KIT Lite board contains an audio interface, facilitating creation of audio signal processing applications. Additionally, the EZ-KIT Lite board provides expansion connectors, allowing you to connect to the processor’s external port (EP). ADSP-TS201S EZ-KIT Lite Evaluation System Manual xi Purpose of This Manual Purpose of This Manual The ADSP-TS201S EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes the operation and configuration of the board components and provides guidelines for running your own code on the ADSP-TS201S EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs. The product software installation is detailed in the VisualDSP++ Installation Quick Reference Card. Intended Audience The primary audience of this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts (such as the ADSP-TS201 TigerSHARC Processor Hardware Reference and the ADSP-TS201 TigerSHARC Processor Programming Reference) that describe your target architecture. Programmers who are unfamiliar with VisualDSP++ should refer to the VisualDSP++ online Help and user’s or getting started guides. For the locations of these documents, see “Related Documents”. xii ADSP-TS201S EZ-KIT Lite Evaluation System Manual Preface Manual Contents The manual consists of: • Chapter 1, “Using ADSP-TS201S EZ-KIT Lite” on page 1-1 Provides information on the EZ-KIT Lite from a programmer’s perspective and outlines the board’s memory map. • Chapter 2, “ADSP-TS201S EZ-KIT Lite Hardware Reference” on page 2-1 Provides information on the hardware aspects of the EZ-KIT Lite. • Appendix A, “ADSP-TS201 EZ-KIT Lite Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board. • Appendix B, “ADSP-TS201S EZ-KIT Lite Schematic” on page B-1 Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design. B now is part of the online Help. The PDF version of L Appendix the ADSP-TS201S EZ-KIT Lite Evaluation System Manual is located in the Docs\EZ-KIT Lite Manuals folder on the installation CD. Alternatively, the schematic can be found on the Analog Devices Web site: www.analog.com/processors. What’s New in This Manual This edition of the ADSP-TS201S EZ-KIT Lite Evaluation System Manual documents ADSP-TS201S EZ-KIT Lite compliance with the RoHS and WEEE directives. ADSP-TS201S EZ-KIT Lite Evaluation System Manual xiii Technical or Customer Support Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technicalSupport • E-mail tools questions to [email protected] • E-mail processor questions to [email protected] (World wide support) [email protected] (Europe support) [email protected] (China support) • Phone questions to 1-800-ANALOGD • Contact your Analog Devices, Inc. local sales office or authorized distributor • Send questions by mail to: Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA Supported Processors The ADSP-TS201S EZ-KIT Lite evaluation system supports the Analog Devices ADSP-TS201S TigerSHARC embedded processors. xiv ADSP-TS201S EZ-KIT Lite Evaluation System Manual Preface Product Information You can obtain product information from the Analog Devices website, from the product CD-ROM, or from the printed publications (manuals). Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and embedded processors. MyAnalog.com MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. Registration: Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as means for you to select the information you want to receive. If you are already a registered user, just log on. Your user name is your e-mail address. Processor Product Information For information on embedded processors and DSPs, visit our Web site at www.analog.com/processors, which provides access to technical publications, data sheets, application notes, product overviews, and product announcements. ADSP-TS201S EZ-KIT Lite Evaluation System Manual xv Product Information You may also obtain additional information about Analog Devices and its products in any of the following ways. • E-mail questions or requests for information to [email protected] (World wide support) [email protected] (Europe support) [email protected] (China support) • Fax questions or requests for information to 1-781-461-3010 (North America) +49-89-76903-157 (Europe) Related Documents For information on product related development software, see the following publications. Table 1. Related Processor Publications Title Description ADSP-TS201S Embedded Processor Data Sheet General functional description, pinout, and timing ADSP-TS201 TigerSHARC Processor Hardware Reference Description of internal processor architecture and all register functions ADSP-TS201 TigerSHARC Processor Programming Reference Description of all allowed processor assembly instructions Table 2. Related VisualDSP++ Publications Title Description VisualDSP++ User’s Guide Description of VisualDSP++ features and usage VisualDSP++ Assembler and Preprocessor Manual Description of the assembler function and commands VisualDSP++ C/C++ Complier and Description of the complier function and comLibrary Manual for TigerSHARC Processors mands for TigerSHARC processors xvi ADSP-TS201S EZ-KIT Lite Evaluation System Manual Preface Table 2. Related VisualDSP++ Publications (Cont’d) Title Description VisualDSP++ Linker and Utilities Manual Description of the linker function and commands VisualDSP++ Loader and Utilities Manual Description of the loader/splitter function and commands All documentation is available online. Most documentation is available in printed form. you plan to use the EZ-KIT Lite board in conjunction with a L IfJTAG emulator, also refer to the documentation that accompanies the emulator. Visit the Technical Library Web site to access all processor and tools manuals and data sheets: http://www.analog.com/processors/technicalSupport/technicalLibrary/. Online Technical Documentation Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary .pdf files of most manuals are provided in the Docs folder on the VisualDSP++ installation CD. Each documentation file type is described as follows. If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD at any time by running the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site. ADSP-TS201S EZ-KIT Lite Evaluation System Manual xvii Product Information File Description .chm Help system files and manuals in Help format .htm or .html Dinkum Abridged C++ library and FlexLM network license manager software documentation. Viewing and printing the .html files requires a browser, such as Internet Explorer 5.01 (or higher). .pdf VisualDSP++ and processor manuals in Portable Documentation Format (PDF). Viewing and printing the .pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher). Accessing Documentation From VisualDSP++ To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP++ documentation via the Start menu. To view ADSP-TS201S EZ-KIT Lite Help, which is part of the VisualDSP++ Help system, use the Contents or Search tab of the Help window. Accessing Documentation From Windows In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documentation from Windows. Help system files (.chm) are located in the Help folder, and .pdf files are located in the Docs folder of your VisualDSP++ installation CD-ROM. The Docs folder also contains the Dinkum Abridged C++ library and the FlexLM network license manager software documentation. Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++ and the ADSP-TS201S EZ-KIT Lite evaluation system. xviii ADSP-TS201S EZ-KIT Lite Evaluation System Manual Preface Accessing Documentation From Web Download manuals at the following Web site: http://www.analog.com/processors/technicalSupport/technicalLibrary/. Select a processor family and book title. Download archive (.zip) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files. Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts. VisualDSP++ Documentation Set To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit. If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir/continent.asp. Hardware Tools Manuals To purchase EZ-KIT Lite and in-circuit emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual. ADSP-TS201S EZ-KIT Lite Evaluation System Manual xix Product Information Processor Manuals Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual. Data Sheets All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site. To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site. xx ADSP-TS201S EZ-KIT Lite Evaluation System Manual Preface Notation Conventions Text conventions used in this manual are identified and described as follows. Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu). {this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. .SECTION Commands, directives, keywords, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. L Note: For correct operation, ... A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. a Caution: Incorrect device operation may result if ... Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol. [ Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-TS201S EZ-KIT Lite Evaluation System Manual xxi Notation Conventions conventions, which apply only to specific chapters, may L Additional appear throughout this document. xxii ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1 USING ADSP-TS201S EZ-KIT LITE This chapter provides specific information to assist you with development of programs for the ADSP-TS201S EZ-KIT Lite evaluation system. The information appears in the following sections. • “Package Contents” on page 1-2 Lists the items contained in your ADSP-TS201S EZ-KIT Lite package. • “Default Configuration” on page 1-3 Shows the default configuration of the ADSP-TS201S EZ-KIT Lite. • “Installation and Session Startup” on page 1-5 Instructs how to start a new or open an existing ADSP-TS201SEZ-KIT Lite session using VisualDSP++. • “Evaluation License Restrictions” on page 1-7 Describes the restrictions of the VisualDSP++ demo license shipped with the EZ-KIT Lite. • “Memory Map” on page 1-7 Describes the ADSP-TS201S EZ-KIT Lite board’s memory map. • “SDRAM Interface” on page 1-8 Defines the register values needed to configure the external memory for SDRAM access. • “Flash Memory” on page 1-9 Describes how to program and use the flash memory. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-1 Package Contents • “Programmable FLAG Pins” on page 1-10 Describes the function and use of the programmable flag pins on the EZ-KIT Lite evaluation system. • “Interrupt Pins” on page 1-11 Describes the function and use of the interrupt pins on the EZ-KIT Lite evaluation system. • “Audio Interface” on page 1-12 Describes how to use and configure the audio interface. • “Processor Link Ports” on page 1-13 Describes how to use and configure the link ports. • “Example Programs” on page 1-13 Provides information about the example programs included in the ADSP-TS201S EZ-KIT Lite evaluation system. • “Flash Programmer Utility” on page 1-14 Provides information on the Flash Programmer utility included with VisualDSP++. For information on the graphical user interface, including the boot loading, target options, and other facilities of the EZ-KIT Lite system, refer to the online Help. For detailed information about programming the ADSP-TS201S TigerSHARC processor, see the documents referred to as “Related Documents”. Package Contents Your ADSP-TS201S EZ-KIT Lite package contains the following items. • ADSP-TS201S EZ-KIT Lite board • VisualDSP++ Installation Quick Reference Card 1-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual Using ADSP-TS201S EZ-KIT Lite • ADSP-TS201S EZ-KIT Lite Evaluation System Manual (this document) • CD containing: D D D D VisualDSP++ software ADSP-TS201 EZ-KIT Lite debug software USB driver files Example programs • Universal 7.5V DC power supply • USB 2.0 cable • Registration card (please fill out and return) If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc. Default Configuration The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. The ADSP-TS201S EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your computer case. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-3 Default Configuration When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which may damage some components. Figure 1-1 shows the default DIP switches, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before using the board. Figure 1-1. EZ-KIT Lite Hardware Setup 1-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual Using ADSP-TS201S EZ-KIT Lite Installation and Session Startup correct operation, install the software and hardware in the L For order presented in the VisualDSP++ Installation Quick Reference Card. 1. Verify that the yellow USB monitor LED (ZLED3, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 2. If you are running VisualDSP++ for the first time, navigate to the VisualDSP++ environment via the Start –> Programs menu. The main window appears. Note that VisualDSP++ does not connect to any session. Skip the rest of this step to step 3. If you have run VisualDSP++ previously, the last opened session appears on the screen. You can override the default behavior and force VisualDSP++ to start a new session by pressing and holding down the Ctrl key while starting VisualDSP++. Do not release the Ctrl key until the Session Wizard appears on the screen. Go to step 4. 3. To connect to a new EZ-KIT Lite session, start Session Wizard by selecting one of the following. • From the Session menu, New Session. • From the Session menu, Session List. Then click New Session from the Session List dialog box. • From the Session menu, Connect to Target. Then click New Session from the Session List dialog box. 4. The Select Processor page of the wizard appears on the screen. Ensure TigerSHARC is selected in Processor family. In Choose a target processor, select ADSP-TS201. Click Next. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-5 Installation and Session Startup 5. The Select Connection Type page of the wizard appears on the screen. Select EZ-KIT Lite and click Next. 6. The Select Platform page of the wizard appears on the screen. In the Select your platform list, select ADSP-TS201S EZ-KIT Lite via Debug Agent. In Session name, highlight or specify the session name. The session name can be a string of any length; although, the box displays approximately 32 characters. The session name can include space characters. If you do not specify a session name, VisualDSP++ creates a session name by combining the name of the selected platform with the selected processor. The only way to change a session name later is to delete the session and to open a new session. Click Next. 7. The Finish page of the wizard appears on the screen. The page displays your selections. If you are satisfied, click Finish. If not, click Back to make changes. disconnect from a session, click the disconnect button L Toor select Session –> Disconnect from Target. To delete a session, select Session –> Session List. Select the session name from the list and click Delete. Click OK. 1-6 ADSP-TS201S EZ-KIT Lite Evaluation System Manual Using ADSP-TS201S EZ-KIT Lite Evaluation License Restrictions The ADSP-TS201S EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires: • VisualDSP++ allows a connection to the ADSP-TS201S EZ-KIT Lite via the USB debug agent interface only. Connections to simulators and emulation products are no longer allowed. • The linker restricts a user program to 128K words of internal memory for code space with no restrictions for data space. Refer to the VisualDSP++ Installation Quick Reference Card for details. Memory Map The ADSP-TS201S processor has 24 Mbits of internal memory that can be used for program storage or data storage. The configuration of internal memory is detailed in the ADSP-TS201 TigerSHARC Processor Hardware Reference. The ADSP-TS201S EZ-KIT Lite board contains 512K x 8-bit of external flash memory. The memory is divided into eight uniform 64 Kb sections. This memory connects to the processor’s ~BMS and ~MSO pins. The flash memory can be accessed in boot memory space as well as the external memory bank zero space. The board also contains 4M x 64-bit of external SDRAM memory. The SDRAM memory connects to the processor’s SDRAM interface. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-7 SDRAM Interface Table 1-1. EZ-KIT Lite Evaluation Board Memory Map Internal Memory External Memory Start Address End Address Content 0x0000 0000 0x 0001 FFFF Internal memory 0 0x0004 0000 0x0005 FFFF Internal memory 2 0x0008 0000 0x0009 FFFF Internal memory 4 0x000C 0000 0x000D FFFF Internal memory 6 0x0010 0000 0x0011 FFFF Internal memory 8 0x0014 0000 0x0015 FFFF Internal memory 10 0x001E 0000 0x001E 03FF Internal registers 0x001F 0000 0x001F 03FF SOC registers 0x0C00 0000 0x0FFF FFFF Broadcast 0x1000 0000 0x13FF FFFF Processor ID 0 0x1400 0000 0x17FF FFFF Processor ID 1 0x3000 0000 0x37FF FFFF External memory space bank 0 (~MS0); ~MS0 includes flash memory which ends at 0x3007 FFFF. 0x3800 0000 0x39FF FFFF External memory space bank 1 0x4000 0000 0x43FF FFFF External memory space (MSSD0); MSSD0 includes SDRAM which ends at 0x407F FFFF. 0x8000 0000 0xFFFF FFFF Host SDRAM Interface The SDRAM on the EZ-KIT Lite evaluation board is 32 MB. To access SDRAM, the SYSCON and SDRCON registers must be configured properly. The SDRAM default values are: 1-8 • SYSCON = 0x00189067 • SDRCON = 0x00005983 ADSP-TS201S EZ-KIT Lite Evaluation System Manual Using ADSP-TS201S EZ-KIT Lite For the supplied memory, the follows: SDRCON register should be configured as • SDRAM enable, CAS latency of two cycles • Pipe depth of zero, page boundary of 256 words • Refresh rate of every 3700 cycles, precharge to RAS of two cycles • RAS to precharge of five cycles • Init sequence is MRS cycle follows refresh and registers define bus control configuration. [ The They can be written only once after reset and cannot be changed SYSCON SDRCON during system operation. emulation space, the and the registers can be L Inwritten to as many times as needed. The USB debug monitor operSYSCON SDRCON ates in emulation space and allows “always writable” mode for these registers. Flash Memory The AT49BV040 chip provides a total of 512K x 8-bits of external flash memory, arranged into eight uniform 64 Kb memory blocks. The block addresses are shown in Table 1-2. Table 1-2. Flash Memory Map Start Address End Address Content 0x3000 0000 0x3000 FFFF Uniform block 0 0x3001 0000 0x3001 FFFF Uniform block 1 0x3002 0000 0x3002 FFFF Uniform block 2 0x3003 0000 0x3003 FFFF Uniform block 3 ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-9 Programmable FLAG Pins Table 1-2. Flash Memory Map (Cont’d) Start Address End Address Content 0x3004 0000 0x3004 FFFF Uniform block 4 0x3005 0000 0x3005 FFFF Uniform block 5 0x3006 0000 0x3006 FFFF Uniform block 6 0x3007 0000 0x3007 FFFF Uniform block 7 To program the flash memory with your boot code, first create a loader file from your processor code. You set up the loader in VisualDSP++ depending on how you plan to boot the flash. For information on creating a loader file, refer to VisualDSP++ online help and the VisualDSP++ Loader and Utilities Manual. Next, the loader file must be programmed into the flash memory. This can be done using the VisualDSP++ Flash Programmer utility (see online Help). Programmable FLAG Pins Each ADSP-TS201S processor has four programmable flag pins. Two flag pins from each processor (FLAG0 and FLAG1) allow interaction with the running program through the use of a switch (SW6–9). The FLAG2 and FLAG3 pins from each processor are connected to LEDs (LED3–6). After the processor is reset, the programmable flags are configured as inputs. The direction of each programmable FLAG is configured in the FLAGREG register. If the flag is configured for output, the value of the flag pin is set in the FLAGREG register. If the flag is configured for input, the value on the flag pin is read from the SQSTAT register. Programmable flags are summarized in Table 1-3. For more information on how to configure the programmable flag pins, see the ADSP-TS201S TigerSHARC Processor Hardware Reference. 1-10 ADSP-TS201S EZ-KIT Lite Evaluation System Manual Using ADSP-TS201S EZ-KIT Lite Table 1-3. Programmable FLAG Pin Summary FLAG Connection Description FLAG0_A SW9 FLAG1_A SW8 The FLAG0 and FLAG1 pins connect to the push buttons to supply feedback for program execution. For instance, you can write user input to trigger a routine when the push button is pressed. FLAG0_B SW6 FLAG1_B SW7 FLAG2_A LED4 FLAG3_A LED6 FLAG2_B LED5 FLAG3_B LED3 The FLAG2 and FLAG3 pins connect to the LEDs to supply feedback during program execution. Interrupt Pins The ADSP-TS201S processor includes four interrupt pins (IRQ3–0) for interaction with the running program. One external interrupt from each processor is directly accessible through push buttons SW4 and SW5 on the EZ-KIT Lite board. Interrupts are summarized in Table 1-4. For more information on configuring the interrupt pins, see the ADSP-TS201S TigerSHARC Processor Hardware Reference. Table 1-4. Interrupt Pin Summary Interrupt Connection Description IRQ0_A SW4 IRQ0_B SW5 The IRQ0 interrupt connects to push buttons to supply feedback for program execution. For instance, you can write your code to perform a different function when an interrupt is detected. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-11 Audio Interface Audio Interface The audio interface of the EZ-KIT Lite board allows you to interface with the board’s analog-to-digital converter (ADC) and digital-to-analog converter (DAC). The audio interface consists of two main ICs: AD1871 and AD1854. The AD1871 is a stereo audio ADC intended for digital audio applications requiring high-performance analog-to-digital conversion. The AD1871 provides 97 dB THD+N and 107 dB dynamic range. The AD1854 is a high-performance, single-chip stereo, audio DAC delivering 113 dB dynamic range and 112 dB SNR at a 48 kHz sample rate. Because the ADSP-TS201S processor does not have any SPORTs, a Xilinx complex programmable logic device (CPLD) generates the audio interface control signals between the processor and the audio circuit. Setting the FLAG3 signal of processor A high enables the audio interface inside of the CPLD. Once the audio interface has been enabled, the audio data can be transferred to and from the processor by generating a DMAR0 cycle. The audio data interfaces with the processor via the lowest 24 bits of the data bus (D23–0). A CPLD IO connector (P6) has been added to allow a user to connect to the CPLD and the external port of the ADSP-TS201S (DSP A) processor. Refer to the schematic for information on how the connector is wired to the CPLD. Refer to the audio example program included in the EZ-KIT Lite’s installation directory for more information on how to use the audio interface. Refer to “Audio (J9 and J10)” on page 2-21 for information about the audio connectors. 1-12 ADSP-TS201S EZ-KIT Lite Evaluation System Manual Using ADSP-TS201S EZ-KIT Lite Processor Link Ports The link ports on the ADSP-TS201S processor uses Low Voltage Differential Signaling (LVDS) to communicate with each other. Each processor has a TX (transmit) port and RX (receive) port for each of its link ports. The RJ-45 connectors, J4–5, are the TX and RX ports for processor A. Similarly, J6–7 are TX and RX for processor B. The TX and RX of one processor’s link ports should be respectively connected to RX and TX of another processor’s link ports. In this manner, the TX of one processor connects to the RX of the other processor. Connect the link ports with a standard CAT 5E networking cable. The length of the cable may affect the maximum frequency at which the data can be transferred. Refer to the ADSP-TS201S embedded processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. There are four link ports on each of the processors on the EZ-KIT Lite. For each processor, the Link Port 0 transmit signals are connected to the receive of the same Link Port 0 signals. Link ports 2 and 3 connect the transmit of one processor to the receive of the other processor. Example Programs Example programs are provided with the ADSP-TS201S EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in the …\TS\Examples\ADSP-TS201 EZ-KIT Lite subdirectory of the VisualDSP++ installation directory. Please refer to the readme file provided with each example program for more information. running the examples, do not change the or [ When register. The change can disable commu(8 or 9) bits in the BGEN NMOD SQCTL nications with the host. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 1-13 Flash Programmer Utility Flash Programmer Utility The ADSP-TS201S EZ-KIT Lite evaluation system includes a Flash Programmer utility. The utility allows you to program the flash memory on the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++. Once the utility is installed, it is accessible from the Tools pull-down menu. For more information on the Flash Programmer utility, refer to the online Help. 1-14 ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2 ADSP-TS201S EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-TS201S EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 2-2 Describes the configuration of the ADSP-TS201S processor and explains how the board components interface with the EZ-KIT Lite. • “Switch Settings” on page 2-5 Shows the location and describes the function of each configuration DIP switch. • “Configuration Resistors” on page 2-10 Shows the location and describes the function of each configuration resistor. • “LEDs and Push Buttons” on page 2-16 Shows the location and describes the function of the LEDs and push buttons. • “Connectors” on page 2-20 Shows the location of and gives the part number for all of the connectors on the board. In addition, provides the manufacturer and part number information for the mating parts. • “Power Supply Specifications” on page 2-23 Describes the power connector. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-1 System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board. CPLD I/O Header Stereo Jack Stereo Jack AD1854 DAC AD1871 ADC CPLD JTAG Header JTAG Port External Bus Interface Unit Flash (512K x 8 bits) ADSP-TS201 Clock Mult (Default 5x) 100MHz SCLKin Link Port 0 PLL Link Port 1 LEDs FLAGs Link Port 2 PBs IRQs Link Port 3 20MHz Osc SDRAM 32MB (2chips x 4M x 32bits) EBIU JTAG Port External Bus Interface Unit PLL ADSP-TS201 3.3V 1.5V 2.5V 5V 1.05V Analog Devices Type A EZ-Kit Expansion Interface IRQs Link Port 0 +7.5V Connector FLAGs Link Port 1 Power Regulation 1.05V VDD_CORE 1.5V VDD_DRAM 2.5V VDD_IO Link Port 2 Link Port 3 Link Port Connectors 4 - RJ45 (2 per port) Figure 2-1. System Architecture This EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-TS201S TigerSHARC processor. The processor is powered by three separate regulators for the core, internal DRAM, and IO. The pro- 2-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference cessor core voltage is set to 1.05V. The internal DRAM is powered by an external 1.5V regulator. Finally, the external interface (IO) operates at 2.5V but can accept up to 3.3V levels. A 20 MHz SMT oscillator, in conjunction with a clock generator set to 5x, supply the input clock to the processors. The speed at which the core operates is determined by pull-up and pull-down resistors on both the clock generator (U1) and the SCLKRAT2–0 bit of each of the processors. For more information, see “Clock Mode Settings” on page 2-12. By default, the processor core runs at 500 MHz (20 MHz x 5 (U1) x 5 (SCLKRAT) =500 MHz). External Port The external port (EP) connects to a 512K x 8-bit flash memory. The flash memory connects to the boot memory select (~BMS) and memory bank 0 (~MS0) pins. The flash can be used to boot the processor as well as to store information during normal operation. Refer to “Flash Memory” on page 1-9 for more information. The EP also connects to a 4MB x 64-bit SDRAM. Refer to “SDRAM Interface” on page 1-8 for more information. Expansion Interface The expansion interface consists of three connectors. The following table shows the interfaces each connector provides. For the exact pinout of the connectors, refer to “Expansion Interface” on page B-11. Table 2-1. Expansion Interface Connectors Connector Interfaces J1 5V, GND, address, data ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-3 System Architecture Table 2-1. Expansion Interface Connectors (Cont’d) Connector Interfaces J2 2.5V, GND, SDRAM control signals, flags, IRQs, timers, data J3 GND, reset, DMA, memory control, CLKOUT, Link Ports signals When you use the expansion interface, limits to the current and to the interface speed must be taken into consideration. The maximum current limit depends on the regulator capabilities. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed. Devices does not support and is not responsible for the L Analog effects of additional circuitry. JTAG Emulation Port The JTAG emulation port allows an emulator to access the processor’s internal and external memory, as well as the special function registers through a 14-pin header. See “JTAG (ZP4)” on page 2-21 for more information about the JTAG connector. To learn more about available emulators, contact Analog Devices as described in “Product Information”. For more information about the JTAG interface and JTAG custom board design, refer to EE-68 found at the Analog Devices Web site. 2-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Switch Settings This section describes the function of the DIP switches SW1, SW2, and SW10. The locations and default settings of the switches are shown in Figure 2-2. Figure 2-2. Switch Locations Audio Amplification Selection (SW1) The SW1 switch determines the amplification of right and left signals connected to the LINE IN connector J9. A non-powered electret microphone can be used by simply varying the switch setting to the values shown in Table 2-2. An amplification gain of a factor of 10 can be achieved by setting the switch into electret microphone use. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-5 Switch Settings Table 2-2. Audio Amplification Selection (SW1) Position 1 Position 2 Position 3 Position 4 Audio Amplification Mode OFF OFF ON ON No amplification (default) ON ON OFF OFF For electret microphone use Processor Mode Selections (SW2) The SW2 switch configures several processor strap pins, which in turn, set the processor’s operating modes after power up or hard reset: • “Processor Boot Strap Settings” • “SYSCON/SDRCON Mode Settings” • “Interrupt Enable Settings” • “Link Port Width Settings” Do not change the switch settings while power is being applied to the board. Many of the strap pin settings can be re-configured in software after the processor is powered up. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. 2-6 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Processor Boot Strap Settings Position 1 of the SW2 switch determines how the processor boots. Table 2-3 shows the available boot mode settings. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. Table 2-3. Processor Boot Strap Settings (SW2 Position 1) SW2 Position 1 Boot Mode OFF EPROM boot (default) ON External boot or link port boot SYSCON/SDRCON Mode Settings Position 2 of the SW2 switch determines how the processor handles writes to the SYSCON and SDRCON registers. Table 2-4 shows the available settings for each write type. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. Table 2-4. SYSCON/SRDCON Mode Settings (SW2 Position 2) Position 2 SYSCON/SDRCON Mode OFF SYSCON/SDRCON one-time writable (default) ON SYSCON/SDRCON always writable space, the and registers can be written L toIn asemulation many times as needed. The USB debug monitor operates in SYSCON SDRCON emulation space and allows “always writable” mode for these registers. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-7 Switch Settings Interrupt Enable Settings Positions 3 and 5 of the SW2 switch determine how each of the processors handles interrupts. Table 2-5 and Table 2-6 show the available interrupt settings. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. Table 2-5. Interrupt Enable Settings (SW2 Position 3) SW2 Position 3 Interrupt Enable Mode for Processor A (U11) OFF Disable interrupts, level-sensitive mode (default) ON Enable interrupts, edge-sensitive mode Table 2-6. Interrupt Enable Settings (SW2 Position 5) SW2 Position 5 Interrupt Enable Mode for Processor B (U12) OFF Disable interrupts, level-sensitive mode (default) ON Enable interrupts, edge-sensitive mode Link Port Width Settings Positions 4 and 6 of the SW2 switch determine the link port data width. Table 2-7 and Table 2-8 show the available settings for the two types of link port data widths. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. Table 2-7. Link Port Width Settings (SW2 Position 4) 2-8 SW2 Position 4 Link Port Data Width for Processor A (U11) OFF 1-bit link port data width (default) ON 4-bit link port data width ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Table 2-8. Link Port Width Settings (SW2 Position 6) SW2 Position 6 Link Port Data Width for Processor B (U12) OFF 1-bit link port data width (default) ON 4-bit link port data width FLAGs and IRQs Switch Settings (SW10) The SW10 switch determines the source of the flag and IRQ signals connected to each of the prospective processors. The source can be modified to drive the nets by either a push button switch or an external source via the expansion header. Refer to “Programmable FLAG Push Buttons (SW6–9)” and “Interrupt Push Buttons (SW4 and SW5)” on page 2-19 for information on the flags, IRQs, and associated push buttons. Table 2-9 shows the available flag and interrupt source settings. Table 2-9. FLAGs and IRQs Switch Settings (SW10) DSP A DSP B Position 1 Position 2 (FLAG0) (FLAG1) Position 3 Position 4 Position 5 Position 6 (FLAG0) (FLAG1) (IRQ0) (IRQ0) OFF OFF OFF OFF OFF OFF External source ON1 ON ON ON ON ON On-board push button switch 1 DSP A DSP B Use With Default settings ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-9 Configuration Resistors Configuration Resistors This section describes the configuration resistors of the two TigerSHARC processors. The locations of the configuration resistors and their respective default settings are shown in Figure 2-3. Figure 2-3. Resistor Locations (Bottom View of the Board) Processor ID Settings The two ADSP-TS201S processors on the EZ-KIT Lite are factory-configured to set the processor A to an ID value of zero and processor B to an ID value of one. This means that in the cluster, processor A is the master. 2-10 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Although it is not recommended, the ID value of each processor can be varied by placing 500 Ohm resistors in the appropriate position. Table 2-10 and Table 2-11 show the available ID settings. EZ-KIT Lite must have a processor with the processor ID set L The to zero ( ) on the board. must be present in order to allow ini0 ID0 tialization of SDRAM external memory. Internal pull-up or pull-downs on certain pins, such as memory interface and bus arbitration, are enabled only when the ID=(000). Refer to the ADSP-TS201S TigerSHARC Processor Hardware Reference for more information. Table 2-10. Processor A ID Pins Configuration R115 (Net: ID2_A) R117 (Net: ID1_A) R120 (Net: ID0_A) ID[2:0] Value Not populated1 Not populated Not populated 0 Not populated Not populated Populated 1 Not populated Populated Not populated 2 Not populated Populated Populated 3 Populated Not populated Not populated 4 Populated Not populated Populated 5 Populated Populated Not populated 6 Populated Populated Populated 7 1 Default settings Table 2-11. Processor B ID Pins Configuration R122 (Net: ID2_B) R123 (Net: ID1_B) R124 (Net: ID0_B) ID[2:0] Value Not populated Not populated Not populated 0 Not populated1 Not populated Populated 1 Not populated Populated Not populated 2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-11 Configuration Resistors Table 2-11. Processor B ID Pins Configuration (Cont’d) R122 (Net: ID2_B) R123 (Net: ID1_B) R124 (Net: ID0_B) ID[2:0] Value Not populated Populated Populated 3 Populated Not populated Not populated 4 Populated Not populated Populated 5 Populated Populated Not populated 6 Populated Populated Populated 7 1 Default settings Clock Mode Settings The resistors on the clock generator (U1) and the resistors on the SCLKRAT2–0 pins of each of the processors determine the frequency at which the two processors operate. The frequency supplied to CLKIN of the processor also can be changed by replacing the 20 MHz oscillator (U18) shipped with the board with a different oscillator. Ensure that the selected clock mode and frequency do not exceed the minimum and maximum specifications of the ADSP-TS201S processor as noted in the product data sheet. The final frequency at which the processors operate is determined by the following equation: (Freq of U18)*(Mult Factor of U1)*(Mult Factor of SCLKRAT pins) = Final Oper Freq The default frequency factory setting is 20 2-12 MHz*5*5 = 500 MHz. ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Table 2-12 through Table 2-14 show the resistor settings for the clock generator and the SCLKRAT pins. For more information on the clock modes, see the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf. Table 2-12. Clock Generator (U1) Settings R215 R224 R3 R223 Multiplication Factor Not populated Populated Not populated Populated 2 Not populated Populated Populated Populated 3 Not populated Populated Populated Not populated 4 Populated Populated Not populated Populated 4.25 Populated1 Populated Populated Populated 5 Populated Populated Populated Not populated 6 Populated Not populated Not populated Populated 6.25 Populated Not populated Populated Populated 8 Populated Not populated Populated Not populated Reserved (test mode) 1 Default settings Table 2-13. SCLK Ratio Settings for Processor A R128 (SCLKRAT2) R127 (SCLKRAT1) R133 (SCLKRAT0) Multiplication Factor Not populated Not populated Not populated 4 Not populated1 Not populated Populated 5 Not populated Populated Not populated 6 Not populated Populated Populated 7 Populated Not populated Not populated 8 Populated Not populated Populated 10 ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-13 Configuration Resistors Table 2-13. SCLK Ratio Settings for Processor A R128 (SCLKRAT2) R127 (SCLKRAT1) R133 (SCLKRAT0) Multiplication Factor Populated Populated Not populated 12 Populated Populated Populated Reserved 1 Default settings Table 2-14. SCLK Ratio Settings for Processor B R126 (SCLKRAT2) R125 (SCLKRAT1) R45 (SCLKRAT0) Multiplication Factor Not populated Not populated Not populated 4 Not populated1 Not populated Populated 5 Not populated Populated Not populated 6 Not populated Populated Populated 7 Populated Not populated Not populated 8 Populated Not populated Populated 10 Populated Populated Not populated 12 Populated Populated Populated Reserved 1 Default settings processor A and processor B L The value. SCLK ratios must be of the same Control Impedance Selection The CONTROLIMP1 and CONTROLIMP0 resistors set the impedance and driver mode of the processors, as described in Table 2-15. The resistors are used together with the drive strength pins to determine the actual impedance and drive strength. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. 2-14 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Table 2-15. Control Impedance Selection R143 (CONTROLIMP1) R131 (CONTROLIMP0) Driver Mode Populated1 Not populated Normal Populated Populated Pulse mode Not populated Not populated A/D mode Not populated Populated Pulse mode, A/D mode 1 Default settings Drive Strength Selection The DS2–0 pins of each processor determine the digital drive strength as described in Table 2-16 and Table 2-17. Refer to the ADSP-TS201S processor data sheet at http://www.analog.com/UploadedFiles/Data_Sheets/ADSP_TS201S.pdf for more information. Table 2-16. Drive Strength Setting for Processor A R136 (DS2) R132 (DS1) R135 (DS0) Drive Strength Output Impedance Populated Not populated Populated 11.1% 26 Ohm Populated Not populated Not populated 23.8% 32 Ohm Populated Populated Populated 36.5% 40 Ohm Populated Populated Not populated 49.2% 50 Ohm Not populated Not populated Populated 61.9% 62 Ohm Not populated1 Not populated Not populated 74.6% 70 Ohm Not populated Populated Populated 87.3% 96 Ohm Not populated Populated Not populated 100% 120 Ohm 1 Default settings ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-15 LEDs and Push Buttons Table 2-17. Drive Strength Setting for Processor B R138 (DS2) R139 (DS1) R137 (DS0) Drive Strength Output Impedance Populated Not populated Populated 11.1% 26 Ohm Populated Not populated Not populated 23.8% 32 Ohm Populated Populated Populated 36.5% 40 Ohm Populated Populated Not populated 49.2% 52 Ohm Not populated Not populated Populated 61.9% 62 Ohm Not populated1 Not populated Not populated 74.6% 70 Ohm Not populated Populated Populated 87.3% 96 Ohm Not populated Populated Not populated 100% 120 Ohm 1 Default settings LEDs and Push Buttons This section describes the function of the LEDs and push buttons. Figure 2-4 shows the locations of the LEDs and push buttons. Power LED (LED1) The green LED, LED1, indicates that power is being supplied properly to the board. Reset LED (LED8) When LED8 is lit, it indicates that the master reset of all the major ICs is active. 2-16 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Figure 2-4. LED and Push Button Locations FLAG LEDs (LED3–6) The flag LEDs connect to the processor’s programmable FLAG pins (FLAG2 and FLAG3). The LEDs are active high and are lit by an output of “1” from the processor. Refer to “Programmable FLAG Pins” on page 1-10 for information on how to utilize the flags when programming the processor. Table 2-18 shows the FLAG signals and corresponding LEDs. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-17 LEDs and Push Buttons Table 2-18. FLAG LEDs FLAG Pin LED Reference Designator FLAG Pin LED Reference Designator FLAG2_A LED4 FLAG2_B LED5 FLAG3_A LED6 FLAG3_B LED3 USB Monitor LED (ZLED3) The USB monitor LED indicates that USB communication has been initialized successfully, allowing you to connect to the processor using VisualDSP++. If ZLED3 is not lit, try resetting the board and/or reinstalling the USB driver. VisualDSP++ is communicating with the EZ-KIT Lite tarL When get board, the LED can flicker, indicating communications handshake. Programmable FLAG Push Buttons (SW6–9) Four push buttons are provided for general-purpose user input. The SW6–9 push buttons connect to the processor’s programmable FLAG pins. The push buttons are active high and when pressed, send a high (1) to the processor. Refer to “Programmable FLAG Pins” on page 1-10 for more information on how to use the flags. Table 2-19 shows the FLAG signals and corresponding switches. Table 2-19. FLAG Push Buttons FLAG Pin Push Button Reference Designator FLAG0_A SW9 FLAG1_A SW8 FLAG0_B SW6 FLAG1_B SW7 2-18 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Interrupt Push Buttons (SW4 and SW5) Two push buttons, SW4 and SW5, are provided for user interrupts. The push buttons connect to the processor’s interrupt pins. The push buttons are active low and, when pressed, send a low (0) to the processor. Refer to “Interrupt Pins” on page 1-11 for more information on how to use the interrupts. Table 2-20 shows the interrupt signals and corresponding switches. Table 2-20. Interrupt Push Buttons Interrupt Pin Push Button Reference Designator IRQ0_A SW4 IRQ0_B SW5 Reset Push Button (SW3) The RESET push button, SW3, resets all ICs on the board, except the USB interface after it has been configured. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-19 Connectors Connectors This section describes the connector functionality and provides information about mating connectors. The connector locations are shown in Figure 2-5. Figure 2-5. Connector Locations 2-20 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Audio (J9 and J10) There are two 3.5 mm stereo audio jacks. Part Description Manufacturer Part Number 3.5 mm stereo jack A/D ELECTRONICS ST-323-5 Mating Connector 3.5 mm stereo plug to 3.5 mm stereo cable RADIO SHACK L12-2397A Power (J8) The power connector provides all the power necessary to operate the EZ-KIT Lite board. Part Description Manufacturer Part Number 2.5 mm power jack SWITCHCRAFT RAPC712X DIGI-KEY RAPC712X-ND Mating Power Supply (shipped with the EZ-KIT Lite) 7.5V power supply CUI DTS075400UDC-P6P-DB JTAG (ZP4) The JTAG header is the connecting point for a JTAG in-circuit emulator pod. For more information about a JTAG custom board design or interface, please refer to EE-68 found at Analog Devices Web site. 3 is missing to provide keying. Pin 3 in the mating connector L Pin should have a plug. When an emulator is connected to the JTAG header, the USB debug interface is disabled. using an emulator with the EZ-KIT Lite board, follow the [ When connection instructions provided with the emulator. ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-21 Connectors USB (ZJ1) The USB connector is a standard type B USB receptacle. Part Description Manufacturer Part Number Type B USB receptacle MILL-MAX 897-43-004-90-000000 DIGI-KEY ED90064-ND Mating Connector USB cable (provided with the kit) ASSMAN AK672/2-3 RANDOM USB-AB-1004A Expansion Interface (J1–3) Three board-to-board connectors provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information about the expansion interface, see “Expansion Interface” on page 2-3. Part Description Manufacturer Part Number 90-position 0.05” spacing SAMTEC SFC-145-T2-F-D-A Mating Connectors 90-position 0.05” spacing (through hole) SAMTEC TFM-145-x1 series 90-position 0.05” spacing (surface mount) SAMTEC TFM-145-x2 series 90-position 0.05” spacing (low cost) SAMTEC TFC-145 series 2-22 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201S EZ-KIT Lite Hardware Reference Link Ports (J4–7) There are four RJ-45 connectors on the EZ-KIT Lite. Two connectors are used for link port 3 of processor A, and two connectors are used for link port 3 of processor B. Part Description Manufacturer Part Number 8-pin RJ-45 connector TYCO 1-16609214-1 Mating Cables BLK CAT 5E cable (1 foot) E-FILLIATE 119-5136 Gray CAT 5E cable (1 meter) DIGI-KEY AE1233-ND Power Supply Specifications The power connector supplies DC power to the EZ-KIT Lite board. Table 2-21 shows the power connector pinout. Table 2-21. Power Connector Terminal Connection Center pin +7.5 VDC@4 amps Outer ring GND ADSP-TS201S EZ-KIT Lite Evaluation System Manual 2-23 Power Supply Specifications 2-24 ADSP-TS201S EZ-KIT Lite Evaluation System Manual A ADSP-TS201 EZ-KIT LITE BILL OF MATERIALS The bill of materials corresponds to “ADSP-TS201S EZ-KIT Lite Schematic” on page B-1. Please check the latest schematic on the Analog Devices Web site: http://www.analog.com/processors/tigersharc/technicalLibrary/manuals/index.html#Evaluation%20Kit%20Manuals. Ref. Qty. Description Reference Designator Manufacturer Part Number 1 2 74LVC14A SOIC14 U14,U30 TI 74LVC14AD 2 1 IDT74FCT3244APY SSOP20 U13 IDT IDT74FCT3244APYG 3 2 SN74AHC1G00 SOT23-5 U31,U38 TI SN74AHC1G00DBVR 4 1 12.288MHZ OSC003 U2 DIGI-KEY SG-8002CA-PCC-ND (12.288M) 5 1 MMBT3904 SOT23 Q1 MOUSER 512-MMBT3904 6 2 MT48LC4M32B2 TSOP86 U24-25 DIGI-KEY 557-1196-1-ND 7 1 IDT5V928PGI TSSOP24 U1 IDT IDT5V928PGGI 8 1 TS201S AT49BV040 "U10" U10 ATMEL AT49BV040B-70JU 9 4 LMV722M SOIC8 U6-8,U26 NATIONAL SEMI LMV722MNOPB 10 1 TS201S XC2C384 “U4” U4 XILINX XC2C384-10TQG144C ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-1 Ref. Qty. Description Reference Designator Manufacturer Part Number 11 1 FDC658P SOT23-6 U15 FAIRCHILD FDC658P 12 2 FDS9926A SOIC8 U16-17 MOUSER 512-FDS9926A 13 2 IRF7832 SOIC8 U20-21 INTERNAT. RECT IRF7832PBF 14 1 IRF7821 SOIC8 U19 INTERNAT. RECT. IRF7821PBF 15 1 20MHz OSC003 U18 DIGI-KEY SG-8002CA-PCC-ND (20.000M) 16 1 ADM708SARZ SOIC8 U5 ANALOG DEVICES ADM708SARZ 17 1 ADP3331ARTZ SOT23-6 VR4 ANALOG DEVICES ADP3331ARTZ-REEL7 18 1 AD1854JRSZ SSOP28 U3 ANALOG DEVICES AD1854JRSZ 19 1 AD1871YRSZ SSOP28 U9 ANALOG DEVICES AD1871YRSZ 20 1 ADP3336ARMZ MSOP8 VR6 ANALOG DEVICES ADP3336ARMZ-REEL 21 2 ADSP-TS201SA BP576 U11-12 ANALOG DEVICES AD91032Z 22 1 ADP1864 SOT23-6 VR1 ANALOG DEVICES ADP1864AUJZ-R7 23 1 ADP1823 LFCSP32 VR3 ANALOG DEVICES ADP1823ACPZ-R7 24 1 ADP1821 QSOP16 VR2 ANALOG DEVICES ADP1821ARQZ-R7 25 5 RUBBER FOOT M1-5 MOUSER 517-SJ-5018BK 26 1 PWR 2.5MM_JACK CON005 J8 SWITCHCRAFT RAPC712X A-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 27 7 MOMENTARY SWT013 SW3-9 PANASONIC EVQ-PAD04M 28 3 .05 45X2 CON019 J1-3 SAMTEC SFC-145-T2-F-D-A 29 2 DIP6 SWT017 SW2,SW10 CTS 218-6LPST 30 4 RJ45 8PIN CON_RJ45 J4-7 TYCO 1-16609214-1 31 1 DIP4 SWT018 SW1 ITT TDA04HOSB1 32 1 IDC 6X1 IDC6X1 P5 FCI 90726-406HLF 33 1 IDC 7X2 IDC7X2 ZP4 FCI 68737-414HLF 34 2 3.5MM STEREO_JACK CON001 J9-10 A/D ELECTRONICS ST-323-5 35 1 IDC 13x2 IDC13x2 P6 BERG 54102-T08-13LF 36 1 5A RESETABLE FUS005 F1 MOUSER 650-RGEF500 37 15 0 1/4W 5% 1206 R76,R91,R104, KOA R107,R109-110, R113,R118, R161-164, R178-179,R202 0.0ECTRk7372BTTED 38 4 YELLOW LED001 LED3-6 PANASONIC LN1461C 39 1 22PF 50V 5% 0805 C63 AVX 08055A220JAT 40 2 330PF 50V 5% 0805 C25,C30 AVX 08055A331JAT 41 4 0.01UF 100V 10% 0805 C1-2,C7-8 AVX 08051C103KAT2A 42 10 0.1UF 50V 10% 0805 C4,C142-143, C145-149, C153,C249 AVX 08055C104KAT ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-3 Ref. Qty. Description Reference Designator Manufacturer Part Number 43 4 1000PF 50V 5% 0805 C10-11,C13-14 AVX 08055A102JAT2A 44 27 10K 1/10W 5% 0805 R3,R26,R39-42, VISHAY R77,R86-87, R89,R94,R100, R102,R108, R112,R116, R153,R158-160, R203,R215, R223-224, R235-236,R238 CRCW080510K0JNEA 45 3 4.7K 1/10W 5% 0805 R5,R93,R188 VISHAY CRCW08054K70JNEA 46 2 2.0K 1/8W 1% 1206 R156-157 VISHAY CRCW12062K00FKEA 47 2 49.9K 1/8W 1% 1206 R60,R63 VISHAY CRCW120649K9FKEA 48 10 100PF 100V 5% 1206 C3,C6,C9,C12, C15,C20-21, C23,C27,C31 AVX 12061A101JAT2A 49 1 2.2UF 35V 10% B CT15 AVX TAJB225K035R 50 3 10UF 16V 10% B CT1-3 AVX TAJB106K016R 51 6 100 1/10W 5% 0805 R78,R85,R95, R99,R101,R103 VISHAY CRCW0805100RJNEA 52 2 220PF 50V 10% 1206 C28,C32 AVX 12061A221JAT2A 53 5 600 100MHZ 500MA 1206 FER1-3,FER6-7 STEWARD HZ1206B601R-10 54 4 237.0 1/8W 1% 1206 R46,R48,R50, R52 VISHAY CRCW1206237RFKEA 55 2 750.0K 1/8W 1% 1206 R47,R49 VISHAY CRCW1206750KFKEA A-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 56 8 5.76K 1/8W 1% 1206 R44,R53-57, R150,R152 VISHAY CRCW12065K76FKEA 57 2 11.0K 1/8W 1% 1206 R61-62 VISHAY CRCW120611K0FKEA 58 4 120PF 50V 5% 1206 C16-19 AVX 12065A121JAT2A 60 3 1UF 16V 10% 0805 C54,C71-72 PANASONIC ECJ2FB1E105K 61 1 47PF 100V 10% 1206 C96 KOA NPO1206HTTD470J 62 1 340.0K 1/8W 1% 0805 R192 VISHAY CRCW0805-3403FRT1E3 63 1 698.0K 1/8W 1% 0805 R201 VISHAY CRCW0805698KFKEA 64 2 680PF 50V 1% 0805 C26,C29 AVX 08055A681FAT2A 65 2 2.74K 1/8W 1% 1206 R68,R73 VISHAY CRCW12062K74FKEA 66 4 5.49K 1/8W 1% 1206 R64-65,R69-70 VISHAY CRCW12065K49FKEA 67 2 3.32K 1/8W 1% 1206 R66,R71 VISHAY CRCW12063K32FKEA 68 2 1.65K 1/8W 1% 1206 R67,R72 VISHAY CRCW12061K65FKEA 69 2 10UF 16V 20% CAP002 CT4-5 PANASONIC EEE1CA100SR 70 2 68UF 25V 20% CAP003 CT6-7 PANASONIC EEE-FC1E680P 71 1 332.0K 1/10W 1% 0805 R234 VISHAY CRCW0805332KFKEA ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-5 Ref. Qty. Description Reference Designator Manufacturer Part Number 72 9 0 1/10W 5% 0805 R1,R7,R9-10, R130,R155, R166,R208-209 VISHAY CRCW08050000Z0EA 73 1 190 100MHZ 5A FER002 FER5 MURATA DLW5BSN191SQ2 74 2 10UH 10% 1008 L1-2 PANASONIC ELJ-FC100KF 75 12 22 1/10W 5% 0805 R4,R6,R11,R24, VISHAY R32,R34-35, R129,R205-207, R219 CRCW080522R0JNEA 76 1 0.47UF 16V 10% 0805 C73 AVX 0805YC474KAT2A 77 7 10UF 6.3V 10% 0805 C33,C57-58, C90-92,C99 AVX 080560106KAT2A 78 6 1000PF 10V 20% 0805 C38-40,C42-43, C45 DIGI-KEY 311-1136-1-ND 79 2 4.7UF 6.3V 10% 0805 C70,C74 AVX 08056D475KAT2A 80 37 0.1UF 10V 10% 0402 C66,C69,C75, AVX C108,C111115,C118,C120, C141,C144, C165-166, C182,C184185,C187, C197-201, C221-225, C228-231, C237-239,C241 0402ZD104KAT2A A-6 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer 81 43 0.01UF 16V 10% 0402 C49-50,C68, AVX C77-85,C103104,C107,C109, C129-140, C167,C181, C183,C202205,C216, C218-220, C227,C232, C240,C242 0402YC103KAT2A 82 3 10K 1/16W 5% 0402 R184,R189, R197 VISHAY CRCW040210K0FKED 83 6 0 1/16W 5% 0402 R170-173, R199-200 PANASONIC ERJ-2GE0R00X 84 1 1.2K 1/16W 5% 0402 R196 PANASONIC ERJ-2GEJ122X 85 2 4.7K 31MW 5% RNET8 RN3-4 CTS 746X101472JP 86 14 499.0 1/10W 1% 0805 R23,R25,R45, R111,R124, R124,R133, R140-146, R154 VISHAY CRCW0805499RFKEA 87 2 100UF 10V 10% C CT20-21 AVX TPSC107K010R0075 88 44 1000PF 50V 5% 0402 C67,C168-180, C186,C188196,C206-215, C217,C226, C233-236, C243-246 AVX 04025C102JAT2A 89 1 64.9K 1/10W 1% 0805 R191 VISHAY CRCW080564K9FKEA 90 2 57.6K 1/4W 1% 1206 R147-148 VISHAY CRCW120657K6FKEA ADSP-TS201S EZ-KIT Lite Evaluation System Manual Part Number A-7 Ref. Qty. Description Reference Designator Manufacturer Part Number 91 1 210.0K 1/4W 1% 0805 R190 VISHAY CRCW0805210KFKEA 92 14 1UF 16V 10% 0603 C37,C41,C44, C46,C60-62, C86,C93-95, C101,C105-106 PANASONIC ECJ-1VB1C105K 93 1 68PF 50V 5% 0603 C53 AVX 06035A680JAT2A 94 1 470PF 50V 5% 0603 C52 AVX 06033A471JAT2A 95 2 100K 1/10W 5% 0603 R169,R183 VISHAY CRCW0603100KJNEA 96 1 0 1/10W 5% 0603 R105 PHYCOMP 232270296001L 97 1 10 1/10W 5% 0603 R198 VISHAY CRCW060310R0JNEA 98 2 4700PF 16V 10% 0603 C88,C97 DIGI-KEY 311-1083-2-ND 99 1 10.0K 1/10W 1% 0603 R211 DIGI-KEY 311-10.0KHRTR-ND 100 1 680PF 50V 5% 0603 C65 PANASONIC ECJ-1VC1H681J 101 1 2200PF 50V 5% 0603 C98 PANASONIC ECJ-1VB1H222K 102 4 470UF 2V 20% E CT16,CT19, CT22-23 PANASONIC EEF-SE0D471R 103 2 15.0K 1/16W 1% 0603 R193,R195 DIGI-KEY 311-15.0KHRTR-ND 104 1 24.9K 1/10W 1% 0603 R92 DIGI-KEY 311-24.9KHTR-ND 105 1 47UF 6.3V 10% B CT14 NIC COMPONENTS NTC-T476K6.3TRBF A-8 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 106 9 2.0K 1/16W 1% 0603 R37-38,R88, R121,R212, R214,R216-218 PANASONIC ERJ-3EKF2001V 107 1 0.05 1/2W 1% 1206 R165 SUSUMA RL16326-R050-F-N 108 3 10UF 16V 10% 1210 C36,C55,C110 AVX 1210YD106KAT2A 109 1 GREEN LED001 LED1 PANASONIC LN1361CTR 110 1 RED LED001 LED8 PANASONIC LN1261CTR 111 2 1000PF 50V 5% 1206 C47-48 AVX 12065A102JAT2A 112 2 2200PF 50V 5% 1206 C22,C24 AVX 12065A222JAT050 113 1 0.1UF 50V 20% 1206 C5 AVX 12065E104MAT2A 114 2 100K 1/8W 5% 1206 R58-59 VISHAY CRCW1206100KFKEA 115 6 270 1/8W 5% 1206 R79-82,R90, R151 VISHAY CRCW1206270RJNEA 116 2 604.0 1/8W 1% 1206 R74-75 PANASONIC ERJ-8ENF6040V 117 6 1UF 20V 20% A CT8-13 AVX TAJA105K020R 118 1 255.0K 1/10W 1% 0603 R168 VISHAY CRCW06032553FK 119 1 80.6K 1/10W 1% 0603 R167 DIGI-KEY 311-80.6KHRCT-ND 120 1 6.8UH 25% IND009 L3 DIGI-KEY 308-1328-1-ND 121 1 4A SSB43L DO-214AA D7 VISHAY SSB43L ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-9 Ref. Qty. Description Reference Designator Manufacturer Part Number 122 1 250MA BZX84C5V6 SOT23D D8 MOUSER 512-BZX84C5V6 123 1 200MA BAT54A SOT23D D6 MOUSER 512-BAT54A 124 3 200MA BAT54 SOT23D D3-5 MOUSER 512-BAT54 125 1 8.2UH 20% IND012 L5 COILCRAFT MSS6132-822ML 126 1 10UH 20% IND012 L4 COILCRAFT MSS6132-103ML 127 1 0.7UH 20% IND010 L6 COILCRAFT MLC1265-701ML 128 2 1.1K 1/16W 1% 0402 R174-175 PANASONIC ERJ-2RKF1101X 129 1 18K 1/16W 5% 0402 R176 DIGIKEY 311-18KJRCT-ND 130 1 12.1K 1/16W 1% 0402 R177 DIGIKEY 311-12.1KLRCT-ND 131 1 38.3K 1/10W 1% 0603 R181 DIGIKEY 311-38.3KHRCT-ND 132 1 820 1/16W 5% 0402 R182 DIGIKEY 311-820JRCT-ND 133 1 430 1/16W 1% 0402 R194 DIGIKEY 311-430LRCT-ND 134 1 2.2PF 50V 10% 0402 C100 DIGIKEY 490-1267-1-ND 135 1 1200PF 50V 10% 0402 C89 DIGIKEY 490-1304-1-ND 136 2 330UF 10V 20% D CT17-18 SANYO 10TPB330M 137 1 82PF 50V 5% 0402 C87 DIGIKEY 490-1290-1-ND A-10 ADSP-TS201S EZ-KIT Lite Evaluation System Manual ADSP-TS201 EZ-KIT Lite Bill Of Materials Ref. Qty. Description Reference Designator Manufacturer Part Number 138 3 22000PF 25V 10% 0402 C59,C76,C102 DIGIKEY 490-3252-1-ND 139 1 1500PF 50V 10% 0402 C64 DIGIKEY 490-3245-1-ND 140 1 1UH 20% IND011 L7 DIGIKEY 495-1985-1-ND 141 2 5A MBRS540T3G SMC D1-2 ON SEMI MBRS540T3G 142 1 8.20K 1/10W 1% 0603 R210 DIGIKEY 541-8.20KHCT-ND 143 1 10.0K 1/16W 1% 0402 R185 DIGIKEY P10.0KLCT-ND 144 1 1.50K 1/16W 1% 0402 R204 DIGIKEY P1.50KLCT-ND ADSP-TS201S EZ-KIT Lite Evaluation System Manual A-11 A-12 ADSP-TS201S EZ-KIT Lite Evaluation System Manual A B C D 1 1 2 2 ADSP-TS201S EZ-KIT Lite 3 3 ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE TITLE Title Size 20 Cotton Road Rev A0178-2002 2.1C Sheet 4-9-2007_15:02 D 1 of 15 A B C DSP A U11 A[0:31] 1 A0 H24 A1 H23 A2 H22 A3 H21 A4 G24 A5 G23 A6 G22 A7 G21 A8 F24 A9 F23 A10 E24 A11 E23 ADDR2 DATA2 ADDR5 ADDR6 ADDR7 F22 F21 ADDR12 DATA12 ADDR13 ADDR16 DATA16 D23 A18 B24 ADDR17 ADDR18 ADDR20 DATA20 A22 A21 A23 B21 ADDR22 ADDR23 DATA21 DATA22 DATA23 A28 A20 DATA25 D19 ADDR25 A27 DATA24 C19 ADDR24 A26 ADDR26 DATA26 ADDR27 DATA27 ADDR28 A29 B20 A30 A19 A31 DATA18 DATA19 ADDR21 D20 DATA17 ADDR19 A23 A25 DATA14 DATA15 A17 C20 DATA13 ADDR15 D24 A24 DATA10 DATA11 E21 A21 DATA7 ADDR11 A15 C21 DATA6 DATA9 ADDR14 A20 DATA5 ADDR9 E22 D22 DATA4 DATA8 A14 A19 DATA3 ADDR8 ADDR10 A13 DATA0 DATA1 ADDR3 ADDR29 ADDR30 B19 ADDR31 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 AA15 NC1 DATA34 NC2 DATA35 NC3 DATA36 AB4 R21 R2 NC4 R3 NC5 DATA37 DATA38 DATA39 DATA40 DATA41 Y1 EMU TCK 3 TCK W3 TDI TDI W4 TDO_A TDO AC4 TMS PLACE CLOSE TO DSP PINS EMU Y2 AD4 TMS TRST TRST DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 DATA48 SCLK_DSP_A DATA49 DATA50 R7 0 0805 DATA51 DATA52 P1 SCLK1 DATA53 DATA54 DATA55 C34 10PF 0805 DNP DATA56 DATA57 DATA58 T1 DSP_RESET RST_IN DATA59 DATA60 U2 RST_OUT R1 0 0805 4 DATA61 DATA62 V3 POR_IN LABEL "DSP A" near this DSP D[0:63] ADDR1 ADDR4 A12 A16 2 ADDR0 D DATA63 D17 D0 A17 D1 B17 D2 C16 D3 D16 D4 A16 D5 B16 D6 C15 D7 D15 D8 A15 D9 B15 D10 A14 D11 KEEP THESE NETS THE SAME LENGTH 1 PLACE CLOSE TO IDT5v929 PINS R4 22 0805 SCLK_DSP_A U11 3.3V B14 D12 C14 D13 D14 D14 WRL A13 D15 WRH D16 ACK C12 D17 BRST D12 D18 B13 C18 RD RD A18 WRL AC7 CPA CPA SCLK_DSP_B AD7 DPA DPA D19 B12 D20 MS1 D21 MSH D11 D22 BMS A11 D23 C11 AA7 ACK DMAR0 BRST DMAR1 D18 B11 D24 A10 D25 B10 D26 C10 D27 D10 D28 A9 D29 B9 D30 C9 D32 A8 D33 DMAR0 AB7 DMAR1_A D35 D8 D36 A7 D37 B7 D38 C7 D39 IOWR BMS IORD IORD AA6 IOEN IOEN L3 L4 CAS B6 D42 A5 D43 BR3 M1 BR3 BR4 T3 BR5 M3 BR6 M4 BR7 R4 BR4 BR6 BR7 D45 D6 D46 SDA10 C5 D47 SDCKE D5 D48 SDWE A4 D49 B4 D50 D55 D2 D56 E3 D57 E4 D58 F3 D59 F4 D60 E1 D61 E2 D62 F1 D63 14 Q4 SDRAM_CLK1 15 R34 22 0805 18 Q6 19 Q7 CLKOUT_EXP R35 22 0805 GND1 R26 10K 0805 ID1_A ID2_A R11 22 0805 U18 H4 SCLKRAT0 M2 SCLKRAT1 T2 SCLKRAT2 TP1 8 ID0_A 1 OE SCLKRAT0_A SCLKRAT1_A 3 20MHZ OSC003 SCLKRAT2_A 24 S0 23 S1 2 TP6 9 GND2 16 GND3 17 GND4 1 REF OUT 21 GND5 IDT5V928PGI TSSOP24 BOFF AD8 BUSLOCK W1 CONTROLIMP0 V4 CONTROLIMP1 CONTROLIMP0 CONTROLIMP1 AA8 HBR AB8 HBG MSSD[0:3] T4 DS0 U4 DS1 V2 DS2 DS0_A DS1_A PLACE CLOSE TO EACH OTHER DS2_A J1 RAS J2 W2 ENEDREG K3 Y3 TMR0E CAS LDQM ENEDREG_A TMR0E_A K4 3 HDQM K1 SDA10 K2 SDCKE L1 SDWE MSSD0 U1 MSSD1 G1 MSSD2 V1 MSSD3 H3 MSSD0 MSSD1 MSSD2 MSSD3 AC1 FLAG0 AA2 FLAG1 AA1 FLAG2 Y4 FLAG3 FLAG0_A FLAG1_A 3.3V FLAG3_A IRQ0_A AB6 IRQ1_A AB5 IRQ2_A AA3 IRQ3_A IRQ1 IRQ2 IRQ3 3.3V FLAG2_A AA5 IRQ0 FLAG[3:0]_A IRQ[3:0]_A C108 0.1UF 0402 C107 0.01UF 0402 C103 0.01UF 0402 C104 0.01UF 0402 C141 0.1UF 0402 ADSP-TS201SA BP576 IDT5V928PGI ANALOG DEVICES ADSP-TS201SA BP576 Size Board No. C Date B C 20MHz 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE DSP A Title A R32 22 0805 11 Q3 BM D51 D1 10 Q2 P4 HDQM C6 D54 R223 10K 0805 2 X1_I 3 X2_O SDRAM_CLK0 7 Q1 22 OE N1 ID0 AD2 ID1 U3 ID2 BR5 AC8 LDQM D44 D3 R224 10K 0805 BR1 BR2 6 Q0 Q5 3.3V BR0 BR2 HBG D41 D53 IOWR AD5 L2 BR1 HBR D40 B1 AC5 4 VDD 5 VDDQ1 12 VDDQ2 13 VDDQ3 20 VDDQ4 PLACE TEST POINTS NEXT TO EACH OTHER A6 D52 DMAR3_A MSH G4 BUSLOCK D7 C4 DMAR3 R3 10K 0805 MS1 BOFF RAS A2 R215 10K 0805 DMAR2_A AD6 F2 H2 BM_A D34 C8 B5 MS0 D31 D9 B8 G3 BR0 BR[0:7] R24 22 0805 WRH AC6 A12 U1 B18 C17 DMAR2 MS0 R6 22 0805 Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 2 of 15 A B C D DSP B U12 A[0:31] 1 A0 H24 A1 H23 A2 H22 A3 H21 A4 G24 A5 G23 A6 G22 A7 G21 A8 F24 A9 F23 A10 E24 A11 E23 A12 F22 A13 F21 A14 E22 A15 A16 2 ADDR0 DATA0 ADDR1 DATA1 ADDR2 DATA2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR12 DATA12 ADDR13 D23 B24 A19 D22 A20 C21 A21 A23 A22 A21 A23 B21 ADDR16 A18 A27 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 ADDR26 DATA26 ADDR27 DATA27 C19 ADDR25 D19 A28 A20 A29 B20 A30 A19 A31 DATA10 DATA11 A17 A26 DATA7 ADDR11 D24 D20 DATA6 DATA9 ADDR15 C20 DATA5 ADDR9 E21 A25 DATA4 DATA8 ADDR14 A24 DATA3 ADDR8 ADDR10 ADDR28 ADDR29 ADDR30 B19 ADDR31 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 AA15 NC1 DATA34 NC2 DATA35 NC3 DATA36 AB4 R21 R2 NC4 R3 NC5 DATA37 DATA38 DATA39 DATA40 DATA41 Y1 EMU 3 TCK TCK W3 TDI_B TDI W4 TDO_B TDO AC4 TMS PLACE CLOSE TO DSP PINS EMU Y2 DATA42 DATA43 DATA44 DATA45 TMS DATA46 TRST DATA47 AD4 TRST DATA48 SCLK_DSP_B DATA49 DATA50 R9 0 0805 DATA51 DATA52 P1 SCLK1 DATA53 DATA54 C35 10PF 0805 DNP DATA55 DATA56 DATA57 DATA58 T1 DSP_RESET RST_IN DATA59 DATA60 U2 RST_OUT R10 0 0805 DATA61 DATA62 V3 POR_IN LABEL "DSP B" near this DSP D[0:63] DATA63 D17 D0 A17 D1 B17 D2 C16 D3 D16 D4 A16 D5 B16 D6 C15 D7 D15 D8 A15 D9 B15 D10 A14 D11 B14 D12 C14 D13 RD D14 D14 WRL 1 2.5V R5 4.7K 0805 BR0 R93 4.7K 0805 HBR U12 D15 WRH D16 ACK C12 D17 BRST D12 D18 A12 D19 MS0 B12 D20 MS1 C11 D21 MSH D11 D22 BMS A11 D23 A13 B13 C18 RD A18 WRL AC7 CPA AD7 DPA DPA B18 WRH C17 ACK D18 BRST RN4 AA7 DMAR0 DMAR0 BR3 AB7 DMAR1 DMAR1_B BR2 DMAR2 G3 MS0 F2 MS1 H2 MSH G4 BMS DMAR2_B BR1 AD6 DMAR3 DMAR3_B SDCKE DMAR2_A AC5 IOWR IOWR DMAR3_A AD5 IORD IORD BOFF AA6 D24 A10 D25 IOEN BR0 BR[0:7] BR1 BR2 B10 D26 BR3 C10 D27 BR4 D10 D28 A9 D29 B9 D30 BR5 BR6 BR7 C9 D9 D31 L2 BR0 L3 BR1 L4 BR2 M1 BR3 T3 BR4 M3 BR5 M4 BR6 R4 BR7 BM_B B8 D34 BOFF C8 D35 BUSLOCK D8 D36 A7 D37 HBR B7 D38 HBG P4 BM AC8 BOFF AD8 BUSLOCK AA8 HBR AB8 HBG IOEN DMAR1_B ID0 ID1 D7 D40 RAS A6 D41 CAS B6 D42 A5 D43 LDQM B5 D44 HDQM C6 D45 ID2 ID2_B D6 D46 C5 D47 SDCKE D48 A4 D49 B4 D50 A2 D51 C4 D52 K3 LDQM K4 HDQM K1 SDA10 K2 SDCKE L1 SDWE SDWE MSSD[0:3] MSSD0 U1 MSSD1 G1 MSSD2 MSSD3 B1 D53 D3 D54 D1 D55 D2 D56 E3 D57 E4 D58 F3 D59 F4 D60 E1 D61 E2 D62 F1 D63 MSSD0 MSSD1 V1 MSSD2 H3 MSSD3 DMAR0 DMAR1_A H4 SCLKRAT0 M2 SCLKRAT1 T2 SCLKRAT0_B DMAR3_B SCLKRAT1_B DMAR2_B SCLKRAT2_B BR5 BR6 W1 CONTROLIMP0 V4 CONTROLIMP1 T4 DS0 U4 ENEDREG TMR0E CONTROLIMP0 BR7 CONTROLIMP1 BR4 1 R1 2 R2 3 R3 4 R4 6 R5 7 R6 8 R7 9 R8 5 COM1 10 COM2 DS1_B DS2_B W2 ENEDREG_B Y3 TMR0E_B 3 FLAG1 FLAG2 FLAG3 IRQ0 IRQ1 IRQ2 IRQ3 AC1 FLAG0_B AA2 FLAG1_B AA1 FLAG2_B Y4 FLAG3_B AA5 IRQ0_B AB6 IRQ1_B AB5 IRQ2_B AA3 IRQ3_B FLAG[3:0]_B IRQ[3:0]_B ADSP-TS201SA BP576 ANALOG DEVICES 4 ADSP-TS201SA BP576 Size Board No. C Date B C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE DSP B Title A 2 4.7K RNET8 DS0_B DS1 FLAG0 SDA10 D5 J1 RAS J2 CAS 10 COM2 RN3 ID1_B U3 DS2 D39 5 COM1 ID0_B AD2 V2 C7 1 R1 2 R2 3 R3 4 R4 6 R5 7 R6 8 R7 9 R8 4.7K RNET8 N1 SCLKRAT2 D32 D33 A8 2.5V CPA AC6 B11 2.5V Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 3 of 15 A B C Link Port 0 Link Port 1 Link Port 2 Link Port 3 ALL NETS ON THIS PAGE EXCEPT L?ACK?_? and L?BCMP?_? ARE DIFFERETIAL PAIRS THESE SIGNAL SHOULD BE ROUTING ACCORDING THE GUIDELINES SET IN EE-179 DSP A DSP A DSP B DSP B RJ45 D DSP B DSP B DSP A DSP A RJ45 2_5V_DSP_A 2_5V_DSP_B DSP A 1 DSP B U11 PLACE CLOSE TO DSP A PINS (CRITICAL) R27 100.0 0805 DNP J24 L0DATI0_P_A L0DATI0_P J23 L0DATI0_N_A L0DATI0_N K22 L0DATI1_P_A L0DATI0_P_A L0DATI0_N_A L0DATI1_P K21 L0DATI1_N_A L0DATI1_N L24 L0DATI2_P_A R12 100.0 0805 DNP L0DATI2_P L23 L0DATI2_N_A L0DATI2_N L22 L0DATI3_P_A L0CLKIN_P_A L0DATI3_P L0CLKIN_N_A L21 L0DATI3_N_A L0DATI3_N K24 L0CLKIN_P_A L0CLKIN_P K23 L0CLKIN_N_A L0CLKIN_N J21 L0ACKO_A L0ACKO J22 L0BCMPI_A L0BCMPI T22 L1DATI0_P_A R13 100.0 0805 DNP 2 L1DATI0_P T21 L1DATI0_N_A L1DATI0_N U24 L1DATI1_P_A L1DATI0_P_A L1DATI0_N_A L1DATI1_P U23 L1DATI1_N_A L1DATI1_N V24 L1DATI2_P_A L1DATI2_P V23 L1DATI2_N_A L1DATI2_N V22 L1DATI3_P_A L1DATI3_P V21 L1DATI3_N_A R14 100.0 0805 DNP L1DATI3_N U22 L1CLKIN_P_A L1CLKIN_P U21 L1CLKIN_N_A L1CLKIN_P_A L1CLKIN_N_A L1CLKIN_N T23 L1ACKO_A L1ACKO T24 L1BCMPI_A R15 100.0 0805 DNP AD21 L2DATI0_P_A L2DATI0_P_A L2DATI0_N_A R16 100.0 0805 DNP AC21 L2DATI0_N_A AB20 L2DATI1_P_A AA20 L2DATI1_N_A L2DATI1_P_A L2DATI1_N_A R17 100.0 0805 DNP AD20 L2DATI2_P_A AC20 L2DATI2_N_A AD19 L2DATI3_P_A L2DATI2_P_A L2DATI2_N_A R18 100.0 0805 DNP AC19 L2DATI3_N_A AB19 L2CLKIN_P_A AA19 L2CLKIN_N_A L2DATI3_P_A 3 L1BCMPI L2DATI3_N_A R19 100.0 0805 DNP AB21 L2ACKO_A AD23 L2BCMPI_A L2CLKIN_P_A L2CLKIN_N_A AD14 L3DATI0_P_A AC14 L3DATI0_N_A AB14 AA14 AB13 AA13 R20 100.0 0805 DNP AD12 AC12 L3DATI0_P_A L3DATI0_N_A AD13 L3CLKIN_P_A R21 100.0 0805 DNP AC13 L3CLKIN_N_A AC15 L3ACKO_A L3CLKIN_P_A L3CLKIN_N_A AD15 L3BCMPI_A 2_5V_DSP_A 4 R108 10K 0805 R116 10K 0805 R119 10K 0805 DNP L2DATI0_P L2DATI0_N L2DATI1_P L2DATI1_N L2DATI2_P L2DATI2_N L2DATI3_P L2DATI3_N L2CLKIN_P L2CLKIN_N L2ACKO L2BCMPI L3DATI0_P L3DATI0_N L3DATI1_P L3DATI1_N L3DATI2_P L3DATI2_N L3DATI3_P L3DATI3_N L3CLKIN_P L3CLKIN_N L3ACKO L3BCMPI U12 P24 L0DATO0_P P23 L0DATO0_N P22 L0DATO1_P P21 L0DATO1_N N22 L0DATO2_P N21 L0DATO2_N M24 L0DATO3_P M23 L0DATO3_N N24 L0CLKO_P N23 L0CLKO_N R24 L0ACKI R23 L0BCMPO PLACE CLOSE TO DSP B PINS (CRITICAL) L0DATI0_P_A L0DATI0_N_A L0DATI1_N_A L0DATI1_P_B L0DATI1_N_B L0DATI0_P_B L0DATI0_N_B L0DATI2_P_A L0DATI2_P_B R28 100.0 0805 DNP L0DATI2_N_A L0DATI3_P_A L0DATI3_N_A AA24 L1DATO0_P AA23 L1DATO0_N Y22 L1DATO1_P Y21 L1DATO1_N Y24 L1DATO2_P Y23 L1DATO2_N W24 L1DATO3_P W23 L1DATO3_N W22 L1CLKO_P W21 L1CLKO_N AC24 L1ACKI AA22 L1BCMPO AB16 L2DATO0_P AA16 L2DATO0_N AD17 L2DATO1_P AC17 L2DATO1_N AD18 L2DATO2_P AC18 L2DATO2_N AB18 L2DATO3_P AA18 L2DATO3_N AB17 L2CLKO_P AA17 L2CLKO_N AD16 L2ACKI AC16 L2BCMPO AD9 L3DATO0_P AC9 L3DATO0_N AB10 L3DATO1_P AA10 L3DATO1_N AD11 L3DATO2_P AC11 L3DATO2_N AB11 L3DATO3_P AA11 L3DATO3_N AD10 L3CLKO_P AC10 L3CLKO_N AB9 L3ACKI AA9 L3BCMPO L0DATI2_N_B L0DATI3_P_B L0CLKIN_P_B L0CLKIN_N_B L0DATI3_N_B L0CLKIN_P_A L0CLKIN_P_B L0CLKIN_N_A L0CLKIN_N_B L0ACKO_A L0ACKO_B L0BCMPI_A L0BCMPI_B L1DATO0_P_A L1DATO0_P_A L1DATO0_N_A L1DATO0_N_A R29 100.0 0805 DNP L1DATO1_P_A L1DATO1_N_A L1DATO1_P_A L1DATO1_N_A L1DATO0_P_A L1DATO0_N_A L1DATO2_P_A L1DATO2_P_A L1DATO2_N_A L1DATO2_N_A L1DATO3_P_A L1DATO3_P_A L1DATO3_N_A L1DATO3_N_A R30 100.0 0805 DNP L1CLKOUT_P_A L1CLKOUT_N_A L1ACKI_A L1CLKOUT_P_A L1CLKOUT_N_A L1CLKOUT_P_A L1CLKOUT_N_A L1BCMPO_A L1ACKI_A L1BCMPO_A R36 100.0 0805 DNP L2DATO0_P_A L2DATO0_N_A L2DATO0_P_A L2DATO0_P_A L2DATO0_N_A R43 100.0 0805 DNP L2DATO1_P_A L2DATO1_N_A L2DATO2_P_A L2DATO1_P_A L2DATO1_N_A R83 100.0 0805 DNP L2DATO2_N_A L2DATO3_P_A L2DATO3_N_A L2DATO3_P_A L2DATO2_N_A R96 100.0 0805 DNP L2CLKOUT_N_A L2ACKI_A L2CLKOUT_N_A L2DATO3_N_A R98 100.0 0805 DNP L3DATO0_P_A L2DATO3_N_A L2CLKOUT_P_A L2DATO3_P_A L2BCMPO_A L2DATO2_P_A L2DATO2_N_A L2DATO2_P_A L2CLKOUT_P_A L2DATO0_N_A L2DATO1_N_A L2DATO1_P_A L2ACKI_A L2BCMPO_A L2CLKOUT_P_A L2CLKOUT_N_A L3DATO0_N_A L3DATI0_P_B L3DATI0_N_B R31 100.0 0805 DNP L3DATI0_P_B L3DATI0_N_B R33 100.0 0805 DNP L3CLKOUT_P_A L3CLKIN_P_B L3CLKIN_P_B L3CLKIN_N_B L3CLKOUT_N_A L3CLKIN_N_B L3ACKI_A L3ACKO_B L3BCMPO_A L3BCMPI_B ADSP-TS201SA BP576 2_5V_DSP_B R235 10K 0805 R153 10K 0805 R236 10K 0805 R237 10K 0805 DNP L0DATI0_N K22 L0DATI1_P K21 L0DATI1_N L24 L0DATI2_P L23 L0DATI2_N L22 L0DATI3_P L21 L0DATI3_N K24 L0CLKIN_P K23 L0CLKIN_N J21 L0ACKO J22 L0BCMPI P24 L0DATO0_P P23 L0DATO0_N P22 L0DATO1_P P21 L0DATO1_N N22 L0DATO2_P N21 L0DATO2_N M24 L0DATO3_P M23 L0DATO3_N N24 L0CLKO_P N23 L0CLKO_N R24 L0ACKI R23 L0BCMPO T22 L1DATI0_P T21 L1DATI0_N U24 L1DATI1_P U23 L1DATI1_N V24 L1DATI2_P V23 L1DATI2_N V22 L1DATI3_P V21 L1DATI3_N U22 L1CLKIN_P U21 L1CLKIN_N T23 L1ACKO T24 L1BCMPI AA24 L1DATO0_P AA23 L1DATO0_N Y22 L1DATO1_P Y21 L1DATO1_N Y24 L1DATO2_P Y23 L1DATO2_N W24 L1DATO3_P W23 L1DATO3_N W22 L1CLKO_P W21 L1CLKO_N AC24 L1ACKI AA22 L1BCMPO AD21 L2DATI0_P AC21 L2DATI0_N AB20 L2DATI1_P AA20 L2DATI1_N AD20 L2DATI2_P AC20 L2DATI2_N AD19 L2DATI3_P AC19 L2DATI3_N AB19 L2CLKIN_P AA19 L2CLKIN_N AB21 L2ACKO AD23 L2BCMPI AB16 L2DATO0_P AA16 L2DATO0_N AD17 L2DATO1_P AC17 L2DATO1_N AD18 L2DATO2_P AC18 L2DATO2_N AB18 L2DATO3_P AA18 L2DATO3_N AB17 L2CLKO_P AA17 L2CLKO_N AD16 L2ACKI AC16 L2BCMPO AD14 L3DATI0_P AC14 L3DATI0_N AB14 L3DATI1_P AA14 L3DATI1_N AB13 L3DATI2_P AA13 L3DATI2_N AD12 L3DATI3_P AC12 L3DATI3_N AD13 L3CLKIN_P AC13 L3CLKIN_N AC15 L3ACKO AD15 L3BCMPI AD9 L3DATO0_P AC9 L3DATO0_N AB10 L3DATO1_P AA10 L3DATO1_N AD11 L3DATO2_P AC11 L3DATO2_N AB11 L3DATO3_P AA11 L3DATO3_N AD10 L3CLKO_P AC10 L3CLKO_N AB9 L3ACKI AA9 L3BCMPO L0DATI0_P J23 L0DATI0_N_B R22 100.0 0805 DNP L0DATI1_P_A J24 L0DATI0_P_B ANALOG DEVICES R238 10K 0805 L0DATI0_N_B L0DATI1_P_B L0DATI1_N_B L0DATI2_P_B L0DATI2_N_B L0DATI3_P_B L0DATI3_N_B L0CLKIN_P_B L0CLKIN_N_B L0ACKO_B L0BCMPI_B L1DATI0_P_A L1DATI0_N_A L1DATI1_P_A 2 L1DATI1_N_A L1DATI2_P_A L1DATI2_N_A L1DATI3_P_A L1DATI3_N_A L1CLKIN_P_A L1CLKIN_N_A L1ACKO_A L1BCMPI_A L2DATI0_P_A L2DATI0_N_A L2DATI1_P_A L2DATI1_N_A L2DATI2_P_A L2DATI2_N_A L2DATI3_P_A L2DATI3_N_A L2CLKIN_P_A L2CLKIN_N_A L2ACKO_A 3 L2BCMPI_A L3DATO0_P_B L3DATO0_N_B L3CLKOUT_P_B L3CLKOUT_N_B L3ACKI_B L3BCMPO_B L0BCMPI_A L1BCMPO_A L1BCMPI_A L2BCMPO_A Size L2BCMPI_A L3BCMPI_B Board No. C L3BCMPI_A Date C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE DSP LINK PORTS Title B L0DATI0_P_B ADSP-TS201SA BP576 L0BCMPI_B A 1 Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 4 of 15 A 3.3V B 3.3V 2.5V C 2.5V 1V_DSP_A R121 2.0K 0603 R218 2.0K 0603 R38 2.0K 0603 DSPA_SCLK_VREF D R216 2.0K 0603 DSPB_SCLK_VREF 1V_DSP_B L1 10UH 1008 DSPA_VREF L2 10UH 1008 DSPB_VREF A1V_DSP_A A1V_DSP_B R37 2.0K 0603 1 R214 2.0K 0603 C41 1UF 0603 R88 2.0K 0603 C106 1UF 0603 R217 2.0K 0603 C37 1UF 0603 C105 1UF 0603 1 C44 1UF 0603 C46 1UF 0603 PLACE CLOSE TOGETHER USE at least 3 vias per connection PLACE CLOSE TOGETHER USE at least 3 vias per connection 1.0V DSP A 1V_DSP_A R76 0 1206 1V_DSP_B 1_5V_DSP_B 1.5V R110 0 1206 U12 U11 2 P8 2 IDC2X1 DNP R161 0 1206 R162 0 1206 3 A1V_DSP_A DSPA_SCLK_VREF F10 F13VDD1 F14VDD2 F17VDD3 F18VDD4 F19VDD5 F6VDD6 F7VDD7 F8VDD8 F9VDD9 G10VDD10 G13VDD11 G14VDD12 G17VDD13 G18VDD14 G19VDD15 G6VDD16 G7VDD17 G8VDD18 G9VDD19 H18VDD20 H19VDD21 H6VDD22 H7VDD23 J18VDD24 J19VDD25 J6VDD26 J7VDD27 K6VDD28 K7VDD29 L6VDD30 L7VDD31 M18VDD32 M19VDD33 M6VDD34 M7VDD35 N18VDD36 N19VDD37 N6VDD38 N7VDD39 P6VDD40 P7VDD41 R6VDD42 R7VDD43 T18VDD44 T19VDD45 T6VDD46 T7VDD47 U10VDD48 U18VDD49 U19VDD50 U6VDD51 U7VDD52 V10VDD53 V13VDD54 V14VDD55 V17VDD56 V18VDD57 V19VDD58 V6VDD59 V7VDD60 V8VDD61 V9VDD62 W10VDD63 W13VDD64 W14VDD65 W17VDD66 W18VDD67 W19VDD68 W6VDD69 W7VDD70 W8VDD71 W9VDD72 VDD73 N3 N4VDD_A1 VDD_A2 P2 SCLK_VREF1 F11 VDD_DRAM1F12 VDD_DRAM2F15 VDD_DRAM3F16 VDD_DRAM4G11 VDD_DRAM5G12 VDD_DRAM6G15 VDD_DRAM7G16 VDD_DRAM8K18 VDD_DRAM9K19 VDD_DRAM10L18 VDD_DRAM11L19 VDD_DRAM12P18 VDD_DRAM13P19 VDD_DRAM14R18 VDD_DRAM15R19 VDD_DRAM16U11 VDD_DRAM17V11 VDD_DRAM18V12 VDD_DRAM19V15 VDD_DRAM20V16 VDD_DRAM21W11 VDD_DRAM22W12 VDD_DRAM23W15 VDD_DRAM24W16 VDD_DRAM25 R104 0 1206 P10 1 2 IDC2X1 DNP 2_5V_DSP_A AB23 VDD_IO1AB24 VDD_IO2AC22 VDD_IO3AC3 VDD_IO4AD22 VDD_IO5AD3 VDD_IO6C23 VDD_IO7C24 VDD_IO8E10 VDD_IO9E11 VDD_IO10E12 VDD_IO11E13 VDD_IO12E14 VDD_IO13E15 VDD_IO14E17 VDD_IO15E19 VDD_IO16E6 VDD_IO17E8 VDD_IO18F20 VDD_IO19F5 VDD_IO20G20 VDD_IO21H20 VDD_IO22H5 VDD_IO23K20 VDD_IO24K5 VDD_IO25L20 VDD_IO26L5 VDD_IO27M20 VDD_IO28M5 VDD_IO29N20 VDD_IO30N5 VDD_IO31P20 VDD_IO32P5 VDD_IO33R20 VDD_IO34R5 VDD_IO35U20 VDD_IO36U5 VDD_IO37V20 VDD_IO38W20 VDD_IO39W5 VDD_IO40Y10 VDD_IO41Y11 VDD_IO42Y12 VDD_IO43Y13 VDD_IO44Y14 VDD_IO45Y15 VDD_IO46Y17 VDD_IO47Y19 VDD_IO48Y6 VDD_IO49Y8 VDD_IO50 J4 VREF 2.5V R107 0 1206 P11 1 2 IDC2X1 DNP DSPA_VREF A1 A22VSS1 A24VSS2 A3VSS3 AA12VSS4 AA21VSS5 AA4VSS6 AB1VSS7 AB12VSS8 AB15VSS9 AB2VSS10 AB22VSS11 AB3VSS12 AC2VSS13 AC23VSS14 AD1VSS15 AD24VSS16 B2VSS17 B22VSS18 B23VSS19 B3VSS20 C1VSS21 C13VSS22 C2VSS23 C22VSS24 C3VSS25 D13VSS26 D21VSS27 D4VSS28 E16VSS29 E18VSS30 E20VSS31 E5VSS32 E7VSS33 E9VSS34 G2VSS35 G5VSS36 H1VSS37 H10VSS38 H11VSS39 H12VSS40 H13VSS41 H14VSS42 H15VSS43 H16VSS44 H17VSS45 H8VSS46 H9VSS47 J10VSS48 J11VSS49 J12VSS50 J13VSS51 J14VSS52 J15VSS53 J16VSS54 J17VSS55 J20VSS56 J3VSS57 J5VSS58 J8VSS59 J9VSS60 K10VSS61 K11VSS62 K12VSS63 K13VSS64 K14VSS65 K15VSS66 K16VSS67 K17VSS68 K8VSS69 K9VSS70 L10VSS71 L11VSS72 L12VSS73 L13VSS74 L14VSS75 L15VSS76 VSS77 L16 VSS78L17 VSS79L8 VSS80L9 VSS81M10 VSS82M11 VSS83M12 VSS84M13 VSS85M14 VSS86M15 VSS87M16 VSS88M17 VSS89M21 VSS90M22 VSS91M8 VSS92M9 VSS93N10 VSS94N11 VSS95N12 VSS96N13 VSS97N14 VSS98N15 VSS99N16 VSS100N17 VSS101N2 VSS102N8 VSS103N9 VSS104P10 VSS105P11 VSS106P12 VSS107P13 VSS108P14 VSS109P15 VSS110P16 VSS111P17 VSS112P3 VSS113P8 VSS114P9 VSS115R1 VSS116R10 VSS117R11 VSS118R12 VSS119R13 VSS120R14 VSS121R15 VSS122R16 VSS123R17 VSS124R22 VSS125R8 VSS126R9 VSS127T10 VSS128T11 VSS129T12 VSS130T13 VSS131T14 VSS132T15 VSS133T16 VSS134T17 VSS135T20 VSS136T5 VSS137T8 VSS138T9 VSS139U12 VSS140U13 VSS141U14 VSS142U15 VSS143U16 VSS144U17 VSS145U8 VSS146U9 VSS147V5 VSS148Y16 VSS149Y18 VSS150Y20 VSS151Y5 VSS152Y7 VSS153Y9 VSS154 C42 1000PF 0805 P9 2 IDC2X1 DNP R163 0 1206 R164 0 1206 A1V_DSP_B DSPB_SCLK_VREF F10 F13VDD1 F14VDD2 F17VDD3 F18VDD4 F19VDD5 F6VDD6 F7VDD7 F8VDD8 F9VDD9 G10VDD10 G13VDD11 G14VDD12 G17VDD13 G18VDD14 G19VDD15 G6VDD16 G7VDD17 G8VDD18 G9VDD19 H18VDD20 H19VDD21 H6VDD22 H7VDD23 J18VDD24 J19VDD25 J6VDD26 J7VDD27 K6VDD28 K7VDD29 L6VDD30 L7VDD31 M18VDD32 M19VDD33 M6VDD34 M7VDD35 N18VDD36 N19VDD37 N6VDD38 N7VDD39 P6VDD40 P7VDD41 R6VDD42 R7VDD43 T18VDD44 T19VDD45 T6VDD46 T7VDD47 U10VDD48 U18VDD49 U19VDD50 U6VDD51 U7VDD52 V10VDD53 V13VDD54 V14VDD55 V17VDD56 V18VDD57 V19VDD58 V6VDD59 V7VDD60 V8VDD61 V9VDD62 W10VDD63 W13VDD64 W14VDD65 W17VDD66 W18VDD67 W19VDD68 W6VDD69 W7VDD70 W8VDD71 W9VDD72 VDD73 N3 N4VDD_A1 VDD_A2 P2 SCLK_VREF1 F11 VDD_DRAM1F12 VDD_DRAM2F15 VDD_DRAM3F16 VDD_DRAM4G11 VDD_DRAM5G12 VDD_DRAM6G15 VDD_DRAM7G16 VDD_DRAM8K18 VDD_DRAM9K19 VDD_DRAM10L18 VDD_DRAM11L19 VDD_DRAM12P18 VDD_DRAM13P19 VDD_DRAM14R18 VDD_DRAM15R19 VDD_DRAM16U11 VDD_DRAM17V11 VDD_DRAM18V12 VDD_DRAM19V15 VDD_DRAM20V16 VDD_DRAM21W11 VDD_DRAM22W12 VDD_DRAM23W15 VDD_DRAM24W16 VDD_DRAM25 A1 A22VSS1 A24VSS2 A3VSS3 AA12VSS4 AA21VSS5 AA4VSS6 AB1VSS7 AB12VSS8 AB15VSS9 AB2VSS10 AB22VSS11 AB3VSS12 AC2VSS13 AC23VSS14 AD1VSS15 AD24VSS16 B2VSS17 B22VSS18 B23VSS19 B3VSS20 C1VSS21 C13VSS22 C2VSS23 C22VSS24 C3VSS25 D13VSS26 D21VSS27 D4VSS28 E16VSS29 E18VSS30 E20VSS31 E5VSS32 E7VSS33 E9VSS34 G2VSS35 G5VSS36 H1VSS37 H10VSS38 H11VSS39 H12VSS40 H13VSS41 H14VSS42 H15VSS43 H16VSS44 H17VSS45 H8VSS46 H9VSS47 J10VSS48 J11VSS49 J12VSS50 J13VSS51 J14VSS52 J15VSS53 J16VSS54 J17VSS55 J20VSS56 J3VSS57 J5VSS58 J8VSS59 J9VSS60 K10VSS61 K11VSS62 K12VSS63 K13VSS64 K14VSS65 K15VSS66 K16VSS67 K17VSS68 K8VSS69 K9VSS70 L10VSS71 L11VSS72 L12VSS73 L13VSS74 L14VSS75 L15VSS76 VSS77 R113 0 1206 P12 1 2 IDC2X1 DNP 2_5V_DSP_B AB23 VDD_IO1AB24 VDD_IO2AC22 VDD_IO3AC3 VDD_IO4AD22 VDD_IO5AD3 VDD_IO6C23 VDD_IO7C24 VDD_IO8E10 VDD_IO9E11 VDD_IO10E12 VDD_IO11E13 VDD_IO12E14 VDD_IO13E15 VDD_IO14E17 VDD_IO15E19 VDD_IO16E6 VDD_IO17E8 VDD_IO18F20 VDD_IO19F5 VDD_IO20G20 VDD_IO21H20 VDD_IO22H5 VDD_IO23K20 VDD_IO24K5 VDD_IO25L20 VDD_IO26L5 VDD_IO27M20 VDD_IO28M5 VDD_IO29N20 VDD_IO30N5 VDD_IO31P20 VDD_IO32P5 VDD_IO33R20 VDD_IO34R5 VDD_IO35U20 VDD_IO36U5 VDD_IO37V20 VDD_IO38W20 VDD_IO39W5 VDD_IO40Y10 VDD_IO41Y11 VDD_IO42Y12 VDD_IO43Y13 VDD_IO44Y14 VDD_IO45Y15 VDD_IO46Y17 VDD_IO47Y19 VDD_IO48Y6 VDD_IO49Y8 VDD_IO50 J4 VREF 2.5V R118 0 1206 P13 1 2 IDC2X1 DNP C45 1000PF 0805 C39 1000PF 0805 3 C43 1000PF 0805 C38 1000PF 0805 ANALOG DEVICES PLACE CLOSE TO DSP A PINS 4 Size Board No. C Date C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE DSP POWER Title B 2 ADSP-TS201SA BP576 PLACE CLOSE TO DSP B PINS A L16 VSS78L17 VSS79L8 VSS80L9 VSS81M10 VSS82M11 VSS83M12 VSS84M13 VSS85M14 VSS86M15 VSS87M16 VSS88M17 VSS89M21 VSS90M22 VSS91M8 VSS92M9 VSS93N10 VSS94N11 VSS95N12 VSS96N13 VSS97N14 VSS98N15 VSS99N16 VSS100N17 VSS101N2 VSS102N8 VSS103N9 VSS104P10 VSS105P11 VSS106P12 VSS107P13 VSS108P14 VSS109P15 VSS110P16 VSS111P17 VSS112P3 VSS113P8 VSS114P9 VSS115R1 VSS116R10 VSS117R11 VSS118R12 VSS119R13 VSS120R14 VSS121R15 VSS122R16 VSS123R17 VSS124R22 VSS125R8 VSS126R9 VSS127T10 VSS128T11 VSS129T12 VSS130T13 VSS131T14 VSS132T15 VSS133T16 VSS134T17 VSS135T20 VSS136T5 VSS137T8 VSS138T9 VSS139U12 VSS140U13 VSS141U14 VSS142U15 VSS143U16 VSS144U17 VSS145U8 VSS146U9 VSS147V5 VSS148Y16 VSS149Y18 VSS150Y20 VSS151Y5 VSS152Y7 VSS153Y9 VSS154 DSPB_VREF ADSP-TS201SA BP576 ADSP-TS201SA BP576 ADSP-TS201SA BP576 C40 1000PF 0805 R109 0 1206 1 1.5V U12 U11 R91 0 1206 1 1_5V_DSP_A 1.0V DSP B Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 5 of 15 A B 2.5V C D 2.5V ID[2-0] have internal 5Kohm pull-down resistors R115 499.0 0805 DNP 1 R117 499.0 0805 DNP R120 499.0 0805 DNP R122 499.0 0805 DNP ID2_A ID2_B ID1_A ID1_B ID0_A ID0_B DSP A Default ID = 0 R123 499.0 0805 DNP ID(2-0) 000 001 010 011 100 101 110 111 R124 499.0 0805 Proc ID 0 1 2 3 4 5 6 7 DSP B Default ID = 1 2.5V 2.5V THESE RESISTORS DO NOT NEED TO BE VERY CLOSE TO THE DSP IF POSSIBLE I WOULD LIKE THEM ALL ON THE BOTTOM OF THE BOARD PLACE A LABEL "HIGH" NEAR SW2.12 ORGANIZED IN GROUPS SIMILAR TO SHOW HERE PLACE A LABEL FOR THE SIGNAL NAME NEXT TO SW2 PINS 1-6 DEPENDING ON HOW MUCH ROOM YOU CAN LEAVE NEAR THEM I WOULD LIKE TO LABEL SOME OF THEM SW2 SCLKRAT2_B SCLKRAT1_A SCLKRAT1_B SCLKRAT0_A SCLKRAT0_B 2 DSP A Default PLL Ratio = 5X CCLK = 500MHz SCLKRAT(2-0) 000 001 010 011 100 101 110 111 TMR0E_B PLL Ratio 4 5 6 7 8 10 12 RESERVED 4 9 5 8 6 7 6 SCLKRAT2_A R45 499.0 0805 10 5 BM_B SCLKRAT[2-0] have internal 5Kohm pull-down resistors R125 499.0 0805 DNP 11 3 4 TMR0E_A R126 499.0 0805 DNP 2 3 BM_A R133 499.0 0805 ON 12 2 BUSLOCK R127 499.0 0805 DNP 1 1 BMS R128 499.0 0805 DNP 1 2.5V R146 R140 499.0 0805 R141 499.0 0805 R142 499.0 0805 R144 499.0 0805 R145 499.0 0805 499.0 0805 DIP6 SWT017 All strap pins have internal 5Kohm pull-down resistors during DSP reset Switch OFF (Signal Pulled Low) Switch ON (Signal Pulled High) BMS * EPROM Boot External or link port boot BM * Disable interupts, level sensitive Enable interupts, edge sensitive TMR0E * 1-bit Link Port Data Width 4-bit Link Port Data Width BUSLOCK * SYSCON/SDRCON one-time writable SYSCON/SDRCON always writable * indicates DEFAULT DSP B Default PLL Ratio = 5X CCLK = 500MHz 2 KEEP STUB TO THE SIGNAL AS SMALL AS POSSIBLE 2.5V R131 499.0 0805 DNP CONTROLIMP0 CONTROLIMP1 DEFAULT = NORMAL CONTROLIMP0 has an internal 5Kohm pull-down resistor CONTROLIMP1 has an internal 5Kohm pull-up resistor CONTROLIMP(1:0) 00 01 10 11 L1BCMPO_A REALLY (L1BCMP0_B) L1BCMPI_A L2BCMPO_A REALLY (L2BCMP0_B) L2BCMPI_A L3BCMPO_A Driver Mode Normal Pulse Mode A/D Mode Pulse Mode, A/D Mode L3BCMPO_B R134 499.0 0805 DNP R23 499.0 0805 R51 499.0 0805 DNP R106 499.0 0805 DNP R111 499.0 0805 R114 499.0 0805 DNP R143 499.0 0805 3 3 ENEDREG_A 2.5V ENEDREG_B 2.5V R25 499.0 0805 R132 499.0 0805 DNP R139 499.0 0805 DNP DS2_A DS2_B DS1_A DS1_B DS0_A DS0_B R135 499.0 0805 DNP R154 499.0 0805 R136 499.0 0805 DNP DS1 has internal 5Kohm pull-down resistor DS2 and DS0 have internal 5Kohm pull-up resistors R137 499.0 0805 DNP DS(2-0) 000 001 010 011 100 101 110 111 R138 499.0 0805 DNP Drive Strength 11.1% 23.8% 36.5% 49.2% 61.9% 74.6% 87.3% 100% OUTPUT IMP 26 32 40 50 62 70 96 120 DEFAULT ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE CONFIGURATION Title Size 20 Cotton Road Rev A0178-2002 2.1C Sheet 4-9-2007_14:58 D 6 of 15 A B C D SDRAM 256Mb (32MB - 4M x 64bits) 1 LABEL "SDRAM(LOW)" FLASH (512Kbx8) LABEL "SDRAM(HIGH)" 1 D[0:63] A[0:18] U24 A1 U25 25 A0 A2 26 A3 27 DQ0 A1 DQ1 A2 A4 60 A5 61 A6 62 DQ2 A3 DQ3 A4 DQ4 A5 A7 63 A8 64 DQ5 A6 DQ6 A7 A9 65 A10 66 DQ7 A8 DQ8 A9 DQ9 24 SDA10 A10 A12 DQ10 21 A11 DQ11 DQ12 A13 22 A14 23 BA0 DQ13 BA1 DQ14 2 DQ15 20 SDRAM_CS CS DQ16 67 SDCKE CKE DQ17 68 SDRAM_CLK0 CLK DQ18 DQ19 17 SDWE WE DQ20 18 CAS CAS DQ21 19 RAS RAS DQ22 DQ23 16 LDQM DQM0 DQ24 71 DQM1 DQ25 28 DQM2 DQ26 59 DQM3 DQ27 DQ28 14 NC1 DQ29 30 NC2 DQ30 57 NC3 DQ31 2 D0 A1 2 DQ0 4 DQ1 5 DQ2 7 DQ3 8 DQ4 10 DQ5 11 DQ6 13 DQ7 74 DQ8 76 DQ9 77 DQ10 79 DQ11 80 DQ12 82 DQ13 83 DQ14 85 DQ15 31 DQ16 33 DQ17 34 DQ18 36 DQ19 37 DQ20 39 DQ21 40 DQ22 42 DQ23 45 DQ24 47 DQ25 48 DQ26 50 DQ27 51 DQ28 53 DQ29 54 DQ30 56 DQ31 A0 D1 A2 26 5 D2 A3 27 A1 A2 7 D3 A4 60 8 D4 A5 61 10 D5 A6 62 A3 A4 A5 11 D6 A7 63 13 D7 A8 64 A6 A7 74 D8 A9 65 76 D9 A10 66 77 D10 79 D11 80 D12 82 D13 A13 22 83 D14 A14 23 85 D15 31 D16 33 D17 34 D18 36 D19 37 D20 39 D21 40 D22 42 D23 45 D24 47 D25 71 48 D26 28 50 D27 59 51 D28 53 D29 14 54 D30 30 56 D31 57 A8 A9 24 SDA10 A10 A12 21 A11 BA0 BA1 20 SDRAM_CS CS 67 SDCKE CKE 68 SDRAM_CLK1 CLK 17 SDWE WE 18 CAS CAS 19 RAS RAS 16 HDQM DQM0 DQM1 DQM2 DQM3 NC1 NC2 NC3 73 11 A2 10 A3 D35 A4 D36 A5 D37 A6 D38 A7 D39 A8 D40 A9 D41 A10 D42 A11 D43 A12 D44 A13 D45 A14 D46 A15 D47 A16 D48 A17 D49 A18 D50 D51 MS0 D52 BMS 1 U31 1 4 4 2 SN74AHC1G00 SOT23-5 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7 D2 24 RD D1 A2 9 A3 8 A4 7 A5 6 A6 5 A7 27 A8 26 A9 23 A10 25 A11 4 A12 28 A13 29 A14 3 A15 2 A16 30 A17 1 A18 22 31 WRL D0 14 D1 2 SN74AHC1G00 SOT23-5 D53 U38 13 D0 A1 D33 D34 A0 D3 D4 D5 D6 D7 2 CE OE WE D54 AT49BV040 PLCC32 D55 D56 D57 D58 D59 D60 D61 D62 D63 70 NC5 73 NC6 NC6 1 VDD1 15 VDD2 29 VDD3 43 VDD4 VSS1 VSS2 VSS3 VSS4 3 VDDQ1 9 VDDQ2 35 VDDQ3 41 VDDQ4 49 VDDQ5 55 VDDQ6 75 VDDQ7 81 VDDQ8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 44 1 58 15 72 29 86 43 44 VSS1 58 VSS2 72 VSS3 86 VSS4 VDD1 VDD2 VDD3 VDD4 6 3 12 9 VDDQ2 32 35 38 41 46 49 52 55 78 75 84 81 3.3V VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 3 3.3V MSSD0 MSSD[0:1] C113 0.1UF 0402 SDRAM_CS R149 0 0805 DNP C112 0.1UF 0402 C109 0.01UF 0402 MSSD1 PLACE CLOSE TO DSP (not so critical) SN74AHC1G00 SN74AHC1G00 AT49BV040 MT48LC4M32B2 TSOP86 3.3V 3.3V ANALOG DEVICES 4 C130 0.01UF 0402 3.3V R155 0 0805 6 VSSQ1 12 VSSQ2 32 VSSQ3 38 VSSQ4 46 VSSQ5 52 VSSQ6 78 VSSQ7 84 VSSQ8 VDDQ1 MT48LC4M32B2 TSOP86 C132 0.01UF 0402 C131 0.01UF 0402 C136 0.01UF 0402 C135 0.01UF 0402 C133 0.01UF 0402 C134 0.01UF 0402 C140 0.01UF 0402 C139 0.01UF 0402 C137 0.01UF 0402 C138 0.01UF 0402 Date B Board No. C SDRAM C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE MEMORY Title Size SDRAM A 12 A1 NC4 3.3V NC5 C129 0.01UF 0402 A0 D32 69 NC4 70 3 25 4 69 3.3V U10 Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 7 of 15 A B C D KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE PLACE NEAR CONNECTOR CT5 10UF CAP002 FER2 600 1206 1 R44 5.76K 1206 R148 57.6K 1206 1 TRY TO KEEP ALL TRACES AS SHORT AS POSSIBLE INL-_AMPIN R58 100K 1206 C16 120PF 1206 C20 100PF 1206 3.3V R52 237.0 1206 U6 2 1 INL-_AMPOUT INL- AGND 3 LMV722M SOIC8 LABEL "LINE IN" R55 5.76K 1206 VREF_AUDIO C14 1000PF 0805 R54 5.76K 1206 J9 C12 100PF 1206 ADC ADC LEFT R42 10K 0805 C17 120PF 1206 1 5 AGND AUDIO_IN_LEFT 4 R49 750.0K 1206 LOOPBACK_LEFT 3 2 U9 13 R50 237.0 1206 U6 6 LOOPBACK_RIGHT AUDIO_IN_RIGHT C11 1000PF 0805 12 7 CON001 INL+ 11 5 10 LMV722M SOIC8 2 18 AGND 19 AGND 16 CT4 10UF CAP002 FER1 600 1206 R53 5.76K 1206 R147 57.6K 1206 17 21 CASC CAPLN CAPLP VINLP VINLN VINRP C18 120PF 1206 C15 100PF 1206 24 RESET 2 VINRN 28 LRCLK 27 BCLK 26 DOUT 25 DIN CAPRN CAPRP 1 MCLK MCLK SLAVE MODE MCLK IS 256 x Fs 48 kHZ SAMPLE RATE I S I/F MODE 8 XCTRL 2 CCLK/{256~/512} 3 COUT/{DF0} 4 CIN/{DF1} 5 CLATCH/{M~/S} INR-_AMPIN R59 100K 1206 R39 10K 0805 LRCLK BCLK DR 14 VREF RESET VREF_AUDIO AD1871YRSZ SSOP28 2 C4 0.1UF 0805 R48 237.0 1206 U7 1 INR-_AMPOUT CT2 10UF B INR- AGND 3 LMV722M SOIC8 PLACE NEAR CONNECTOR R57 5.76K 1206 C13 1000PF 0805 C3 100PF 1206 R56 5.76K 1206 C9 100PF 1206 AGND ADC RIGHT C19 120PF 1206 AGND R47 750.0K 1206 3 C7 0.01UF 0805 C2 0.01UF 0805 C1 0.01UF 0805 C10 1000PF 0805 3 KEEP THESE CLOSE TO AD1871 7 U26 2 C8 0.01UF 0805 R46 237.0 1206 U7 6 C6 100PF 1206 INR+ AGND 5 1 LMV722M LMV722M SOIC8 3 LMV722M SOIC8 AGND THE GND AND AGND PLANES SHOULD GO FROM PIN 8 to PIN 21 of U9 AGND A5V 6 7 VREF_AUDIO C147 0.1UF 0805 WHEN USING AN ELECTRET MICROPHONE PLACE SW1.1 AND SW1.2 IN ON POSITION PLACE SW1.3 AND SW1.4 IN OFF POSITION 5 LMV722M SOIC8 A5V A5V 3.3V R179 0 1206 5V AGND R157 2.0K 1206 U26 A5V C146 0.1UF 0805 C145 0.1UF 0805 C148 0.1UF 0805 C249 0.1UF 0805 C149 0.1UF 0805 PLACE RESISTOR BETWEEN AD1871 and AD1854 R156 2.0K 1206 ANALOG DEVICES SW1 3 6 4 5 4 R152 5.76K 1206 ON 7 3 INR-_AMPIN 8 2 2 R150 5.76K 1206 1 1 4 AUDIO_IN_RIGHT AUDIO_IN_LEFT INR-_AMPOUT AGND AGND AGND AGND NEAR U6 NEAR U7 NEAR U26 AD1871 AD1871 AD1871 DIP4 SWT018 Size Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE AUDIO IN Title INL-_AMPOUT INL-_AMPIN 20 Cotton Road Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 8 of 15 A B C D 1 1 KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE R65 5.49K 1206 R62 11.0K 1206 C27 100PF 1206 R66 3.32K 1206 THE GND AND AGND PLANES SHOULD GO FROM PIN 10 to PIN 20 of U3 DAC LEFT C25 330PF 0805 6 384/256~ R74 604.0 1206 1 3 U3 96/48~ CT7 68UF CAP003 U8 C23 100PF 1206 DAC 10 2 16 OUTL- 17 OUTL+ 13 OUTR- 12 OUTR+ OUTLOUTL+ R64 5.49K 1206 C26 680PF 0805 LMV722M SOIC8 R67 1.65K 1206 C24 2200PF 1206 R63 49.9K 1206 7 X2MCLK 2 MCLK BCLK LRCLK DT 2 OUTR- BCLK OUTR+ 26 MCLK 25 LRCLK 27 SDATA C28 220PF 1206 LABEL "LINE OUT" 14 FILTR FILTB 3.3V 2 R68 2.74K 1206 AGND 19 J10 1 VREF_AUDIO 4 CCLK 3 CLATCH 5 CDATA ZEROL ZEROR 22 CT3 10UF B 8 C5 0.1UF 1206 5 CT1 10UF B AGND LOOPBACK_LEFT LOOPBACK_RIGHT RESET 24 4 3 2 RESET CON001 R40 10K 0805 R70 5.49K 1206 9 DEEMP 23 21 20 MUTE R61 11.0K 1206 AGND IDPM0 C31 100PF 1206 R71 3.32K 1206 IDPM1 AD1854JRSZ SSOP28 C30 330PF 0805 DAC RIGHT 6 CT6 68UF CAP003 U8 C21 100PF 1206 R75 604.0 1206 7 5 3 R69 5.49K 1206 SLAVE MODE MCLK IS 256 x Fs 48 kHZ SAMPLE RATE I S I/F MODE 5V A5V C29 680PF 0805 LMV722M SOIC8 R72 1.65K 1206 3 C22 2200PF 1206 R60 49.9K 1206 A5V R73 2.74K 1206 C32 220PF 1206 AGND C142 0.1UF 0805 C143 0.1UF 0805 C153 0.1UF 0805 AGND AD1854 AGND AGND AD1854 NEAR U8 ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE AUDIO OUT Title Size 20 Cotton Road Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 9 of 15 A B C D 3.3V 3.3V R89 10K 0805 LABEL "IRQ_A" LABEL "FLAG0_A" R94 10K 0805 1 R99 100 0805 U14 U30 1 R95 100 0805 SW4 SWT013 MOMENTARY U14 11 SW9 SWT013 MOMENTARY 10 2 1 74LVC14A SOIC14 1 2 IRQ0_A_S 74LVC14A SOIC14 CT9 1UF A 74LVC14A SOIC14 3.3V CT8 1UF A R86 10K 0805 LABEL "RESET" 3.3V U5 3.3V 1 MR 4 PFI SW3 SWT013 MOMENTARY LABEL "FLAG1_A" DA_SOFT_RESET U14 3 U14 13 2 DSP_RESET R85 100 0805 R78 100 0805 SW8 SWT013 MOMENTARY 12 SW5 SWT013 MOMENTARY 74LVC14A SOIC14 RESET R130 0 0805 ADM708SARZ SOIC8 R100 10K 0805 LABEL "IRQ_B" R77 10K 0805 8 RESET 7 RESET 5 PFO U30 4 3 74LVC14A SOIC14 4 IRQ0_B_S 74LVC14A SOIC14 2 CT10 1UF A CT13 1UF A 3.3V 3.3V RESET LED8 RED LED001 LABEL "RESET" 3.3V R112 10K 0805 R160 10K 0805 R158 10K 0805 R90 270 1206 R159 10K 0805 R87 10K 0805 LABEL "FLAG0_B" U13 U30 R103 100 0805 5 2 1A1 6 U14 5 SW6 SWT013 MOMENTARY 6 74LVC14A SOIC14 9 1A3 1A4 11 FLAG2_A FLAG2_B FLAG3_A 10 FLAG3_B 74LVC14A SOIC14 13 1 ON 12 2 11 3 10 4 9 1 2 8 IRQ0_A_S 6 6 IRQ0_B_S 5 5 74LVC14A SOIC14 4 9 3 U14 17 2A3 2A4 DIP6 SWT017 8 7 3 OE1 FLAG3_B LED3 YELLOW LED001 OE2 12 FLAG3_A/AUDIO LED6 YELLOW LED001 R80 270 1206 FLAG2_A LED4 YELLOW LED001 POWER LED1 GREEN LED001 R81 270 1206 R82 270 1206 R151 270 1206 FLAG0_A FLAG1_A FLAG0_B FLAG1_B 3.3V 3.3V 3.3V 3.3V LABEL "POWER" LABEL "FLAG3_B" LABEL "FLAG2_B" LABEL "FLAG3_A/AUDIO" LABEL "FLAG2_A" 3.3V IRQ0_A IRQ0_B C114 0.1UF 0402 C118 0.1UF 0402 C111 0.1UF 0402 C120 0.1UF 0402 ANALOG DEVICES C144 0.1UF 0402 SN74AHC1G00 74LVC14 Size 74LVC14 IDT74FCT3244APY ADM708 Board No. C Date B C 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE RESET/PB/LED Title A FLAG2_B LED5 YELLOW LED001 IDT74FCT3244APY SSOP20 R79 270 1206 Switch ON = Pushbutton will drive DSP net. Switch OFF = DSP net can come from an external source DEFAULT = All Switches ON 4 2A2 15 9 2Y1 7 2Y2 5 2Y3 3 2Y4 SW10 R101 100 0805 CT11 1UF A 2A1 13 1 74LVC14A SOIC14 SW7 SWT013 MOMENTARY 11 19 U30 R102 10K 0805 3.3V 8 U30 LABEL "FLAG1_B" 1A2 8 74LVC14A SOIC14 3.3V 4 6 U30 CT12 1UF A 3 RESET 74LVC14A SOIC14 18 1Y1 16 1Y2 14 1Y3 12 1Y4 Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 10 of 15 A B C D Expansion Interface (TYPE A) PLACE LABEL "EXPANSION INTERFACE (TYPE A)" NEAR MIDDLE CONNECTOR 5V 1 2.5V 2.5V 5V 3.3V WARNING: WHEN CONNECTING TO ANOTHER BOARD MAKE SURE TX CONNECTOR GOES TO A RX CONNECTOR DO NOT USE CROSSOVER CABLE D[0:63] A[0:31] J4 J3 2 J1 2 1 J2 2 1 4 3 4 3 6 5 6 5 1 L3CLKOUT_P_A 4 3 L3CLKOUT_N_A 6 5 L3DATO0_P_A 8 7 1 LABEL "DSP A TX" 2 3 4 A1 2 1 A0 A3 8 7 A2 A5 10 9 A4 A7 12 11 A6 A9 14 13 A11 16 A13 A15 CLKOUT_EXP 8 7 10 9 12 11 A8 14 13 15 A10 16 15 18 17 A12 D49 18 17 20 19 A14 D51 20 19 A17 22 21 A16 D53 22 A19 24 23 A18 D55 24 A21 26 25 A20 D57 A23 28 27 A22 A25 30 29 A24 A27 32 31 A26 A29 34 33 A28 A31 36 35 A30 9 12 11 14 13 16 15 18 17 D48 20 19 D50 22 21 21 D52 24 23 23 D54 26 25 26 25 D56 28 27 D59 28 27 D58 30 29 D61 30 29 D60 32 31 D63 32 31 D62 34 33 34 33 36 35 36 35 38 37 38 37 40 39 40 39 42 41 SDCKE HDQM FLAG3_A DPA 10 CAS FLAG1_A SDWE SDA10 RAS LDQM MSSD0 DMAR3_B IOWR MSSD1 MSSD3 RESET FLAG0_A FLAG2_A 38 37 D1 40 39 D0 D3 42 41 D2 42 41 44 43 D5 44 43 D4 44 43 46 45 D7 46 45 D6 46 45 48 47 FLAG1_B FLAG3_B FLAG0_B FLAG2_B DMAR0 L3ACKI_A DMAR1_A L3DATO0_N_A DMAR2_B L3BCMPO_A MSH DSP A TX 5 6 7 8 IORD CON_RJ45 MSSD2 BM_B J5 L3CLKIN_P_A L3CLKIN_N_A L3DATI0_P_A 1 2 LABEL "DSP A RX" 3 4 L3ACKO_A L3DATI0_N_A L3BCMPI_A DSP A RX 2 5 6 7 8 CON_RJ45 3 D9 48 47 D8 48 47 50 49 D11 50 49 D10 50 49 52 51 D13 52 51 D12 52 51 54 53 D15 54 53 D14 54 53 56 55 D17 56 55 D16 56 55 58 57 D19 58 57 D18 58 57 60 59 D21 60 59 D20 60 59 62 61 D23 62 61 D22 62 61 64 63 D25 64 63 D24 64 63 66 65 D27 66 65 D26 66 65 68 67 D29 68 67 D28 68 67 70 69 D31 70 69 D30 70 69 72 71 D33 72 71 D32 72 71 74 73 D35 74 73 D34 74 73 76 75 D37 76 75 D36 76 75 78 77 D39 78 77 D38 78 77 80 79 D41 80 79 D40 80 79 82 81 D43 82 81 D42 82 81 84 83 D45 84 83 D44 84 83 86 85 IRQ1_A IRQ3_A IRQ1_B IRQ3_B IOEN TMR0E_A BUSLOCK HBG IRQ0_A BMS IRQ2_A MS0 IRQ0_B MS1 IRQ2_B ACK J6 BOFF L3CLKOUT_P_B L3CLKOUT_N_B L3DATO0_P_B 1 2 3 LABEL "DSP B TX" 4 L3ACKI_B HBR L3DATO0_N_B L3BCMPO_B DSP B TX 5 6 7 8 CPA RD CON_RJ45 3 WRL WRH J7 D47 86 85 88 87 90 89 D46 BM_A BRST 86 85 88 87 L3CLKIN_P_B 88 87 90 89 L3CLKIN_N_B 90 89 L3DATI0_P_B CON019 1 2 LABEL "DSP B RX" 3 DSP B RX 4 CON019 CON019 L3ACKO_B L3DATI0_N_B L3BCMPI_B 5 6 7 8 CON_RJ45 ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE EXPANSION INTERFACE Title Size 20 Cotton Road Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 11 of 15 A B C D 3.3V 3.3V PLACE CLOSE TO OSC R41 10K 0805 C115 0.1UF 0402 R129 22 0805 U2 1 OE OUT 3 AUDIOCLK 12.288MHZ OSC003 1 1 12.288MHz U4 CPLD_MISC14 34 CPLD_MISC16 33 CPLD_MISC18 PLACE CLOSE TO CPLD CPLD_MISC20 R205 22 0805 CPLD_MISC22 32 31 30 CPLD_MISC24 MCLK MCLK_S 38 AUDIOCLK 39 CPLD_MISC26 R206 22 0805 40 BCLK_S BCLK BCLK_S 41 LRCLK_S 42 MCLK_S R207 22 0805 43 LRCLK R219 22 0805 LRCLK_S 26 DT 25 DR R97 0 0805 DNP 44 45 46 DSP_RESET 2 28 48 RESET 49 50 24 23 22 21 20 19 51 52 53 54 BK1_FB7_MC1_CDRST BK1_FB7_MC4 BK1_FB7_MC5 BK1_FB7_MC12_GCK1 BK1_FB7_MC14 BK1_FB7_MC15_GCK0 BK1_FB8_MC2_GCK2 BK1_FB8_MC5_DGE BK1_FB8_MC13 BK1_FB8_MC14 BK1_FB8_MC15 BK1_FB8_MC16 BK1_FB9_MC2 BK1_FB9_MC15 BK1_FB9_MC16 BK1_FB10_MC1 R208 0 0805 P6 XILINX 143 BK2_FB1_MC3_GSR 142 BK2_FB1_MC4 140 BK2_FB1_MC12 139 BK2_FB1_MC13 2 BK2_FB2_MC1_GTS2 3 BK2_FB2_MC3_GTS3 4 BK2_FB2_MC4 5 BK2_FB2_MC5_GTS0 6 BK2_FB2_MC15_GTS1 7 BK2_FB2_MC16 138 BK2_FB3_MC3 137 BK2_FB3_MC4 136 BK2_FB3_MC5 135 BK2_FB3_MC12 134 BK2_FB3_MC16 9 BK2_FB4_MC1 10 BK2_FB4_MC2 11 BK2_FB4_MC3 12 BK2_FB4_MC4 133 BK2_FB5_MC2 132 BK2_FB5_MC3 131 BK2_FB5_MC13 130 BK2_FB5_MC15 129 BK2_FB5_MC16 13 BK2_FB6_MC2 14 BK2_FB6_MC3 15 BK2_FB6_MC4 16 BK2_FB6_MC13 17 BK2_FB6_MC14 18 BK2_FB6_MC16 CoolRunner II CPLD BK1_FB10_MC2 BK1_FB10_MC4 BK1_FB10_MC14 BK1_FB10_MC15 BK1_FB10_MC16 BK1_FB11_MC1 BK1_FB11_MC2 BK1_FB11_MC3 BK1_FB11_MC4 BK1_FB11_MC5 BK1_FB11_MC12 BK1_FB12_MC1 BK1_FB12_MC2 BK1_FB12_MC3 BK1_FB12_MC5 CPLD_MISC1 1 2 CPLD_MISC3 3 4 CPLD_MISC5 5 6 CPLD_MISC7 7 8 CPLD_MISC9 9 10 CPLD_MISC11 11 12 CPLD_MISC13 13 14 CPLD_MISC15 15 16 CPLD_MISC17 17 18 CPLD_MISC19 19 20 CPLD_MISC21 21 22 CPLD_MISC23 23 24 CPLD_MISC25 25 26 CPLD_MISC2 CPLD_MISC2 TDO_A TDI_B CPLD_MISC4 R180 0 0805 DNP CPLD_MISC6 CPLD_MISC8 CPLD_MISC10 R209 0 0805 TDO TDO_B CPLD_MISC12 CPLD_MISC14 CPLD_MISC16 CPLD_MISC18 CPLD_MISC20 CPLD_MISC22 3.3V CPLD_MISC24 CPLD_MISC26 IDC13X2 CPLD_MISC4 3.3V CPLD_MISC6 R203 10K 0805 CPLD_MISC8 CPLD_MISC10 DSP JTAG HEADER 2 CPLD_MISC12 DA_EMULATOR_SELECT 3V ZP4 1 2 3 4 TMS TMS TCK TCK DA_EMULATOR_SELECT DA_EMULATOR_EMU 5 6 DA_EMULATOR_TMS 7 8 DA_EMULATOR_TCK 9 10 DA_EMULATOR_TRST 11 12 DA_EMULATOR_TDI 13 14 DA_EMULATOR_TDO DA_EMULATOR_EMU TRST TRST DA_EMULATOR_TMS TDI TDI TDO TDO EMU EMU DA_EMULATOR_TCK DA_EMULATOR_TRST DA_EMULATOR_TDI DA_EMULATOR_TDO IDC7X2 RESET DA_GP0 CPLD_TCK DA_GP1 CPLD_TDO DA_GP2 CPLD_TDI DA_GP3 CPLD_TMS RESET R188 4.7K DA_SOFT_RESET 0805 DA_SOFT_RESET GND XC2C384 TQFP144 SHGND 35 DEBUG_AGENT U4 D[0:23] U4 TCK 67 3.3V 63 TDI 122 TDO 3 65 TMS 27 VDD_BK1_IO1 55 VDD_BK1_IO2 141 XILINX VDD_BK2_IO1 73 VDD_BK3_IO1 CoolRunner II 93 VDD_BK3_IO2 109 CPLD 127 VDD_BK4_IO2 1.8V 71 62 70 72 69 89 68 90 66 99 64 108 80 123 81 144 82 GND5 GND9 VDD_INT2 GND10 84 VDD_INT3 77 47 GND3 GND8 37 CPLD_TMS 79 GND6 VDD_INT1 76 36 GND2 VDD_AUX 1 75 CPLD_TDO 78 GND7 8 74 CPLD_TDI 29 GND1 GND4 VDD_BK4_IO1 CPLD_TCK GND11 83 XC2C384 TQFP144 61 60 3.3V 59 85 86 P5 4 CPLD_TCK CPLD_TDO CPLD_TDI CPLD_TMS 1 87 2 88 3 91 4 92 5 58 6 57 IDC6X1 56 112 BK4_FB13_MC3 113 BK4_FB13_MC4 114 BK4_FB13_MC12 115 BK4_FB13_MC13 111 BK4_FB14_MC1 110 BK4_FB14_MC2 107 BK4_FB14_MC3 106 BK4_FB14_MC4 105 BK4_FB14_MC5 104 BK4_FB14_MC13 116 BK4_FB15_MC2 117 BK4_FB15_MC5 118 BK4_FB15_MC13 119 BK4_FB15_MC15 120 BK4_FB15_MC16 103 BK4_FB16_MC1 102 BK4_FB16_MC3 101 BK4_FB16_MC14 100 BK4_FB16_MC16 121 BK4_FB17_MC2 124 BK4_FB17_MC12 125 BK4_FB17_MC13 126 BK4_FB17_MC14 128 BK4_FB17_MC16 98 BK4_FB18_MC3 97 BK4_FB18_MC4 96 BK4_FB18_MC5 95 BK4_FB18_MC12 94 BK4_FB18_MC13 BK3_FB19_MC3 BK3_FB19_MC4 BK3_FB19_MC5 BK3_FB19_MC12 BK3_FB19_MC13 BK3_FB19_MC14 BK3_FB20_MC1 BK3_FB20_MC2 BK3_FB20_MC3 BK3_FB20_MC4 BK3_FB20_MC5 BK3_FB20_MC13 BK3_FB21_MC1 XILINX CoolRunner II CPLD BK3_FB21_MC3 BK3_FB21_MC12 BK3_FB21_MC15 BK3_FB22_MC2 BK3_FB22_MC12 BK3_FB22_MC14 BK3_FB23_MC3 BK3_FB23_MC4 BK3_FB23_MC5 BK3_FB23_MC12 BK3_FB23_MC13 BK3_FB23_MC14 BK3_FB24_MC2 BK3_FB24_MC12 BK3_FB24_MC14 1.8V D0 D1 SHGND D2 D3 3 D4 C85 0.01UF 0402 D5 C84 0.01UF 0402 C83 0.01UF 0402 All USB interface is considered proprietary and has been omitted from this schematic. D6 D7 When designing your JTAG interface please refer to the D8 Engineer to Engineer Note EE-68 which can be found at CPLD D9 http://www.analog.com D10 D11 3.3V D12 D13 D14 D15 D16 C77 0.01UF 0402 D17 C78 0.01UF 0402 C80 0.01UF 0402 C79 0.01UF 0402 C50 0.01UF 0402 C49 0.01UF 0402 C81 0.01UF 0402 C82 0.01UF 0402 D18 D19 D20 D21 CPLD ANALOG DEVICES D22 D23 RD 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE JTAG/CPLD FOR AUDIO Title FLAG3_A DMAR0 MS1 Size Board No. C Date B Nashua, NH 03063 WRL XC2C384 TQFP144 A 20 Cotton Road C Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 12 of 15 A B F1 5A FUS005 C D D2 MBRS540T3G 5A SMC FER5 190 FER002 4 3 1 2 UNREG_IN J8 1 2 1 D1 MBRS540T3G 5A SMC C48 1000PF 1206 3 7_5V_POWER CON005 1 UNREG_IN C47 1000PF 1206 FER7 600 1206 C55 10UF 1210 C51 10UF 0805 DNP FER6 600 1206 SHGND PGND R92 24.9K 0603 R165 0.05 1206 VR1 FDC658P 5 TP7 IN 1 SHGND CS C52 470PF 0603 C53 68PF 0603 4 4 6 PGATE FB 1.8V GND 2 R167 80.6K 0603 R105 0 0603 ADP1864 SOT23-6 3 C73 0.47UF 0805 OUTPUT 3 D7 SSB43L DO-214AA CT14 47UF B CT15 2.2UF B C56 1UF 0805 DNP R202 0 1206 2 W2 COPPER R168 255.0K 0603 VR4 ERR R166 0 0805 6 FDC658P SOT23-6 R234 332.0K 0805 2 INPUT 6 SD L3 6.8UH IND009 5 3.3V 2 1 2 3 3.3V U15 COMP 3A PGND 1 5 FB GND 4 ADP3331ARTZ SOT23-6 PGND PGND R192 340.0K 0805 C74 4.7UF 0805 R201 698.0K 0805 TP2 5V 3 TP3 TP4 TP5 TP9 TP10 TP11 TP8 MH1 MH2 MH3 MH4 MH5 A5V UNREG_IN 3 R178 0 1206 VR6 7 IN1 8 IN2 OUT1 OUT2 OUT3 6 SD FER3 600 1206 1 SHGND 2 3 5 FB GND 4 ADP3336ARMZ MSOP8 M1 R190 210.0K 0805 C70 4.7UF 0805 C54 1UF 0805 C72 1UF 0805 RUBBER FOOT MSC009 M2 M3 M4 RUBBER FOOTRUBBER FOOTRUBBER FOOT MSC009 MSC009 MSC009 M5 RUBBER FOOT MSC009 C71 1UF 0805 R191 64.9K 0805 AGND ANALOG DEVICES 4 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE POWER PAGE1 Title Size 20 Cotton Road Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 13 of 15 A B C D U19 L7 1UH IND011 1 Q1 MMBT3904 SOT23 3 UNREG_IN D5 BAT54 SOT23D VR2 2 R198 10 0603 C93 1UF 0603 R197 10K 0402 D8 BZX84C5V6 SOT23D CT18 330UF D 4 GATE 3 S3 2 S2 1 S1 R200 0 0402 1 R196 1.2K 0402 CT17 330UF D C101 1UF 0603 C95 1UF 0603 C94 1UF 0603 C102 22000PF 0402 16 PVCC 12 VCC 5 FREQ 6 SHND 7 PWGD 9 SS 4 SYNC 8 GND 1 2 DH 3 SW 15 DL 13 CSL 11 COMP 14 PGND 10 FB R199 0 0402 R204 1.50K 0402 D2 8 D1 L6 0.7UH IND010 U21 R195 15.0K 0603 C96 47PF 1206 4 GATE 3 S3 2 S2 1 S1 R212 2.0K 0603 R210 8.20K 0603 C100 2.2PF 0402 1 1.0V 7 IRF7821 SOIC8 DGND3 C97 4700PF 0603 CT19 470UF E 5 D4 BGND R211 10.0K 0603 C99 10UF 0805 C92 10UF 0805 CT22 470UF E CT23 470UF E 6 7 D2 8 D1 W1 COPPER BGND 4 GATE 3 S3 2 S2 1 S1 DGND3 CT16 470UF E D3 IRF7832 SOIC8 U20 C98 2200PF 0603 POK_1V 6 D3 BST ADP1821 QSOP16 BGND 5 D4 5 15A D4 6 D3 7 D2 BGND 8 D1 W5 COPPER IRF7832 SOIC8 1A BGND 2 2 DGND3 SW1 SW2 C62 1UF 0603 D3 BAT54 SOT23D 2.5V R175 1.1K 0402 R174 1.1K 0402 20 23 DH1 21 R170 0 0402 22 18 DL1 1 32 R176 18K 0402 R183 100K 0603 C65 680PF 0603 C64 1500PF 0402 3 C63 22PF 0805 24 VREG 31 25 UNREG_IN 27 R2 0 0402 DNP R177 12.1K 0402 D4 BAT54 SOT23D UNREG_IN U16 2.5V VR3 R171 0 0402 R182 820 0402 C61 1UF 0603 VREG VREG R181 38.3K 0603 DGND3 D6 BAT54A SOT23D 28 30 4 EN2 POK_1V C66 0.1UF 0402 C59 22000PF 0402 33 2 DGND2 CSL1 BST1 SW1 DH1 DL1 FB1 COMP1 POK1 TRK1 EN1 LDOSD IN SS1 GND NC R173 0 0402 14 CSL2 11 BST2 13 SW2 12 DH2 16 DL2 7 COMP2 6 FB2 5 UV2 DH1 4 5 D1A 6 D1B 3 S1 2 7 D2A 8 D2B 1 S2 G1 DH2 R172 0 0402 C36 10UF 1210 DL2 DL1 G2 1.5V SW1 L4 10UH IND012 C90 10UF 0805 C91 10UF 0805 C33 10UF 0805 CT20 100UF C FDS9926A SOIC8 R169 100K 0603 10 POK2 26 EN2 8 TRK2 3 FREQ 29 VREG 17 PV R189 10K 0402 R193 15.0K 0603 R184 10K 0402 EN2 C87 82PF 0402 VREG R194 430 0402 C88 4700PF 0603 3 AGND2 UNREG_IN C89 1200PF 0402 9 SS2 19 PGND1 15 PGND2 U17 C110 10UF 1210 C60 1UF 0603 SYNC C76 22000PF 0402 DH2 4 2 7 D2A 8 D2B 1 S2 G1 R185 10.0K 0402 C86 1UF 0603 DL2 1.5V 5 D1A 6 D1B 3 S1 G2 ADP1823 LFCSP32 SW2 L5 8.2UH IND012 C58 10UF 0805 C57 10UF 0805 CT21 100UF C FDS9926A SOIC8 DGND2 DGND2 AGND2 DGND2 W3 COPPER AGND2 3A ANALOG DEVICES AGND2 W4 COPPER 4 1A DGND2 Board No. C Date A B C Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE POWER PAGE2 Title Size 20 Cotton Road Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 14 of 15 A B C D 1V_DSP_A 1 VDD (1.0V) Bypass Caps (per DSP) (8) 1nF (4) 0.01uF (5) 0.1uF (1) 100uF C173 1000PF 0402 C174 1000PF 0402 C175 1000PF 0402 C176 1000PF 0402 C177 1000PF 0402 C178 1000PF 0402 C179 1000PF 0402 C180 1000PF 0402 C219 0.01UF 0402 C218 0.01UF 0402 C216 0.01UF 0402 C220 0.01UF 0402 C221 0.1UF 0402 C222 0.1UF 0402 C223 0.1UF 0402 C224 0.1UF 0402 C225 0.1UF 0402 1 1V_DSP_B ALL BYPASS CAPS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE CORISPONDING IC TRACES FROM COMPONENT TO CAPACITOR AND FROM THE CAPACITOR TO GND SHOULD BE AS SHORT AS POSSIBLE THE PRIORITY FOR THE PLACEMENT: 1V_DSP_X 1_5V_DSP_X 2_5V_DSP_X C206 1000PF 0402 C196 1000PF 0402 C207 1000PF 0402 C208 1000PF 0402 C209 1000PF 0402 C210 1000PF 0402 C195 1000PF 0402 C211 1000PF 0402 C203 0.01UF 0402 C204 0.01UF 0402 C205 0.01UF 0402 C202 0.01UF 0402 C201 0.1UF 0402 C200 0.1UF 0402 C199 0.1UF 0402 C198 0.1UF 0402 C197 0.1UF 0402 2 2 1_5V_DSP_A 1_5V_DSP_B VDD_DRAM (1.5V) Bypass Caps (per DSP) (6) 1nF (2) 0.01uF (4) 0.1uF (1) 100uF C67 1000PF 0402 C168 1000PF 0402 C169 1000PF 0402 C170 1000PF 0402 C171 1000PF 0402 C172 1000PF 0402 C68 0.01UF 0402 C167 0.01UF 0402 C165 0.1UF 0402 C166 0.1UF 0402 C75 0.1UF 0402 C69 0.1UF 0402 C212 1000PF 0402 C226 1000PF 0402 C217 1000PF 0402 C215 1000PF 0402 C214 1000PF 0402 2_5V_DSP_A C213 1000PF 0402 C232 0.01UF 0402 C227 0.01UF 0402 C229 0.1UF 0402 C228 0.1UF 0402 C230 0.1UF 0402 C231 0.1UF 0402 2_5V_DSP_B 3 3 VDD_IO (2.5V) Bypass Caps (per DSP) (8) 1nF (2) 0.01uF (4) 0.1uF (1) 100uF C194 1000PF 0402 C193 1000PF 0402 C192 1000PF 0402 C191 1000PF 0402 C190 1000PF 0402 C189 1000PF 0402 C188 1000PF 0402 C186 1000PF 0402 C181 0.01UF 0402 C183 0.01UF 0402 C182 0.1UF 0402 C187 0.1UF 0402 C185 0.1UF 0402 C184 0.1UF 0402 C234 1000PF 0402 C246 1000PF 0402 C236 1000PF 0402 C245 1000PF 0402 C233 1000PF 0402 C244 1000PF 0402 C243 1000PF 0402 C235 1000PF 0402 C242 0.01UF 0402 ANALOG DEVICES 4 Board No. C Date A B C C241 0.1UF 0402 C237 0.1UF 0402 C238 0.1UF 0402 C239 0.1UF 0402 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD ADSP-TS201S EZ-KIT LITE DSP BYPASS CAPS Title Size C240 0.01UF 0402 Rev A0178-2002 2.1C Sheet 1-10-2007_10:57 D 15 of 15 I INDEX A AD1854 digital-to-analog converters (DACs), 1-12 AD1871 analog-to-digital converters (ADCs), 1-12 amplification gains, 2-5 audio amplification selection (SW1), 2-5 connectors (J9-10), 2-21 interface, 1-12 B bill of materials, A-1 ~BMS boot memory select pins, 1-7, 2-3 board schematic, B-1 boot mode switch (SW2), 2-7 bus control configuration, 1-9 connectors diagram of locations, 1-4, 2-20 J10 (audio out), 2-21 J1 (expansion), 2-3, 2-22 J2 (expansion), 2-3, 2-22 J3 (expansion), 2-3, 2-22 J4-7 (link ports), 2-23 J8 (power), 2-21 J9 (audio in), 2-5, 2-21 ZJ1 (USB), 2-22 ZP4 (JTAG), 2-4, 2-21 contents, of this EZ-KIT Lite package, 1-2 CONTROLIMP1-0 resistors, 2-14 control impedance selection (R131, R143), 2-14 core power regulators, 2-2 speed, 2-3 customer support, xiv C CLKIN pins, 2-12 CLKOUT pins, 2-4 clock frequency, 2-12 generator (U1), 2-3, 2-12 ratio settings, 2-13 codecs, See AD1871, AD1854 complex programmable logic device (CPLD), 1-12 configuration, of this EZ-KIT Lite, 1-3 configuration resistors, 2-10 D D23-0 pins, 1-12 default configuration, of this EZ-KIT Lite, 1-3 DIP switches diagram of locations, 2-5 SW10, 2-5, 2-9 SW1 (audio amplification) switch, 2-5 SW2, 2-5, 2-7, 2-8 driver mode resistors (CONTROLIMP1-0), 2-14 drive strength selection (R132, R135-136), 2-15 ADSP-TS201S EZ-KIT Lite Evaluation System Manual I-1 INDEX I DS2-0 pins, 2-15 E EPROM boot mode, 2-7 example programs, 1-13 expansion interface, 2-3, 2-9, 2-22 external interrupts, 1-11 memory, xi, 1-7, 2-4 memory space (MSSD0), 1-8 ports, 2-3 voltage regulator, 2-3 EZ-KIT Lite board architecture, 2-2 F features, of this EZ-KIT Lite, x field-programmable gate arrays (FPGAs), ix FLAG LEDs (LED3-6), 2-17 push buttons (SW6-9), 2-18 source switch (SW10), 2-9 FLAG0_A (SW9) pins, 1-11, 2-18 FLAG0_B (SW6) pins, 1-11, 2-18 FLAG1_A (SW8) pins, 1-11, 2-18 FLAG1_B (SW7) pins, 1-11, 2-18 FLAG2_A (LED4) pins, 1-11, 2-18 FLAG2_B (LED5) pins, 1-11, 2-18 FLAG3_A (LED6) pins, 1-11, 1-12, 2-18 FLAG3_B (LED3) pins, 1-11, 1-12, 2-18 FLAGREG registers, 1-10 flash memory boot memory select pins, 2-3 map of, 1-9 frequency, 1-13, 2-12 G impedance selection, 2-14 input clock, 2-3 installation, of this EZ-KIT Lite, 1-5 interface connectors, xi internal DRAM power regulator, 2-2 memory, 1-7, 1-8, 2-4 interrupt enable settings (SW2), 2-8 pins (IRQ3-0), 1-11 push buttons (SW4-5), 2-19 source switch (SW10), 2-9 IRQ0_A (SW4) interrupt pins, 1-11, 2-19 IRQ0_B (SW5) interrupt pins, 1-11, 2-19 J JTAG connector (ZP4), 2-4, 2-21 emulation port, 2-4 L LEDs diagram of locations, 1-4, 2-16 LED1 (power), 2-16 LED3 (FLAG3_B), 1-11, 2-18 LED4 (FLAG2_A), 1-11, 2-18 LED5 (FLAG2_B), 1-11, 2-18 LED6 (FLAG3_A), 1-11, 2-18 LED8 (master reset), 2-16 ZLED3 (USB monitor), 1-5, 2-18 license restrictions, 1-7 link ports connections, 1-12 width settings (SW2), 2-8 LVDS signaling, 1-12 general-purpose IO pins, -xi, 2-18 GND pins, 2-23 I-2 ADSP-TS201S EZ-KIT Lite Evaluation System Manual INDEX M resistors diagram of locations, 2-10 master processors, 2-10 clock mode settings, 2-12 memory control impedance selection, 2-14 map, of this EZ-KIT Lite, 1-7 drive strength selection, 2-15 select pins, See ~BMS, ~MS0, 1-7 processor ID settings, 2-11 microphones, 2-5 restrictions, of the license, 1-7 ~MS0 memory bank 0 select pins, 1-7, 1-8, 2-3 RJ-45 connectors, 1-12, 2-23 MSSD0 external memory space, 1-8 RX port, 1-12 N notation conventions, xxi O oscillators (U18), 2-3, 2-12 P package contents, 1-2 power connector (J8), 2-21 LED (LED1), 2-16 regulators, 2-2 supply specifications, 2-23 processor IDs, 1-8, 1-12, 2-10, 2-15 programmable flag pins, See flags by name (FLAGs) push buttons See also push buttons by name (SWx) diagram of locations, 2-16 R registration, of this product, 1-3 reset master (LED8), 2-16 processor, 2-6 push button (SW3), 2-19 S schematic, of this EZ-KIT Lite, B-1 SCLK pins, 2-14 SCLKRAT2-0 pins, 2-3, 2-12, 2-13 SDRAM interface, 1-8 start/end addresses, 1-8 SDRCON registers, 1-8, 2-7 setup, of this EZ-KIT Lite, 1-4 SOC registers, 1-8 specifications, of the power supply, 2-23 SQSTAT registers, 1-10 startup, of this EZ-KIT Lite, 1-5 SW10 (FLAG/IRQ) DIP switch, 2-9 SW1 (audio amplification) switch, 2-5 SW2 DIP switch, 2-7, 2-8 SW3 (reset) push button, 2-19 SW4 (IRQ0_A) push button, 1-11, 2-19 SW5 (IRQ0_B) push button, 1-11, 2-19 SW6 (FLAG0_B) push button, 1-11, 2-18 SW7 (FLAG1_B) push button, 1-11, 2-18 SW8 (FLAG1_A) push button, 1-11, 2-18 SW9 (FLAG0_A) push button, 1-11, 2-18 SYSCON registers, 1-8, 2-7 system architecture, of this EZ-KIT Lite, 2-2 T TX port, 1-12 ADSP-TS201S EZ-KIT Lite Evaluation System Manual I-3 INDEX U V USB cable, 1-3 connector (ZJ1), 2-22 interface, 1-9, 2-7, 2-21 monitor LED (ZLED3), 2-18 VisualDSP++ documentation, xix environment, 1-5 online Help, xviii voltage regulators, xi, 2-2 I-4 ADSP-TS201S EZ-KIT Lite Evaluation System Manual