ETC ADSP-TS101SAB1-000

T
a
DSP Microcomputer
ADSP-TS101S
KEY FEATURES
250 MHz, 4.0 ns Instruction Cycle Rate
6M Bits of Internal—On-Chip—SRAM Memory
19 ⴛ 19 mm (484-Ball) or 27 ⴛ 27 mm (625-Ball) PBGA
Package
Dual Computation Blocks—Each Containing an ALU, a
Multiplier, a Shifter, and a Register File
Dual Integer ALUs, Providing Data Addressing and
Pointer Manipulation
Integrated I/O Includes 14 Channel DMA Controller,
External Port, Four Link Ports, SDRAM Controller,
Programmable Flag Pins, Two Timers, and Timer
Expired Pin for System Integration
1149.1 IEEE Compliant JTAG Test Access Port for
On-Chip Emulation
On-Chip Arbitration for Glueless Multiprocessing with
up to Eight TigerSHARC® DSPs on a Common Bus
KEY BENEFITS
Provides High Performance Static Superscalar DSP
Operations, Optimized for Telecommunications
Infrastructure and Other Large, Demanding
Multiprocessor DSP Applications
Performs Exceptionally Well on DSP Algorithm and I/O
Benchmarks (See Benchmarks in Table 1 and Table 2)
Supports Low Overhead DMA Transfers Between
Internal Memory, External Memory, Memory-Mapped
Peripherals, Link Ports, Host Processors, and Other
(Multiprocessor) DSPs
Eases DSP Programming Through Extremely Flexible
Instruction Set and High Level Language Friendly DSP
Architecture
Enables Scalable Multiprocessing Systems with Low
Communications Overhead
FUNCTIONAL BLOCK DIAGRAM
COMPUTATIONAL BLOCKS
SHIFTER
PROGRAM SEQUENCER
PC
IAB
ALU
BTB
DATA ADDRESS GENERATION
IRQ
INTEGER
J ALU
ADDR
FETCH
32
32
INTEGER
K ALU
32x32
32x32
INTERNAL MEMORY
MEMORY
M0
64Kx32
A
D
MEMORY
M1
64Kx32
A
D
6
JTAG PORT
MEMORY
M2
64Kx32
A
SDRAM CONTROLLER
D
MULTIPLIER
X
REGISTER
FILE
32x32
128
32
M0 ADDR
128
M0 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
32
HOST INTERFACE
32
M1 ADDR
128
M1 DATA
128
ADDR
INPUT FIFO
64
DAB
OUTPUT BUFFER
DAB
32
M2 ADDR
128
M2 DATA
DATA
OUTPUT FIFO
128
128
Y
REGISTER
FILE
32x32
I/O ADDRESS
32
CNTRL
CLUSTER BUS
ARBITER
I/O PROCESSOR
3
DMA
CONTROLLER
L0
LINK PORT
CONTROLLER
MULTIPLIER
L1
DMA ADDRESS
DMA DATA
ALU
SHIFTER
8
3
CONTROL/
STATUS/
TCBs
32
256
256
LINK
PORTS
LINK DATA
CONTROL/
STATUS/
BUFFERS
8
3
8
L2
3
L3
8
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2002
ADSP-TS101S
TABLE OF CONTENTS
GENERAL DESCRIPTION
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
Dual Compute Blocks . . . . . . . . . . . . . . . . . . . . . . . . 3
Data Alignment Buffer (DAB) . . . . . . . . . . . . . . . . . . 4
Dual Integer ALUs (IALUs) . . . . . . . . . . . . . . . . . . . 4
Program Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 4
Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 4
On-Chip SRAM Memory . . . . . . . . . . . . . . . . . . . . . 5
External Port
(Off-Chip Memory/Peripherals Interface) . . . . . . 5
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Multiprocessor Interface . . . . . . . . . . . . . . . . . . . . . 5
SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . 6
EPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timer and General-Purpose I/O . . . . . . . . . . . . . . . . 8
Reset and Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Filtering Reference Voltage and Clocks . . . . . . . . . . . 9
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Designing an Emulator-Compatible DSP
Board (Target) . . . . . . . . . . . . . . . . . . . . . . . 10
Additional Information . . . . . . . . . . . . . . . . . . . . . . 11
Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . 11
Strap Pin Function Descriptions . . . . . . . . . . . . . . . . . 19
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 21
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 21
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 22
General AC Timing . . . . . . . . . . . . . . . . . . . . . . . 22
Link Ports Data Transfer
and Token Switch Timing . . . . . . . . . . . . . . . 25
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 28
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . 29
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 29
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 30
Environmental Conditions . . . . . . . . . . . . . . . . . . . . 32
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 32
484-Ball PBGA Pin Configurations . . . . . . . . . . . . . . . 33
625-Ball PBGA Pin Configurations . . . . . . . . . . . . . . . 36
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 39
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . 40
The ADSP-TS101S TigerSHARC DSP is an ultra high performance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32- and 40-bit floating-point and 8-, 16-,
32-, and 64-bit fixed-point processing—to set a new standard of
performance for digital signal processors. The TigerSHARC
DSP’s static superscalar architecture lets the processor execute
up to four instructions each cycle, performing twenty-four 16-bit
fixed-point operations or six floating-point operations.
Three independent 128-bit wide internal data buses, each
connecting to one of the three 2M bit memory banks, enable
quad word data, instruction, and I/O accesses and provide
12G bytes per second of internal memory bandwidth. Operating
at 250 MHz, the ADSP-TS101S DSP’s core has a 4.0 ns instruction cycle time. Using its Single-Instruction, Multiple-Data
(SIMD) features, the ADSP-TS101S can perform 2 billion
40-bit MACs or 500 million 80-bit MACs per second. Table 1
and Table 2 show the DSP’s performance benchmarks.
Table 1. General-Purpose Algorithm Benchmarks
at 250 MHz
Benchmark
Clock
Cycles
Speed
32-bit Algorithm, 500 million MACs/s peak performance
1024 Point Complex FFT (Radix 2) 39.34 µs
9,835
50-tap FIR on 1024 input
110 µs
27,500
Single FIR MAC
2.2 ns
0.55
16-bit Algorithm, 2 billion MACs/s peak performance
256 Point Complex FFT (Radix 2) 4.4 µs
1,100
50-tap FIR on 1024 input
28.8 µs
7,200
Single FIR MAC
0.56 ns
0.14
Single Complex FIR MAC
2.28 ns
0.57
I/O DMA Transfer Rate
External port
800M bytes/s n/a
Link ports (each)
250M bytes/s n/a
Table 2. 3G Wireless Algorithm Benchmarks
Benchmark
Execution
(MIPS)1
Turbo Decode
51 MIPS
384 kbps Data Channel
0.86 MIPS
Viterbi Decode
12.2 kbps AMR2 Voice Channel
0.27 MIPS
Complex Correlation
3.84 Mcps3 with a Spreading Factor of 256
1 The
Execution Speed is in Instruction Cycles Per Second.
Multi Rate (AMR)
3 Megachips per second (Mcps)
2 Adaptive
The ADSP-TS101S is code compatible with the other TigerSHARC processors.
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ADSP-TS101S
The Functional Block Diagram on Page 1 shows the ADSPTS101S DSP’s architectural blocks. These blocks include:
The TigerSHARC DSP uses a Static Superscalar™ architecture.
This architecture is superscalar in that the ADSP-TS101S DSP’s
core can execute simultaneously from one to four 32-bit instructions encoded in a Very Large Instruction Word (VLIW)
instruction line using the DSP’s dual compute blocks. Because
the DSP does not perform instruction reordering at runtime—
the programmer selects which operations will execute in parallel
prior to runtime—the order of instructions is static.
• Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, and 32-word register file and
associated Data Alignment Buffers (DABs)
• Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing
• A program sequencer with Instruction Alignment Buffer
(IAB), Branch Target Buffer (BTB), and interrupt
controller
With few exceptions, an instruction line, whether it contains one,
two, three, or four 32-bit instructions, executes with a throughput
of one cycle in an eight-deep processor pipeline.
• Three 128-bit internal data buses, each connecting to one
of three 2M bit memory banks
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruction
line resources each instruction requires and on the source and
destination registers used in the instructions. The programmer
has direct control of three core components—the IALUs, the
compute blocks, and the program sequencer.
• On-chip SRAM (6M bit)
• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memory
mapped peripherals, and external SRAM and SDRAM
• A 14-channel DMA controller
• Four link ports
The ADSP-TS101S, in most cases, has a two-cycle arithmetic
execution pipeline that is fully interlocked, so whenever a computation result is unavailable for another operation dependent on
it, the DSP automatically inserts one or more stall cycles as
needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer
data dependencies.
• Two 32-bit interval timers and timer expired pin
• A 1149.1 IEEE compliant JTAG test access port for
on-chip emulation
Figure 1 shows a typical single processor system with external
SDRAM. Figure 3 on Page 7 shows a typical multiprocessor
system.
ADSP-TS101S
LCLK_P
CLK
CS
ADDR RAS
DATA CAS
DQM
IRQ3–0
Dual Compute Blocks
DATA
The ADSP-TS101S has compute blocks that can execute computations either independently or together as a SIMD engine.
The DSP can issue up to two compute instructions per compute
block each cycle, instructing the ALU, multiplier, or shifter to
perform independent, simultaneous operations.
FLAG3–0
ID2–0
MSSD
RAS
MEMORY
(OPTIONAL)
DATA63–0
OE
RD
WE
ACK
WRH/WRL
ACK
MS1–0
CS
CAS
LDQM
HDQM
WE
CKE
SDWE
SDCKE
A10
SDA10
FLYBY
IOEN
LINK
DEVICES
(4 MAX)
(OPTIONAL)
DATA
LXDAT7–0
LXCLKIN
LXCLKOUT
MSH
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
HBR
HBG
BR7–0
ADDR
CPA
DATA
The compute blocks are referred to as X and Y in assembly
syntax, and each block contains three computational units—an
ALU, a multiplier, a 64-bit shifter—and a 32-word register file.
• Register File—Each compute block has a multiported
32-word, fully orthogonal register file used for transferring data between the computation units and data buses
and for storing intermediate results. Instructions can
access the registers in the register file individually (word
aligned), or in sets of two (dual aligned) or four (quad
aligned).
DPA
BOFF
DMAR3–0
DMA DEVICE
(OPTIONAL)
DATA
LXDIR
TMR0E
BM
BUSLOCK
CONTROLIMP2–0
DS2–0
RESET JTAG
DATA
SDRAM
MEMORY
(OPTIONAL)
ADDR
CS
ADDR
ADDRESS
REFERENCE
BMS
SCLK_P
S/LCLK_N
VREF
BRST
LCLKRAT2–0
SCLKFREQ ADDR31–0
CONTROL
CLOCK
In addition, the ADSP-TS101S supports SIMD operations two
ways—SIMD compute blocks and SIMD computations.The
programmer can direct both compute blocks to operate on the
same data (broadcast distribution) or on different data (merged
distribution). In addition, each compute block can execute four
16-bit or eight 8-bit SIMD computations in parallel.
BOOT
EPROM
(OPTIONAL)
• ALU—The ALU performs a standard set of arithmetic
operations in both fixed- and floating-point formats. It
also performs logic operations.
Figure 1. Single Processor System with External SDRAM
Static Superscalar is a trademark of Analog Devices, Inc.
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–3–
• Multiplier—The multiplier performs both fixed- and
floating-point multiplication and fixed-point multiply and
accumulate.
ADSP-TS101S
• Shifter—The 64-bit shifter performs logical and arithmetic shifts, bit and bit stream manipulation, and field
deposit and extraction operations.
Program Sequencer
The ADSP-TS101S DSP’s program sequencer supports:
• A fully interruptible programming model with flexible
programming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles.
• Accelerator—128-bit unit for Trellis Decoding (for
example, Viterbi and Turbo decoders) and complex correlations for communication applications.
• An eight-cycle instruction pipeline—three-cycle fetch
pipe and five-cycle execution pipe—with computation
results available two cycles after operands are available.
Using these features, the compute blocks can:
• Provide 8 MACs per cycle peak and 7.1 MACs per cycle
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit performance (based on FIR)
• The supply of instruction fetch memory addresses; the
sequencer’s Instruction Alignment Buffer (IAB) caches
up to five fetched instruction lines waiting to execute; the
program sequencer extracts an instruction line from the
IAB and distributes it to the appropriate core component
for execution.
• Execute six single precision floating-point or execute
twenty-four 16-bit fixed-point operations per cycle,
providing 1500 MFLOPS or 6.0 GOPS performance
• Perform two complex 16-bit MACs per cycle
• The management of program structures and determination of program flow according to JUMP, CALL, RTI,
RTS instructions, loop structures, conditions, interrupts,
and software exceptions.
• Execute eight Trellis butterflies in one cycle
Data Alignment Buffer (DAB)
The DAB is a two quad word FIFO that enables loading of quad
word data from non-aligned addresses. Normally, load instructions must be aligned to their data size so that quad words are
loaded from a quad aligned address. Using the DAB significantly
improves the efficiency of some applications, such as FIR filters.
• Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero-to-two overhead cycles, overcoming the three-to-six stage branch penalty.
Dual Integer ALUs (IALUs)
The ADSP-TS101S has two IALUs that provide powerful
address generation capabilities and perform many generalpurpose integer operations. Each of the IALUs:
• Compact code without the requirement to align code in
memory; the IAB handles alignment.
• Provides memory addresses for data and update pointers
Interrupt Controller
• Supports circular buffering and bit-reverse addressing
The DSP supports nested and non-nested interrupts. Each
interrupt type has a register in the interrupt vector table. Also,
each has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level sensitive or
edge sensitive, except the IRQ3–0 hardware interrupts, which are
programmable.
• Performs general-purpose integer operations, increasing
programming flexibility
• Includes a 31-word register file for each IALU
As address generators, the IALUs perform immediate or indirect
(pre- and post-modify) addressing. They perform modulus and
bit-reverse operations with no constraints placed on memory
addresses for the modulus data buffer placement. Each IALU can
specify either a single , dual , or quad word access from memory.
The DSP distinguishes between hardware interrupts and
software exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
efficient programming of delay lines and other data structures
required in digital signal processing, and they are commonly used
in digital filters and Fourier transforms. Each IALU provides
registers for four circular buffers, so applications can set up a total
of eight circular buffers. The IALUs handle address pointer
wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can
start and end at any memory location.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and
a subtract in both computation blocks while it also branches to
another location in the program. Some key features of the instruction set include:
• Enhanced instructions for communications infrastructure to govern Trellis Decoding (for example, Viterbi
and Turbo decoders) and Despreading via complex
correlations
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle.
Hardware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
• Algebraic assembly language syntax
• Direct support for all DSP, imaging, and video arithmetic types, eliminating hardware modes
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ADSP-TS101S
• Branch prediction encoded in instruction, enables zerooverhead loops
The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memory
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
• Parallelism encoded in instruction line
• Conditional execution optional for all instructions
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or slow
devices, host processors, and other memory-mapped peripherals
with variable access, hold, and disable time requirements.
• User-defined partitioning between program and
data memory
On-Chip SRAM Memory
The ADSP-TS101S has 6M bits of on-chip SRAM memory,
divided into three blocks of 2M bits (64K words × 32 bits). Each
block—M0, M1, and M2—can store program, data, or both, so
applications can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch.
Host Interface
The ADSP-TS101S provides an easy and configurable interface
between its external bus and host processors through the external
port. To accommodate a variety of host processors, the host
interface supports pipelined or slow protocols for accesses of the
host as slave. Each protocol has programmable transmission
parameters, such as idle cycles, pipe depth, and internal
wait cycles.
The DSP’s internal and external memory (Figure 2) is organized
into a unified memory map, which defines the location (address)
of all elements in the system.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The memory map is divided into four memory areas—host space,
external memory, multiprocessor space, and internal memory—
and each memory space, except host memory, is subdivided into
smaller memory spaces.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mechanism. When the host asserts BOFF, the DSP backs off the current
transaction and asserts HBG and relinquishes the external bus.
Each internal memory block connects to one of the 128-bit wide
internal buses—block M0 to bus MD0, block M1 to bus MD1,
and block M2 to bus MD2—enabling the DSP to perform three
memory transfers in the same cycle. The DSP’s internal bus
architecture provides a total memory bandwidth of 12G bytes per
second, enabling the core and I/O to access eight 32-bit data
words (256 bits) and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables:
The host can directly read or write the internal memory of the
ADSP-TS101S, and it can access most of the DSP registers,
including DMA control (TCB) registers. Vector interrupts
support efficient execution of host commands.
• DSP core and I/O access of different memory blocks in
the same cycle
Multiprocessor Interface
The ADSP-TS101S offers powerful features tailored to multiprocessing DSP systems through the external port and link ports.
This multiprocessing capability provides highest bandwidth for
interprocessor communication, including:
• DSP core access of all three memory blocks in parallel—
one instruction and two data accesses
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
• Up to eight DSPs on a common bus
• On-chip arbitration for glueless multiprocessing
• Complete context switch in less than 20 cycles (80 ns)
• Link ports for point-to-point communication
External Port (Off-Chip Memory/Peripherals Interface)
The external port and link ports provide integrated, glueless multiprocessing support.
The ADSP-TS101S DSP’s external port provides the processor’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—three 128-bit data buses and three
32-bit address buses—are multiplexed at the external port to
create an external system bus with a single 64-bit data bus and a
single 32-bit address bus. The external port supports data
transfer rates of 800M bytes per second over external bus.
The external port supports a unified address space (see Figure 2)
that enables direct interprocessor accesses of each ADSPTS101S DSP’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glueless
connection for systems containing up to eight ADSP-TS101S
DSPs and a host processor. Bus arbitration has a rotating priority.
Bus lock supports indivisible read-modify-write sequences for
semaphores. A bus fairness feature prevents one DSP from
holding the external bus too long.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the lower
32 bits of the external data bus connect to even addresses, and
the upper 32 bits connect to odd addresses.
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The DSP’s four link ports provide a second path for interprocessor communications with throughput of 1G bytes per second.
The cluster bus provides 800M bytes per second throughput—
with a total of 1.8G bytes per second interprocessor bandwidth.
–5–
ADSP-TS101S
GLOBAL SPACE
0xFFFFFFFF
HOST
(MSH)
INTERNAL SPACE
0x10000000
0x003FFFFF
RESERVED
0x00280000
EXTERNAL MEMORY SPACE
0x00300000
BANK 1
(MS1)
0x0C000000
BANK 0
(MS0)
0x08000000
SDRAM
(MSSD)
0x00200000
0x00180000
RESERVED
0x0010FFFF
INTERNAL MEMORY 2
0x00100000
RESERVED
MULTIPROCESSOR MEMORY SPACE
0x001807FF
INTERNAL REGISTERS (UREGS)
0x04000000
PROCESSOR ID 7
0x03C00000
PROCESSOR ID 6
0x03800000
PROCESSOR ID 5
0x03400000
PROCESSOR ID 4
0x03000000
PROCESSOR ID 3
0x02C00000
EACH IS A COPY
OF INTERNAL SPACE
PROCESSOR ID 2
0x02800000
PROCESSOR ID 1
0x02400000
PROCESSOR ID 0
0x02000000
BROADCAST
0x0008FFFF
0x01C00000
INTERNAL MEMORY 1
0x00080000
RESERVED
RESERVED
0x003FFFFF
0x0000FFFF
INTERNAL MEMORY 0
INTERNAL MEMORY
0x00000000
0x00000000
Figure 2. Memory Map
read access. During booting, the BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
SDRAM Controller
The SDRAM controller controls the ADSP-TS101S DSP’s
transfers of data to and from synchronous DRAM (SDRAM).
The throughput is 32 or 64 bits per SCLK cycle using the external
port and SDRAM control pins.
The SDRAM interface provides a glueless interface with
standard SDRAMs—16M bit, 64M bit, 128M bit, and
256M bit. The DSP directly supports a maximum of
64M words × 32 bit of SDRAM. The SDRAM interface is
mapped in external memory in the DSP’s unified memory map.
The EPROM or Flash Memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
Flash Memory interface can be used after boot via a DMA.
DMA Controller
The ADSP-TS101S DSP’s on-chip DMA controller, with 14
DMA channels, provides zero-overhead data transfers without
processor intervention. The DMA controller operates independently and invisibly to the DSP’s core, enabling DMA operations
EPROM Interface
The ADSP-TS101S can be configured to boot from external
8-bit EPROM at reset through the external port. An automatic
process (which follows reset) loads a program from the EPROM
into internal memory. This process uses 16 wait cycles for each
–6–
REV. 0
CONTROL
ADDRESS
DATA
ADDRESS
DATA
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
CONTROL
ADSP-TS101S
ADSP-TS101 #1
001
BR7–2,0
BR1
ID2–0
RESET
CLKS/REFS
LINK
ADDR31–0
DATA63–0
CONTROL
ADSP-TS101 #0
BR7–1
BR0
ID2–0
000
RESET
RESET
ADDR31–0
ADDR
CLKS/REFS
DATA63–0
DATA
RD
SCLK_P
CLOCK
LCLK_P
REFERENCE
VOLTAGE
WRH/L
ACK
MS1–0
BUSLOCK
BMS
CPA
S/LCLK_N
DPA
VREF
BOFF
LCLKRAT2–0
DMAR3–0
SCLKFREQ
BRST
IRQ3–0
HBR
FLAG3–0
HBG
MSH
LINK
LINK
DEVICES
(4 MAX)
(OPTIONAL)
LXDAT7–0
LXCLKIN
ACK
CS
CS
ADDR
DATA
ADDR
IOEN
DATA
RAS
CAS
CS
RAS
CAS
TMR0E
LDQM
HDQM
SDWE
BM
SDCKE
WE
CKE
SDA10
A10
CONTROLIMP2–0
DS2–0
CONTROL
BOOT
EPROM
(OPTIONAL)
CLOCK
FLYBY
MSSD
LXCLKOUT
LXDIR
OE
WE
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
SDRAM
MEMORY
(OPTIONAL)
DQM
ADDR
DATA
CLK
Figure 3. Shared Memory Multiprocessing System
to occur while the DSP’s core continues to execute program
instructions. The DMA controller performs DMA transfers
between:
The DMA controller supports Flyby transfers. Flyby operations
only occur through the external port (DMA channel 0) and do
not involve the DSP’s core. The DMA controller acts as a conduit
to transfer data from one external device to another through
external memory. During a transaction, the DSP:
• Internal memory and external memory and memorymapped peripherals
• Relinquishes the external data bus
• Internal memory of other DSPs on a common bus, a host
processor, or link port I/O
• Outputs addresses, memory selects (MS1–0, MSSD,
RAS, CAS, and SDWE) and the FLYBY, IOEN, and
RD/WR strobes
• External memory and external peripherals or link port I/O
• External bus master and internal memory or link port I/O
• Responds to ACK
The DMA controller provides a number of additional features.
REV. 0
DMA chaining is also supported by the DMA controller. DMA
chaining operations enable applications to automatically link one
DMA transfer sequence to another for continuous transmission.
The sequences can occur over different DMA channels and have
different transmission attributes.
–7–
ADSP-TS101S
The DMA controller also supports two-dimensional transfers.
The DMA controller can access and transfer two-dimensional
memory arrays on any DMA transmit or receive channel. These
transfers are implemented with index, count, and modify
registers for both the X and Y dimensions.
Timer and General-Purpose I/O
The ADSP-TS101S has a timer pin (TMR0E) that generates
output when a programmed timer counter has expired. Also, the
DSP has four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single bit input or output.
As outputs, these pins can signal peripheral devices; as inputs,
they can provide the test for conditional branching.
The DMA controller performs the following DMA operations:
• External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the
DSP’s internal memory and any external memory or
memory-mapped peripheral on the external bus. These
transfers support master mode and handshake mode
protocols.
Reset and Booting
The ADSP-TS101S has three levels of reset:
• Power-up reset—After power-up of the system, and strap
options are stable, the RESET pin must be asserted (low)
for a minimum of 2 ms followed by a deasserted (high)
pulse of a minimum of 50 SCLK cycles and asserted (low)
for a minimum of 100 SCLK cycles. TRST must also be
asserted (low) during power-up to ensure proper
operation of the device. See Figure 4.
• Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad word data only
between link ports and between a link port and internal
or external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
• Normal reset—For any resets following the power-up
reset sequence, the RESET pin must be asserted for at
least 100 SCLK cycles.
• AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus
master to internal memory or to link port I/O. These
transfers only use slave mode protocol, and an external
bus master must initiate the transfer.
• Core reset—When setting the SQRST bit in SQCTL, the
core is reset, but not the external port or I/O.
RESET
Link Ports
The DSP’s four link ports provide additional 8-bit bidirectional
I/O capability. With the ability to operate at a double data rate—
latching data on both the rising and falling edges of the clock—
running at 125 MHz, each link port can support up to
250M bytes per second, for a combined maximum throughput
of 1G bytes per second.
tSTART_LO
tPULSE1_HI
tPULSE2_LO
NOTES:
tSTART_LO = 2ms MINIMUM AFTER POWER SUPPLIES ARE STABLE
tPULSE1_HI = 50ⴛtSCLK MINIMUM TO 100ⴛtSCLK MAXIMUM
tPULSE2_LO = 100ⴛtSCLK MINIMUM
The link ports provide an optional communications channel that
is useful in multiprocessor systems for implementing point to
point interprocessor communications. Applications can also use
the link ports for booting.
Figure 4. Power-up Reset Waveform
After reset, the ADSP-TS101S has four boot options for
beginning operation:
Each link port has its own double-buffered input and output
registers. The DSP’s core can write directly to a link port’s
transmit register and read from a receive register, or the DMA
controller can perform DMA transfers through eight (four
transmit and four receive) dedicated link port DMA channels.
• Boot from EPROM. The DSP defaults to EPROM
booting when the BMS pin strap option is set low. See
Strap Pin Function Descriptions on Page 19.
• Boot by an external master (host or another ADSPTS101S). Any master on the cluster bus can boot the
ADSP-TS101S through writes to its internal memory or
through auto DMA.
Each link port has three signals that control its operation.
LxCLKOUT and LxCLKIN implement clock/acknowledge
handshaking. LxDIR indicates the direction of transfer and is
used only when buffering the LxDAT signals. An example application would be using differential low-swing buffers for long
twisted-pair wires. LxDAT provides the 8-bit data bus
input/output.
• Boot by link port. All four receive link DMA channels are
initialized after reset to transfer a 256-word block to
internal memory address 0 to 255, and to issue an
interrupt at the end of the block (similar to EP DMA).
The corresponding DMA interrupts are set to address
zero (0).
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are
transmitted.
• No boot—Start running from an external memory. Using
the ‘no boot’ option, the ADSP-TS101S must start
running from an external memory, caused by asserting
one of the IRQ3–0 interrupt signals.
Under certain conditions, the link port receiver can initiate a
token switch to reverse the direction of transfer; the transmitter
becomes the receiver and vice versa.
–8–
REV. 0
ADSP-TS101S
The ideal power-on sequence for the DSP is to provide powerup of all supplies simultaneously. If there is going to be some delay
between power-up of the supplies, provide VDD (and VDD_A) first,
then VDD_IO.
The ADSP-TS101S core always exits from reset in the idle state
and waits for an interrupt. Some of the interrupts in the interrupt
vector table are initialized and enabled after reset.
Low Power Operation
The ADSP-TS101S can enter a low power sleep mode in which
its core does not execute instructions, reducing power consumption to a minimum. The ADSP-TS101S exits sleep mode when
it senses a falling edge on any of its IRQ3–0 interrupt inputs. The
interrupt, if enabled, causes the ADSP-TS101S to execute the
corresponding interrupt service routine. This feature is useful for
systems that require a low power standby mode.
Filtering Reference Voltage and Clocks
Figure 5 shows a possible circuit for filtering VREF, SCLK_N, and
LCLK_N. This circuit provides the reference voltage for the
switching voltage, system clock, and local clock references.
VDD_IO
VREF
SCLK_N
Clock Domains
R1
The ADSP-TS101S has two clock inputs that drive its two major
clock domains:
R2
LCLK_N
• SCLK (system clock). Provides clock input for the
external bus interface and defines the ac specification
reference for the external bus signals. The external bus
interface runs at 1× the SCLK frequency. A DLL locks
internal SCLK to SCLK input. The maximum SCLK
frequency is the minimum of either 100 MHz or
CCLK/2, where CCLK is the internal DSP clock frequency. SCLK must be connected to the same clock
source as LCLK.
C2
VSS
R1: 2k⍀ SERIES RESISTOR
R2: 1.67k⍀ SERIES RESISTOR
C1: 1␮F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
Figure 5. VREF, SCLK_N, and LCLK_N Filter
Development Tools
The ADSP-TS101S is supported with a complete set of
CROSSCORE™ software and hardware development tools,
including Analog Devices emulators and VisualDSP++™ development environment. The same emulator hardware that
supports other TigerSHARC DSPs also fully emulates the
ADSP-TS101S.
• LCLK (local clock). Provides clock input to the internal
clock driver, CCLK, which is the internal clock for the
core, internal buses, memory, and link ports. The instruction execution rate is equal to CCLK. A PLL from LCLK
generates CCLK which is phase-locked. The LCLKRAT
pins define the clock multiplication of LCLK to CCLK
(see Table 4 on Page 12). The link port clock is generated
from CCLK via a software programmable divisor.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural
features that improve the efficiency of compiled C/C++ code.
RESET must be asserted until LCLK is stable and within
specification for at least 2 ms. This applies to power-up
as well as any dynamic modification of LCLK after powerup. Dynamic modification may include LCLK going out
of specification as long as RESET is asserted.
Connecting SCLK and LCLK to the same clock source is a
requirement for the device. Using an integer clock multiplication value provides predictable cycle-by-cycle operation, a
requirement of fault-tolerant systems and some multiprocessing systems.
The VisualDSP++ debugger has a number of important features.
Data visualization is enhanced by a plotting package that offers
a significant level of flexibility. This graphical representation of
user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this
capability can have increasing significance on the designer’s
development schedule, increasing productivity. Statistical
profiling enables the programmer to nonintrusively poll the
processor as it is running the program. This feature, unique to
VisualDSP++, enables the software developer to passively gather
important code execution metrics without interrupting the
realtime characteristics of the program. Essentially, the developer
can identify bottlenecks in software quickly and efficiently. By
using the profiler, the programmer can focus on those areas in
the program that impact performance and take corrective action.
Power Supplies
The ADSP-TS101S has separate power supply connections for
internal logic (VDD), analog circuits (VDD_A), and I/O buffer
(VDD_IO) power supply. The internal (VDD) and analog (VDD_A)
supplies must meet the 1.2 V requirement. The I/O buffer
(VDD_IO) supply must meet the 3.3 V requirement.
The analog supply (VDD_A) powers the clock generator PLLs. To
produce a stable clock, systems must provide a clean power
supply to power input VDD_A. Designs must pay critical attention
to bypassing the VDD_A supply.
CROSSCORE is a trademark of Analog Devices, Inc.
VisualDSP++ is a trademark of Analog Devices, Inc.
REV. 0
C1
–9–
ADSP-TS101S
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
different areas of the DSP or external memory with the drag of
the mouse, examine run time stack and heap usage. The Expert
Linker is fully compatible with existing Linker Definition File
(LDF), allowing the developer to move between the graphical
and textual environments.
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program
execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the TigerSHARC processor family. Hardware
tools include TigerSHARC DSP PC plug-in cards. Third party
software tools include DSP libraries, real time operating systems,
and block diagram design tools.
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permit programmers to:
Designing an Emulator-Compatible DSP
Board (Target)
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory
and timing constraints of DSP programming. These capabilities
enable engineers to develop code more effectively, eliminating the
need to start from the very beginning, when developing new
application code. The VDK features include Threads, Critical
and Unscheduled regions, Semaphores, Events, and Device flags.
The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the
VDK was designed to be scalable. If the application does not use
a specific feature, the support code for that feature is excluded
from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system
state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization
in a color-coded graphical form, easily move code and data to
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-TS101S processor to monitor and
control the target board processor during emulation. The
emulator provides full speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
The Analog Devices family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test
Access Port (TAP) on each JTAG DSP. The emulator uses the
TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be halted
to send data and commands, but once an operation has been
completed by the emulator, the DSP system is set running at full
speed with no impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in Figure 6. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
square post header, set on 0.1" ⴛ 0.1" spacing, with a minimum
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.
As can be seen in Figure 6, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,
TDO, TRST, and EMU used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and BTRST that are optionally used for boardlevel (boundary scan) testing.
–10–
REV. 0
ADSP-TS101S
1
2
3
4
5
6
7
8
9
10
GND
KEY (NO PIN)
EMU
should contain no components (chips, resistors, capacitors, and
so on). The dimensions are referenced to the center of the 0.25"
square post pin.
GND
TMS
BTMS
BTCK
TCK
BTRST
0.64"
TRST
9
11
12
13
14
BTDI
TDI
GND
0.88"
0.24"
TDO
Figure 8. JTAG Pod Connector Dimensions
TOP VIEW
Figure 6. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in Place)
0.10"
When the emulator is not connected to this header, place jumpers
across BTMS, BTCK, BTRST, and BTDI as shown in Figure 7.
These jumpers hold the JTAG signals in the correct state to allow
the DSP to run free. Remove all the jumpers when connecting
the emulator to the JTAG header.
0. 15"
Figure 9. JTAG Pod Connector Keep-Out Area
Design for Emulation Circuit Information
GND
1
2
3
4
EMU
GND
KEY (NO PIN)
5
6
BTMS
TMS
7
8
9
10
BTCK
For details on target board design issues including single
processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68:
Analog Devices JTAG Emulation Technical Reference on the Analog
Devices website (www.analog.com)—use site search on
“EE-68”. This document is updated regularly to keep pace
with improvements to emulator support.
TCK
Additional Information
BTRST
9
11
12
BTDI
GND
TRST
TDI
13
14
TDO
TOP VIEW
This data sheet provides a general overview of the ADSP-TS101S
DSP’s architecture and functionality. For detailed information
on the ADSP-TS101S DSP’s core architecture and instruction
set, see the TigerSHARC DSP Hardware Specification and the
TigerSHARC DSP Instruction Set Specification. For detailed information on the development tools for this processor, see the
VisualDSP++ User’s Guide for TigerSHARC DSP.
PIN FUNCTION DESCRIPTIONS
Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
JTAG Emulator Pod Connector
Figure 8 details the dimensions of the JTAG pod connector at the
14-pin target end. Figure 9 displays the keep-out area for a target
board header. The keep-out area allows the pod connector to
properly seat onto the target board header. This board area
REV. 0
While most of the ADSP-TS101S DSP’s input pins are normally
synchronous—tied to a specific clock—a few are asynchronous.
For these asynchronous signals, an on-chip synchronization
circuit prevents metastability problems. The ac specification for
asynchronous signals is used only when predictable cycle-bycycle behavior is required.
–11–
ADSP-TS101S
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these pins
to get to their internal pull-up or pull-down state. Some output
pins (control signals) have a pull-up or pull-down that maintains
a known value during transitions between different drivers.
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Description
LCLK_N
I
Local Clock Reference. Connect this pin to VREF as shown in Figure 5.
LCLK_P
I
Local Clock Input. DSP clock input. The instruction cycle rate = n × LCLK, where n
is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. See Clock Domains on Page 9.
LCLKRAT2–01
I (pd2)
LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n × LCLK, where n is
user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These pins must
have a constant value while the DSP is powered.
SCLK_N
I
System Clock Reference. Connect this pin to VREF as shown in Figure 5.
SCLK_P
I
System Clock Input. The DSP’s system input clock for cluster bus. This pin must be
connected to the same clock source as LCLK_P. See Clock Domains on Page 9.
SCLKFREQ3
I (pu2)
SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must have a
constant value while the DSP is powered.
RESET
I/A
Reset. Sets the DSP to a known state and causes program to be in idle state. RESET
must be asserted at specified time according to the type of reset operation. For details,
see Reset and Booting on Page 8.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Electrical Characteristics on Page 20.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2 See
Table 4. LCLK Ratio
LCLKRAT2–0
Ratio
000
001
010
011
100
101
110
111
2
2.5
3
3.5
4
5
6
Reserved
(default)
–12–
REV. 0
ADSP-TS101S
Table 5. Pin Definitions—External Port Bus Controls
Signal
Type
Description
ADDR31–01
I/O/T
Address Bus. The DSP issues addresses for accessing memory and peripherals on these
pins. In a multiprocessor system, the bus master drives addresses for accessing internal
memory or I/O processor registers of other ADSP-TS101S DSPs. The DSP inputs
addresses when a host or another DSP accesses its internal memory or I/O processor
registers.
DATA63–01
I/O/T
External Data Bus. The DSP drives and receives data and instructions on these pins.
I/O/T
(pu3)
Memory Read. RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave, RD is an input and indicates read
transactions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives RD. The RD pin changes concurrently with ADDR pins.
WRL2
I/O/T
(pu3)
Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to an even
address word of external memory or to another external bus agent; and when the
ADSP-TS101S writes to a 32-bit zone (host, memory, or DSP programmed to 32-bit
bus). An external master (host or DSP) asserts WRL for writing to a DSP’s low word
of internal memory. In a multiprocessor system, the bus master drives WRL. The WRL
pin changes concurrently with ADDR pins. When the DSP is a slave, WRL is an input
and indicates write transactions that access its internal memory or universal registers.
WRH2
I/O/T
(pu3)
Write High. WRH is asserted when the ADSP-TS101S writes a long word (64 bits)
or writes to an odd address word of external memory or to another external bus agent
on a 64-bit data bus. An external master (host or another DSP) must assert WRH for
writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system, the bus
master drives WRH. The WRH pin changes concurrently with ADDR pins. When the
DSP is a slave, WRH is an input and indicates write transactions that access its internal
memory or universal registers.
ACK
I/O/T
Acknowledge. External slave devices can deassert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data phase. The DSP can deassert ACK to add wait states to read accesses
of its internal memory. The ADSP-TS101S does not drive ACK during slave writes.
Therefore, an external (approximately 10 kΩ) pull-up is required.
BMS2, 4
O/T
(pu/pd3)
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. When the
DSP is configured to boot from EPROM, BMS is active during the boot sequence.
Pull-down enabled during RESET (asserted); pull-up enabled after RESET
(deasserted). In a multiprocessor system, the DSP bus master drives BMS. For details
see Reset and Booting on Page 8 and the EBOOT signal description in Table 16 on
Page 19.
RD
2
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
REV. 0
–13–
ADSP-TS101S
Table 5. Pin Definitions—External Port Bus Controls (continued)
Signal
Type
Description
MS1–02
O/T (pu3)
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks
0 or 1, respectively. MS1–0 are decoded memory address pins that change concurrently
with ADDR pins. When ADDR31:26 = 0b000010, MS0 is asserted. When
ADDR31:26 = 0b000011, MS1 is asserted. In multiprocessor systems, the master
DSP drives MS1–0.
MSH2
O/T (pu3)
Memory Select Host. MSH is asserted whenever the DSP accesses the host address
space (ADDR31:28 ≠ 0b0000). MSH is a decoded memory address pin that changes
concurrently with ADDR pins. In a multiprocessor system, the bus master DSP
drives MSH.
BRST2
I/O/T
(pu3)
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automatically while BRST is asserted.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
address and data buses may float for several cycles during bus mastership transitions between a TigerSHARC DSP and a host. Floating in this case
means that these inputs are not driven by any source and that dc-biased terminations are not present. It is not necessary to add pull-ups as there are no
reliability issues and the worst-case power consumption for these floating inputs is negligible. Unconnected address pins may require pull-ups or pulldowns to avoid erroneous slave accesses, depending on the system. Unconnected data pins may be left floating.
2 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
3 See Electrical Characteristics on Page 20.
4 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 6. Pin Definitions—External Port Arbitration
Signal
Type
Description
BR7–0
I/O
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to
arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the
value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight
DSPs, set the unused BRx pins high.
ID2–01
I (pd2)
Multiprocessor ID. Indicates the DSP’s ID. From the ID, the DSP determines its order
in a multiprocessor system. These pins also indicate to the DSP which bus request
(BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,
011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a
constant value during system operation and can change during reset only.
BM1
O (pd2)
Bus Master. The current bus master DSP asserts BM. For debugging only. At reset
this is a strap pin. For more information, see Table 16 on Page 19.
BOFF
I
Back Off. A deadlock situation can occur when the host and a DSP try to read from
each other’s bus at the same time. When deadlock occurs, the host can assert BOFF
to force the DSP to relinquish the bus before completing its outstanding transaction.
BUSLOCK3
O/T (pu2)
Bus Lock Indication. Provides an indication that the current bus master has locked
the bus.
HBR
I
Host Bus Request. A host must assert HBR to request control of the DSP’s external
bus. When HBR is asserted in a multiprocessing system, the bus master relinquishes
the bus and asserts HBG once the outstanding transaction is finished.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
–14–
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ADSP-TS101S
Table 6. Pin Definitions—External Port Arbitration (continued)
Signal
Type
Description
HBG3
I/O/T
(pu2)
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master DSP three-states the
ADDR31–0, DATA63–0, MSH, MSSD, MS1–0, RD, WRL, WRH, BMS, BRST,
FLYBY, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM and HDQM pins, and
the DSP puts the SDRAM in self-refresh mode. The DSP asserts HBG until the host
deasserts HBR. In multiprocessor systems, the current bus master DSP drives HBG,
and all slave DSPs monitor HBG.
CPA
I/O (o/d)
Core Priority Access. Asserted while the DSP’s core accesses external memory. This
pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and
gain control of the external bus for core-initiated transactions. CPA is an open drain
output, connected to all DSPs in the system. The CPA pin has an internal 500 Ω pullup resistor, which is only enabled on the DSP with ID2–0 = 0. If not required in the
system, leave CPA unconnected (external pull-ups will be required for ID1–ID7).
DPA
I/O (o/d)
DMA Priority Access. Asserted while a high priority DSP DMA channel accesses
external memory. This pin enables a high priority DMA channel on a slave DSP to
interrupt transfers of a normal priority DMA channel on a master DSP and gain
control of the external bus for DMA-initiated transactions. DPA is an open drain
output, connected to all DSPs in the system. The DPA pin has an internal 500 Ω
pull-up resistor, which is only enabled on the DSP with ID2–0 = 0. If not required
in the system, leave DPA unconnected (external pull-ups will be required for IDs 1
through 7).
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Electrical Characteristics on Page 20.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2 See
Table 7. Pin Definitions—External Port DMA/Flyby
Signal
Type
Description
DMAR3–0
I/A
DMA Request Pins. Enable external I/O devices to request DMA services from the
DSP. In response to DMARx, the DSP performs DMA transfers according to the
DMA channel’s initialization. The DSP ignores DMA requests from uninitialized
channels.
FLYBY1
O/T (pu2 )
Flyby Mode. When a DSP DMA channel is initiated in FLYBY mode, it generates
flyby transactions on the external bus. During flyby transactions, the DSP asserts
FLYBY, which signals the source or destination I/O device to latch the next data or
strobe the current data, respectively, and to prepare for the next data on the next cycle.
IOEN1
O/T (pu2)
I/O Device Output Enable. Enables the output buffers of an external I/O device for
flyby transactions between the device and external memory. Active on flyby
transactions.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd= Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
2 See
internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Electrical Characteristics on Page 20.
REV. 0
–15–
ADSP-TS101S
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Description
MSSD1
I/O/T
(pu2)
Memory Select SDRAM. MSSD is asserted whenever the DSP accesses SDRAM
memory space. MSSD is a decoded memory address pin that is asserted whenever the
DSP issues an SDRAM command cycle (access to ADDR31:26 = 0b000001). In a
multiprocessor system, the master DSP drives MSSD.
RAS1
I/O/T
(pu2)
Row Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, RAS defines the type of
operation to execute according to SDRAM specification.
CAS1
I/O/T
(pu2)
Column Address Select. When sampled low, CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, CAS defines the type
of operation to execute according to the SDRAM specification.
LDQM1
O/T (pu2)
Low Word SDRAM Data Mask. When LDQM sampled high, the DSP three-states
the SDRAM DQ buffers. LDQM is valid on SDRAM transactions when CAS is
asserted and is inactive on read transactions. On write transactions, LDQM is active
when accessing an odd address word on a 64-bit memory bus to disable the write of
the low word.
HDQM1
O/T (pu2)
High Word SDRAM Data Mask. When HDQM sampled high, the DSP three-states
the SDRAM DQ buffers. HDQM is valid on SDRAM transactions when CAS is
asserted and is inactive on read transactions. On write transactions, HDQM is active
when accessing an even address in word accesses or is active when memory is
configured for a 32-bit bus to disable the write of the high word.
SDA101
O/T (pu2)
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation
while the DSP executes non-SDRAM transactions.
SDCKE1, 3
I/O/T
(pu/pd2)
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or
suspend modes. A slave DSP in a multiprocessor system does not have the pull-up or
pull-down. A master DSP (or ID=0 in a single processor system) has a 100 kΩ pullup before granting the bus to the host, except when the SDRAM is put in self-refresh
mode. In self-refresh mode, the master has a 100 kΩ pull-down before granting the
bus to the host.
SDWE1
I/O/T
(pu2)
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation
to execute according to SDRAM specification.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Electrical Characteristics on Page 20.
3 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
2 See
Table 9. Pin Definitions—JTAG Port
Signal
Type
Description
EMU
O (o/d)
Emulation. Connected to the DSP’s JTAG emulator target board connector only.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
TDI1
2
I (pu )
Test Data Input (JTAG). A serial data input of the scan path.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
–16–
REV. 0
ADSP-TS101S
Table 9. Pin Definitions—JTAG Port (continued)
Signal
Type
Description
TDO
O/T
Test Data Output (JTAG). A serial data output of the scan path.
TMS1
TRST
I
1
(pu2)
Test Mode Select (JTAG). Used to control the test state machine.
2
I/A (pu )
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed
low after power-up for proper device operation. For more information, see Reset and
Booting on Page 8.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
2 See
internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Electrical Characteristics on Page 20.
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal
Type
Description
FLAG3–01
I/O/A
(pd2)
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each
pin can be configured individually for input or for output. FLAG3–0 are inputs after
power-up and reset.
IRQ3–03
I/A
(pu2)
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0
pins can be independently set for edge triggered or level sensitive operation. After reset,
these pins are disabled unless the IRQ3–0 strap option is initialized for booting.
TMR0E1
O (pd2)
Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0 expires.
At reset this is a strap pin. For more information, see Table 16 on Page 19.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The
internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Electrical Characteristics on Page 20.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2 See
Table 11. Pin Definitions—Link Ports
Signal
Type
Description
L0DAT7–01
I/O
Link0 Data 7–0
L1DAT7–01
I/O
Link1 Data 7–0
1
I/O
Link2 Data 7–0
L3DAT7–01
I/O
Link3 Data 7–0
L0CLKOUT
O
Link0 Clock/Acknowledge Output
L1CLKOUT
O
Link1 Clock/Acknowledge Output
L2CLKOUT
O
Link2 Clock/Acknowledge Output
L3CLKOUT
O
Link3 Clock/Acknowledge Output
L0CLKIN
I/A
Link0 Clock/Acknowledge Input
L1CLKIN
I/A
Link1 Clock/Acknowledge Input
L2CLKIN
I/A
Link2 Clock/Acknowledge Input
L3CLKIN
I/A
Link3 Clock/Acknowledge Input
L0DIR
O
Link0 Direction. (0 = input, 1 = output)
L2DAT7–0
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
REV. 0
–17–
ADSP-TS101S
Table 11. Pin Definitions—Link Ports (continued)
Signal
Type
Description
L1DIR
O
Link1 Direction. (0 = input, 1 = output)
L2DIR2
(pd3)
O
L3DIR
O (pd3)
Link2 Direction. (0 = input, 1 = output)
At reset this is a strap pin. For more information, see Table 16 on Page 19.
Link3 Direction. (0 = input, 1 = output)
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
1 The link port data pins, if connected or floated for extended periods (for example, token slave with no token master), do not require pull-ups or pull-downs
as there are no reliability issues and the worst-case power consumption for these floating inputs is negligible. Floating in this case means that these inputs
are not driven by any source and that dc-biased terminations are not present.
2 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
3 See Electrical Characteristics on Page 20.
Table 12. Pin Definitions—Impedance and Drive Strength Control
Signal
Type
Description
CONTROLIMP2–11 I (pu3)
CONTROLIMP02
I (pd3)
Impedance Control. For ADC (Address/Data/Controls) and LINK (all link port
outputs) signals, the CONTROLIMP2–0 pins control impedance as shown in Table 13.
These pins enable or disable dig_ctrl mode. When dig_ctrl:
0 = Disabled (maximum drive strength)
1 = Enabled (use DS2–0 drive strength selection)
DS2–01
Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength
calculation, see Output Drive Currents on Page 28.
I (pu3)
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 kΩ; pu = internal pull-up approximately 100 kΩ; T = three-state
1 The
internal pull-up may not be sufficient. A stronger pull-up may be necessary.
internal pull-down may not be sufficient. A stronger pull-down may be necessary.
3 See Electrical Characteristics on Page 20.
2 The
Table 13. Control Impedance Selection
CONTROLIMP2–0
ADC
dig_ctrl
LINK
dig_ctrl
000
001
010
011
100
101
110 (default)
111
0
0
0
reserved
1
reserved
1
reserved
0
0
1
reserved
0
reserved
1
reserved
Table 14. Drive Strength Selection
DS2–0
Drive Strength
000
001
010
011
100
101
110
111 (default)
Strength 0
Strength 1
Strength 2
Strength 3
Strength 4
Strength 5
Strength 6
Strength 7
–18–
REV. 0
ADSP-TS101S
Table 15. Pin Definitions—Power, Ground, and Reference
Signal
Type
Description
VDD
P
VDD pins for internal logic.
VDD_A
P
VDD pins for analog circuits. Pay critical attention to bypassing this supply.
VDD_IO
P
VDD pins for I/O buffers.
VREF
I
Reference voltage defines the trip point for all input buffers, except RESET, IRQ3–0,
DMAR3–0, ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and TRST. The value is
1.5 V ± 100 mV (which is the TTL trip point). VREF can be connected to a power supply
or set by a voltage divider circuit. The voltage divider should have an HF decoupling
capacitor (1 nF HF SMD) connected to VSS. Tie the decoupling capacitor between VREF
input and VSS, as close to the DSP’s pins as possible. See Filtering Reference Voltage
and Clocks on Page 9.
VSS
G
Ground pins.
VSS_A
G
Ground pins for analog circuits.
A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an approximately 100 kΩ pull-down
for the default value. If a strap pin is not connected to an external
pull-up or logic load, the DSP samples the default value during
reset. If strap pins are connected to logic inputs, a stronger
external pull-down may be required to ensure default value
depending on leakage and/or low level input current of the logic
load. To set a mode other than the default mode, connect the
strap pin to a sufficiently stronger external pull-up. Table 16 lists
and describes each of the DSP’s strap pins.
Table 16. Pin Definitions—I/O Strap Pins
Signal
On Pin…
Description
EBOOT
BMS
EPROM boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP through the
external port or a link port
IRQEN
BM
Interrupt Enable.
0 = disable and set IRQ3–0 interrupts to level sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to edge sensitive immediately after reset
TM1
L2DIR
Test Mode 1.
0 = required setting during reset.
1 = reserved.
TM2
TMR0E
Test Mode 2.
0 = required setting during reset.
1 = reserved.
REV. 0
–19–
ADSP-TS101S
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Test Conditions
Min
Typ
Max
Unit
1.26
V
VDD
Internal Supply Voltage
1.14
VDD_A
Analog Supply Voltage
1.14
1.26
V
VDD_IO
I/O Supply Voltage
3.15
3.45
V
TCASE
Case Operating Temperature
–40
+85
ºC
@ VDD, VDD_IO = max
2
VDD_IO + 0.5 V
@ VDD, VDD_IO = min
–0.5
+0.8
1
VIH
High Level Input Voltage
VIL
Low Level Input Voltage1
IDD
VDD Supply Current for Typical @ CCLK = 250 MHz,
Activity2
VDD = 1.25 V, TCASE = 25ºC
1.2
A
IDD_IO
VDD_IO Supply Current for
Typical Activity2
137
mA
VREF
Voltage reference
@ SCLK = 100 MHz,
VDD_IO = 3.3 V, TCASE = 25ºC
1.4
1.6
V
V
Specifications subject to change without notice.
1 Applies
2 For
to input and bidirectional pins.
details on Typical Activity used for these measurements, see EE-169, Estimating Power for the ADSP-TS101S.
ELECTRICAL CHARACTERISTICS
Parameter
VOH
High Level Output Voltage1
1
Test Conditions
Min
@VDD_IO = min, IOH = –2 mA
2.4
Max
Unit
V
VOL
Low Level Output Voltage
@VDD_IO = min, IOL = 4 mA
0.4
V
IIH
High Level Input Current2
@VDD_IO = max, VIN = VDD_IO max
10
µA
IIHP
High Level Input Current (pd)3
@VDD_IO = max, VIN = VDD_IO max
44.5
µA
Current4
IIL
Low Level Input
IILP
Low Level Input Current (pu)5
IOZH
Three-State Leakage Current High6, 7
@VDD_IO = max, VIN = 0 V
@VDD_IO = max, VIN = 0 V
Three-State Leakage Current High (pd)
IOZL
Three-State Leakage Current Low9
IOZLP
Three-State Leakage Current Low (pu)10 @VDD_IO = max, VIN = 0 V
IOZLO
Three-State Leakage Current Low
Input Capacitance11, 12
–69
@VDD_IO = max, VIN = VDD_IO max
8
IOZHP
CIN
17.2
(od)7
@VDD_IO = max, VIN = VDD_IO max
17.2
@VDD_IO = max, VIN = 0 V
@VDD_IO = max, VIN = 0 V
@fIN = 1 MHz, TCASE = 25C, VIN = 2.5 V
–69
–9.8
10
µA
–23
µA
10
µA
44.5
µA
10
µA
–23
µA
–4.6
µA
5
pF
Specifications subject to change without notice.
1 Applies
to output and bidirectional pins.
to input pins without internal pull-downs (pd).
3 Applies to input pins with internal pull-downs (pd).
4 Applies to input pins without internal pull-ups (pu).
5 Applies to input pins with internal pull-ups (pu).
6 Applies to three-stateable pins without internal pull-downs (pd).
7 Applies to open drain (od) pins with 500 Ω pull-ups (pu).
8 Applies to three-stateable pins with internal pull-downs (pd).
9 Applies to three-stateable pins without internal pull-ups (pu).
10Applies to three-stateable pins with internal pull-ups (pu).
11Applies to all signals.
12Guaranteed but not tested.
2 Applies
–20–
REV. 0
ADSP-TS101S
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDD)1 . . . –0.3 V to +1.40 V
Analog (PLL) Supply Voltage (VDD_A)1 . . –0.3 V to +1.40 V
External (I/O) Supply Voltage (VDD_IO)1 . . . –0.3 V to +4.6 V
Input Voltage1 . . . . . . . . . . . . . . . . . –0.5 V to VDD_IO +0.5 V
Output Voltage Swing1 . . . . . . . . . . –0.5 V to VDD_IO +0.5 V
Storage Temperature Range1 . . . . . . . . . . . –65ºC to +150ºC
1 Stresses
greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-TS101S features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. 0
–21–
ADSP-TS101S
TIMING SPECIFICATIONS
With the exception of Link port, DMAR3–0, and IRQ3–0 pins,
all ac timing for the ADSP-TS101S is relative to a reference clock
edge. Because input setup/hold, output valid/hold, and output
enable/disable times are relative to a clock edge, the timing data
for the ADSP-TS101S has few calculated (formula-based)
values. For information on ac timing, see General AC Timing on
Page 22. For information on link port transfer timing, see Link
Ports Data Transfer and Token Switch Timing on Page 25.
General AC Timing
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 10 on Page 24. All delays (in nanoseconds)
are measured between the point that the first signal reaches 1.5 V
and the point that the second signal reaches 1.5 V.
The ac asynchronous timing data for the IRQ3–0 and DMAR3–0
pins appears in Table 17.
The general ac timing data appears in Table 18 and Table 19.
All ac specifications are measured with the load specified in
Figure 25 on Page 30, and with the output drive strength set to
strength 4. In order to calculate the output valid and hold times
for different load conditions and/or output drive strengths, refer
to Figure 26 on Page 30 through Figure 33 on Page 31 (Rise and
Fall Time vs. Load Capacitance) and Figure 34 on Page 31
(Output Valid vs. Load Capacitance vs. Drive Strength).
Table 17. AC Asynchronous Signal Specifications (all values in this table are in nanoseconds)
Name
IRQ3–01
DMAR3–0
1
TMR0E
FLAGS3–0
1, 2
TRST
Description
Pulsewidth Low (min)
Pulsewidth High (min)
Interrupt request input
tCCLK + 3 ns
–
DMA request output
tCCLK + 4 ns
tCCLK + 4 ns
Timer 0 expired output
–
4 × tSCLK ns
Flag pins input
3 × tCCLK ns
3 × tCCLK ns
JTAG test reset input
1 ns
–
1 These
2 For
input pins do not need to be synchronized to a clock reference.
output specifications, see Table 19.
Table 18. Reference Clocks
Input
Clock
Clock
Clock
Skew to Jitter1
Cycle
High
Low
LCLK
Tolerance
Max (ns) Min (ns) Min (ns) Max (ps) (ps)
Type
Description
Speed Clock
Grade Cycle
(MHz) Min (ns)
–
Core Clock
250
4.0
12.5
Input Local Clock
250
CR × 4.0
CR × 12.5
SCLK_P5, 7, 8
Input System Clock,
SCLKFREQ = 1
All
Greater of 10 20
or CCLK × 2
TCK9
Input Test Clock (JTAG) All
Signal
CCLK2, 3
LCLK_P
4, 5, 6
Greater of 30 –
or CCLK × 4
–
–
–
–
{40% to 60%
Duty Cycle}
–
100
{40% to 60%
Duty Cycle}
50
100
–
–
12.5
12.5
1 Actual
input jitter should be combined with ac specifications for accurate timing analysis.
is the internal DSP clock or instruction cycle time. The period of this clock is equal to the Local Clock (LCLK_P) period divided by the Local
Clock Ratio (LCLKRAT2–0). For information on available internal DSP clock rates, see the ORDERING GUIDE on Page 40.
3 The period of CCLK is t
CCLK.
4 The Core Clock Ratio (CR) is 2, 2.5, 3, 3.5, 4, 5, or 6 as set by the LCLKRAT2–0 pins. For more information, see Table 4 on Page 12.
5 See Clock Domains on Page 9.
6 The period of LCLK is t
LCLK.
7 For more information, see Table 3 on Page 12.
8 The period of SCLK is t
SCLK.
9 The period of TCK is t
TCK.
2 CCLK
–22–
REV. 0
ADSP-TS101S
Description
Input Hold (min)
Output Valid (max)1
Output Hold (min)
Output Enable (min)2
Output Disable (max)2
ADDR31–0
DATA63–0
MSH
MSSD
MS1–0
RD
WRL
WRH
ACK
SDCKE
RAS
CAS
SDWE
LDQM
HDQM
SDA10
HBR
HBG
BOFF
BUSLOCK
BRST
BR7–0
FLYBY
IOEN
CPA 3, 4
DPA 3, 4
BMS5
FLAG3–06
TMR0E5
RESET4, 7
TMS4
TDI4
TDO
TRST4, 7, 9
BM5
EMU10
External Address Bus
External Data Bus
Memory Select HOST Line
Memory Select SDRAM Line
Memory Select for Static Blocks
Memory Read
Write Low Word
Write High Word
Acknowledge for Data
SDRAM Clock Enable
Row Address Select
Column Address Select
SDRAM Write Enable
Low Word SDRAM Data Mask
High Word SDRAM Data Mask
SDRAM ADDR10
Host Bus Request
Host Bus Grant
Back Off Request
Bus Lock
Burst pin
Multiprocessing Bus Request pins
FLYBY pin
FLYBY pin
Core Priority Access
DMA Priority Access
Boot Memory Select
FLAG pins
Timer 0 Expired
Global Reset pin
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Data Output (JTAG)
Test Reset (JTAG)
Bus Master Debug aid only
Emulation
2.2
2.2
—
2.2
—
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
—
—
—
2.2
2.2
2.2
—
2.2
2.2
—
—
2.2
2.2
—
—
—
—
1.5
1.5
—
—
—
—
0.5
0.5
—
0.5
—
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
0.5
0.5
0.5
—
0.5
0.5
—
—
0.5
0.5
—
—
—
—
1.0
1.0
—
—
—
—
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
—
4.2
—
4.2
4.2
4.2
4.2
4.2
5.8
5.8
4.2
4.2
4.2
—
—
—
6.0
—
4.2
5.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
1.0
—
1.0
1.0
1.0
1.0
1.0
—
—
1.0
1.0
1.0
—
—
—
1.0
—
1.0
—
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
—
0.9
—
0.9
0.9
—
0.9
0.9
—
—
0.9
1.0
—
—
—
—
1.0
—
—
—
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
—
2.5
—
2.5
2.5
—
2.5
2.5
2.5
2.5
2.5
4.0
—
—
—
—
5.0
—
—
5.0
JTAG_SYS_IN11
JTAG_SYS_OUT12
ID2–09
CONTROLIMP2–09
System input
System output
Chip ID – must be constant
Static pins – must be constant
1.5
—
—
—
11.0
—
—
—
—
16.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REV. 0
–23–
Reference Clock
Name
Input Setup (min)
Table 19. AC Signal Specifications—All values in this table are in nanoseconds.
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
TCK
TCK
TCK_FE8
TCK
SCLK
TCK or
LCLK
TCK
TCK_FE8
—
—
ADSP-TS101S
DS2–0
LCLKRAT2–09
SCLKFREQ9
Static pins – must be constant
Static pins – must be constant
Static pins – must be constant
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reference Clock
Output Disable (max)2
Output Enable (min)2
Output Hold (min)
Output Valid (max)1
Description
9
Input Hold (min)
Name
Input Setup (min)
Table 19. AC Signal Specifications—All values in this table are in nanoseconds. (continued)
—
—
—
1 The
output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive
loading, see Figure 34 on Page 31.
2 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus
contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.
3 CPA and DPA pins are open drains and have 0.5 kΩ internal pull-ups.
4 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for
recognition in the current clock reference cycle.
5 This pin is a strap option. During reset, an internal resistor pulls the pin low.
6 For input specifications, see Table 17.
7 For additional requirement details, see Reset and Booting on Page 8.
8 TCK_FE indicates TCK falling edge.
9 These pins may change only during reset; recommend connecting it to V
DD_IO/VSS.
10Reference clock depends on function.
11System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE,
CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN,
L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0, CONTROLIMP2–0, RESET, DMAR3–0.
12System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD,
SDCKE, SDWE, CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0,
L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT, L3DAT7–0, L3DIR, EMU.
REFERENCE
CLOCK
1.5V
INPUT
SIGNAL
1.5V
INPUT
SETUP
INPUT
HOLD
OUTPUT
SIGNAL
OUTPUT
VALID
OUTPUT
HOLD
1.5V
THREE-STATE
OUTPUT
DISABLE
OUTPUT
ENABLE
ASYNCHONOUS
INPUT OR
OUTPUT
SIGNAL
PULSEWIDTH
1.5V
Figure 10. General AC Parameters Timing
–24–
REV. 0
ADSP-TS101S
Link Ports Data Transfer and Token Switch Timing
Table 20, Table 21, Table 22, and Table 23 with Figure 11,
Figure 12, Figure 13, and Figure 14 provide the timing specifications for the link ports data transfer and token switch.
Table 20. Link Ports—Transmit
Parameter
Min
Timing Requirements
Connectivity Pulse Setup
tCONNS1
tCONNS2
Connectivity Pulse Setup
tCONNIW3
Connectivity Pulse Input Width
tACKS
Acknowledge Setup
Switching Characteristics
Transmit Link Clock Period
tLXCLK_TX4
tLXCLKH_TX1
Transmit Link Clock Width High
tLXCLKH_TX2
Transmit Link Clock Width High
tLXCLKL_TX1
Transmit Link Clock Width Low
Transmit Link Clock Width Low
tLXCLKL_TX2
tDIRS
LxDIR Transmit Setup
LxDIR Transmit Hold
tDIRH
tDOS1
LxDAT7–0 Output Setup
tDOH1
LxDAT7–0 Output Hold
tDOS2
LxDAT7–0 Output Setup
LxDAT7–0 Output Hold
tDOH2
tLDOE
LxDAT7–0 Output Enable
tLDOD5
LxDAT7–0 Output Disable
Max
Unit
2 × tCCLK + 3.5
8
tLXCLK_TX + 1
0.5 × tLXCLK_TX
ns
ns
ns
ns
0.9 × LR × tCCLK
0.33 × tLXCLK_TX
0.4 × tLXCLK_TX
0.33 × tLXCLK_TX
0.4 × tLXCLK_TX
0.5 × tLXCLK_TX
0.5 × tLXCLK_TX
0.25 × tLXCLK_TX – 1
0.25 × tLXCLK_TX – 1
0.17 × tLXCLK_TX – 1
0.17 × tLXCLK_TX – 1
1
1
1.1 × LR × tCCLK
0.66 × tLXCLK_TX
0.6 × tLXCLK_TX
0.66 × tLXCLK_TX
0.6 × tLXCLK_TX
2 × tLXCLK_TX
2 × tLXCLK_TX
1 The
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
formula for this parameter applies when LR is 2.
formula for this parameter applies when LR is 3, 4, or 8.
3 LxCLKIN shows the connectivity pulse with each of the three possible transitions to “Acknowledge.” After a connectivity pulse low minimum, LxCLKIN
may [1] return high and remain high for “Acknowledge,” [2] return high and subsequently go low (meeting tacks) for “Not Acknowledge,” or [3] remain
low for “Not Acknowledge.”
4 The Link clock Ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
5 This specification applies to the last data byte or the “Dummy” byte that follows the verification byte if enabled. For more information, see the TigerSHARC
DSP Hardware Specification.
2 The
tCONNS
tLxCLK_Tx
tDIRS
tDOH
tLxCLKH_Tx
tDOS
tDOS
0
tDOH
tLxCLKL_Tx
1
LxCLKOUT
tDIRH
tACKS
3
2
5
4
7
6
9
8
11
10
13
12
15
14
tCONNIW
LxCLKIN
tLDOD
tLDOE
LxDAT7–0
LxDIR
Figure 11. Link Ports—Transmit
REV. 0
–25–
ADSP-TS101S
Table 21. Link Ports—Receive
Parameter
Timing Requirements
Receive Link Clock Period
tLXCLK_RX1
tLXCLKH_RX2
Receive Link Clock Width High
tLXCLKH_RX3
Receive Link Clock Width High
tLXCLKL_RX2
Receive Link Clock Width Low
Receive Link Clock Width Low
tLXCLKL_RX3
tDIS
LxDAT7–0 Input Setup
tDIH
LxDAT7–0 Input Hold
Switching Characteristics
Connectivity Pulse Valid
tCONNV
Connectivity Pulse Output Width
tCONNOW
Min
Max
Unit
0.9 × LR × tCCLK
0.33 × tLXCLK_RX
0.4 × tLXCLK_RX
0.33 × tLXCLK_RX
0.4 × tLXCLK_RX
0.6
0.6
1.1 × LR × tCCLK
0.66 × tLXCLK_RX
0.6 × tLXCLK_RX
0.66 × tLXCLK_RX
0.6 × tLXCLK_RX
ns
ns
ns
ns
ns
ns
ns
0
1.5 × tLXCLK_RX
2.5 × tLXCLK_RX
ns
ns
1 The
link clock ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
formula for this parameter applies when LR is 2.
3 The formula for this parameter applies when LR is 3, 4, or 8.
2 The
tLxCLK_Rx
tDIS
tLxCLKL_Rx
1
LxCLKIN
0
3
5
2
4
tDIH
tDIH
tLxCLKH_Rx
tCONNV
tDIS
7
6
9
8
13
11
10
12
15
14
tCONNOW
LxCLKOUT
LxDAT7–0
LxDIR
Figure 12. Link Ports—Receive
Table 22. Link Ports—Token Switch, Token Master
Parameter
Min
Timing Requirements
Token Request Input Width
tREQI
tTKRQ
Token Request from Token Enable1
Switching Characteristics
Token Switch Enable Output
tTKENO
Token Request Output Width2
tREQO
1 For
Max
Unit
3.0 × tLXCLK_TX
ns
ns
5.0 × tLXCLK_RX
8.0 × tLXCLK_TX
6.0 × tLXCLK_TX
ns
ns
guaranteeing token switch during token enable.
2 LxCLKOUT shows both possible responses to the token request: [1] a “Token Grant” (LxCLKOUT remains high), and [2] a “Token Regret” (LxCLKOUT
goes low).
tTKENO
LxCLKOUT
tREQO
15
14
tTKRQ
tREQI
LxCLKIN
Figure 13. Link Ports—Token Switch, Token Master
–26–
REV. 0
ADSP-TS101S
Table 23. Link Ports—Token Switch, Token Requester
Parameter
Min
Timing Requirements
Token Switch Enable Input
tTKENI1
Switching Characteristics
Token Request Output Width2
tREQO
1 Required
Max
Unit
8.0 × tLXCLK_RX
ns
6.0 × tLXCLK_RX
ns
whenever there is a break in transmission.
2 LxCLKOUT shows both possible responses to the token request: [1] a “Token Grant” (LxCLKOUT remains high), and [2] a “Token Regret” (LxCLKOUT
goes low).
tTKENI
LxCLKIN
for token
regret
13
12
tREQO
15
14
tTKRQ
tREQO
LxCLKOUT
for token
regret
tTKENI
LxCLKIN
for token
grant 12
13
15
14
tTKRQ
tREQO
1
LxCLKOUT
for token grant
0
Figure 14. Link Ports—Token Switch, Token Requester
REV. 0
–27–
3
2
ADSP-TS101S
Output Drive Currents
Figure 15 through Figure 22 show typical I–V characteristics for
the output drivers of the ADSP-TS101S. The curves in these
diagrams represent the current drive capability of the output
drivers as a function of output voltage over the range of drive
strengths.
STRENGTH 2
80
IOL
SOURCE (VDD_IO) CURRENT – mA
60
STRENGTH 0
30
25
IOL
20
VDD_IO = 3.45V, –40°C
SOURCE (VDD_IO) CURRENT – mA
15
VDD_IO = 3.3V, +25°C
10
5
–5
20
VDD_IO = 3.3V, +25°C
–20
VDD_IO = 3.15V, +85°C
–40
–60
IOH
0
0.5
VDD_IO = 3.3V, +25°C
–10
VDD_IO = 3.45V, –40°C
VDD_IO = 3.15V, +85°C
0
–100
VDD_IO = 3.15V, +85°C
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
3.5
Figure 17. Typical Drive Currents at Strength 2
–15
–20
IOH
STRENGTH 3
–25
125
–30
0.5
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
3.5
Figure 15. Typical Drive Currents at Strength 0
STRENGTH 1
60
IOL
50
40
VDD_IO = 3.45V, –40°C
30
IOL
100
SOURCE (VDD_IO) CURRENT – mA
0
SOURCE (VDD_IO ) CURRENT – mA
VDD_IO = 3.3V, +25°C
–80
VDD_IO = 3.45V, –40°C
VDD_IO = 3.15V, +85°C
0
VDD_IO = 3.45V, –40°C
40
75
VDD_IO = 3.45V, –40°C
50
VDD_IO = 3.3V, +25°C
25
VDD_IO = 3.45V, –40°C
VDD_IO = 3.15V, +85°C
0
VDD_IO = 3.3V, +25°C
–25
VDD_IO = 3.15V, +85°C
–50
–75
VDD_IO = 3.3V, +25°C
20
IOH
–100
10
VDD_IO = 3.15V, +85°C
0
VDD_IO = 3.45V, –40°C
–125
0
0.5
VDD_IO = 3.3V, +25°C
–10
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
3.5
–20 V
DD_IO = 3.15V, +85°C
Figure 18. Typical Drive Currents at Strength 3
–30
–40
IOH
–50
STRENGTH 4
–60
140
–70
0.5
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
IOL
120
3.5
100
Figure 16. Typical Drive Currents at Strength 1
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry (IDD) and one due to the switching of external output
drivers (IDD_IO).
For details on internal and external power calculation issues
including: power vector definitions, current usage descriptions,
and formulas, see the EE-169: Estimating Power for the ADSPTS101S on the Analog Devices website—use site search on “EE169” (www.analog.com). This document is updated regularly to
keep pace with silicon revisions.
SOURCE (VDD_IO) CURRENT – mA
0
80
VDD_IO = 3.45V, –40°C
60
VDD_IO = 3.3V, +25°C
40
20
VDD_IO = 3.15V, +85°C
0
–20
VDD_IO = 3.45V, –40°C
VDD_IO = 3.3V, +25°C
–40
VDD_IO = 3.15V, +85°C
–60
–80
–100
–120
IOH
–140
–160
0
0.5
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
3.5
Figure 19. Typical Drive Currents at Strength 4
–28–
REV. 0
ADSP-TS101S
Test Conditions
STRENGTH 5
SOURCE (VDD_IO ) CURRENT – mA
160
140
IOL
120
100
80
VDD_IO = 3.45V, –40°C
The test conditions for timing parameters appearing in Table 19
on Page 23 include output disable time, output enable time, and
capacitive loading. The timing specifications for the DSP apply
for the voltage reference levels in Figure 23.
VDD_IO = 3.3V, +25°C
60
40
20
VDD_IO = 3.45V, –40°C
VDD_IO = 3.15V, +85°C
0
–20
–40
INPUT
OR
OUTPUT
1.5V
1.5V
VDD_IO = 3.3V, +25°C
–60
–80
–100
VDD_IO = 3.15V, +85°C
Figure 23. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
–120
–140
–160
IOH
–180
0
0.5
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
3.5
REFERENCE
SIGNAL
tMEASURED_DIS
Figure 20. Typical Drive Currents at Strength 5
tENA
tDIS
VOH (MEASURED)
VOH (MEASURED) – ⌬V
SOURCE (VDD_IO) CURRENT – mA
STRENGTH 6
180
160
140
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–220
tDECAY
OUTPUT STOPS
DRIVING
1.0V
tRAMP
OUTPUT STARTS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
VDD_IO = 3.45V, –40°C
VDD_IO = 3.15V, +85°C
VDD_IO = 3.3V, +25°C
Figure 24. Output Enable/Disable
VDD_IO = 3.15V, +85°C
Output Disable Time
IOH
0.5
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
3.0
3.5
Figure 21. Typical Drive Currents at Strength 6
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
following equation:
C L ∆V
t DECAY = --------------IL
STRENGTH 7
SOURCE (VDD_IO) CURRENT – mA
2.0V
VDD_IO = 3.45V, –40°C
VDD_IO = 3.3V, +25°C
0
220
200
180
160
140
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
–220
IOL
VDD_IO = 3.45V, –40°C
VDD_IO = 3.3V, +25°C
VDD_IO = 3.15V, +85°C
VDD_IO = 3.45V, –40°C
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The time for the voltage on the bus to ramp by ∆V is
dependent on the capacitive load, CL, and the drive current, ID.
This ramp time can be approximated by the following equation:
VDD_IO = 3.15V, +85°C
IOH
0.5
1.0
1.5
2.0
2.5
SOURCE (VDD_IO ) VOLTAGE – V
The output disable time tDIS is the difference between
tMEASURED_DIS and tDECAY as shown in Figure 24. The time
tMEASURED_DIS is the interval from when the reference signal
switches to when the output voltage decays ∆V from the
measured output high or output low voltage. The tDECAY value is
calculated with test loads CL and IL, and with ∆V equal to 0.5 V.
Output Enable Time
VDD_IO = 3.3V, +25°C
0
3.0
C L ∆V
t RAMP = --------------ID
3.5
Figure 22. Typical Drive Currents at Strength 7
REV. 0
VOL (MEASURED) + ⌬V
VOL (MEASURED)
IOL
tMEASURED_ENA
–29–
ADSP-TS101S
The output enable time tENA is the difference between
tMEASURED_ENA and tRAMP as shown in Figure 24. The time
tMEASURED_ENA is the interval from when the reference signal
switches to when the output voltage ramps ∆V from the measured
three-stated output level. The tRAMP value is calculated with test
load CL, drive current ID, and with ∆V equal to 0.5 V.
STRENGTH 1
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see Figure 25). The delay and hold specifications given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF. Figure 26
through Figure 33 show how output rise time varies with capacitance. Figure 34 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not apply
to output disable delays; see Output Disable Time on Page 29.)
The graphs of Figure 26 through Figure 34 may not be linear
outside the ranges shown.
RISE AND FALL TIMES – ns
25
(VDD_IO = 3.3V)
20
15
RISE TIME
10
y = 0.1349x + 1.9955
5
0
0
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE – pF
Figure 27. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 1
50⍀
TO
OUTPUT
PIN
1.5V
30pF
STRENGTH 2
RISE AND FALL TIMES – ns
25
Figure 25. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
STRENGTH 0
25
(VDD_IO = 3.3V)
RISE AND FALL TIMES – ns
FALL TIME
y = 0.1163x + 1.4058
(VDD_IO = 3.3V)
20
15
RISE TIME
10
y = 0.1304x + 0.8427
FALL TIME
y = 0.1144x + 0.7025
5
20
RISE TIME
15
0
y = 0.2015x + 3.8869
0
FALL TIME
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE – pF
y = 0.174x + 2.6931
10
Figure 28. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 2
5
0
0
10
20
30
40
50
60
70
80
90
100
STRENGTH 3
25
RISE AND FALL TIMES – ns
LOAD CAPACITANCE – pF
Figure 26. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 0
(VDD_IO = 3.3V)
20
15
RISE TIME
10
y = 0.1082x + 1.3123
FALL TIME
y = 0.0912x + 1.2048
5
0
0
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE – pF
Figure 29. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 3
–30–
REV. 0
ADSP-TS101S
STRENGTH 4
25
RISE AND FALL TIMES – ns
RISE AND FALL TIMES – ns
20
15
10
RISE TIME
y = 0.1071x + 0.9877
FALL TIME
5
20
30
40
50
60
70
80
90
20
15
10
RISE TIME
y = 0.0907x + 1.0071
FALL TIME
y = 0.09x + 0.3134
0
10
(VDD_IO = 3.3V)
5
y = 0.0798x + 1.0743
0
STRENGTH 7
25
(VDD_IO = 3.3V)
0
100
0
10
20
LOAD CAPACITANCE – pF
30
40
50
60
70
80
90
100
LOAD CAPACITANCE – pF
Figure 30. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 4
Figure 33. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 7
15
STRENGTH 5
25
STRENGTH 0–7
(VDD_IO = 3.3V)
0
20
OUTPUT VALID – ns
RISE AND FALL TIMES – ns
(VDD_IO = 3.3V)
15
10
RISE TIME
y = 0.1001x + 0.7763
10
1
2
3
4
5
5
6
FALL TIME
5
7
y = 0.0793x + 0.8691
0
0
10
20
30
40
50
60
70
80
90
0
100
0
LOAD CAPACITANCE – pF
STRENGTH 6
RISE AND FALL TIMES – ns
20
15
10
RISE TIME
y = 0.0946x + 1.2187
FALL TIME
5
y = 0.0906x + 0.4597
0
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE – pF
Figure 32. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 6
REV. 0
40
50
60
70
80
90
100
line equations for the output valid versus load capacitance are:
Strength 0: y = 0.0956x + 3.5662
Strength 1: y = 0.0523x + 3.2144
Strength 2: y = 0.0433x + 3.1319
Strength 3: y = 0.0391x + 2.9675
Strength 4: y = 0.0393x + 2.7653
Strength 5: y = 0.0373x + 2.6515
Strength 6: y = 0.0379x + 2.1206
Strength 7: y = 0.0399x + 1.9080
(VDD_IO = 3.3V)
10
30
Figure 34. Typical Output Valid (VDD_IO = 3.3 V) vs. Load
Capacitance at Max Case Temperature and Strength 0–71
1 The
0
20
LOAD CAPACITANCE – pF
Figure 31. Typical Output Rise and Fall Time (10%–90%,
VDD_IO = 3.3 V) vs. Load Capacitance at Strength 5
25
10
–31–
ADSP-TS101S
Environmental Conditions
The ADSP-TS101S is rated for performance over the extended
commercial temperature range, TCASE = –40°C to +85°C.
Thermal Characteristics
The ADSP-TS101S is packaged in a 19 mm × 19 mm and
27 mm × 27 mm Plastic Ball Grid Array (PBGA). The ADSPTS101S is specified for a case temperature (TCASE). To ensure
that the TCASE data sheet specification is not exceeded, a heat sink
and/or an air flow source may be used. See Table 24 and
Table 25 for thermal data.
Table 24. Thermal Characteristics
for 19 mm × 19 mm Package
Parameter
Condition
Typical
Unit
θJA1
Airflow2 = 0 m/s
16.6
°C/W
3
Airflow = 1 m/s
14.0
°C/W
3
Airflow = 2 m/s
12.9
°C/W
θJC
–
6.7
°C/W
θJB
–
5.8
°C/W
determination of θJA is system dependent and is based on a number
of factors including device power dissipation, package thermal resistance,
board thermal characteristics, ambient temperature, and air flow.
2 Per JEDEC JESD51-2 procedure using a four layer board (compliant with
JEDEC JESD51-9).
3 Per SEMI Test Method G38-87 using a four layer board (compliant with
JEDEC JESD51-9).
1 The
Table 25. Thermal Characteristics
for 27 mm × 27 mm Package
Parameter
Condition
Typical
Unit
θJA1
Airflow2 = 0 m/s
13.8
°C/W
3
Airflow = 1 m/s
11.7
°C/W
3
Airflow = 2 m/s
10.8
°C/W
θJC
–
3.1
°C/W
θJB
–
5.9
°C/W
determination of θJA is system dependent and is based on a number
of factors including device power dissipation, package thermal resistance,
board thermal characteristics, ambient temperature, and air flow.
2 Per JEDEC JESD51-2 procedure using a four layer board (compliant with
JEDEC JESD51-9).
3 Per SEMI Test Method G38-87 using a four layer board (compliant with
JEDEC JESD51-9).
1 The
–32–
REV. 0
ADSP-TS101S
484-BALL PBGA PIN CONFIGURATIONS
Table 26. 484-Ball (19 mm × 19 mm) PBGA Pin Assignments
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No. Mnemonic
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
VSS
DATA14
DATA11
DATA8
DATA4
DATA1
L0DIR
L0CLKIN
L0DAT6
L0DAT3
L0DAT1
VSS
LCLK_N
VSS_A
SCLK_N
SCLK_P
CONTROLIMP2
CONTROLIMP1
RESET
DMAR1
EMU
VSS
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
DATA21
DATA18
DATA12
DATA13
DATA7
DATA5
DATA2
NC
L0DAT7
L0DAT4
L0DAT0
VSS
VDD_A
VSS_A
VSS
DS1
CONTROLIMP0
DMAR2
DMAR0
TMS
TDI
IRQ1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
DATA23
DATA17
DATA15
DATA9
DATA10
DATA6
DATA3
DATA0
L0CLKOUT
L0DAT5
L0DAT2
LCLK_P
VSS
VDD_A
DS0
DS2
VREF
TRST
DMAR3
TCK
IRQ3
IRQ0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
DATA24
DATA19
DATA16
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD
VDD_IO
VDD
VDD_IO
TDO
IRQ2
LCLKRAT1
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
DATA25
DATA22
DATA20
VDD_IO
VDD
VDD
VDD_IO
VDD
VDD
VDD
VDD_IO
VDD
VDD_IO
VDD
VDD_IO
VDD
VDD_IO
VDD_IO
VDD_IO
BM
BMS
LCLKRAT2
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
DATA29
DATA30
DATA26
VDD_IO
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
LCLKRAT0
SCLKFREQ
TMR0E
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
L3DAT1
DATA28
DATA27
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
FLAG3
BUSLOCK
FLAG0
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
L3DAT2
L3DAT0
DATA31
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
VDD_IO
FLAG1
FLAG2
ID1
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
L3DAT5
L3DAT3
L3DAT4
VDD_IO
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
ID0
ID2
MSH
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L3CLKOUT
L3DAT7
L3DAT6
VDD_IO
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
IOEN
FLYBY
WRL
REV. 0
–33–
ADSP-TS101S
Table 26. 484-Ball (19 mm × 19 mm) PBGA Pin Assignments (continued)
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No. Mnemonic
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L3CLKIN
NC
L3DIR
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
VDD_IO
BRST
WRH
RD
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
L1DAT0
L1DAT2
L1DAT1
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
VDD
HDQM
MS0
MS1
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
L1DAT3
L1DAT5
L1DAT7
VDD_IO
VDD_IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
SDWE
MSSD
LDQM
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
L1DAT4
L1CLKOUT
L1CLKIN
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_IO
VDD_IO
ADDR31
RAS
SDCKE
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
L1DAT6
DATA32
DATA33
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
ADDR28
ADDR29
CAS
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
L1DIR
DATA36
DATA37
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
ADDR23
ADDR25
ADDR27
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
NC
DATA38
DATA39
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
ADDR30
ADDR22
ADDR26
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
DATA34
DATA41
DATA35
VDD_IO
VDD
VDD
VDD_IO
VDD
VDD
VDD
VDD
VDD_IO
VDD
VSS
VDD
VDD
VDD
VDD
VDD_IO
ADDR14
ADDR19
ADDR24
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
DATA40
DATA43
DATA46
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
ADDR12
ADDR17
ADDR20
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
DATA42
DATA45
L2DAT5
DATA48
DATA52
DATA58
DATA60
DATA63
L2DAT4
L2CLKOUT
NC
BR4
ACK
CPA
ADDR0
BR7
HBG
ADDR1
ADDR11
ADDR21
ADDR18
ADDR16
–34–
REV. 0
ADSP-TS101S
Table 26. 484-Ball (19 mm × 19 mm) PBGA Pin Assignments (continued)
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
DATA44
DATA50
DATA47
DATA49
DATA51
DATA54
DATA57
DATA61
L2DAT0
L2DAT3
L2DAT7
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
BR2
BR6
HBR
DPA
ADDR2
ADDR5
ADDR8
SDA10
ADDR10
ADDR13
ADDR15
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
VSS
DATA53
DATA55
DATA56
DATA59
DATA62
L2DAT1
L2DAT2
L2DAT6
L2CLKIN
L2DIR
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
BR0
BR1
BR3
BR5
BOFF
ADDR3
ADDR4
ADDR6
ADDR7
ADDR9
VSS
Pin
No. Mnemonic
484-Ball PBGA Pin Configurations (Top View, Summary)
2
1
4
3
6
5
8
7
10
9
14
12
11
13
16
15
20
18
17
19
22
21
A
B
C
D
E
F
G
KEY:
H
J
VDD
K
VDD_IO
L
VSS
M
SIGNAL
N
VDD_A
P
VSS_A
R
T
U
V
W
Y
AA
AB
TOP VIEW
REV. 0
–35–
ADSP-TS101S
625-BALL PBGA PIN CONFIGURATIONS
Table 27. 625-Ball (27 mm × 27 mm) PBGA Pin Assignments
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Pin
Mnemonic No.
Mnemonic
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
VSS
DATA17
DATA14
DATA11
DATA9
DATA7
DATA4
DATA1
L0DIR
L0DAT7
L0DAT4
L0DAT1
LCLK_N
LCLK_P
VDD_A
SCLK_N
VREF
DS1
CONTROLIMP2
RESET
DMAR2
EMU
TRST
TMS
VSS
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
VSS
VSS
DATA16
DATA13
DATA12
DATA10
DATA5
DATA2
NC
L0CLKOUT
L0DAT5
L0DAT2
VSS
VSS
VSS_A
SCLK_P
VSS
DS2
CONTROLIMP1
DMAR3
DMAR0
IRQ3
TCK
IRQ1
TDO
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
VSS
DATA20
DATA21
DATA18
DATA15
DATA8
DATA6
DATA3
DATA0
L0CLKIN
L0DAT6
L0DAT3
L0DAT0
VSS_A
VDD_A
VSS
DS0
CONTROLIMP0
DMAR1
TDI
IRQ2
LCLKRAT0
LCLKRAT1
IRQ0
VSS
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
VSS
VSS
DATA19
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
BMS
VSS
VSS
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
DATA23
DATA22
VSS
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD_IO
VSS
SCLKFREQ
LCLKRAT2
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
DATA26
DATA25
DATA24
VDD_IO
VDD_IO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_IO
BM
BUSLOCK
TMR0E
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
DATA29
DATA28
DATA27
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
FLAG3
FLAG2
FLAG1
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
L3DAT0
DATA31
DATA30
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
FLAG0
ID2
ID1
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
L3DAT3
L3DAT2
L3DAT1
VDD_IO
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
ID0
NC
NC
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
L3DAT6
L3DAT5
L3DAT4
VDD_IO
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
NC
NC
NC
–36–
REV. 0
ADSP-TS101S
Table 27. 625-Ball (27 mm × 27 mm) PBGA Pin Assignments (continued)
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Pin
Mnemonic No.
Mnemonic
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L3CLKIN
L3CLKOUT
L3DAT7
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
NC
NC
FLYBY
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
L1DAT0
NC
L3DIR
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
IOEN
MSH
BRST
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
L1DAT2
NC
L1DAT1
VDD_IO
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
WRH
WRL
RD
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
L1DAT5
L1DAT4
L1DAT3
VDD_IO
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
MS1
MS0
HDQM
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
L1CLKOUT
L1DAT7
L1DAT6
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
LDQM
NC
MSSD
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
NC
L1DIR
L1CLKIN
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
SDCKE
NC
SDWE
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
DATA34
DATA33
DATA32
VDD_IO
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD_IO
VDD_IO
CAS
NC
RAS
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
DATA37
DATA36
DATA35
VDD_IO
VDD_IO
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
ADDR31
ADDR30
ADDR29
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
DATA40
DATA39
DATA38
VDD_IO
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD_IO
ADDR28
NC
ADDR27
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
DATA43
DATA42
DATA41
VDD_IO
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD_IO
VDD_IO
ADDR26
ADDR25
ADDR24
REV. 0
–37–
ADSP-TS101S
Table 27. 625-Ball (27 mm × 27 mm) PBGA Pin Assignments (continued)
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Mnemonic
Pin
No.
Pin
Mnemonic No.
Mnemonic
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
DATA46
DATA45
DATA44
VDD_IO
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
VDD
VDD
VDD_IO
VDD_IO
ADDR23
ADDR22
ADDR21
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
DATA49
DATA48
DATA47
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
ADDR20
ADDR19
ADDR18
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
VSS
VSS
DATA50
DATA51
DATA54
DATA57
DATA60
DATA63
L2DAT2
L2DAT5
L2CLKOUT
NC
BR2
BR5
ACK
HBG
ADDR0
ADDR3
ADDR6
ADDR9
ADDR11
ADDR14
VSS
ADDR17
ADDR16
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
VSS
VSS
VSS
DATA52
DATA55
DATA58
DATA61
L2DAT0
L2DAT3
L2DAT6
L2CLKIN
BR0
BR3
BR6
HBR
CPA
ADDR1
ADDR4
ADDR7
SDA10
ADDR12
ADDR15
VSS
VSS
VSS
VSS
VSS
VSS
DATA53
DATA56
DATA59
DATA62
L2DAT1
L2DAT4
L2DAT7
L2DIR
BR1
BR4
BR7
BOFF
DPA
ADDR2
ADDR5
ADDR8
ADDR10
ADDR13
VSS
VSS
VSS
VSS
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
625-Ball PBGA Pin Configurations (Top View, Summary)
2
1
4
3
6
5
8
7
10
9
14
12
11
13
16
15
20
18
17
19
24
22
21
23
25
A
B
C
D
E
F
G
H
KEY:
J
K
VDD
L
VDD_IO
M
N
VSS
P
SIGNAL
R
VDD_A
T
VSS_A
U
V
W
Y
AA
AB
AC
AD
AE
TOP VIEW
–38–
REV. 0
ADSP-TS101S
OUTLINE DIMENSIONS
The ADSP-TS101S is available in a 19 mm ⴛ 19 mm, 484-ball PBGA package with 22 rows of balls (B-484);
the DSP also is available in a 27 mm ⴛ 27 mm, 625-ball PBGA package with 25 rows of balls (B-625).
484-Ball PBGA (B-484)
19.10
19.00
18.90
22 20 18 16 14 12 10 8 6 4 2
21 19 17 15 13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
1.10
BSC
19.10
19.00
18.90
17.05
16.95
16.85
16.80
BSC
SQ
0.80
BSC
SQ
BALL
PITCH
1.10
BSC
17.05
16.95
16.85
19.10
19.00 SQ
18.90
TOP VIEW
BOTTOM VIEW
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25mm OF ITS IDEAL
POSITION RELATIVE TO THE PACKAGE EDGES.
3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10mm OF ITS IDEAL
POSITION RELATIVE TO THE BALL GRID.
4. CENTER DIMENSIONS ARE NOMINAL.
REV. 0
1.30 MAX
0.65
0.55
0.45
2.50 MAX
–39–
SEATING PLANE
0.55
0.50
0.45
BALL DIAMETER
DETAIL A
0.40 MIN
0.20 MAX
ADSP-TS101S
625-Ball PBGA (B-625)
27.20
27.00
26.80
24 22 20 18 16 14 12 10 8 6 4 2
25 23 21 19 17 15 13 11 9 7 5 3 1
24.20
24.00
23.80
27.20
27.00
26.80
24.00
BSC
SQ
1.00
BSC
SQ
BALL
PITCH
1.50
BSC
SQ
24.20
24.00
23.80
C03164–0–9/02(0)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
1.50
BSC
SQ
27.20
27.00 SQ
26.80
TOP VIEW
BOTTOM VIEW
DETAIL A
1.25 MAX
0.65
0.55
0.45
2.50 MAX
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25mm OF ITS
IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10mm OF ITS
IDEAL POSITION RELATIVE TO THE BALL GRID.
4. CENTER DIMENSIONS ARE NOMINAL.
5. THIS PACKAGE COMPLIES WITH THE JEDEC MS-034 SPECIFICATION,
BUT USES TIGHTER TOLERANCES THAN THE MAXIMUMS ALLOWED IN
THAT SPECIFICATION.
SEATING PLANE
BALL DIAMETER
0.70
0.60
0.50
0.40 MIN
0.20 MAX
DETAIL A
ORDERING GUIDE
Part Number1, 2, 3, 4
Temperature
Range (Case)
Core Clock
(CCLK) Rate5
On-chip
SRAM
Operating
Voltage
ADSP-TS101SAB1-000
–40°C to +85°C
250 MHz
6M Bit
ADSP-TS101SAB2-000
–40°C to +85°C
250 MHz
6M Bit
1.2 VDD
3.3 VDD_IO
1.2 VDD
3.3 VDD_IO
Package
(B-625)6
(B-484)7
1S
indicates 1.2 and 3.3 V supplies.
indicates –40°C to +85°C temperature.
3 B = Plastic Ball Grid Array (PBGA) package.
4 1-000 indicates B-625 package and 250 MHz speed grade, and 2-000 indicates B-484 package and 250 MHz speed grade.
5 The instruction rate runs at the internal DSP clock (CCLK) rate.
6 The B-625 package measures 27 mm × 27 mm.
7 The B-484 package measures 19 mm × 19 mm.
–40–
PRINTED IN U.S.A.
2A
REV. 0