INFINEON MGP3006X6

MGP 3006X6
GHz PLL with I2C Bus
and Four Chip Addresses
Bipolar IC
Features
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1-chip system for MPU-control (I2C Bus)
4 programmable chip addresses
Short pull-in time for quick channel switch-over
and optimized loop stability
3 high-current band switch outputs (20 mA)
Software-compatible with SDA 3202 series
Oxis III technology
P-DSO-16-1
Type
Ordering Code
Package
MGP 3006X6
Q67000-H5113
P-DSO-16-1 (SMD)
MGP 3006X6
Q67006-H5113
P-DSO-16-1 Tape & Reel (SMD)
Combined with a VCO (tuner), the MGP 3006X6 device, with four hard-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets
with PLL-frequency synthesis tuning. The PLL permits precise crystal-controlled setting
of the frequency of the tuner oscillator between 16 and 1300 MHz in increments of
62.5 kHz, and, with a 2.4-GHz prescaler 1/2, in the TV-SAT band in increments of
125 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The
I2C Bus noise immunity has been improved by a factor of 10 compared to the
SDA 3202-2, and the new crystal oscillator generates a sinusoidal signal, suppressing
the higher-order harmonics, which reduces the moiré noise considerably.
Semiconductor Group
1
04.93
MGP 3006X6
Circuit Description
Tuning Section
UHF/VHF
The tuner signal is capacitively coupled at the UHF/VHF-input and
subsequently amplified.
REF
The reference input REF should be decoupled to ground using a capacitor
of low series inductance. The signal passes through an asynchronous
divider with a fixed ratio of P = 8, an adjustable divider with ratio N = 256
through 32767, and is then compared in a digital frequency/phase
detector to a reference frequency fREF = 7.8125 kHz.
Q1, Q2
This frequency is derived from a balanced, low-impedance 4-MHz crystal
oscillator (pin Q1, Q2) by dividing its output signal by Q = 512.
The phase detector has two outputs UP and DOWN that drive the two
current sources I+ and I– of a charge pump. If the negative edge of the
divided VCO-signal appears prior to the negative edge of the reference
signal, the I+ current source pulses for the duration of the phase
difference. In the reverse case the I– current source pulses.
PD, UD
If the two signals are in phase, the charge pump output (PD) goes into the
high-impedance state (PLL is locked). An active low-pass filter integrates
the current pulses to generate the tuning voltage for the VCO (internal
amplifier, external output transistor at UD and external RC-circuitry). The
charge pump output is also switched into the high-impedance state when
the control bit T0 = 1. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a
result of self-discharge in the peripheral circuitry. UD may be switched off
by the control bit OS to allow external adjustments.
By means of a control bit 5I the pump current can be switched between
two values by software. This programmability permits alteration of the
control response of the PLL in the locked-in state. In this way different
VCO-gains in the different TV-bands can be compensated, for example.
P0, P1, P2
The software-switched outputs P0, P1, P2 can be used for direct band
selection (20 mA current output).
P4, P7
P4 and P7 are general-purpose open-collector outputs. The test bit T1 = 1
switches the test signal Cy (divided input signal) to P7.
CAU
Four different chip addresses can be set by appropriate connection of pin
CAU.
Semiconductor Group
2
MGP 3006X6
I2C Bus Interface
Data are exchanged between the processor and the PLL on the I2C Bus.
SCL, SDA
The clock is generated by the processor (input SCL), while pin SDA works
as an input or output depending on the direction of the data (open
collector; external pull-up resistor). Both inputs have hysteresis and a
low-pass characteristic, which enhances the noise immunity of the I2C
Bus.
The data from the processor pass through an I2C Bus control. Depending
on their function the data are subsequently stored in registers. If the bus
is free, both lines will be in the marking state (SDA, SCL are high). Each
telegram begins with the start condition and ends with the stop condition.
Start condition: SDA goes low, while SCL remains high. Stop condition:
SDA goes high while SCL remains high. All further information transfer
takes place during SCL = low, and the data is forwarded to the control
logic on the positive clock edge.
The table “bit allocation” should be referred to in the following paragraph.
All telegrams are transmitted byte-by-byte, followed by a ninth clock
pulse, during which the control logic returns the SDA-line to low
(acknowledge condition). The first byte is comprised of seven address
bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The eighth bit is always low.
In the data portion of the telegram the first bit of the first or third data byte
determines whether a divider ratio or control information is to follow. In
each case the second byte of the same data type or a stop condition has
to follow the first byte.
VS, GND
When the supply voltage is applied a power-on reset circuit prevents the
PLL from setting the SDA-line to low, which would block the bus.
Semiconductor Group
3
MGP 3006X6
Circuit Description (cont’d)
Bit Allocation
MSB
A = Acknowledge
Address byte
1
1
0
0
0
MA1
MA0
0
A
Prog. divider Byte 1
0
n14
n13
n12
n11
n10
n9
n8
A
Prog. divider Byte 2
n7
n6
n5
n4
n3
n2
n1
n0
A
Control info. Byte 1
1
5I
T1
T0
X
X
1
OS
A
Control info. Byte 2
P7
X
X
P4
X
P2
P1
P0
A
Divider Ratio
N = 16384 × n14 + 8192 × n13 + 4096 × n12 + 2048 × n11 + 1024 × n10 + 512 × n9 +
256 × n8 + 128 × n7 + 64 × n6 + 32 × n5 + 16 × n4 + 8 × n3 + 4 × n2 + 2 × n1 + n0
Band Selection
P0, P1, P2, P4, P7 = 1
Open-collector output is active.
Pump Current Programming
5I = 1
High current
UD Disable
OS = 1
UD is disabled.
Test Mode
T1, T0 = 0, 0
T1 = 1
T0 = 1
Semiconductor Group
Normal operation
P3 = fREF; P4 = Cy
Tristate: charge pump output PD is in high-impedance state.
4
MGP 3006X6
Chip Address Switching
MA1
MA0
Voltage at CAU
0
0
(0 … 0.1) VS
0
1
open-circuit
1
0
(0.4 … 0.6) VS
1
1
(0.9 … 1) VS
Telegram Examples
Start-Addr-DR1-DR2-CW1-CW2-Stop
Start-Addr-CW1-CW2-DR1-DR2-Stop
Start-Addr-DR1-DR2-CW1-Stop
Start-Addr-CW1-CW2-DR1-Stop
Start-Addr-DR1-DR2-Stop
Start-Addr-CW1-CW2-Stop
Start-Addr-DR1-Stop
Start-Addr-CW1-Stop
Semiconductor Group
Start
Addr
DR1
DR2
CW1
CW2
Stop
5
=
=
=
=
=
=
=
start condition
address
divider ratio 1st byte
divider ratio 2nd byte
control word 1st byte
control word 2nd byte
stop condition
MGP 3006X6
Pin Configuration
(top view)
Semiconductor Group
6
MGP 3006X6
Pin Definitions and Functions
Pin No.
Symbol
Function
1
PD
Input active filter/charge pump output
2
Q1
Quartz crystal
3
Q2
Quartz crystal
4
SDA
Data input/output for I2C Bus
5
SCL
Clock input for I2C Bus
6
P7
Port output (open collector)
7
P4
Port output (open collector)
8
CAU
Address switch input
9
P2
Port output (open collector)
10
P1
Port output (open collector)
11
P0
Port output (open collector)
12
VS
Supply voltage
13
UHF/VHF
Signal input
14
REF
Amplifier reference input
15
GND
Ground
16
UD
Output active filter
Semiconductor Group
7
MGP 3006X6
Block Diagram
Semiconductor Group
8
MGP 3006X6
Absolute Maximum Ratings
TA = – 20 to 80 °C
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
Supply voltage
VS
– 0.3
6
V
Output PD
V1
– 0.3
VS
V
Crystal oscillator pins Q1, Q2
V2
– 0.3
VS
V
Bus input/output SDA
V4
– 0.3
6
V
Bus input SCL
V5
– 0.3
6
V
Port outputs P0, P1, P2, P4, P7
V6
– 0.3
16
V
Chip address switch CAU
V8
– 0.3
VS
V
Signal input UHF/VHF
V13
– 0.3
0.3
V
for VS = 0 V
Reference input REF
V14
– 0.3
0.3
V
for VS = 0 V
Output active filter UD
V16
– 0.3
VS
V
Bus output SDA
I4L
–1
5
mA
open collector
Port outputs P0, P1, P2
I9L
–1
20
mA
open collector
Port outputs P4
P7
I7L
I6L
–1
–1
5
7
mA
mA
open collector
open collector
Total port output current
ΣIL
25
mA
Junction temperature
Tj
125
°C
Storage temperature
Tstg
125
°C
Thermal resistance
(junction to ambient)
Rth JA
125
K/W
Semiconductor Group
– 40
9
MGP 3006X6
Absolute Maximum Ratings (cont’d)
TA = – 20 to 80 °C
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
Operating Range
Supply voltage
VS
4.5
5.5
V
Ambient temperature
TA
– 20
80
°C
Input frequency
f13
16
1300
MHz (at 25 °C)
Crystal frequency
f2
3.2
4.8
MHz
Programmable divider factor
N
256
32767
AC/DC Characteristics
TA = – 20 to 80 °C; VS = 4.5 to 5.5 V
Parameter
Symbol
Limit Values
min.
Supply current
IS
typ.
max.
41
55
Unit
Test Condition
Test
Circuit
mA
VS = 5 V
1
fQ = 4 MHz
1
dBm/2) f13 = 70 … 500 MHz
dBm/2) f13 = 1000 MHz
dBm/2) f13 = 1100 MHz
2
2
2
Crystal Oscillator Connections Q1, Q2
Oscillation frequency f2
3.999754.000
4.00025MHz
20
Margin from 1st
(fundamental) to 2nd
and 3rd harmonics1)
dB
Signal Input UHF/VHF
Sensitivity
a13
a13
a13
3/315
3/315
3/315
— 27/10
— 27/10
— 20/22
Port Outputs P0, P1, P2 (switch with open collector)
H-output current
I9H
10
µA
V6H = 13.5 V
3
L-output voltage
V9L
0.5
V
I6L = 20 mA
3
Notes see page 11.
Semiconductor Group
10
MGP 3006X6
AC/DC Characteristics (cont’d)
TA = – 20 to 80 °C; VS = 4.5 to 5.5 V
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
Test
Circuit
max.
Port Outputs P4, P7 (switch with open collector)
H-output current
I6H
10
µA
V6H = 13.5 V
4
L-output voltage
V6L
0.5
V
I6L = 1.7 mA
4
Phase-Detector Output PD (VS = 5 V)
Pump current
Pump current
I1H
I1H
± 90
± 22
± 220
± 50
± 300
± 75
µA
µA
5I = 1; V1 = 2 V
5I = 0; V1 = 2 V
5
5
Tristate current3)
I1Z
–3
1
3
nA
T1 = 1; V1 = 2 V
5
Current gain from
PD to UD3)
β2
6400
T1 = 1; V1 = 2 V;
I1 = 2 nA
5
Output voltage
V1L
1.0
locked
5
µA
V16 = 0.8 V;
I1H = 90 µA
5
100
500
mV
mV
V1L = 0 V
OS = 1; VS = 5 V;
TA = 25 °C
5
5
50
50
µA
µA
V8H = 5 V
V8L = 5 V
7
7
2.5
V
Active Filter Output UD (Test mode T0 = 1; PD = tristate)
Output current
– I16
Output voltage
Output voltage
V16
V16
500
Chip Address Switch CAU
Input current
Input current
I8H
– I8L
1) Design note only: no 100 % final inspection.
2) mVrms into 50 Ω.
3) Ripple voltage on tuning line (see application circuit) = 128 µs (I1Z + I16/β2)(C1 + C2) / (C1 C2)
e.g. for I16 = 8 µA, C1 = 180 nF, C2 = 9 pF, worst-case ripple voltage = 61 µA.
Semiconductor Group
11
MGP 3006X6
AC/DC Characteristics
TA = – 20 to 80 °C; VS = 4.5 to 5.5 V; refer to test circuit 6
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
max.
Bus Inputs SCL, SDA
H-input voltage
V4IH
L-input voltage
3
5.5
V
V4IL
1.5
V
H-input current
I4IH
10
µA
V4IH = VS
L-input current
– I4IL
20
µA
V4IL = 0 V
Bus Output SDA (open collector)
H-output current
I4OH
10
µA
V4OH = 5.5 V
L-output voltage
V4OL
0.4
V
I4OL = 3 mA
Rise time
tR
1
µs
Fall time
tF
0.3
µs
100
kHz
Edges SCL, SDA
Shift Clock SCL
Frequency
f5
0
H-pulse width
t5HIGH
4
µs
L-pulse width
t5LOW
4.7
µs
Set-up time
tSUSTA
4.7
µs
Hold time
tHDSTA
4
µs
Start
Notes see page 19
Semiconductor Group
12
MGP 3006X6
AC/DC Characteristics (cont’d)
TA = – 20 to 80 °C; VS = 4.5 to 5.5 V; refer to test circuit 6
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Stop
Set-up time
tSUSTO
4.7
µs
Bus free
tBUF
4.7
µs
Set-up time
tSUDAT
0.25
µs
Hold time
tHDDAT
0
µs
Data Transfer
Input hysteresis
SCL, SDA1)
300
mV
Low-pass cutoff
frequency SCL,
SDA1)
500
kHz
1) Design note only: no 100 % final inspection.
Semiconductor Group
13
Test Condition
MGP 3006X6
Crystal Oscillator
Test Circuit 1
Semiconductor Group
14
MGP 3006X6
Calibration of Signal Generator
Measurement of Input Sensitivity
Test Circuit 2
Semiconductor Group
15
MGP 3006X6
Test Circuit 3
Test Circuit 4
Test Circuit 5
Semiconductor Group
16
MGP 3006X6
Test Circuit 6
I2C Bus Timing Diagram
Set-up time (start)
Hold time (start)
H-pulse width (clock)
L-pulse width (clock)
Set-up time (data transfer)
Hold time (data transfer)
Set-up time (stop)
Bus free time
Fall time
Rise time
tSUSTA
tHDSTA
tHIGH
tLOW
tSUDAT
tHDDAT
tSUSTO
tBUF
tF
tR
All times related to 10 % and 90 % values.
Semiconductor Group
17
MGP 3006X6
Test Circuit 7
Application Circuit
Semiconductor Group
18
MGP 3006X6
Notes
1. Loop bandwidth ωR = √[(IP × KVCO) / (C1 × P × N)]
Attenuation
a = 0.5 ωR × R × C1
with
IP
KVCO
R, C 1
P
N
= charge pump current
= VCO-gain
= loop filter component values
= prescaler division ratio
= programmable division ratio
e.g. IP = 50 µA, KVCO = 18.7 MHz/V, R = 22 kΩ,
C1 = 180 nF, P = 8, N = 11520 (channel 47):
ωR = 237 Hz, fR = 38 Hz, a = 0.47
Typically, C2 = C1/5.
2. Symmetrical capacitive coupling improves the balance of the crystal oscillator and
thus reduces cross-talk.
3. High-impedance port outputs and the address selection input P3 can be decoupled
from external noise with a 1 nF capacitor.
4. It is important to keep to the I2C Bus specification concerning maximum capacitance
and impedance.
Semiconductor Group
19
MGP 3006X6
Diagrams
Sensitivity at UHF/VHF-Input
I2C Bus Noise Immunity
Sinusoidal noise pulses are applied via a coupling capacitance of 33 pF to the SCL- and
SDA-inputs.
Semiconductor Group
20
MGP 3006X6
Plastic Package, P-DSO-16-1 (SMD)
(Plastic Dual Small Outline)
GPS05119
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
Semiconductor Group
21
Dimensions in mm