Components for Entertainment Electronics Satellite Sound IF TDA6170X with Wegener Expander Data Sheet 07.99 Edition 07.99 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. 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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. Ausgabe 07.99 Herausgegeben von Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. Alle Rechte vorbehalten. Wichtige Hinweise! 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Sollten sie ausfallen, besteht berechtigter Grund zur Annahme, daß die Gesundheit des Anwenders gefährdet werden kann. TDA6170X Revision History:Current Version: 07.99 Previous Version: old Page new Page Subjects (major changes since last revision) Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview". Data Sheet TDA6170X 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 4.1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 5.1 Pinconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Package outline P-DSO-28-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.6 8.7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PLL Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Fast I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IF-Muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Converter Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IF Limiter with Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Expander Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AF Switch and Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 14 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15 15.1 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Semiconductor Group 21.7.99 Satellite Sound IF with Wegener Expander TDA6170X Data Sheet 1 BIPOLAR Features • Fast I2C-bus controlled (max. 400 kHz) • PLL controlled sound IF tuning with 10 kHz stepwidth • Second order high-pass mixer input • IF MUX for 10.7 MHz broad / small IF filters • Two identical high sensitive alignment free FM demodulators • Original Wegener PANDA 1TM expander • Volume control for individual settings • 50 µs / 75 µs / J17 de-emphasis for main sound reception • Fully ESD protection P-DSO-28 Package 2 3 Ordering Information Type Package Ordering Code TDA6170X P-DSO-28-1 Q67001-A5214 General Description Multistandard satellite sound IF device consisting of a mixer and a voltage controlled oscillator (VCO) as a frequency converter that can be continuously tuned in 10 kHz increments with crystal accuracy by means of a PLL, two FM limiter amplifiers with PLL FM demodulators followed by two Wegener PANDA1TM expanders. The AF signal passes through two switches. Each switch can select the AF sources and the mono / stereo mode the de-emphasis networks together with the two following volume control stages with audio buffers. In front of one FM section an IF multiplexer is used to select the IF bandwidth. The switching functions and settings of the PLL are controlled by an I2C-bus. 3.1 Application • For use in satellite receivers Semiconductor Group 1 21.7.99 Data Sheet 4 TDA6170X Pinconfiguration P-DSO 28-1 XTAL 1 28 SDA PD 2 27 SCL GNDD 3 26 VD CAS 4 25 MIXIN LP1 5 24 MIXOUT LP2 6 23 VA EXT1 7 22 IF1 AF1 8 21 GNDA AF2 9 20 IF2 EXT2 10 19 IF3 DEEMP2 11 18 DEEMP1 EXP2 CT 12 17 EXP1 CT EXP2 CR 13 16 EXP1 CR EXP2 TC 14 15 EXP1 TC 4.1 Package outline P-DSO-28-1 Semiconductor Group 2 21.7.99 Data Sheet 5 TDA6170X Pin Definitions and Functions Pin No. Symbol Function 1 XTAL crystal input for 4 MHz oscillator 2 PD synthesizer loop-filter 3 GNDD I2C-bus and synthesizer ground 4 CAS I2C-bus address selection 5 LP1 FM-PLL lowpass capacitor (channel 1) 6 LP2 FM-PLL lowpass capacitor (channel 2) 7 EXT1 external audio input (channel 1) 8 AF1 audio output (channel 1) 9 AF2 audio output (channel 2) 10 EXT2 external audio input (channel 2) 11 DEEMP2 de-emphasis capacitor (channel 2) 12 EXP2 CT expander tracking capacitor (channel 2) 13 EXP2 CR expander release capacitor (channel 2) 14 EXP2 TC expander time constant (channel 2) 15 EXP1 TC expander time constant (channel 1) 16 EXP1 CR expander release capacitor (channel 1) 17 EXP1 CT expander tracking capacitor (channel 1) 18 DEEMP1 de-emphasis capacitor (channel 1) 19 IF3 intercarrier input 3 20 IF2 intercarrier input 2 21 GNDA analog ground 22 IF1 intercarrier input 1 23 VA analog supply voltage (+8V) 24 MIXOUT intercarrier mixer output 25 MIXIN mixer input 26 VD I2C-bus and synthesizer supply voltage (+5V) 27 SCL I2C-bus serial clock input 28 SDA I2C-bus serial data input/output Semiconductor Group 3 21.7.99 Data Sheet 6 TDA6170X Block Diagram Semiconductor Group 4 21.7.99 Data Sheet 7 TDA6170X Circuit Description 7.1 General The sound intermediate frequencies contained in the baseband of a demodulated FM satellite signal can lie between 5 and 9.9 MHz. This band of frequencies is applied rough filtered to the high-pass input of the converter mixer. The purpose of this mixer is to convert the different sound IF‘s in the baseband to fixed output frequencies (e.g. 10.7 / 10.72 MHz). These frequencies are then fed by external filters to the three sound IF inputs. The VCO of the mixer can be continuously tuned between 29 and 40 MHz in 20 kHz increments with crystal accuracy by means of a PLL circuit. The settings of the programmable divider and switching of the IF MUX and de-emphasis networks and volume control are done by the I2C-bus. Pin 5 (CAS) offers two switchable chip addresses to enable parallel operation of two devices. All pins are guarded against electrostatic discharge. SCL and SDA include special protective structures to permit continued bus operation when the device is switched off. 7.2 PLL Description The VCO signal is applied to the PLL input. It passes through a programmable divider (N=1024 to 2047) and then compared with a reference frequency (fREF = 20 kHz in a digital frequency / phase detector. This frequency is derived from a 4 MHz crystal oscillator whose signal is divided by 200. The phase detector has a charge pump push-pull current output. If the negative edge of the divided VCO signal appears before the negative edge of the reference signal, the current source I+ will pulse for the duration of the phase difference. In the reverse case it is the current sink I-. If both signals are in phase, the output has a high impedance and the PLL is locked. The current pulses are filtered by means of an integrator. The pump current can be switched between two values (1 and 5) by software with a control bit 5I. This permits a change in the control response during and after lock-in state. 7.3 Fast I2C-Bus Interface Information is exchanged between the processor and the sound IF device on an fast asynchronous bidirectional data bus. The timing for this comes from the processor (input SCL), while pin SDA functions as an I/O depending on the direction of the data (open collector; external pull-up resistor). The bus will work with clock frequencies up to 400 kHz. The data from the processor goes to an I2C-bus controller and are put into registers (latches 0 to x) according to their function. When the bus is not busy, both lines are in the marking state (SDA, SCL are high). Each telegram begins with the start condition: SDA goes low while SCL remains high. All further exchanges of information occur when SCL is low and are read by the controller with the positive clock edge. If SDA goes high while the clock is high, the I2C-bus interface recognizes this as a stop condition and thus the end of the telegram. For what follows, refer to the table of logic assignments below. All telegrams are transferred byte for byte, followed by a ninth clock pulse during which the controller pulls the SDA line to low (i.e. acknowledge condition). The first byte consists of seven address bits with which the processor selects the PLL from among several other peripheral devices (chip select). The eighth bit is always low. The first bit of the first or third data byte in the data part of the telegram determines whether a divider ratio or control information for the IF or audio part will follow. In every case the first byte must be followed by a byte of the same data type (or stop condition). When the supply voltage is applied, a power-on reset circuit prevents the PLL from pulling the SDA line to low and thus blocking the bus. Semiconductor Group 5 21.7.99 Data Sheet 7.3.1 TDA6170X Logic Allocation Byte Data Remarks Address Byte 0 1 0 0 0 0 MA R/W A Progr. Divider Byte 1 0 0 N11 N10 N9 N8 N7 N6 A Progr. Divider Byte 2 0 0 N5 N4 N3 N2 N1 N0 A Control Byte 1 1 5I Z2 Z1 Z0 X X X A Control Byte 2 1 VL2 VL1 VL0 VR2 VR1 VR0 X A Control Byte 3 1 X A PVL2 PVL1 PVL0 PVR2 PVR1 PVR0 11 0 1 0 0 0 1 0 0 A =H44 Address Byte 22 0 1 0 0 0 1 1 0 A =H46 Address Byte 1. Chip address (CAS) Pin 5 grounded 2. Chip address (CAS) Pin 5 open 7.3.2 IF-Muting Control Bits IF-Source Function Z2 Z1 Z0 IF1 IF2 IF3 0 0 0 on on off expanders are working, audio = stereo 0 0 1 off on off expanders are working, audio = mono 0 1 0 on off off expanders are working, audio = mono 0 1 1 off off on de-emphasis = 50µ; audio = mono 1 0 0 off off on de-emphasis = 75µ; audio = mono 1 0 1 off off on de-emphasis = J17; audio = mono 1 1 0 off off off External audio 1 1 1 off off off Mute 7.4 Converter Mixer In the converter mixer the sound subcarriers (frequency band approx. 5 to 9.9 MHz) contained in the baseband of the received composite satellite signal are converted to an output frequency of 10.52 MHz and 10.7 MHz for example. The converter consists of a high-pass input filter followed by a double balanced mixer and a low impedance output. The signal of the on chip voltage controlled oscillator (VCO) is applied to the PLL input. 7.5 IF Limiter with Demodulator The two limiter amplifiers are implemented as balanced five stage, capacitively coupled differential amplifiers. The three inputs are designed as high-pass inputs. The load resistors for the IF filters are connected to ground. The output signals of the limiter amplifiers are fed directly to the internal PLL FM demodulators. The demodulated AF signals are fed to the input of a pre volume control part in front of the expander the deemphasis networks and audio switches. Semiconductor Group 6 21.7.99 Data Sheet TDA6170X 7.6 Expander Description The demodulated and level controlled audio signals are fed via low-pass filters to the inputs of two identical expander circuits. The IF3 audio signal is also applied in parallel via different de-emphasis networks to the input of the audio switch for broadband mono reception. The expander circuits have the reverse characteristics of the audio compressor of the TV station. A 3 bit pre volume control (control byte 3: PVL2...PVL0 and PVR2...PVR0) for each audio channel enables a correct adjustment of the expander characteristics and allows the possibility to align to the right level for both broadband and smallband sound IF reception. 7.7 AF Switch and Volume Control The input signals of the AF switch can be derived from the external audio input pair. However, these signals can also be derived from either the different de-emphasis networks or from both expanders. The selection of the output signals from IF1, IF2 or IF3 is done by using the I2C-bus interface. The switches are followed by a volume control section with buffered outputs Ch1 and Ch2. In case of small-band reception the demodulated signals of IF1 and IF2 are processed in both expanders and fed to the switches. So it is possible to select one of each or both in the audio switches for both AF outputs Ch1 and Ch2. In the case of broad-band audio transmission with 50µs, 75µs or J17 pre-emphasis the IF3 input is active and with the audio switch the demodulated audio signals are selected after the three de-emphasis networks and fed to both AF outputs in mono mode. The 3 bit volume control (control byte 2: VL2...VL0 and VR2...VR0) in front of each AF output enables the same audio level for different FM deviations of several satellite transponders. Semiconductor Group 7 21.7.99 Data Sheet 8 TDA6170X Pinning Pin No. Symbol 1 XTAL 2 PD 3 GNDD 4 CAS Semiconductor Group Equivalent Circuit 8 21.7.99 Data Sheet Pin No. Symbol 5 LP1 6 LP2 7 EXT1 8 AF1 Semiconductor Group TDA6170X Equivalent Circuit 9 21.7.99 Data Sheet Pin No. Symbol 9 AF2 10 EXT2 11 DEEMP2 12 EXP2 CT Semiconductor Group TDA6170X Equivalent Circuit 10 21.7.99 Data Sheet Pin No. Symbol 13 EXP2 CR 14 EXP2 TC 15 EXP1 TC 16 EXP1 CR Semiconductor Group TDA6170X Equivalent Circuit 11 21.7.99 Data Sheet Pin No. Symbol 17 EXP1 CT 18 DEEMP1 19 IF3 20 IF2 Semiconductor Group TDA6170X Equivalent Circuit 12 21.7.99 Data Sheet Pin No. Symbol 21 GNDA 22 IF1 23 VA 24 MIXOUT Semiconductor Group TDA6170X Equivalent Circuit 13 21.7.99 Data Sheet Pin No. Symbol 25 MIXIN 26 VD 27 SDA 28 SCL Semiconductor Group TDA6170X Equivalent Circuit 14 21.7.99 Data Sheet 9 TDA6170X Absolute Maximum Ratings The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result. Ambient Temperature under bias: TA=0 to 70°C Limit Values Parameter Symbol Unit min max Supply voltage (digital) VVD 0 6 V Supply voltage (analog) VVA 0 13.2 V Mixer input VMIXIN -0.3 13.2 V IF inputs VIF -0.3 1 V Crystal oscillator VXTAL 0 1.5 V SDA; SCL; CAS V -0.3 6 V Junction temperature Tj 0 150 °C Storage temperature Tstg 0 125 °C Thermal resistance Rth j-a 75 K/W 2 kV ESD-Protection VESD Test Conditions all pins All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign. Semiconductor Group 15 21.7.99 Data Sheet TDA6170X 10 Operating Range Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed. Parameter Symbol (Name) Limit Values Unit min max Supply voltage (digital) VVD 4.5 5.5 V Supply voltage (analog) VVA 7.2 13.2 V Input frequency range of converter mixer fMIXIN 5 10 MHz Input frequency range of sound IF amplifier fIF 10 12 MHz VCO frequency fVCO 29 42 MHz Ambient temperature TA 0 70 °C Semiconductor Group 16 Test Conditions 21.7.99 Data Sheet TDA6170X 11 Electrical Characteristics AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Limit Values Parameter Symbol Unit min typ max Test conditions Power Supply Current consumption Vdigital IVD 30 40 50 mA Current consumption Vanalog IVA 30 40 50 mA 200 mV 8 mA Mixer Mixer input voltage VMIXIN(rms) Mixer output current IMIXOUT 4 Input impedance RMIXIN 3.5 Output frequency range fMIXOUT 10 10.7 11.5 Mixer gain GMIX 2 3 4 dB RL = 100 Ω Phase detector charge current IPD 32 50 75 µA I Phase detector charge current IPD 160 250 360 µA 5I repetition time of charge pump pulses t 6 kΩ MHz Charge pump µs 50 VCO Frequency range VCO ∆fVCO VCO frequency fVCO 35.5 MHz VCO sensitivity SVCO -16 MHz/V 29 43 MHz VPD = 2.5V Cyrstal oscillator (4 MHz) crystal oscillator frequency fxtal resonance resistance of crystal Rxtal parallel capacitance of crystal Cxtal input current from external source Ii 4 4.5 MHz 60 W 10 pF µA 50 Sound IF Sound IF input resistance RIF 260 Input frequency range fIF 10 Input sensitivity VIF(rms) AM rejection aAM Semiconductor Group 330 0.3 45 17 400 W 11.5 MHz 1 mV S/N(A) > 40 dB; fIF = 10.7 MHz; ∆f = 27 kHz; fmod = 1 kHz dB fIF = 10.7 MHz; VIF = 5 to 100mV; fmod = 30% 21.7.99 Data Sheet TDA6170X Limit Values Parameter Symbol Unit min typ Test conditions max FM PLL demodulators free-running frequency fcco lock range of PLL ∆fCCO 10.6 10 MHz 11.5 MHz Expander Pre volume control range ∆PV 2.5 -3.5 3 -3 3.5 -2.5 dB Control resolution δV 0.6 0.8 1 dB 16 20 24 kHz 2 V Low-pass filter response PVL = 000 PVL = 111 AF Switch and Volume Control Max. external input voltage VEXT(rms) Volume control range ∆V -1 -12 0 -14 1 -16 dB Control resolution δV 1.6 2 2.4 dB VL = 000 VL = 111 Output Buffer Output DC level VAF Output resistance RAF total harmonic distortion THD signal to noise ratio S/N (A) 80 dB A-weighted VEXT = 500 mVrms Control Byte = 110 crosstalk between channels αL/R; αR/L 80 dB VEXT = 2 Vrms f = 1 kHz Control Byte = 110 3.6 100 V 125 150 W 0.01 0.2 % Overall performance Input voltage Output voltage Semiconductor Group 0.5 1 mV S/N > 40 dB ∆f = 27kHz, Control Byte = 000 1.5 3 mV S/N > 40 dB ∆f = 50kHz, Control Byte = 011 400 500 600 mV ∆f = 27kHz, fmod = 1kHz, Control Byte = 000 400 500 600 mV ∆f = 50kHz, fmod = 1kHz, Control Byte = 011 VMIXIN VAF 18 21.7.99 Data Sheet TDA6170X Limit Values Parameter Symbol Unit min typ 0.2 total harmonic distortion Test conditions max 0.5 % VMIXIN > 2 mV ∆f = 27kHz, fmod = 1kHz, Control Byte = 000 % VMIXIN > 2 mV ∆f = 50kHz, fmod = 1kHz, Control Byte = 011 THD 0.2 0.5 signal to noise ratio S/N 70 75 dB A-weighted, ∆f = 27kHz, fmod = 1kHz, Control Byte = 000 Mute attenuation aMUTE 75 90 dB Control Byte = 111 I2C-Bus Interface LOW level input voltage for both SDA and SCL VIL -0.5 1.5 V HIGH level input voltage for both SDA and SCL VIH 3 VVD + 0.5 V Hysteresis of Schmitt trigger inputs Vhys 0.2 Pulse width of spikes which must t be suppressed by the input filters SP LOW level output voltage (open collector) VOL1 VOL2 Output fall time from VIHmin to VILmax with a bus tOF capacitance from 10 pF to 400 pF Input current for both SDA + SCL Ii V 50 ns 0 0 0.4 0.6 V 20 + 0.1Cb 250 ns -10 10 µA 400 kHz SCL clock frequency fSCL 0 Bus free time between a STOP and START condition tBUF 1.3 µs 0.6 µs Hold time (repeated) START condition. After this period, the first tHD,STA clock pulse is generated LOW period of the SCL clock tLOW 1.3 µs HIGH period of the SCL clock tHIGH 0.6 µs Set-up time for repeated START condition tSU,DAT 0.6 µs Data hold time: for I2C-bus devices tHD,DAT 0 Data set-up time tSU,DAT 100 Rise time of both SDA + SCL tR Semiconductor Group 20 + 0.1Cb 19 0.9 3 mA sink current 6 mA sink current µs ns 300 ns 21.7.99 Data Sheet TDA6170X Limit Values Parameter Symbol Unit min Fall time of both SDA + SCL tF Set-up time for STOP condition tSU,STO Capacitive load for each bus line Cb Semiconductor Group 20 + 0.1Cb typ 300 ns µs 0.6 400 20 Test conditions max pF 21.7.99 Data Sheet TDA6170X 12 Application Circuit Semiconductor Group 21 21.7.99 Data Sheet TDA6170X 13 Test circuit Semiconductor Group 22 21.7.99 Data Sheet TDA6170X 14 Diagrams 14.1 I2C-Bus Timing Semiconductor Group 23 21.7.99