November 1996 LMX2301 PLLatinum TM 160 MHz Frequency Synthesizer for RF Personal Communications General Description Features The LMX2301 is a high performance frequency synthesizer designed for RF operation up to 160 MHz. It is fabricated using National’s ABiC IV BiCMOS process. LMX2301, which employs the digital phase lock loop technique, combined with a high quality reference oscillator and a loop filter, provides the tuning voltage for the voltage controlled oscillator to generate a very stable, low noise local oscillator signal. Serial data is transferred into the LMX2301 via a three line MICROWIRETM interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2301 features very low current consumption, typically 2 mA at 3V. The LMX2301 is available in a TSSOP 20-pin surface mount plastic package. Y Y Y Y Y RF operation up to 160 MHz 2.7V to 5.5V operation Low current consumption: ICC e 2 mA (typ) at VCC e 3V Internal balanced, low leakage charge pump Small-outline, plastic, surface mount TSSOP, 0.173× wide package Applications Y Y Y Analog Cellular telephone systems (AMPS, ETACS, NMT) Portable wireless communications (PCS/PCN, cordless) Other wireless communication systems Block Diagram TL/W/12458 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/W/12458 RRD-B30M126/Printed in U. S. A. http://www.national.com LMX2301 PLLatinum 160 MHz Frequency Synthesizer for RF Personal Communications PRELIMINARY Connection Diagram LMX2301 TL/W/12458 – 2 20-Lead (0.173× Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2301TM or LMX2301TMX See NS Package Number MTC20 Pin Descriptions Pin No. Pin Name I/O Description 1 OSCIN I Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for operation as an oscillator. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. May also be from a reference oscillator. 3 OSCOUT O 4 VP Power supply for charge pump. Must be t VCC. 5 VCC Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 6 Do 7 GND 8 Oscillator output. O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO. LD O Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is locked, the pin’s output is HIGH with narrow low pulses. 10 fIN I RF buffer input. Small signal input from the VCO. 11 CLOCK I High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various counters and registers. 13 DATA I Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input. 14 LE I Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low when LE toggles high or low. See Serial Data Input Timing Diagram. 15 FC I Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase comparator and charge pump combination is reversed. 16 BISW O Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge pump output through BISW (as well as through Do). 17 fOUT O Monitor pin of phase comparator input. CMOS output. 18 wp O Output for external charge pump. wp is an open drain N-channel transistor and requires a pull-up resistor. 19 PWDN I Power Down (with internal pull-up resistor). PWDN e HIGH for normal operation. PWDN e LOW for power saving. Power down function is gated by the return of the charge pump to a TRI-STATE condition. 20 wr O 2,9,12 NC http://www.national.com Ground. Output for external charge pump. wr is a CMOS logic output. No connect. 2 Functional Block Diagram TL/W/12458 – 3 Note 1: The power down function is gated by the charge pump to prevent any unwanted frequency jumps. Once the power down pin is brought low the part will go into power down mode when the charge pump reaches a TRI-STATE condition. 3 http://www.national.com Absolute Maximum Ratings (Notes 1 and 2) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Power Supply Voltage VCC VP b 0.3V to a 6.5V b 0.3V to a 6.5V Voltage on Any Pin with GND e 0V (VI) b 0.3V to VCC a 0.3V Storage Temperature Range (TS) Lead Temperature (TL) (solder, 4 sec.) Power Supply Voltage VCC VP 2.7V to 5.5V VCC to a 5.5V b 40§ C to a 85§ C Operating Temperature (TA) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. b 65§ C to a 150§ C a 260§ C Note 2: This device is a high performance RF integrated circuit with an ESD rating k 2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD workstations. Electrical Characteristics VCC e 5V, VP e 5V; b40§ C k TA k 85§ C, except as specified Symbol ICC ICC-PWDN Parameter Power Supply Current Power Down Current Typ Max Units VCC e 3.0V Conditions Min 2.0 5 mA VCC e 5.0V 3.0 VCC e 3.0V 30 180 VCC e 5.0V 60 350 mA 160 MHz fIN RF Input Operating Frequency 45 fOSC Oscillator Input Operating Frequency 5 fw Phase Detector Frequency PfIN Input Sensitivity VCC e 2.7V to 5.5V VOSC Oscillator Sensitivity OSCIN VIH High-Level Input Voltage * VIL Low-Level Input Voltage * IIH High-Level Input Current (Clock, Data) VIH e VCC e 5.5V b 1.0 IIL Low-Level Input Current (Clock, Data) VIL e 0V, VCC e 5.5V b 1.0 IIH Oscillator Input Current VIH e VCC e 5.5V IIL b 10 mA mA 20 MHz 10 MHz a6 dBm 0.5 VPP 0.7 VCC V 0.3 VCC V 1.0 mA 1.0 mA 100 mA VIL e 0V, VCC e 5.5V b 100 IIH High-Level Input Current (LE, FC) VIH e VCC e 5.5V b 1.0 1.0 mA IIL Low-Level Input Current (LE, FC) VIL e 0V, VCC e 5.5V b 100 1.0 mA *Except fIN and OSCIN http://www.national.com 4 mA Electrical Characteristics VCC e 5.0V, VP e 5.0V; b40§ C k TA k 85§ C, except as specified (Continued) Symbol IDo-source Parameter Charge Pump Output Current IDo-sink Conditions Min Typ Max Units VDo e VP/2 b 5.0 mA VDo e VP/2 5.0 mA IDo-Tri Charge Pump TRI-STATEÉ Current 0.5V s VDo s VP b 0.5V TA e 25§ C VOH High-Level Output Voltage IOH e b1.0 mA** VOL Low-Level Output Voltage IOL e 1.0 mA** VOH High-Level Output Voltage (OSCOUT) IOH e b200 mA VOL Low-Level Output Voltage (OSCOUT) IOL e 200 mA IOL Open Drain Output Current (wp) VCC e 5.0V, VOL e 0.4V IOH Open Drain Output Current (wp) VOH e 5.5V RON Analog Switch ON Resistance tCS Data to Clock Set Up Time tCH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns tES Clock to Enable Set Up Time See Data Input Timing 50 ns tEW Enable Pulse Width See Data Input Timing 50 ns b 5.0 5.0 VCC b 0.8 V 0.4 VCC b 0.8 0.4 1.0 V mA 100 50 V V 100 See Data Input Timing nA mA X ns **Except OSCOUT 5 http://www.national.com Functional Description The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the R15 Latch, and the 11-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (power up counter reset). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable divider). TL/W/12458 – 1 PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND COUNTER RESET (R15 LATCH) If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch, which can be used to force an immediate load of the R and N counters during a cold power up condition. Serial data format is shown below. TL/W/12458 – 14 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) 1-BIT COUNTER RESET (R15 LATCH) Divide R R R R R R R R R R R R R R Ratio 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R Counter Reset R 15 Remove Forced Load 0 Force Load State 1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 # # # # # # # # # # # # # # # 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 16383 R1 to R14: These bits select the divide ratio of the programmable reference divider. The 1-bit counter reset latch controls whether the R and N counters are immediately forced to load conditions upon power up. If R e HIGH, the N and R latch states are immediately read into the respective counters. C: Control bit (set to HIGH level to load R counter and R15 Latch) Data is shifted in MSB first. SUGGESTED PROGRAMMING SEQUENCE AFTER COLD POWER-UP 1. Program N counter with desired divide ratio. 2. Program R counter with R15 e 1 and desired divide ratio. (N and R counters hold at load state.) 3. Program R counter with R15 e 0 and desired divide ratio. (N and R counters start counting.) http://www.national.com 6 Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 11-bit programmable counter. If the Control Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into an 11-bit latch, which sets the 11-bit programmable Counter. Serial data format is shown below. TL/W/12458 – 15 Note: R8 to R18: Programmable counter divide ratio control bits (3 to 2047) 7 LSB BITS OF N REGISTER Divide Ratio N 7 N 6 N 5 N 4 N 3 N 2 N 1 X X X X X X X X EQUATION FOR OUTPUT FREQUENCY DETERMINATION fVCO e [N] c fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) N: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) fOSC: Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16383) Note: X e Don’t care state 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO Divide Ratio N N 18 N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 # # # # # # # # # # # # 2047 1 1 1 1 1 1 1 1 1 1 1 Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited) 7 http://www.national.com Functional Description (Continued) SERIAL DATA INPUT TIMING TL/W/12458 – 16 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ VCC e 2.7V and 2.6V @ VCC e 5.5V. Phase Characteristics In normal operation, the FC pin is used to reverse the polarity of the phase detector. Both the internal and any external charge pump are affected. Depending upon VCO characteristics, FC pin should be set accordingly: When VCO characteristics are like (1), FC should be set HIGH or OPEN CIRCUIT; When VCO characteristics are like (2), FC should be set LOW. When FC is set HIGH or OPEN CIRCUIT, the monitor pin of the phase comparator input, fout, is set to the reference divider output, fr. When FC is set LOW, fout is set to the programmable divider output, fp. VCO Characteristics TL/W/12458 – 17 PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS TL/W/12458 – 18 Notes: Phase difference detection range: b 2q to a 2q The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked. FC e HIGH http://www.national.com 8 Analog Switch The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the Do pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode). TL/W/12458 – 19 Typical Crystal Oscillator Circuit Typical Lock Detect Circuit A typical circuit which can be used to implement a crystal oscillator is shown below. A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state. A typical circuit is shown below. TL/W/12458 – 20 TL/W/12458 – 21 9 http://www.national.com Typical Application Example Operational Notes: * ** TL/W/12458 – 22 VCO is assumed AC coupled. RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10X to 200X depending on the VCO power level. fIN RF impedance ranges from 40X to 100X. *** 50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSCIN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below) TL/W/12458 – 23 Application Hints: Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. This is an electrostatic sensitive device. It should be handled only at static free work stations. http://www.national.com 10 Application Information LOOP FILTER DESIGN A block diagram of the basic phase locked loop is shown. TL/W/12458 – 24 FIGURE 1. Basic Charge Pump Phase Locked Loop An example of a passive loop filter configuration, including the transfer function of the loop filter, is shown in Figure 2 . TL/W/12458 – 25 Z(s) e s (C2 # R2) a 1 s2 (C1 # C2 # R2) a sC1 a sC2 FIGURE 2. 2nd Order Passive Filter Define the time constants which determine the pole and zero frequencies of the filter transfer function by letting (1a) T2 e R2 # C2 and C1 # C2 T1 e R2 # C1 a C2 (1b) The PLL linear model control circuit is shown along with the open loop transfer function in Figure 3 . Using the phase detector and VCO gain constants [Kw and KVCO] and the loop filter transfer function [Z(s)], the open loop Bode plot can be calculated. The loop bandwidth is shown on the Bode plot (0p) as the point of unity gain. The phase margin is shown to be the difference between the phase at the unity gain point and b180§ . TL/W/12458 – 26 FIGURE 3. Open Loop Transfer Function Thus we can calculate the 3rd order PLL Open Loop Gain in terms of frequency G(s) # H(s)ls e j # 0 e # KVCO (1 a j0 # T2) T1 # 02C1 # N(1 a j0 # T1) T2 b Kw (2) From equation 2 we can see that the phase term will be dependent on the single pole and zero such that w(0) e tanb1 (0 # T2) b tanb1 (0 # T1) a 180§ (3) By setting T2 T1 dw e b e0 d0 1 a (0 # T2)2 1 a (0 # T1)2 (4) we find the frequency point corresponding to the phase inflection point in terms of the filter time constants T1 and T2. This relationship is given in equation 5. 0p e 1/0T2 # T1 (5) For the loop to be stable the unity gain point must occur before the phase reaches b180 degrees. We therefore want the phase margin to be at a maximum when the magnitude of the open loop gain equals 1. Equation 2 then gives TL/W/12458 – 27 C1 e Open Loop Gain e ii/ie e H(s) G(s) e Kw Z(s) KVCO/Ns Closed Loop Gain e io/ii e G(s)/[1 a H(s) G(s)] 11 Kw # KVCO # T1 (1 a j0p # T2) 0p2 # N # T2 (1 a j0p # T1) Ó Ó (6) http://www.national.com Application Information (Continued) Therefore, if we specify the loop bandwidth, 0p, and the phase margin, wp, Equations 1 through 6 allow us to calculate the two time constants, T1 and T2, as shown in equations 7 and 8. A common rule of thumb is to begin your design with a 45§ phase margin. secwp b tanwp T1 e 0p (7) T2 e In choosing the loop filter components a trade off must be made between lock time, noise, stability, and reference spurs. The greater the loop bandwidth the faster the lock time will be, but a large loop bandwidth could result in higher reference spurs. Wider loop bandwidths generally improve close in phase noise but may increase integrated phase noise depending on the reference input, VCO and division ratios used. The reference spurs can be reduced by reducing the loop bandwidth or by adding more low pass filter stages but the lock time will increase and stability will decrease as a result. 1 0p2 # T1 (8) From the time constants T1, and T2, and the loop bandwidth, 0p, the values for C1, R2, and C2 are obtained in equations 9 to 11. THIRD ORDER FILTER A low pass filter section may be needed for some applications that require additional rejection of the reference sidebands, or spurs. This configuration is given in Figure 4 . In order to compensate for the added low pass section, the component values are recalculated using the new open loop unity gain frequency. The degradation of phase margin caused by the added low pass is then mitigated by slightly increasing C1 and C2 while slightly decreasing R2. The added attenuation from the low pass filter is: ATTEN e 20 log[(2qfref # R3 # C3)2 a 1] (12) T1 Kw # KVCO 1 a (0p # T2)2 # T2 0p2 # N 1 a (0p # T1)2 (9) T2 b1 C2 e C1 # T1 (10) T2 R2 e C2 (11) Voltage Controlled Oscillator (VCO) KVCO (MHz/V) Tuning Voltage constant. The frequency vs voltage tuning ratio. Kw (mA) Phase detector/charge pump gain constant. The ratio of the current output to the input phase differential. N Main divider ratio. Equal to RFopt/fref C1 e # 0 J RFopt (MHz) Radio Frequency output of the VCO at which the loop filter is optimized. fref (kHz) Frequency of the phase detector inputs. Usually equivalent to the RF channel spacing. T2 e Defining the additional time constant as T3 e R3 # C3 (13) Then in terms of the attenuation of the reference spurs added by the low pass pole we have 0 10ATTEN/20 b 1 (14) (2q # fref)2 We then use the calculated value for loop bandwidth 0c in equation 11, to determine the loop filter component values in equations 15 – 17. 0c is slightly less than 0p, therefore the frequency jump lock time will increase. T3 e 1 0c2 # (T1 a T3) (15) (T1 a T3)2 a T1 # T3 b1 [tanw # (T1 a T3)] 2 0c e tanw # (T1 a T3) # [(T1 a T3)2 a T1 # T3] C1 e (/2 T1 Kw # KVCO (1 a 0c2 # T22) # # T2 0c2 # N (1 a 0c2 # T12) (1 a 0c2 # T32) http://www.national.com Ð01 a Ð ( 12 ( (16) (17) Application Information (Continued) EXAMPLE EXTERNAL CHARGE PUMP The LMX PLLatinum series of frequency synthesizers are equipped with an internal balanced charge pump as well as outputs for driving an external charge pump. Although the superior performance of NSC’s on board charge pump eliminates the need for an external charge pump in most applications, certain system requirements are more stringent. In these cases, using an external charge pump allows the designer to take direct control of such parameters as charge pump voltage swing, current magnitude, TRI-STATE leakage, and temperature compensation. One possible architecture for an external charge pump current source is shown in Figure 9 . The signals wp and wr in the diagram, correspond to the phase detector outputs of the LMX2301 frequency synthesizer. These logic signals are converted into current pulses, using the circuitry shown in Figure 9 , to enable either charging or discharging of the loop filter components to control the output frequency of the PLL. Referring to Figure 9 , the design goal is to generate a 5 mA current which is relatively constant to within 0.5V of the power supply rail. To accomplish this, it is important to establish as large of a voltage drop across R5, R8 as possible without saturating Q2, Q4. A voltage of approximately 300 mV provides a good compromise. This allows the current source reference being generated to be relatively repeatable in the absence of good Q1, Q2/Q3, Q4 matching. (Matched transistor pairs is recommended.) The wp and wr outputs are rated for a maximum output load current of 1 mA while 5 mA current sources are desired. The voltages developed across R4, 9 will consequently be approximately 258 mV, or 42 mV k R8, 5, due to the current density differences À0.026*1n (5 mA/1 mA)Ó through the Q1, Q2/Q3, Q4 pairs. In order to calculate the value of R7 it is necessary to first estimate the forward base to emitter voltage drop (Vfn,p) of the transistors used, the VOL drop of wp, and the VOH drop of wr’s under 1 mA loads. (wp’s VOL k 0.1V and wr’s VOH k 0.1V.) Knowing these parameters along with the desired current allow us to design a simple external charge pump. Separating the pump up and pump down circuits facilitates the nodal analysis and give the following equations. VR5 b VT # ln R4 e R9 e R8 e R6 e R7 e isource p max isource VR8 b VT # ln R5 e #i isink #i isink n max Typical Device Parameters bn e 100, bp e 50 Typical System Parameters VP e 5.0V; Vcntl e 0.5V b 4.5V; Vwp e 0.0V; Vwr e 5.0V ISINK e ISOURCE e 5.0 mA; Vfn e Vfp e 0.8V Irmax e Ipmax e 1 mA VR8 e VR5 e 0.3V VOLwp e VOHwr e 100 mV Design Parameters TL/W/12458 – 28 FIGURE 9 Therefore select R4 e R9 e J 0.3V b 0.026 # 1n(5.0 mA/1.0 mA) e 51.6X 5 mA R5 e 0.3V e 300X 1.0 mA R8 e 0.3V e 300X 1.0 mA R6 e R7 e (5V b 0.1V) b (0.3V a 0.8V) e 3.8 kX 1.0 mA J VR5 ip max VR8 ir max (Vp b VVOLwp) b (VR5 a Vfp) ip max (VP b VVOHwr) b (VR8 a Vfn) imax 13 http://www.national.com LMX2301 PLLatinum 160 MHz Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number MTC20 20-Lead (0.173× Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2301TM For Tape and Reel Order Number LMX2301TMX (2500 Units per Reel) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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