AN6448NFBP Speech Network IC Incorporating Cross-Point Switch ■ Overview Unit : mm 17.2±0.4 14.0±0.3 The AN6448NFBP is a speech network IC suitable for multifunction cordless telephones. It incorporates a cross-point switch controlled by serial input. It allows speech path switching and mixing, and provides for three- or four-person communication and other sophisticated functions. It also incorporates REC/PLAY amplifiers with VOX circuits. 48 33 32 64 17 14.0±0.3 17.2±0.4 49 ■ Features • • • • 16 +0.1 1 (0.8) +0.1 0.8 0.35 -0.05 SEATING PLANE QFP package with 64 pins (QFH064-P-1414A) ■ Block Diagram 48 49 50 47 46 45 – + 44 – + 43 42 40 38 37 36 35 34 33 32 VOX Det. 0dB 0dB 51 39 ACL Det ACL VREF 41 Comp 0dB 31 I N J 10dB 52 0/12 dB 18 dB 18 dB 20 dB 28 54 27 0dB 58 0dB 61 Power Supply Control 59 26 25 24 23 22 P.O.R DC Cont. Line Supply Monitor 0dB AP 62 VREF 63 2 3 4 5 6 7 DM Cont. AP AP Cont. 64 1 D a1 a2 a3 a4 a5 a6 Decoder 57 Latch 0dB Hold off – + 56 0dB 8 9 10 19 0dB 20 dB 11 12 13 – + 14 15 21 20 0dB – + 55 60 30 29 – + 53 1.3±0.1 0.1±0.1 • nal power supply, and is operational even during a commercial power failure. Incorporates auto. PAD, dial mute, DC voltage regulation, and other basic speech functions. The cross-point switch can be operated independently. Each output of the cross-point switch can correspond to multiple inputs, allowing three-or four-person communication. The REC/PLAY amplifiers incorporate ALC and VOX circuits. Receiver volume can be increased by 6 dB or 9 dB. 0.2 -0.05 1.3±0.1 2.85±0.2 • The speech block can operate on line voltage, with no exter- 18 17 16 ■ Absolute Maximum Ratings (Ta=25˚C) Parameter Symbol Rating Unit Supply voltage (1) VCC 7.0 V Supply current (1) ICC 50 mA Supply voltage (2) VL 12.0 V Supply current (2) IL 135 mA mW Power dissipation Note) PD 640 Operating ambient temperature Topr –20 to +75 ˚C Storage temperature Tstg –55 to +150 ˚C Note) In a free-air condition with Ta=75˚C. ■ Recommended Operating Conditions (Ta=25˚C) Parameter Symbol Condition min typ max Unit 5 5.5 V Operating supply voltage range (1) VCC 4.5 Operating supply voltage range (2) VL 3 Clock frequency fCLK 11 V 250 kHz max Unit ■ Electrical Characteristics (Ta=25˚C) Parameter Symbol Condition min typ 30.5 32.5 34.5 dB 2.5 3.7 5 dB 27.7 29.7 31.7 dB Speech network block Rec. gain GV–ER1 Rec. automatic PAD width AP–ER Trans. gain GV–EM1 Trans. automatic PAD width AP–EM DTMF gain GV–ED1 DTMF automatic PAD width AP–EDT IL=30mA, VCC=5V, Vin=–42dBm IL=30 to 80mA, VCC=5V, Vin=–42dBm IL=30mA, VCC=5V, Vin=–38dBm IL=30 to 80mA, VCC=5V, Vin=–38dBm IL=30mA, VCC=5V, DM=ON, Vin=–30dBm IL=30 to 80mA, VCC=5V, V–DMC=LOW, Vin=–30dBm 2.5 4 5 dB 16.9 18.9 20.9 dB 2.5 4.1 5.5 dB 145 180 215 µA –13.4 –11.4 –9.4 dBm 27.8 29.8 31.8 dB REC/PLAY amp. block Head bias current I–REC REC preamp. output VO–RP Vin=–45dBm, Rin=10kΩ EQ amp. gain GV–EQ Vin=–40dBm SP out max output VO–SP Input L-SP IN, THD=5% 0 4 dBm DH out max output VO–DH Input RF1 IN, THD=5% 0 4 dBm RF1 out max output VO–RF1 Input RF2 IN, THD=5% 0 4 dBm RF2 out max output VO–RF2 Input RF1 IN, THD=5% 0 4 dBm L-REC out max output VO–LR Input AUX IN, THD=5% 0 4 dBm Switch block ■ Timing Chart 1/fCLK twh tWL (CLK) 90% 90% CLK 10% 2.5V DATA tsu 2.5V 2.5V 10% 2.5V tr (CLK) tf (CLK) (CLK) 2.5V (DATA) th (DATA) tsu tsr (STB) (STB) 2.5V STR 2.5V tW (STB) ■ Pin Descriptions Pin No. Description Pin No. Description 1 Ground 33 RF2 link output 2 Line power (+) input 34 RF1 link output 3 Side-tone adjustment 35 Intercom link output 4 Line voltage control (1) 36 VOX detection control 5 Int. ref. voltage output (1) 37 VOX amp. input 6 Int. ref. voltage output (2) 38 Time stamp link output 7 Hold-reset control 39 Recording link output 8 Trans. preamp. output 40 ALC input 9 Auto. PAD control 41 ALC detection control 10 Rec. preamp. input 42 Loudspeaker link input 11 Rec. preamp. output 43 Recording input 12 Rec. amp. input 44 Recording inverse input 13 Rec. amp. output (1) 45 Recording preamp. output 14 Rec. amp. output (2) 46 Recording bias current control 15 MIC preamp. output 47 To recording head 16 MIC preamp. input (1) 48 EQ amp. inverse input 17 MIC preamp. input (2) 49 EQ amp. output 18 DTMF signal input 50 REC/PLAY int. ref. voltage output 19 BT signal input 51 Ground 20 Dial mute control 52 MIX preamp. output 21 Line voltage control 53 MIX link input 22 Line interruption detector output 54 AUX preamp. output 23 Hold-reset signal output 55 AUX link input 24 No connection 56 Intercom link input 25 Strobe signal input 57 RF1 link input 26 Clock signal input 58 RF2 link input 27 No connection 59 Power-ON reset control 28 Data input 60 External supply voltage input 29 Ground 61 Internal supply voltage output 30 Logic power supply input 62 Circuit voltage control (2) 31 VOX detector output 63 Line current bypass (2) 32 SP link output 64 Line current bypass (1) ■ Pin Descriptions PinNo. Symbol I/O Waveform 1 GND 0V DC 2 VL 3 ST L– 4 V CONT I 3 to 10V O DC 0.3V I DC1V 1V 5 VREF O (Const) VREF– 6 SN 1V (Const) O IL VCC 23 HCC 0V Hold-reset signal 8 T– FILTER O DC1V 10 RV IN RV 11 PRE– OUT I I O 12 RV FILTER O RV 13 OUT (1) · RV 14 OUT (2) Equivalent Circuit Vreg-R · I IL VREF VREF VREF VREF O VREF Remarks GND for REC/PLY, VRER SPEECH and LINK. Line power input : • Connects to the positive output of the diode bridge. The line drive gain (G) is : Z //ZTel G = Line R1 Also assuming ZLine 600Ω ZTel 600Ω R1=27Ω : 2 TO Side-tone adjustment : • Grounded through R1 (27Ω). • Connects to the side-tone adjusting circuit to adjust side tone and receiver level. 300 =20.9dB 27 C2 and the internal resistance determine the f. characteristics. 3 G=20log Line voltage control (1) : Int. ref. voltage output (1) : • Outputs half the Vreg reference voltage. • Grounded through a 0.01µF capacitor. 61 Vreg 24kΩ 5 + 24 kΩ – 62 + – 6 Int. ref. voltage output (2) : • Output impedance=50Ω Hold-reset control : • Grounded through C5. Adjusts the output time of control signals. 7 HCO 9 APC Description Ground : • This is the ground pin for the speech network. Hold-reset signal output : • This is an open-collector output to a microprocessor. • Requires a pull-up resistor. The larger the capacitance of C5, the wider the pulse width. 30kΩ 7 + – 120kΩ 4 Trans. preamp. output : • C6 as connected between this pin and the ground forms a low-pass filter. Auto. PAD control : • Connects through a resistance to Pin61 (Vreg). If the resistance increases, the PAD operates closer to the near end. If the resistance decreases, the PAD operates closer to the far end. Rec. preamp. input : • Receiver signals are input from the side-tone circuit to this pin. • R7 and C8 connected between Pin11 and this pin determine Rec. preamp. output : • R7 and C8 connected between Pin10 and this pin determine the f. characteristics. • The output impedance is 100 ±50Ω. 23 C6 and the 6-kΩ internal resistance as illustrated on the left form a low-pass filter. 6kΩ 8 9 I IχIL + 10 11 – 10kΩ + – The receiver preamplifier gain (G) is : 1 1 +ωC8 G= –20log R7 1 R6 + ωC9 11 Rec. amp. input : Rec. amp. outputs (1 and 2) : • A ceramic or dynamic receiver is connected. • The output circuit is a BTL configuration. • The output impedance is 50± 30Ω. 13 + – 14 12 The larger the capacitance of C10, the lower the high band gain as with a LPF. ■ Pin Descriptions (cont.) PinNo. Symbol I/O 15 MIC OUT O VREF MIC 16 IN (+) I MIC 17 IN (–) I MF– 18 IN Waveform VREF I With signal ON I VREF With signal ON 20 DMC VCC DC– 21 CONT I 0.2V Line voltage increases VCC 22 CPC O 0.2V Line interruption 24 NC 5V 25 STR I 0V 5V 26 CLK I 0V 27 NC VREF 10kΩ 16 + + 17 – – 15 Remarks Feedback is input to this pin through a capacitor. The capacitor and R9 to R11, and C12 and C13 determine the f. characteristics. MIC preamp. input (2) : • R11 and C13 connected between Pin15 and this pin determine the f. characteristics. DTMF signal input : • DTMF signals are input through a coupling capacitor C14. • When DMC is low at Pin20, DTMF is enabled. • Input impedance is 10kΩ. BT signal input : • Beep tone (BT) signals are input through a coupling capacitor C15. • Input impedance is 10kΩ. Dial mute control : • Normal speech mode when Pin20 is high or open (MIC amp. ON and rec. amp. ON). • DTMF mode when Pin20 is low (DTMF amp. ON and BT amp. ON). I Equivalent Circuit MIC preamp. output : • R11 and C13 connected between Pin17 and this pin determine the f. characteristics. • The output impedance is 300 ±100Ω. MIC preamp. input (1) : • A bias resistor and a microphone connect to this pin. VREF 19 BT– IN Description Line voltage control : • Line voltage is normal when this pin is high. Line voltage increases by 1 to 1.5V when this pin is low. Line interruption detector output : • This is an open collector output to a microprocessor, requiring a pull-up resistor connected to the microprocessor's power supply. This pin goes low when line voltage is 3.0V or more, and goes high when 1.5V or less. No connection Strobe signal input : • The strobe signal for serial control data is input to this pin. The rising edge of the strobe signal determines the timing at which internal control address or ON/OFF status is validated. Clock signal input : • The clock signal for serial control data is input to this pin. The rising edge of the clock signal determines the timing at which data is read. No connection VREF/SN 10kΩ 18 + – The input impedance (10kΩ) and C14 or C15 form an input HPF. VREF 10kΩ 19 + – 61 200kΩ 20 100kΩ 150kΩ 21 200kΩ VL 2 R2 144kΩ R1 22 TrCPC 56kΩ 25 VCC 10kΩ 300kΩ 26 10kΩ 300kΩ VCC • Referring to the left figure, the voltage, VCPC, at which T rCPC turns ON is calculated as follows: VCPC (ON) = R1 + R2 × VBE (TrCPC) R1 = 2.5V (Ta=25˚C) ■ Pin Descriptions (cont.) PinNo. Symbol I/O Waveform 5V 28 DATA I 0V Description Data input : • Serial data is input to this pin. Data is read into the internal shift register in synchronization with clock signals. 29 GND Ground : • This is the ground pin for the logic circuits. L– 30 V CC Logic power supply input : VCC 31 VOX. O OUT 32 SP. OUT 33 0V Voice on O VREF RF2 – O OUT VREF Equivalent Circuit VCC 28 10kΩ 300kΩ VOX detector output : • This is an open collector output. • This pin goes low when voice signals are input to Pin37. Loudspeaker link output : • This is a link switch output to an external loudspeaker amplifier. • The output amplifier gain is selectable between 12 and 0dB. • Output impedance is 50±30Ω. RF2 link output : • This is a link switch output. • Output impedance is 50±30Ω. Remarks • Output waveforms are shaped stable internally (by the threshold circuit). 31 VREF LINK From LINK SW 50kΩ 0/12dB + 32 – 30kΩ 10kΩ VREF VREF LINK From LINK SW 50kΩ 33 34 + – 34 RF1 – O OUT VREF When address 2F of the crosspoint switch is OFF, the output amplifier gain is set to 12 dB. RF1 link output : • This is a link switch output. • Output impedance is 50±30Ω. 10kΩ 68kΩ VREF 35 36 DH – OUT O VOX DET O VREF DC (with a capacitor) Pin36 output Pin37 input (with no capacitor) Half-wave rectification Intercom link output : • This is a link switch output to a intercom. • Output impedance is 50±30Ω. VOX detection control : • A smoothing capacitor (C17) and a resistor (R19) connect in parallel to this pin to adjust the attack and recovery times of the VOX detector. LINK From LINK SW 50kΩ + 35 – 10kΩ 90kΩ VREF + 37 500Ω – 500Ω R1 36 37 VOX IN I VOX amp. input : • VOX (voice detection) signals are input to this pin. • Input impedance is 500Ω. C1 • VOX detection can be done in two ways : A) With small C17 (560pF) and small R19 (39kΩ) VOX input VOX output B) With large C17 (22µF) and large R19 (100kΩ) VOX input VOX output • Input sensitivity is calculated as follows : R2 R2//ZC1 R1 Adjust the f. characteristics and sensitivity based on the above calculation. G= ■ Pin Descriptions (cont.) PinNo. Symbol I/O LTS – 38 OUT 39 Waveform O VREF LRC – O OUT 40 ALC. IN VREF Description Time stamp link output : • This is a buffered link switch output. • Output impedance is 50±30Ω. Equivalent Circuit LINK To LINK SW 38 39 + – Recording link output : • This is a buffered link switch output. • Output impedance is 50±30Ω. ALC input : • Pin45 connects through a coupling capacitor to this pin. • Input impedance is 10kΩ. I Remarks VCC VREF + 41 ALC. DET – 42 SP IN RD 43 PRE – IN RD 44 PRE – NF REC 45 PRE – OUT O DC (with a capacitor) Pin$1 output Input (with no capacitor) Full-wave rectification I VREF I VREF I VREF O VREF 46 BIAS ADJ VREF 47 HEAD I/O Bias voltage During recording 0V During playing 48 EQ. NF 49 EQ. OUT 50 VREF – PR I 0V VREF O VREF O 1 2 VREF (CONST) ALC detection control : • A smoothing capacitor (C20) and a resistor (R22) connect in parallel to this pin to adjust the attack and recovery times of the ALC. Loudspeaker link input : • SP signals to this pin are output through a coupling capacitor to the link switch. • Input impedance is 50kΩ. Recording input : • Recording signals are input through a coupling capacitor to this pin. • Input impedance is normally 10 kΩ. It decreases during ALC operation. Recording preamp. inverse input : • A C/R combination between Pin45 and this pin determines the gain and f. characteristics of the recording preamplifier. 40 – 41 VREF To recording head : • A recording head connects to this pin. 42 – 50kΩ VREF 10kΩ 43 + – REC/PLAY int. ref. voltage output : • The pin5 ref. voltage is buffered and output from this pin. 22kΩ 10kΩ From ALC + The gain (G) of the recording preamplifier is : 45 – G=– 44 VCC + – 46 47 R27 VREF + From recording head 49 – 48 VREF 5 + – 50 1 ωC23 • Address 07 of the cross-point SW determines the ON/OFF status of the rec. preamp. • The bias current to the head is : Vref ×3 IH = R27 1 Vref = VREG 2 61 45 R26 R24 + EQ amp. inverse input : • A C/R combination between pin49 and this pin determines the equalizer characteristics. EQ amp. output : • Outputs amplified equalizer signals. • Output impedance is 50±30Ω. LINK To LINK SW + Recording preamp. output : • Outputs amplified recording signals. • Output impedance is 50±30Ω. Recording bias current control : • A C/R combination connected to this pin determines the recording bias current and gain of a recording head. • The smaller the resistance of the C/R combination, the greater the bias current and gain. 2kΩ • Ground Pin41 if no ALC circuit is used. • The larger C20, the longer the attack time. The smaller R22, the shorter the recovery time. • The gain of the equalizer amp. is calculated the same way as the receiver preamp. • Address 0F of the cross-point SW determines the ON/OFF status of the EQ amp. ■ Pin Descriptions (cont.) PinNo. Symbol I/O Waveform Description 51 GND Ground : • Output impedance is 50±30Ω. 52 MIX OUT MIX preamp. output : • A C/R combination between Pin53 and this pin determines the gain and f. characteristics of the MIX preamp. • Output impedance is 50±30Ω. 53 MIX IN AUX 54 OUT 55 AUX IN 56 DH IN 57 RF1 IN O VREF I MIX link input : • MIX signals are input through a coupling capacitor to this pin. O AUX preamp. output : • A C/R combination between Pin55 and this pin determines the gain and f. characteristics of the AUX preamp. • Output impedance is 50±30Ω. VREF I AUX link input : • AUX signals are input through a coupling capacitor to this pin. I Intercom link input : • Intercom signals are input through a coupling capacitor C33 to this pin. • Input impedance is 10kΩ. VREF I VREF RF1 link input : • RF1 signals are input through a coupling capacitor C34 to this pin. • Input impedance is 10kΩ. Equivalent Circuit VREF + I 53 The gain of the MIX preamp. is calculated the same way as the rec. preamp. To LINK SW The gain of the AUX preamp. is calculated the same way as the rec. preamp. 52 VREF + – 55 54 VREF 10kΩ 56 To LINK SW + – The input impedance as illustrated left and C33, C34, or C35 form a HPF. VREF 57/58 10kΩ RF2 link input : • RF1 signals are input through a coupling capacitor C34 to this pin. • Input impedance is 10kΩ. VREF To LINK SW – To LINK SW + 58 RF2 IN – VCC 59 PR Power-ON reset control : • C36 between this pin and GND determines the power-ON reset time of the logic circuits. I 5V 60 VCC ±0.5V VCC – 0.2V 61 Vreg O DC 2V during power failure 50kΩ 59 + Comparator 150kΩ – Reset signal • The larger C36, the longer the power-ON reset time. • The power-ON reset signal is output when the supply voltage reaches 4V. External supply voltage input : • 5 ± 0.5 V power supply is input to this pin. VL Internal supply voltage output : • A power supply derived from line voltage is output from this pin to the internal speech network. 2 61 2 62 VLC Remarks Circuit voltage control (2) : 2-5 VDC depending on VL • This pin is grounded through C38. 64 C38 (typically 47µF) determines how the circuit voltage fluctuates. 62 63 ■ Pin Descriptions (cont.) Waveform DC 63 PD2 64 PDI O 0 to 3V depending on VL DC I Same as above VL– 33Ω × IL Equivalent Circuit Description Remarks ZTel is 1.5 to 2kΩ on the IC side. It must be adjusted to 600Ω by inserting a 820Ω resistor between VL and GND. 2 VL Line current bypass (2) : • Line current is bypassed from this pin through R39 to GND. R39 must be 1/2 W or more. 33Ω 64 Power supply PinNo. Symbol I/O Line current bypass (1) : • Line current is bypassed from this pin through R40 to Pinw. R40 must be 1/2 W or more. 64 R40 VL 33Ω 820Ω 63 100µ 15Ω ■ Logic Specifications (Basic Block Diagrams) Output (cross-point SW and other controls) Latch circuit Reset Decoder (6 bit, 48 channels) Decoder A6 Shift register A5 A4 A3 A2 D A1 Clock Data Strobe Time charts (assuming the address h26 latch is to be set) Clock Data 1 0 0 1 1 0 1 (A6) (A5) (A4) (A3) (A2) (A1) (D) Strobe 1. Data is read into the shift register in synchronization with a rising edge of the clock, with the higher data being shifted sequentially on a first-come highest-bit basis. 2. When the strobe is low, data is shifted sequentially on the sift register in synchronization with the clock. Data on the latch circuit will not change. 3. When the strobe goes high, the latched data whose address is represented by the highest 6-bit of the shift register is updated. Latched data is set when the least significant bit is 1, and reset when the bit is 0. 4. Referring to 3 above, if the address is h00 (the highest 6bit of the shift register are all 0s), the latch circuit is cleared (all reset) regardless of the data content. 5. At power-on, the latch circuit is cleared (by power-ON reset). ■ Logic Circuits Address Specifications 1. Cross-point switch Input Output Handset rec. Line output Loudspeaker Intercom RF1 RF2 Recording 0B 0C 0D 0E Time stamp 02 Loudspeaker 09 Microphone 0A Receiver 10 12 14 15 16 Intercom 18 1A 1C 1D 1E RF1 20 21 23 RF2 28 29 2B MIX 30 31 32 33 34 35 AUX 38 39 3A 3B 3C 3D 25 2C Note) Empty space means “not applicable.” Address is in hexadecimal. 2. Other control switches (Address) 00 07 0F 17 1F 27 2F (Description) All reset Recording amp. ON Playing amp. ON Receiver volume 6 dB up Receiver volume 9 dB up (when address 17 is on) Handset receiver amp. mute Loudspeaker amp. gain 12 dB down Note) Address is in hexadecimal. ■ Package power dissipation PD – Ta Power Dissipation PD (mW) 1600 1400 1200 1000 900mW 800 600 640mW 400 200 0 0 25 50 75 100 125 150 Ambient Temperature Ta (˚C) 26 2E 37 3E ■ Application Circuit EQ. OUT ALC IN LINK SP– IN LINK R– OUT C23 0.1µF 46 45 44 43 40 39 38 37 36 RF2. OUT DH. OUT 35 RF1. OUT C17 R20 R19 10kΩ VOX. 560pF DET VOX. IN C18 10kΩ 0.033µF TS. OUT LINK. REC. OUT JP3 41 C19 100kΩ 42 ALC. 22µF DET C20 ALC. IN 0.068µF 10kΩ REC. IN 10kΩ 0.15µF R21 J4 JP2 R23 C22 0.068µF C21 C24 22µF R27 REC. ADJ 47 VOX IN C25 12kΩ REC. PRE. OUT R26 R25 56kΩ 1kΩ REC. PRE. NF R24 47kΩ 48 0.47µF R26 EQ. IN P.R. HEAD 10kΩ R30 R29 C27 0.01µF R31 330kΩ 1kΩ C26 22µF C42 1µF PLAY IN REC OUT To test the circuit, short R41 and use a 1kΩ resistor for a head. 34 33 SP. OUT 49 – + 100µF 32 – + ALC Det ALC 50 C28 0dB Vref P/R. VREF R43 120kΩ VOX Det. VOX. OUT 31 COMP 0dB 0dB 51 I N J 10dB P/R. GND LOGIC. VCC 100µF 30 C16 MIX. OUT SP R34 + – R37 RF2. IN R38 0.068µF C35 MIC a1 LIN 56 0dB a2 Latch 57 0dB 58 Decoder RF2 a4 MIX a5 C39 100µF C37 61 VREG DC Cont. AP DM Cont. AP Hold off 62 47µF VLC C39 0dB 0.068µF DYMF. IN C14 0dB 17 + – J3 14 15 16 R9 10kΩ C11 0.1µF R– OUT (2) 0.001µF R7 47kΩ 13 R. FILTER C8 12 R– OUT (1) 11 R. PreOUT 10 R. PreIN T. FILTER R8 6.8kΩ HCO 0.01µF C6 C4 22µF 9 0.068µF 820kΩ R4 C1 2.7kΩ R5 121kΩ J1 Side-tone circuit 8 + C7 R6 0.1µF APC C9 12kΩ 0.022µF R3 4.7kΩ JP1 7 + Vref2 6 Vref1 100µF C3 5 + VL. CONT 0.01µF 22µF ST C2 + – 4 R2 470 100 µF 3 VL GND 2 18 10kΩ 20 dB PD1 1 SW2 19 0dB + – GND Open DM. CONT 20 BT. IN C15 64 R33 R13 AP Cont. PD2 R1 27 R15 VL Vref 63 R40 DC. CONT 21 0dB Line Supply C5 C38 CPC 22 VREG Power Supply Control 60 100µF HCC 23 P.O.R 10µF PRC VCC 24 a6 (R36 to 38 : for level adjustment) 0.068µF C36 59 a3 NC AUX 0dB STR 25 DH RF1 CLK 26 0.068µF MIC. IN (–) C13 0.0015µF RF1. IN 0.068µF C34 D R11 27kΩ 55 27 NC SP R10 10kΩ 0.068µF AUX. IN R38 C33 DH. IN 10kΩ DATA 28 MIC. OUT MIC. IN C32 R35 20kΩ 54 DH AUX. OUT LIN REC OUT 20 dB RF2 0/12 dB LOGIC. GND 18 dB TS OUT 18 dB + – 53 MIX. IN RF1 0.068µF 10kΩ 29 R32 C30 20kΩ 52 R33 C12 0.068µF MIC MIC. IN (+)