ETC TW2834

TW2834
4 Channel Video QUAD/MUX Controller
For Security Applications
Preliminary Data Sheet from Techwell, Inc.
Information may change without notice
Disclaimer
This document provides technical information for the user. Techwell Inc. reserves the right
to modify the information in this document as necessary. The customer should make sure
that they have the most recent data sheet version. Techwell Inc. holds no responsibility for
any errors that may appear in this document. Customers should take appropriate action to
ensure their use of the products does not infringe upon any patents. Techwell Inc. respects
valid patent rights of third parties and does not infringe upon or assist others to infringe
upon such rights.
Techwell, Inc.
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1
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Table of Contents
Introduction........................................................................................................................................... 5
Features ............................................................................................................................................. 5
Applications ...................................................................................................................................... 6
Block Diagram .................................................................................................................................. 7
Pin Diagram ...................................................................................................................................... 8
Pin Description ................................................................................................................................. 9
Functional Description ....................................................................................................................... 14
Video Input ..................................................................................................................................... 14
Analog Video Input ...................................................................................................................... 15
Anti-aliasing Filter ................................................................................................................... 16
Analog-to-Digital Converter .................................................................................................... 16
Sync Processing........................................................................................................................ 17
Color Decoding ........................................................................................................................ 18
Luminance Processing.............................................................................................................. 20
Chrominance Processing .......................................................................................................... 21
Digital Video Input....................................................................................................................... 23
Digital Video Input Format ...................................................................................................... 23
Channel ID Decoder ................................................................................................................. 24
Cropping and Scaling Function .................................................................................................... 26
Cropping Function.................................................................................................................... 26
Scaling Function....................................................................................................................... 28
Motion Detection ............................................................................................................................ 32
Mask and Detection Region Selection ......................................................................................... 33
Sensitivity Control ....................................................................................................................... 34
Level Sensitivity....................................................................................................................... 34
Spatial Sensitivity..................................................................................................................... 34
Temporal Sensitivity ................................................................................................................ 34
Velocity Control ........................................................................................................................... 35
Blind Detection ............................................................................................................................ 37
Video Control ................................................................................................................................. 38
Channel Input Selection ............................................................................................................... 39
Channel Operation Mode ............................................................................................................. 40
Live Mode ................................................................................................................................ 40
Strobe Mode ............................................................................................................................. 41
Switch Mode............................................................................................................................. 43
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Channel Attribute ......................................................................................................................... 47
Background Control ................................................................................................................. 47
Boundary Control ..................................................................................................................... 47
Blank Control ........................................................................................................................... 47
Freeze Control .......................................................................................................................... 47
Last Image Capture .................................................................................................................. 48
Horizontal / Vertical Mirroring ................................................................................................ 48
Display Path Control .................................................................................................................... 49
Save and Recall Function ......................................................................................................... 49
Image Enhancement ................................................................................................................. 50
Zoom Function ......................................................................................................................... 50
Picture Size and Popup Control................................................................................................ 51
Dummy Channel Function........................................................................................................ 52
Record Path Control ..................................................................................................................... 53
Normal Record Mode ............................................................................................................... 54
Frame Record Mode ................................................................................................................. 55
DVR Normal Record Mode...................................................................................................... 56
DVR Frame Record Mode........................................................................................................ 57
Realtime Record/Playback Mode ............................................................................................. 58
Playback Path Control .................................................................................................................. 59
Normal Record Mode ............................................................................................................... 60
Frame Record Mode ................................................................................................................. 61
DVR Normal Record Mode...................................................................................................... 63
DVR Frame Record Mode........................................................................................................ 64
Real-time Record/playback Mode ............................................................................................ 65
Real-time Record/Spot Mode ................................................................................................... 66
Channel ID Encoder ..................................................................................................................... 67
Channel ID Information ........................................................................................................... 67
Analog Type Channel ID in VBI.............................................................................................. 69
Digital Type Channel ID in VBI .............................................................................................. 70
Digital Type Channel ID in Channel Boundary ....................................................................... 71
Active Line number.................................................................................................................... 71
Chip-to-Chip Cascade Operation ................................................................................................. 72
Channel Priority Control .......................................................................................................... 72
120 CIF/Sec Record Mode ....................................................................................................... 74
240 CIF/Sec Record Mode ....................................................................................................... 75
480 CIF/Sec Record Mode ....................................................................................................... 76
Realtime Record Mode............................................................................................................. 77
Infinite Cascade Mode for Display Path .................................................................................. 78
OSD (On Screen Display) Control ............................................................................................... 79
Character/Bitmap Overlay........................................................................................................ 80
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Download Font Group .............................................................................................................. 80
Write Character and Select Font Group ................................................................................... 82
Character Attribute ................................................................................................................... 84
Box Overlay ................................................................................................................................. 85
Single Box ................................................................................................................................ 85
2Dimensional Arrayed Box ...................................................................................................... 87
Mouse Pointer .............................................................................................................................. 90
Video Output .................................................................................................................................. 91
Analog Video Output ................................................................................................................... 92
Output Standard Selection........................................................................................................ 92
Luminance Filter ...................................................................................................................... 93
Chrominance Filter................................................................................................................... 93
Digital-to-Analog Converter .................................................................................................... 94
Digital Video Output .................................................................................................................... 95
Single Output Mode ................................................................................................................. 96
Dual Output Mode.................................................................................................................... 97
Timing Interface and Control ....................................................................................................... 98
Host Interface...................................................................................................................................... 99
Serial Interface ............................................................................................................................. 100
Parallel Interface.......................................................................................................................... 102
Interrupt Interface ....................................................................................................................... 104
Control Register ........................................................................................................................... 105
Register Map .............................................................................................................................. 105
Recommended Value.................................................................................................................. 115
Register Description................................................................................................................... 120
Parametric Information .................................................................................................................... 237
DC Electrical Parameters ............................................................................................................ 237
AC Electrical Parameters ............................................................................................................ 239
Application Schematic ...................................................................................................................... 243
Package Dimension........................................................................................................................... 244
Revision History ................................................................................................................................ 245
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4
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Introduction
The TW2834 has four high quality NTSC/PAL video decoders, dual color display controllers and
dual video encoders. The TW2834 contains four built-in analog anti-aliasing filters, four 10bit
Analog-to-Digital converters, proprietary digital gain/clamp controller, high quality Y/C separator
to reduce cross-noise and high performance free scaler. Four built-in motion and blind detectors
can increase the feature of security system. The TW2834 has flexible video display controller
including basic QUAD and MUX functions. The TW2834 also has excellent graphic overlay
function that displays character/bitmap for OSD, single box, 2D array box, and mouse pointer.
The built-in channel ID CODEC allows auto decoding and displaying during playback and the
additional scaler on the playback supports multi-cropping function of the same field or frame
image. The TW2834 contains two video encoders with four 10bit Digital-to-Analog converters for
providing 2 composite or S-video. The TW2834 also can be extended up to 8/16 channel video
controller using chip-to-chip cascade connection.
Features
Four Video Decoders
Accepts all NTSC/PAL standard formats with auto detection
Integrated four analog anti-aliasing filters and four 10 bit CMOS ADCs
High performance adaptive comb filters for all NTSC/PAL standards
IF compensation filter for improvement of color demodulation
PAL delay lines for correcting PAL phase errors
Programmable hue, saturation, contrast, brightness and sharpness
High performance horizontal and vertical scaler for each path including playback input
Fast video locking system for non-realtime application
Four built-in motion detectors with 16X12 cells and blind detectors
Additional digital input for playback with ITU-R BT.656 standard
Auto cropping / strobe for playback input with Channel ID decoder
Supports four channel full D1 record and playback mode
Dual Video Controllers
Full Live/Strobe/Switch function
Various channel attribute control
Supports pseudo 8 Channel or Dual page mode
Horizontal / Vertical Mirroring for each channel
Last image capture when video-loss detected
Auto sequence switch with 128 queues and/or manual switch by interrupt for record path
Channel skip in Auto sequence switch for record path when video-loss detected
Image enhancement for zoomed or still image in display path
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
High performance 2X zoom to horizontal and vertical direction for display path
Supports save and recall function for display path
Extendable up to 8/16 channel video controller using cascade connection
Quad MUX switch with 32 queues and/or manual control by interrupt for record path
Character/Bitmap overlay for OSD with 720x480 resolution in NTSC / 720x588 in PAL
Sixteen programmable single boxes overlay
Four 2D arrayed boxes overlay with dual color for motion result or table display
Mouse pointer overlay
Analog/Digital Channel ID Encoder
Dual Video Encoders
Dual path digital outputs with ITU-R BT.656 standard
Dual path analog outputs with all analog NTSC/PAL standards
Programmable bandwidth of luminance and chrominance signal for each path
Four 10bit video CMOS DACs
Applications
Analog QUAD/MUX System
4/8/16 Channel DVR System
Car Rear Vision System
Hair Shop System
Dental Care System
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Block Diagram
ADDRX/BA1X/BA0X/RASBX/CASBX/WENBX/DQM X/DATAX
VIN0B
Video
Decoder
Channel ID
Decoder
8x1
VIN0A
ITU-R BT656
Decoder
MUX
PBCLK
PBIN
Scaler
Memory Interface
Scaler
Motion Detect
VIN1B
Video
Decoder
8x1
VIN1A
MUX
Write
Control
Read
Control
Scaler
Zoom
&
Image
Enhance
OSD
Box
Mouse
Overlay
Video
Encoder
VOUTYX
VOUTCX
ITU-R BT656
Encoder
VDOUTX
Scaler
Motion Detect
HSENC
VSENC
FLDENC
LINK
VIN3A
VIN3B
HSPB
HCSB0
HCSB1
HALE
HRDB
HWRB
HDAT
8x1
Scaler
Scaler
Motion Detect
Video
Decoder
HOST Interface
Write
Control
Read
Control
Scaler
Scaler
Motion Detect
Channel
ID
Encoder
OSD
Box
Mouse
Overlay
Video
Encoder
VOUTYY
VOUTCY
ITU-R BT656
Encoder
VDOUTY
Memory Interface
IRQ Interface
NM IRQ
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4x4
Matrix
Video
Decoder
8x1
VIN2B
MUX
VIN2A
MUX
Encoder Timing Interface
Clock Generator
ADDRY/BA0Y/RASBY/CASBY/WENBY/DQM Y/DATAY
7
CLK27ENCX
CLK27ENCY
CLK54I
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
TW2834
(208QFP)
VSSO
DATAY[10]
DATAY[11]
DATAY[12]
VDDI
DATAY[13]
DATAY[14]
DATAY[15]
VSSI
CLK54MEMY
DQMY
WEBY
VDDO
CASBY
RASBY
BA0Y
VSSO
ADDRY[0]
ADDRY[1]
ADDRY[2]
VDDI
ADDRY[3]
ADDRY[4]
ADDRY[5]
VSSI
ADDRY[6]
ADDRY[7]
VSSI
ADDRY[8]
ADDRY[9]
ADDRY[10]
VDDI
CLK54I
DATAX[0]
DATAX[1]
VSSO
DATAX[2]
DATAX[3]
DATAX[4]
VDDO
DATAX[5]
DATAX[6]
DATAX[7]
VSSI
DATAX[8]
DATAX[9]
DATAX[10]
VDDI
DATAX[11]
DATAX[12]
DATAX[13]
VSSO
VDDI
VDOUTY[1]
VDOUTY[0]
CLK27ENCY
VSSI
LINK
HSENC
FLDENC
VSSO
VSENC
VDOUTX[7]
VDOUTX[6]
VDDO
VDOUTX[5]
VDOUTX[4]
VDOUTX[3]
VDDI
VDOUTX[2]
VDOUTX[1]
VDOUTX[0]
VSSI
CLK27ENCX
ADDRX[12]
ADDRX[11]
VSSO
ADDRX[10]
ADDRX[9]
VDDI
ADDRX[8]
ADDRX[7]
ADDRX[6]
VDDO
ADDRX[5]
ADDRX[4]
ADDRX[3]
VSSI
ADDRX[2]
ADDRX[1]
ADDRX[0]
VSSO
BA1X
BA0X
RASBX
VDDI
CASBX
WEBX
DQMX
VSSI
CLK54MEMX
DATAX[15]
DATAX[14]
VDDO
VSSI
PBIN[3]
PBIN[4]
PBIN[5]
VDDO
PBIN[6]
PBIN[7]
RSTB
VSSO
TEST
VDDDADC
VDDAADC
VIN0A
VSSAADC
VIN0B
VDDAADC
VIN1A
VSSAADC
VIN1B
VDDAADC
VIN2A
VSSAADC
VIN2B
VDDAADC
VIN3A
VSSAADC
VIN3B
VSSDADC
VSSDDAC
VSSADAC
VAOUTCX
VDDADAC
VAOUTYX
COMPX
ISETX
VREF
ISETY
COMPY
VAOUTCY
VDDADAC
VAOUTYY
VSSADAC
VDDDDAC
VSSO
VDOUTY[7]
VDOUTY[6]
VDOUTY[5]
VDDO
VDOUTY[4]
VDOUTY[3]
VDOUTY[2]
VSSI
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VDDI
PBIN[2]
PBIN[1]
PBIN[0]
VSSI
PBCLK
TRIGGER
MPPDECY[3]
VSSO
MPPDECY[2]
MPPDECY[1]
MPPDECY[0]
VDDO
MPPDECX[3]
MPPDECX[2]
MPPDECX[1]
VDDI
MPPDECX[0]
NMIRQ
HDAT[0]
VSSI
HDAT[1]
HDAT[2]
HDAT[3]
VDDI
HDAT[4]
HDAT[5]
VSSO
HDAT[6]
HDAT[7]
HWRB
VDDO
HRDB
HALE
HCSB1
VSSI
HCSB0
HSPB
DATAY[0]
VSSO
DATAY[1]
DATAY[2]
DATAY[3]
VDDI
DATAY[4]
DATAY[5]
DATAY[6]
VSSI
DATAY[7]
DATAY[8]
DATAY[9]
VDDO
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
Pin Diagram
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Pin Description
Analog Interface Pins
Name
Number
Type
VIN0A
169
A
VIN0B
171
A
VIN1A
173
A
VIN1B
175
A
VIN2A
177
A
VIN2B
179
A
VIN3A
181
A
VIN3B
183
A
VOUTYX
189
A
Analog video output
VOUTCX
187
A
Analog video output
VOUTYY
197
A
Analog video output
VOUTCY
195
A
Analog video output
COMPX
190
A
Compensation capacitance.
COMPY
194
A
Compensation capacitance.
ISETX
191
A
Current setting resistor for display path.
ISETY
193
A
Current setting resistor for record path.
A
Voltage reference.
Must be connected though 0.1uF to VSSDAC.
VREF
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192
Description
Composite video input 0A.
Must be connected through 2.2uF to input.
Composite video input 0B.
Must be connected through 2.2uF to input.
Composite video input 1A.
Must be connected through 2.2uF to input.
Composite video input 1B.
Must be connected through 2.2uF to input.
Composite video input 2A.
Must be connected through 2.2uF to input.
Composite video input 2B.
Must be connected through 2.2uF to input.
Composite video input 3A.
Must be connected through 2.2uF to input.
Composite video input 3B.
Must be connected through 2.2uF to input.
9
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Digital Video Interface Pins
Name
VDOUTX [7:0]
VDOUTY [7:0]
Number
11,12,14,
15,16,18,
19,20,
201,202,203,
205,206,207,
2,3
Type
Description
O
Digital video data output for display path or
Chip-to-chip cascade connection pin.
I/O
Digital video data output for record path or
Playback input 1
Clock of VDOUTX.
Clock phase/frequency is controlled via register.
Clock of VDOUTY.
Clock phase/frequency is controlled via register.
Encoder horizontal sync or
Chip-to-chip cascade connection pin.
Encoder vertical sync or
Chip-to-chip cascade connection pin.
CLK27ENCX
22
O
CLK27ENCY
4
O
HSENC
7
I/O
VSENC
10
I/O
FLDENC
8
I/O
Encoder field flag.
LINK
6
I/O
Chip-to-chip cascade connection pin.
PBIN[7:0]
163,162,160,
159,158,155,
154,153
I
Video data of playback input 0
PBCLK
151
I
Clock of playback input 0.
TRIGGER
150
I
Pin trigger Input for switch operation or
Chip-to-chip cascade connection pin.
MPPDECY[3:0]
MPPDECX[3:0]
149,147,146,
145,143,142,
141,139
I/O
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Multi-purpose output or
Chip-to-chip cascade connection pin.
10
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Memory Interface Pins
Name
DATAX[15:0]
ADDRX[12:0]
Number
50,51,54,
55,56,58,
59,60,62,
63,64,66,
67,68,70,
71
23,24,26,
27,29,30,
31,33,34,
35,37,38,
39
Type
Description
I/O
SDRAM data bus of display path.
O
SDRAM address bus of display path.
ADDRX[10] is AP.
ADDRX[12] can be used for PBIN 2 clock.
ADDRX[11] can be used for PBIN 1 clock.
BA1X
41
O
SDRAM bank1 selection of display path or
Can be used for PBIN 3 clock.
BA0X
42
O
SDRAM bank0 selection of display path.
RASBX
43
O
SDRAM row address selection of display path.
CASBX
45
O
SDRAM column address selection of display path
WEBX
46
O
SDRAM write enable of display path.
DQMX
47
O
SDRAM write mask of display path.
CLK54MEMX
49
O
SDRAM clock of display path.
Clock phase/frequency is controlled via register.
I/O
SDRAM data bus of record path or
PBIN 2 and PBIN 3 input.
DATAY[15:0]
ADDRY[10:0]
97,98,99,
101,102,103,
106,107,108,
110,111,112,
114,115,116,
118
74,75,76,
78,79,81,
82,83,85,
86,87
O
BA0Y
89
O
RASBY
90
O
CASBY
91
O
WEBY
93
O
DQMY
94
O
CLK54MEMY
95
O
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SDRAM address bus of record path.
ADDRY[10] is AP. or
ADDRY[10:3] is Decoder Bypass output 1/3.
ADDRY[2:0] is Decoder Bypass output 0/2 [7:5].
SDRAM Bank0 Selection of record path or
Decoder Bypass output 0/2 [4].
SDRAM row address selection of record path or
Decoder Bypass output 0/2 [3].
SDRAM column address selection of record path
or Decoder Bypass output 0/2 [2].
SDRAM write enable of record path or
Decoder Bypass output 0/2 [1].
SDRAM write mask of record path or
Decoder Bypass output 0/2 [0]
SDRAM clock of record path.
Clock phase/frequency is controlled via register.
11
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
System Control Pins
Name
Number
Type
Description
TEST
166
I
Only for the test purpose.
Must be connected to VSSO.
RSTB
164
I
System reset.
NMIRQ
138
O
Interrupt request signal.
Data bus for parallel interface.
HDAT[7] is serial data for serial interface.
HDAT[6:1] is slave address[6:1] for serial
interface.
Write enable for parallel interface.
VSSO for serial interface.
Read enable for parallel interface.
VSSO for serial interface.
Address line enable for parallel interface.
Serial clock for serial interface.
Chip select 1 for parallel interface.
VSSO for serial interface.
Chip select 0 for parallel interface.
Slave address[0] for serial interface.
HDAT[7:0]
127,128,130,
131,133,134,
135,137
I/O
HWRB
126
I
HRDB
124
I
HALE
123
I
HCSB1
122
I
HCSB0
120
I
HSPB
119
I
Select serial/parallel host interface.
CLK54I
72
I
54MHz system clock.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Power / Ground Pins
Name
VDDO
VSSO
VDDI
VSSI
Number
204,161,144,
125,105,92,
65,52,32,
13
200,165,148,
129,117,104,
88,69,53,
40,25,9
156,140,132,
113,100,84,
73,57,44,
28,17,1
208,157,152,
136,121,109,
96,80,77,
61,48,36,
21,5
Type
Description
P
Digital power for output driver. 3.3V.
G
Digital ground for output driver.
P
Digital power for internal logic. 2.5V.
G
Digital ground for internal logic.
VDDDAC
199,196,188
P
Analog power for DAC. 2.5V.
VSSDAC
198,186,185
G
Analog ground for DAC.
P
Analog power for ADC. 2.5V.
G
Analog ground for ADC.
VDDADC
VSSADC
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180,176,172,
168, 167
184,182,178,
174, 170
13
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Functional Description
Video Input
The TW2834 has 8 input interfaces that consist of 4 digital video inputs and 4 analog composite
video inputs. 4 analog video inputs are converted to digital video stream through 10 bits ADC
and luminance/chrominance processor in built-in four video decoders. 4 digital video inputs are
decoded by internal ITU-R BT656 decoder and then fed to video control part and channel ID
decoder. Each built-in video decoder has own motion detector and dual scaler. For playback
application, each scaler in display path can receive the digital video data from internal ITU-R
BT656 decoder. The structure of video input is shown in the following Fig 1.
PBIN 3
BT. 656 Decoder
PBIN 2
BT. 656 Decoder
PBIN 1
BT. 656 Decoder
PBIN 0
BT. 656 Decoder
VIN0A
VIN0B
VIN1A
VIN1B
VIN2A
VIN2B
VIN3A
VIN3B
Analog MUX
& Anti-aliasing
Filter
Analog MUX
& Anti-aliasing
Filter
Optional
PB Input
Channel ID
Decoder
8X1
MUX
Color Decoder
H/V Crop & Scaler
CH0_X
H/V Crop & Scaler
VIN0_Y
Motion
Detector
8X1
MUX
Color Decoder
H/V Crop & Scaler
CH1_X
H/V Crop & Scaler
VIN1_Y
To
Video
Control
Part
Motion
Detector
8X1
MUX
Analog MUX
& Anti-aliasing
Filter
Color Decoder
Analog MUX
& Anti-aliasing
Filter
Color Decoder
H/V Crop & Scaler
CH2_X
H/V Crop & Scaler
VIN2_Y
Motion
Detector
8X1
MUX
H/V Crop & Scaler
CH3_X
H/V Crop & Scaler
VIN3_Y
Motion
Detector
VIN0 ~
VIN3
Optional
record Output
Fig 1 The structure of video input
For the special 4ch real-time record and playback application, the TW2834 supports 4 video
decoder output and additional 3 digital video input interfaces via the SDRAM interface in record
path.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Analog Video Input
The TW2834 supports all NTSC/PAL video standards for analog input and contains automatic
standard detection circuit. Automatic standard detection can be overridden by writing the value
into the IFMTMAN and IFORMAT (0x01, 0x41, 0x81, 0xC1) registers. Even if video loss is
detected, the TW2834 can be forced to free-running in a particular video standard mode by
IFORMAT register. The Table 1 shows the video input standards supported by TW2834.
Table 1 Video input standards
Format
NTSC-M*
NTSC-J
NTSC-4.43*
Line/Fv (Hz)
Fh (KHz)
Fsc (MHz)
525/59.94
15.734
3.579545
525/59.94
15.734
4.43361875
625/50
15.625
3.579545
NTSC-N
PAL-BDGHI
PAL-N*
PAL-M*
625/50
15.625
4.43361875
525/59.94
15.734
3.57561149
PAL-NC
625/50
15.625
3.58205625
PAL-60
525/59.94
15.734
4.43361875
Notes: * 7.5 IRE Setup
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Anti-aliasing Filter
The TW2834 contains an anti-aliasing filter to prevent out-of-band frequency in analog video
input signal. So there is no need of external components in analog input pin except ac coupling
capacitor and termination resistor. The anti-aliasing filer can be bypassed via the AFIL_BYP
(0xFC) register. The following Fig 2 shows the frequency response of the anti-aliasing filter.
Magnitude Response (dB)
5
0
-5
-10
-15
-20
-25
0
2
4
6
8
Frequency (Hz)
10
12
x 10
6
Fig 2. The frequency response of anti-aliasing filter
Analog-to-Digital Converter
The TW2834 contains four 10-bit ADC (Analog to Digital Converters) to digitize the analog video
inputs. Each ADC has two analog switches that are controlled by the ANA_SW (0x22, 0x62,
0xA2, and 0xE2) register. The ADC can also be put into power-down mode by the ADC_PWDN
(0x78) register.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Sync Processing
The sync processor of the TW2834 detects horizontal and vertical synchronization signals in the
composite video signal. The TW2834 utilizes proprietary technology for locking to weak, noisy,
or unstable signals such as those from on air signal or fast forward/backward play of VCR
system.
A digital gain and clamp control circuit restores the ac coupled video signal to a fixed dc level.
The clamping circuit provides line-by-line restoration of the video pedestal level to a fixed dc
reference voltage. In no AGC mode, the gain control circuit adjusts only the video sync gain to
achieve desired sync amplitude so that the active video is bypassed regardless of the gain
control. But when AGC mode is enabled, both active video and sync are adjusted by the gain
control.
The horizontal synchronization processor contains a sync separator, a PLL and the related
decision logic. The horizontal sync separator detects the horizontal sync by examining low-pass
filtered video input whose level is lower than a threshold. Additional logic is also used to avoid
false detection on glitches. The horizontal PLL locks onto the extracted horizontal sync in all
conditions to provide jitter free image output. In case of missing horizontal sync, the PLL is on
free running status that matches the standard raster frequency.
The vertical sync separator detects the vertical synchronization pattern in the input video
signals. The field status is determined at vertical synchronization time. When the location of the
detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field
start. Otherwise, it indicates an even field.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Color Decoding
The digitized composite video data at 2X pixel clock rate first passes through decimation filter.
The decimation filter is required to achieve optimum performance and prevent high frequency
components from being aliased back into the video image. Fig 3 shows the frequency
characteristic of the decimation filter.
0
Magnitude Response (dB)
-10
-20
-30
-40
-50
-60
0
2
4
6
8
Frequency (Hertz)
10
12
x 10
6
Fig 3 The frequency characteristic of the decimation Filter
The adaptive comb filter is used for high performance luminance/chrominance separation from
NTSC/PAL composite video signals. The comb filter improves the luminance resolution and
reduces noise such as cross-luminance and cross-color. The adaptive algorithm eliminates
most of errors without introducing new artifacts or noise. To accommodate some viewing
preferences, additional chrominance trap filters are also available in the luminance path.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Fig 4 and Fig 5 show the frequency response of notch filter for each system NTSC and PAL.
0
Magnitude Response (dB)
-10
-20
-30
-40
-50
-60
0
1
2
3
Frequency (Hertz)
4
5
6
x 10
6
Fig 4 The frequency response of luminance notch filter for NTSC
0
Magnitude Response (dB)
-10
-20
-30
-40
-50
-60
0
1
2
3
Frequency (Hertz)
4
5
6
x 10
6
Fig 5 The frequency response of luminance notch filter for PAL
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Luminance Processing
The luminance signal separated by adaptive comb or trap filter is then fed to a peaking circuit.
The peaking filter enhances the high frequency components of the luminance signal via the
Y_PEAK (0x14, 0x54, 0x94, 0xD4) register. The following Fig 6 shows the characteristics of the
peaking filter for four different gain modes.
7
YPEAKFLT = 0
YPEAKFLT = 1
6
Manitude Response (dB)
5
4
3
2
1
0
0
1
2
3
4
Frequency (Hertz)
5
6
x 10
6
Fig 6 The frequency characteristic of luminance peaking filter
The picture contrast and brightness adjustment is provided through the CONT (0x11, 0x51,
0x91, 0xD1) and BRT (0x12, 0x52, 0x92, 0xD2) registers. The contrast adjustment range is
from approximately 0 to 200 percent and the brightness adjustment is in the range of ±25 IRE.
Moreover, a high frequency coring function is also embedded in TW2834 to minimize a high
frequency noise. The coring level is adjustable through the Y_H_CORE (0xF8) register.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Chrominance Processing
The chrominance demodulation is done by first quadrature mixing for NTSC and PAL. The
mixing frequency is equal to the sub-carrier frequency of NTSC and PAL. After the mixing, a
LPF is used to remove 2X carrier signal and yield chrominance components. The characteristic
of LPF can be selected for optimized transient color performance. The Fig 7 is showing the
frequency response of chrominance LPF.
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
-45
0
0.5
1
1.5
2
2.5
Frequency (Hertz)
3
3.5
4
x 10
6
Fig 7 The frequency response of chrominance LPF
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
In case of a mistuned IF source, IF compensation filter makes up for any attenuation at higher
frequencies or asymmetry around the color sub-carrier. The gain for the upper chrominance
side band is controlled by the IFCOMP (0x13, 0x53, 0x93, 0xD3) register. The Fig 8 shows the
frequency response of IF-compensation filter.
10
Magnitude Response (dB)
5
0
-5
-10
-15
1.5
2
2.5
3
3.5
4
Frequency (Hertz)
4.5
5
5.5
x 10
6
Fig 8 The frequency characteristics of IF-compensation filter
The ACC (Automatic Color gain Control) compensates for reduced chrominance amplitudes
caused by high frequency suppression in video signal. The range of ACC is from –6dB to 30dB
approximately. For black & white video or very weak & noisy signals, the internal color killer
circuit will turn off the color. The color killing function can also be always enabled or disabled by
programming CKIL (0x14, 0x54, 0x94, 0xD4) register.
The color saturation can be adjusted by changing SAT (0x10, 0x50, 0x90, 0xD0) register. The
Cb and Cr gain can be also adjusted independently by programming UGAIN (0x3C) and VGAIN
(0x3D) registers. Likewise, the Cb and Cr offset can be programmed through the U_OFF (0x3E)
and V_OFF (0x3F) registers. Hue control is achieved with phase shift of the digitally controlled
oscillator. The phase shift can be programmed through the HUE (0x0F, 0x4F, 0x8F, 0xCF)
register.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Digital Video Input
The TW2834 supports digital video input with 8bit ITU-R BT.656 standard for playback. This
digital input is decoded in built-in ITU-R BT 656 decoder and fed to the scaler block to display
scaled video data. The TW2834 supports error correction code for decoding ITU-R BT.656. The
decoded video data are also transferred to channel ID decoder part for auto cropping and
strobe function.
Digital Video Input Format
The timing of digital video input is illustrated in Fig 9.
PBCLK
PBIN[7:0]
FFh 00h 00h XY 80h 10h
80h 10h FFh 00h 00h XY Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 Cb6 Y6 Cr6 Y7 Cb8 Y8 Cr8 Y9
EAV code
SAV code
Horizontal Blanking Period
Horizontal Active Period
Fig 9 Timing diagram of ITU-R BT.656 format for digital video input
The SAV and EAV sequences are shown in Table 2.
Table 2 ITU-R BT.656 SAV and EAV code sequence
Condition
656 FVH Value
SAV/EAV Code Sequence
Field
Vertical
EVEN
Blank
EVEN
Active
ODD
Blank
ODD
Active
Horizontal
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
F
V
1
1
1
0
0
1
0
0
H
First
Second
Third
Fourth
1
0xF1
0
0xEC
1
0xDA
0
1
0xFF
0x00
0x00
0xC7
0xB6
0
0xAB
1
0x9D
0
0x80
To display the playback input in display path, PB_CH_EN (0x38) register should be set to “1”
and PB_PATH_CH (0x39) register should set properly to select playback input for each input
path.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Channel ID Decoder
The TW2834 provides channel ID CODEC for auto cropping and strobe function. The channel
ID includes the channel number, analog switch, event, region enable and field/frame mode
information. The TW2834 supports two kinds of channel ID such as User channel ID and Auto
channel ID. The User channel ID is used for customized information like system information and
date. The auto channel ID is employed for automatic identification of picture configuration. The
TW2834 also supports both analog and digital type channel ID during VBI period.
The TW2834 can receive 4 playback inputs, but channel ID detection can be supported only in
PBIN0 input from PBIN pin. The TW2834 can detect the channel ID automatically, which can be
enabled via AUTO_VBI_DET (1xC9) register. For automatic channel ID detection mode, the
playback input should be included with run-in clock. For manual channel ID detection mode, the
playback input can be included with or without run-in clock via VBI_RIC_ON (1xC9) register. In
manual detection mode, the TW2834 has several related register such as VBI_PIXEL_H_OS
(1xCA) to define horizontal start offset, VBI_FLD_OS (1xCB) to define line offset between odd
and even field, VBI_PIXEL_HW to define pulse width for 1 bit data, VBI_LINE_SIZE (1xCC) to
define channel ID line size and VBI_LINE_OS (1xCC) to define line offset for channel ID. The
VBI_MID_VAL (1xCD) register is used to define the threshold level between high and low. Even
in automatic channel ID detection mode, the line size and bit width can be discriminated by
reading of VBI_LINE_SIZE, VBI_PIXEL_HW (1xCB) register. The following Fig 10 shows the
relationship between channel ID and register setting.
Playback Input
H
V
VBI_LINE_OS + VBI_FLD_OS
VBI_SIZE
F
Analog Channel ID Type 1
Horizontal Active Period
Run-In Clock
A0 = 11000000
A1 = 11000001
VBI_MID_VAL
1
VBI_HOS
1
0
0
0
0
0
0
VBI_HW
P0 1
1
0
0
0
0
0
1
P1
Parity
Parity
Channel ID Type of each line can be detected with parity bit type.
Analog Channel ID Type 2 (Mixed Format)
Auto Channel ID
A0 = 11000000,1
1st
User Channel ID
A1 = 11000001,0
2 Bytes are auto channel ID which has odd parity and
2nd
U0 = 11000000,0
U1 = 11000001,1
2 Bytes is user channel ID which has even parity.
Fig 10 The related register for manual channel ID detection
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
The channel ID type can be discriminated by reading the CHID_TYPE (1xCF) register, which
indicates the Auto channel ID type with “1” value and User channel ID type with “0” value. The
CHID_VALID (1xCE) register indicates whether the detected channel ID type is valid or not.
When both Auto and User channel ID are mixed in the same line, the VBI_MIX_ON (1xC9)
register should be set into “1”. The channel ID data can be read through the AUTO_CHID (1xE0
~ 1xE3) register for Auto channel ID and the VIS_MAN0~7 (1xD0 ~ 1xDF) register for User
channel ID. Originally the VIS_MAN0~7 registers are used to insert the user information in the
channel ID encoding, but in read mode it indicates the decoded User channel ID information
when VBI_RD_CTL (1xC9) = “1”. This channel ID information is updated as soon as it is
detected and decoded during VBI period. For a robust error detection mode, the Auto channel
ID can be repeated two times by setting “1” into the VBI_EC_ON (1xC9) register.
The TW2834 also supports the digital channel ID decoding via the VBI_CODE_EN (1xC9)
register. The digital channel ID has priority over analog channel ID. The digital channel ID can
also be detected automatically in automatic channel ID detection. The digital channel ID also
supports the robust error detection for the Auto channel ID type via VBI_EC_ON (1xC9) register.
Additionally to detect properly the channel ID against noise such as VCR source, the channel ID
LPF can be enabled via the VBI_FLT_EN (1xC9) register.
The detailed auto strobe and cropping function will be described at “Cropping Function” section
(page 26) and “Playback Path Control” section (page 59).
Normally the channel ID is located in VBI period and auto strobe and cropping is executed after
channel ID decoding. But for some case, the channel ID can be placed in vertical active period
instead of VBI period. For this mode, the TW2834 also supports the channel ID decoding
function within vertical active period via the VAV_CHK (1xCB) register and manual cropping
function via the MAN_PB_CROP (0x38) register with proper VDELAY value.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Cropping and Scaling Function
The TW2834 provides two methods to reduce the amount of video pixel data, scaling and
cropping. The scaling function provides video image at lower resolution while the cropping
function supplies only a portion of the video image. The TW2834 also supports an auto cropping
function for playback input with channel ID decoding. The TW2834 has a free scaler for a
variable image size in display path, but has a limitation of image size in record path like as Full /
QUAD / CIF size and has a limitation of image cropping in record path as recommended value
on page 114.
Cropping Function
The cropping function allows only subsection of a video image to be output. The active video
region is determined by the HDELAY, HACTIVE (0x04 ~ 0x07, 0x44 ~ 0x47, 0x84 ~ 0x87, 0xC4
~ 0xC7), VDELAY and VACTIVE (0x09 ~ 0x0D, 0x49 ~ 0x4D, 0x89 ~ 0x8D, 0xC9 ~ 0xCD)
register. The first active line is defined by the VDELAY register and the first active pixel is
defined by the HDELAY register. The VACTIVE register can be programmed to define the
number of active lines in a video field, and the HACTIVE register can be programmed to define
the number of active pixels in a video line. This function is used to implement for panning and tilt.
The horizontal delay register HDELAY determines the number of pixel delays between the
horizontal reference and the leading edge of the active region. The horizontal active register
HACTIVE determines the number of active pixels to be processed. Note that these values are
referenced to the pixel number before scaling. Therefore, even if the scaling ratio is changed,
the active video region used for scaling remains unchanged as set by the HDEALY and
HACTIVE register. In order for the cropping to work properly, the following equation should be
satisfied.
HDELAY + HACTIVE < Total number of pixels per line
Where the total number of pixels per line is 858 for NTSC and 864 for PAL
To process full size region, the HDELAY should be set to 32 and HACTIVE set to 720 for both
NTSC and PAL system.
The vertical delay register (VDELAY) determines the number of line delays from the vertical
reference to the start of the active video lines. The vertical active register (VACTIVE)
determines the number of lines to be processed. These values are referenced to the incoming
scan lines before the vertical scaling. In order for the vertical cropping to work properly, the
following equation should be satisfied.
VDELAY + VACTIVE < Total number of lines per field
Where the total number of lines per field is 262 for NTSC and 312 for PAL
To process full size region, the VDELAY should be set to 6 and VACTIVE set to 240 for NTSC
and the VDELAY should be also set to 5 and VACTIVE set to 288 for PAL.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
The TW2834 supports an auto cropping function with channel ID decoding for playback input.
Each channel with the multiplexed playback input can be mapped into the desired position with
the auto cropping function.
If the PB_AUTO_EN (1x16) = “0”, it is manual cropping mode so that user can control cropping
with VDELAY and HDELAY register. If PB_AUTO_EN = “1”, it is auto cropping mode and the
TW2834 has several related registers for this mode such as PB_CH_NUM (1x16, 1x1E, 1x26,
1x2E), PB_CROP_MD, and PB_ACT_MD (0x38) registers.
To operate auto cropping function, the playback input should be selected for each path with
PB_CH_EN (0x38) register and the PB_AUTO_EN register should also be set into “1”. In this
case, the desired channel can be chosen by PB_CH_NUM register and it will be cropped
automatically to horizontal and vertical direction in playback input.
The PB_CROP_MD defines the record mode of the playback input such as normal record mode
or DVR record mode (refer to Record Path Control section, page 54). The PB_ACT_MD defines
an active pixel size of horizontal direction such as 720 / 704 / 640 pixels. The following Fig 11
shows the effect of auto cropping function.
Play back Input
Display Output with New position
CH3
CH2
CH0
CH1
CH1
CH0
CH2
CH3
CH0 : PB_CH_NUM0 = 0, (cropping H/V) CH1 : PB_CH_NUM1 = 1, (cropping V)
CH2 : PB_CH_NUM2 = 2, (cropping H)
CH3 : PB_CH_NUM3 = 3, (No cropping)
Fig 11 The effect of auto cropping function
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Scaling Function
The TW2834 includes a high quality free horizontal and vertical down scaler for display path.
But the TW2834 cannot use a free scaler function in record path because channel size
definition for record path has a limitation such as Full / QUAD / CIF (Please refer to “Record
Path Control” section, page 54).
The video images can be downscaled in both horizontal and vertical direction to an arbitrary
size. The luminance horizontal scaler includes an anti-aliasing filter to reduce image artifacts in
the resized image and a 32 poly-phase filter to accurately interpolate the value of a pixel. This
results in more aesthetically pleasing video as well as higher compression ratio in bandwidthlimited application. Fig 12 shows the frequency response of anti-aliasing filter for horizontal
scaling.
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
-45
0
1
2
3
4
Frequency (Hertz)
5
6
x 10
6
Fig 12 The frequency response of anti-aliasing filter for horizontal scaling
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Similarly, the vertical scaler also contains an anti-aliasing filter and 16 poly-phase filters for
down scaling. The filter characteristics are shown in Fig 13.
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Vertical Frequency/Line Rate
0.4
0.45
0.5
Fig 13 The characteristics of anti-aliasing filter for vertical scaling
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Down scaling is achieved by programming the horizontal scaling register HSCALE (0x1C ~
0x1F, 0x5C ~ 0x5F, 0x9C ~ 0x9F, 0xDC ~ 0xDF) and vertical scaling register VSCALE (0x18 ~
0x1B, 0x58 ~ 0x5B, 0x98 ~ 0x9B, 0xD8 ~ 0xDB). When no scaled video image, the TW2834 will
output the number of pixels per line as specified by the HACTIVE (0x04 ~ 0x07, 0x44 ~ 0x47,
0x84 ~ 0x87, 0xC4 ~ 0xC7) register. If the number of output pixels required is smaller than the
number specified by the HACTIVE register, the 16bit HSCALE register is used to reduce the
output pixels to the desired number.
The following equation is used to determine the horizontal scaling ratio to be written into the
16bit HSCALE register.
HSCALE = [Npixel_desired/ HACTIVE] * (2^16 – 1)
Where Npixel_desired is the desired number of active pixels per line
For example, to scale picture from full size (HACTIVE = 720) to CIF (360 pixels), the HSCALE
value can be found as:
HSCALE = [360/720] * (2^16 – 1) = 0x7FFF
The following equation is used to determine the vertical scaling ratio to be written into the 16bit
VSCALE register.
VSCALE = [Nline_desired / VACTIVE] * (2^16 - 1)
Where Nline_desired is the desired number of active lines per field
For example, to scale picture from full size (VACTIVE = 240 lines for NTSC and 288 lines for
PAL) to CIF (120 lines for NTSC and 144 lines for PAL), the VSCALE value can be found as:
VSCALE = [120 / 240] * (2^16 – 1) = 0x7FFF for NTSC
VSCALE = [144 / 288] * (2^16 – 1) = 0x7FFF for PAL
The scaling ratios of popular case are listed in Table 3.
Table 3 HSCALE and VSCALE value for popular video formats
Scaling Ratio
1
1/2 (CIF)
1/4 (QCIF)
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Format
Output Resolution
HSCALE
VSCALE
NTSC
PAL
NTSC
PAL
NTSC
PAL
720x480
720x576
360x240
360x288
180x120
180x144
0xFFFF
0xFFFF
0x7FFF
0x7FFF
0x3FFF
0x3FFF
0xFFFF
0xFFFF
0x7FFF
0x7FFF
0x3FFF
0x3FFF
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
VACTIVE
V reference
VDELAY
The effect of scaling and cropping is shown in Fig 14.
HACTIVE
HDELAY
VACTIVE * VSCALE
VACTIVE
V reference
VDELAY
H reference
HACTIVE * HSCALE
Cropping and Scaling
HACTIVE
HDELAY
H reference
Fig 14 The effect of cropping and scaling
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Motion Detection
The TW2834 supports motion detector individually for 4 analog video inputs. The built-in motion
detection algorithm uses the difference of luminance level between current and reference field.
The TW2834 also supports blind input detection for 4 analog video inputs.
To detect motion properly according to situation, the TW2834 provides several sensitivity and
velocity control parameters for each motion detector. The TW2834 supports manual strobe
function to update motion detection so that it is more appropriate for non-realtime application or
user-defined motion sensitivity control.
When motion or blind is detected in any video inputs, the TW2834 provides the interrupt request
to host via NMIRQ pin. The host processor (i.e. Micom or CPU) can take the information of
motion or blind by accessing the DET_MOTION (1x7B), DET_BLIND (1x7C), MD_MASK (2x86
~ 2x9D, 2xA6 ~ 2xBD, 2xC6 ~ 2xDD, 2xE6 ~ 2xFD) register. This status information is updated
in the vertical blank period of each input.
The TW2834 also provides the motion detection result through MPPDEC pin with the control of
MPPSET (1x50) register. The TW2834 supports an overlay function to display the motion
detection result in the picture with 2D arrayed box.
The MD_PATH (2x9E) register is used to determine which path is selected to store the motion
detection information between display and record path. In case that 64M/128M/256M/512M
SDRAM is used for display path and 16M SDRAM for record path, the MD_PATH should be set
into “0” to select the SDRAM of display path. If 16M SDRAM is used for both display and record
path, the MD_PATH should be set into “1” to use the SDRAM of record path for motion
information because of OSD page expansion of display path. When 16M SDRAM is used for
display path and no SDRAM is for record path to support the special 4ch real-time record and
playback application, the MD_PATH should be set into “0” so that no OSD page expansion for
display path can be achieved.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Mask and Detection Region Selection
The motion detection algorithm utilizes the full screen video data and detects individual motion
of 16x12 cells. This full screen for motion detection consists of 704 pixels and 240 lines for
NTSC and 288 lines for PAL. Starting pixel in horizontal direction can be shifted from 0 to 15
pixels using the MD_ALIGN (2x81, 2xA1, 2xC1, 2xE1) register.
Each cell can be masked via the MD_MASK (2x86 ~ 2x9D, 2xA6 ~ 2xBD, 2xC6 ~ 2xDD, 2xE6 ~
2xFD) register as illustrated in Fig 15. If the mask bit in specific cell is programmed to high, the
related cell is ignored for motion detection.
The MD_MASK register has different function for reading and writing mode. For writing mode,
setting “1” to MD_MASK register inhibits the specific cell from detecting motion. For reading
mode, the state of MD_MASK register has two kinds of information depending on MASK_MODE
(2x82, 2xA2, 2xC2, 2xE2) register. For MASK_MODE = “1”, the state of MD_MASK register
means masking information of cell. For MASK_MODE = “0”, the state of MD_MASK register
means the result of motion detection that “1” indicates detecting motion and “0” denotes no
motion detection in the cell.
240 Lines for 60Hz (20 Lines/Cell), 288 Lines for 50Hz (24 Lines/Cell)
704 Pixels (44 Pixels/Cell)
MD_
MASK0
[0]
MD_
MASK0
[1]
MD_
MASK0
[2]
MD_
MASK0
[3]
MD_
MASK0
[4]
MD_
MASK0
[5]
MD_
MASK0
[6]
MD_
MASK0
[7]
MD_
MASK0
[8]
MD_
MASK0
[9]
MD_
MASK0
[10]
MD_
MASK0
[11]
MD_
MASK0
[12]
MD_
MASK0
[13]
MD_
MASK0
[14]
MD_
MASK0
[15]
MD_
MASK1
[0]
MD_
MASK1
[1]
MD_
MASK1
[2]
MD_
MASK1
[3]
MD_
MASK1
[4]
MD_
MASK1
[5]
MD_
MASK1
[6]
MD_
MASK1
[7]
MD_
MASK1
[8]
MD_
MASK1
[9]
MD_
MASK1
[10]
MD_
MASK1
[11]
MD_
MASK1
[12]
MD_
MASK1
[13]
MD_
MASK1
[14]
MD_
MASK1
[15]
MD_
MASK2
[0]
MD_
MASK2
[1]
MD_
MASK2
[2]
MD_
MASK2
[3]
MD_
MASK2
[4]
MD_
MASK2
[5]
MD_
MASK2
[6]
MD_
MASK2
[7]
MD_
MASK2
[8]
MD_
MASK2
[9]
MD_
MASK2
[10]
MD_
MASK2
[11]
MD_
MASK2
[12]
MD_
MASK2
[13]
MD_
MASK2
[14]
MD_
MASK2
[15]
MD_
MASK3
[0]
MD_
MASK3
[1]
MD_
MASK3
[2]
MD_
MASK3
[3]
MD_
MASK3
[4]
MD_
MASK3
[5]
MD_
MASK3
[6]
MD_
MASK3
[7]
MD_
MASK3
[8]
MD_
MASK3
[9]
MD_
MASK3
[10]
MD_
MASK3
[11]
MD_
MASK3
[12]
MD_
MASK3
[13]
MD_
MASK3
[14]
MD_
MASK3
[15]
MD_
MASK4
[0]
MD_
MASK4
[1]
MD_
MASK4
[2]
MD_
MASK4
[3]
MD_
MASK4
[4]
MD_
MASK4
[5]
MD_
MASK4
[6]
MD_
MASK4
[7]
MD_
MASK4
[8]
MD_
MASK4
[9]
MD_
MASK4
[10]
MD_
MASK4
[11]
MD_
MASK4
[12]
MD_
MASK4
[13]
MD_
MASK4
[14]
MD_
MASK4
[15]
MD_
MASK5
[0]
MD_
MASK5
[1]
MD_
MASK5
[2]
MD_
MASK5
[3]
MD_
MASK5
[4]
MD_
MASK5
[5]
MD_
MASK5
[6]
MD_
MASK5
[7]
MD_
MASK5
[8]
MD_
MASK5
[9]
MD_
MASK5
[10]
MD_
MASK5
[11]
MD_
MASK5
[12]
MD_
MASK5
[13]
MD_
MASK5
[14]
MD_
MASK5
[15]
MD_
MASK6
[0]
MD_
MASK6
[1]
MD_
MASK6
[2]
MD_
MASK6
[3]
MD_
MASK6
[4]
MD_
MASK6
[5]
MD_
MASK6
[6]
MD_
MASK6
[7]
MD_
MASK6
[8]
MD_
MASK6
[9]
MD_
MASK6
[10]
MD_
MASK6
[11]
MD_
MASK6
[12]
MD_
MASK6
[13]
MD_
MASK6
[14]
MD_
MASK6
[15]
MD_
MASK7
[0]
MD_
MASK7
[1]
MD_
MASK7
[2]
MD_
MASK7
[3]
MD_
MASK7
[4]
MD_
MASK7
[5]
MD_
MASK7
[6]
MD_
MASK7
[7]
MD_
MASK7
[8]
MD_
MASK7
[9]
MD_
MASK7
[10]
MD_
MASK7
[11]
MD_
MASK7
[12]
MD_
MASK7
[13]
MD_
MASK7
[14]
MD_
MASK7
[15]
MD_
MASK8
[0]
MD_
MASK8
[1]
MD_
MASK8
[2]
MD_
MASK8
[3]
MD_
MASK8
[4]
MD_
MASK8
[5]
MD_
MASK8
[6]
MD_
MASK8
[7]
MD_
MASK8
[8]
MD_
MASK8
[9]
MD_
MASK8
[10]
MD_
MASK8
[11]
MD_
MASK8
[12]
MD_
MASK8
[13]
MD_
MASK8
[14]
MD_
MASK8
[15]
MD_
MASK9
[0]
MD_
MASK9
[1]
MD_
MASK9
[2]
MD_
MASK9
[3]
MD_
MASK9
[4]
MD_
MASK9
[5]
MD_
MASK9
[6]
MD_
MASK9
[7]
MD_
MASK9
[8]
MD_
MASK9
[9]
MD_
MASK9
[10]
MD_
MASK9
[11]
MD_
MASK9
[12]
MD_
MASK9
[13]
MD_
MASK9
[14]
MD_
MASK9
[15]
MD_
MASK10
[0]
MD_
MASK10
[1]
MD_
MASK10
[2]
MD_
MASK10
[3]
MD_
MD_
MASK10 MASK10
[4]
[5]
MD_
MASK10
[6]
MD_
MASK10
[7]
MD_
MASK10
[8]
MD_
MASK10
[9]
MD_
MASK10
[10]
MD_
MASK10
[11]
MD_
MD_
MASK10 MASK10
[12]
[13]
MD_
MASK10
[14]
MD_
MASK10
[15]
MD_
MASK11
[0]
MD_
MASK11
[1]
MD_
MASK11
[2]
MD_
MASK11
[3]
MD_
MD_
MASK11 MASK11
[4]
[5]
MD_
MASK11
[6]
MD_
MASK11
[7]
MD_
MASK11
[8]
MD_
MASK11
[9]
MD_
MASK11
[10]
MD_
MASK11
[11]
MD_
MD_
MASK11 MASK11
[12]
[13]
MD_
MASK11
[14]
MD_
MASK11
[15]
Fig 15 Motion mask and detection cell
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Sensitivity Control
The motion detector has 4 sensitivity parameters to control threshold of motion detection such
as level sensitivity via the MD_LVSENS (2x82, 2xA2, 2xC2, 2xE2) register, spatial sensitivity via
the MD_SPSENS (2x85, 2xA5, 2xC5, 2xE5) and MD_CELSENS (2x82, 2xA2, 2xC2, 2xE2)
register, and temporal sensitivity parameter via the MD_TMPSENS (2x85, 2xA5, 2xC5, 2xE5)
register.
Level Sensitivity
In built-in motion detection algorithm, motion is detected when luminance level difference
between current and reference field is greater than MD_LVSENS value. Motion detector is more
sensitive for the smaller MD_LVSENS value and less sensitive for the larger. When the
MD_LVSENS is too small, the motion detector may be weak in noise.
Spatial Sensitivity
The TW2834 uses 192 (16x12) detection cells in full screen for motion detection. Each detection
cell is composed of 44 pixels and 20 lines for NTSC and 24 lines for PAL. Motion detection from
only luminance level difference between two fields is very weak in spatial random noise. To
remove the fake motion detection from the random noise, a spatial filter is used. The
MD_SPSENS defines the number of detected cell to decide motion detection in full size image.
The large MD_SPSENS value increases the immunity of spatial random noise.
Each detection cell has 4 sub-cells also. Actually motion detection of each cell comes from
comparison of sub-cells in it. The MD_CELSENS defines the number of detected sub-cell to
decide motion detection in cell. Likewise, the large MD_CELSENS value increases the immunity
of spatial random noise in small area.
Temporal Sensitivity
Similarly, temporal filter is used to remove the fake motion detection from the temporal random
noise. The MD_TMPSENS regulates the number of taps in the temporal filter to control the
temporal sensitivity so that the large MD_TMPSENS value increases the immunity of temporal
random noise.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Velocity Control
Motion has various velocities. That is, in a fast motion an object appears and disappears rapidly
between the adjacent fields while in a slow motion it is to the contrary. As the built-in motion
detection algorithm uses the only luminance level difference between two adjacent fields, a slow
motion is inferior in detection rate to a fast motion. To compensate this weakness, MD_SPEED
(2x83, 2xA3, 2xC3, 2xE3) parameter is used which is controllable up to 64 fields. MD_SPEED
parameter adjusts the field interval in which the luminance level is compared. Thus, for
detection of a fast motion a small value is needed and for a slow motion a large value is
required. The parameter MD_SPEED value should be greater than MD_TMPSENS value.
Additionally, the TW2834 has 2 more parameters to control the selection of reference field. The
MD_FLD (2x81, 2xA1, 2xC1, 2xE1) register is a field selection parameter such as odd, even,
any field or frame.
The MD_REFFLD (2x80, 2xA0, 2xC0, 2xE0) register is provided to control the updating period
of reference field. For MD_REFFLD = “0”, the interval from current field to reference field is
always same as the MD_SPEED. It means that the reference filed is always updated every field.
The Fig 16 shows the relationship between current and reference field for motion detection
when MD_REFFLD is “0”.
Time
Field0
Field1
Field2
Field3
Field4
Field5
Field6
M1
Field7
Field8
Field9 Field10 Field11 Field12
M7
M2
M8
M3
M9
M4
M10
M5
M11
M6
Reference Field
Current Field
M12
Detection between Reference and Current Field
Fig 16 The relationship between current and reference field when MD_REFFLD = “0”
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
The TW2834 can update the reference field only at the period of MD_SPEED when
MD_REFFLD is high. For this case, the TW2834 can detect a motion with sense of a various
velocity. The Fig 17 shows the relationship between current and reference field for motion
detection when MD_REFFLD = ”1”.
Time
Field0
Field1
Field2
Field3
Field4
Field5
Field6
M1
Field7
Field8
Field9 Field10 Field11 Field12
M7
M2
M8
M3
M9
M4
M10
M5
M11
M6
Reference Field
Current Field
M12
Detection between Reference and Current Field
Fig 17 The relationship between current and reference field when MD_REFFLD = “1”
The TW2834 also supports the update timing control of the reference field/frame via the
MD_STRB_EN and MD_STRB (2x83, 2xA3, 2xC3, 2xE3) register. For MD_STRB_EN = “0”, the
reference field/frame is automatically updated and reserved on every reference field/frame. For
MD_STRB_EN = “1”, the reference field/frame is updated and reserved only when MD_STRB =
“1”. In this mode, the interval between current and reference field/frame depends on user’s
strobe timing. This mode is very useful for non-realtime application such as pseudo-8ch
application or for a specific purpose like non-periodical velocity control and very slow motion
detection.
The TW2834 also provides the interrupt period control from the motion detection via the
MD_DET_PERIOD (2x84, 2xA4, 2xC4, 2xE4) register. Normally, the motion detection
information is sent to host by interrupt pin whenever motion is detected. However, if motion is
detected very frequently, the host will be burden by too many interrupt requests. In this case,
the TW2834 can send one interrupt request during the defined motion interrupt period.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Blind Detection
The TW2834 supports a blind input detection individually for 4 analog video inputs and makes
an interrupt of blind detection to host. If video level in wide area of field is almost equal to
average video level of field due to camera shaded by something, this input is defined as blind
input.
The TW2834 has two sensitivity parameters to detect blind input such as level sensitivity via the
BD_LVSENS (2x80, 2xA0, 2xC0, 2xE0) register and spatial sensitivity via the BD_CELSENS
(2x80, 2xA0, 2xC0, 2xE0) register. The BD_LVSENS parameter controls threshold of level
between cell and field average. The BD_CELSENS parameter defines the number of cells to
detect blind. The TW2834 uses total 768 (32x24) cells of full screen. For BD_CELSENS = “0”,
the number of cell whose level is same as average of field should be over than 60% to detect
blind. The large value of BD_LVSENS and BD_CELSENS makes blind detector less sensitive.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Video Control
The TW2834 has dual video controllers for display and record path. Basically, each path
requires only external 16M SDRAM for normal operation. However for display path, external
SDRAM can be extended from 16M to 512M bits. This capability is related to save and recall
function. The block diagram of video controller is shown in following Fig 18.
16M ~ 512M SDRAM (X Path)
Memory Interface
From
Video
Input
Part
CH0_X
CH1_X
CH2_X
CH3_X
Write
Control
Read
Control
Zoom
&
Image
Enhance
VOUT_X
To
OSD
Overlay
Control
Part
CH0_Y
VIN0_Y
VIN1_Y
VIN2_Y
VIN3_Y
VIN0 ~
VIN3
Optional Record
Output
4X4 CH1_Y
INPUT CH2_Y
MUX
Write
Control
Read
Control
CH3_Y
Channel
ID
Encoding
VOUT_Y
Memory Interface
16M SDRAM (Y Path)
Fig 18 Block diagram of video controller
The TW2834 supports channel blanking, boundary on/off, blink, horizontal/vertical mirroring,
and freeze function for each channel. The TW2834 can capture last 4 images automatically for
each channel when video loss is detected.
The TW2834 has three operating modes such as live, strobe and switch mode. Each channel
can be operated in its individual operating mode. That is, the TW2834 can be operated as multioperating mode if each channel has different operating mode. Live mode is used to display real
time video as QUAD or full live display, strobe mode is used to display non-realtime video with
strobe signal from host and switch mode is used to display time-multiplexed video from several
channels. For switch mode, the TW2834 supports two different types such as switch live and
switch still mode.
The TW2834 also provides four record picture modes such as normal record mode and frame
record mode and DVR normal record mode and DVR frame record mode. For record path,
channel size and position have a limitation to half or full size in the horizontal and vertical
direction.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
For display path, the TW2834 can save and recall video through external extended SDRAM and
support image enhancement function for non-realtime video such as freezing or playback video
and provide high performance 2X zoom function. The TW2834 also supports dummy channel
operation for display path. So it is very useful to implement pseudo-8ch display.
The TW2834 provides the channel ID encoding in both display and record path. The channel ID
of record path contains all current picture configurations while the channel ID of display path has
only channel switching information.
The TW2834 supports 4ch full D1 record output using SDRAM interface in record path. It’s
useful for 4ch realtime recording and playback application. In this case, external SDRAM in
record path cannot be used.
The TW2834 also provides chip-to-chip cascade connection for 8 or 16 channel application.
Channel Input Selection
The channel for display path can select 8 video inputs including 4 analog video inputs and 4
playback inputs, but the channel for record path can choose 4 analog video inputs. The analog
video inputs can be selected via the DEC_PATH (0x22, 0x62, 0xA2, 0xE2 for display path, 1x60,
1x63, 1x66, 1x69 for record path) register and the playback inputs can be chosen via the
PB_PATH (0x39) register. For display path, the PB_CH_EN (0x38) register can control the
following video input path. The Fig 19 shows the internal channel input selection.
DEC_PATH0_X (0x22)
VIN0
VIN1
VIN2
VIN3
4X1
MUX
VIN0_X
DEC_PATH1_X (0x62)
4X1
MUX
VIN1_X
DEC_PATH2_X (0xA2)
4X1
MUX
VIN2_X
DEC_PATH3_X (0xE2)
4X1
MUX
VIN3_X
PB_CH0_EN (0x38)
2X1
MUX
DEC_PATH0_Y (1x60)
CH0_X
VIN0_Y
VIN1_Y
VIN2_Y
VIN3_Y
PB_CH1_EN (0x38)
2X1
MUX
4X1
MUX
CH1_X
To Write
Control Part
(Display Path)
CH2_X
PB_CH3_EN (0x38)
2X1
MUX
CH0_Y
DEC_PATH1_Y (1x63)
PB_CH2_EN (0x38)
2X1
MUX
4X1
MUX
CH1_Y
DEC_PATH2_Y (1x66)
4X1
MUX
To Write
Control Part
(Record Path)
CH2_Y
DEC_PATH3_Y (1x69)
CH3_X
4X1
MUX
CH3_Y
PB_PATH0 (0x39)
PBIN0
PBIN1
PBIN2
PBIN3
4X1
MUX
PB0_X
PB_PATH1 (0x39)
4X1
MUX
PB1_X
PB_PATH2 (0x39)
4X1
MUX
PB2_X
PB_PATH3 (0x39)
4X1
MUX
PB3_X
Fig 19 Channel input selection
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Channel Operation Mode
Each channel can be working with three kinds of operating mode such as live, strobe and switch
mode via the FUNC_MODE (1x10, 1x18, 1x20, 1x28 for display path, 1x60, 1x63, 1x66, 1x69
for record path) register. The operation mode can be selected individually for each channel so
that multi-operating mode can be implemented.
Live Mode
If FUNC_MODE is “0”, channel is operated in live mode. For the live mode, the video display is
updated with real time. This mode is used to display a live video such as QUAD, PIP, and POP.
When changing the picture configuration such as input path, popup priority, PIP, POP, and etc,
the TW2834 supports anti-rolling sequence by monitoring channel update via the STRB_REQ
register (1x04 for display path, 1x54 for record path) after changing to strobe operation mode
(FUNC_MODE = “1”). The following Fig 20 shows the sequence to change picture configuration.
Picture Configuration
Start
Change FUNC_MODE = 1
NO
STRB_REQ = “0”
?
YES
Change
Change
Change
Change
Channel Scaling
Channel Size
Channel Position
DEC_PATH
Change FUNC_MODE = 0
Picture Configuration
End
Fig 20 The sequence to change picture configuration
The status of STRB_REQ register can also be read through MPPDEC pin with control of the
MPPSET (1x50) register.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Strobe Mode
If FUNC_MODE is “1”, channel is operated in strobe mode. For strobe mode, video display is
updated whenever the TW2834 receives strobe command from host like CPU or Micom. If host
doesn’t send a strobe command to the TW2834 anymore, the channel maintains the last strobe
image until getting a new strobe command. This mode is useful to display non-realtime video
input such as playback video with multiplexed signal input and to implement pseudo 8 channel
application or dual page mode or panorama channel display. Specially, the TW2834 supports
easy interface for pseudo 8channel application that will be covered in dummy channel function
section. The TW2834 also supports auto strobe function for auto playback display that will be
covered later in auto strobe function section.
Strobe operation is performed independently for each channel via the STRB_REQ (1x04, 1x54)
register. But the STRB_REQ register has a different mode for reading and writing. Writing “1”
into STRB_REQ in each channel makes the TW2834 updated by each incoming video. The
updating status after strobe command can be known by reading the STRB_REQ register. If
reading value is “1”, updating is not completed after getting the strobe command. In that case,
this channel cannot accept a new strobe command or a disabling strobe command from host.
To send a new strobe command, host should wait until STRB_REQ state is “0”. For freeze or
non-strobe channel, the TW2834 can ignore the strobe command even though host sends it. In
this case, the STRB_REQ register is cleared to “0” automatically without any updating video.
The status of STRB_REQ register can also be read through MPPDEC pin with control of the
MPPSET (1x50) register.
When updating video with a strobe command, the TW2834 supports field or frame updating
mode via the STRB_FLD (1x04, 1x54) register. Odd field of input video can be updated and
displayed for STRB_FLD = “0”, even field for “1”. For “2” of STRB_FLD register, the TW2834
doesn’t care for even or odd field, and updates video by next any field. If the STRB_FLD
register is “3”, the strobe command updates video by frame. The following Fig 21 shows the
example of strobe sequence for various STRB_FLD value.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Vertical Vertical
Blank
Active
Analog Input
STRB_FLD
User strobe
00 (Odd)
STRB_REQ
Odd
Even
Odd
Even
S1
Odd
Even
S2
Odd
S1 Update
Even
Odd
Even
S4
S3
S2 Update
S3 Update
S4 Ignored due to S3 is not finished
01 (Even)
STRB_REQ
S1 Update
S2 Update
S4 Update
S3 Ignored due to S2 is not finished
10 (Any Field) STRB_REQ
11 (Frame)
S1 Update
S2 Update
STRB_REQ
S3 Update
S4 Update
S1 Update
S3 Update
S4 Ignored due to S3 is not finished
S2 Ignored due to S1 is not finished
Fig 21 The example of strobe sequence for various STRB_FLD setting
The timing of strobe operation is related only with input video timing and strobe operation can
be performed independently for each channel. So each channel is updated with different timing.
The TW2834 provides a special feature as dual page mode using the DUAL_PAGE (1x04,
1x54) register. Although each channel is updated with different time, all channels can be
displayed simultaneously in dual page mode. This means that the TW2834 waits until all
channels are updated and then displays all channels with updated video at the same time.
When dual page mode is enabled, host should send a strobe command for all channels and
host should wait until all channels complete their strobe operations to send a new strobe
command. The Fig 22 shows the example of 4 channel strobe sequences for dual page.
S2 is ignored because strobe sequence for CH 0 and CH 1 is not completed
S1
User strobe
CH 0
S2
Odd
S4
S3
Even
Odd
Even
Odd
Even
S5
Odd
Even
Odd
Even
STRB_REQ[0]
CH 1
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
STRB_REQ[1]
CH 2
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
STRB_REQ[2]
CH 3
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
STRB_REQ[3]
Fig 22 The example of 4 channel strobe sequences for dual page mode
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TW2834 Video Controller
Preliminary
Switch Mode
If FUNC_MODE is “2”, channel is operated in switch mode. The TW2834 supports 2 different
types of switching mode such as still switching and live switching mode via the MUX_MODE
(1x06, 1x56) register. For still switching mode, the TW2834 maintains the switched channel
video as still image until next switching request, but for live switching mode the TW2834
updates every field of switched channel until next switching request. The live switching mode is
used for channel sequencer without any timing loss or disturbing. In switch mode, there is a
constraint that the picture size of all switched channel should be same even though their size
can be varied. The TW2834 can switch the channel by fields or frames that can be programmed
up to 1 field or 1 frame rate. But if the channel is on freeze state or disabled, the TW2834
ignores the request for switch mode.
The TW2834 contains 128 depth internal queues that have channel sequence information with
internal or external triggering. Actual queue size can be defined by the QUE_SIZE (1x57)
register. The channel switching sequence in the internal queue is changed by setting “1” to
QUE_WR (1x5A) register after defining the queue address with the QUE_ADDR (1x5A) register
and the channel switching information with the MUX_WR_CH (1x59) register. The QUE_WR
register will be cleared automatically after updating queue. The channel sequence information
can be read via the CHID_MUX_OUT (1x0A for display path, 1x5E for record path) register.
To operate the switching function properly, the channel switching should be requested with
triggering that has three kinds of mode such as internal triggering from internal field counter,
external triggering from external host or pin and interrupted triggering like alarm. The triggering
Q4
Q5
Q6
INTR_REQ
INTR_CH
TRIG_MODE
Q3
Internal
Queue
Q2
Q1
Q7
QUE_POS_RST
QUE_SIZE = 7
QUE_POS
QUE_ADDR
Record Path Only
QUE_CH
mode can be selected by the TRIG_MODE (1x56) register. The TW2834 supports all triggering
mode in record path, but provides only interrupt triggering mode in display path. The Fig 23
shows the structure of switching operation.
Queue
Read/Write
Control
INT_CNT_RST
External
Triggering
Detector
Q0
Switching
Interrupt
Detector
QUE_PERIOD
Internal
Field
Counter
Switching
Operation
Control
Switching
Arbitration
EXT_TRIG
PIN_TRIG
MUX_OUT_CH
Fig 23 The structure of switching operation when QUE_SIZE = 7
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TW2834 Video Controller
Preliminary
For internal triggering mode, the switching period can be specified in the QUE_PERIOD (1x58)
register that has 1 ~ 1024 field range. The internal field counter can be reset at anytime using
the QUE_CNT_RST (1x5B) register and restarted automatically after reset. To reset an internal
queue position, set “1” to QUE_POS_RST (1x5B) register and then the queue position will be
restarted after reset. Both QUE_CNT_RST and QUE_POS_RST register can be cleared
automatically after set to “1”. The following Fig 24 shows an illustration of QUE_POS_RST and
QUE_CNT_RST. The next queue position can be read via the QUE_ADDR (1x5A) register.
Period restart
Triggering
T1
T2
T3
Position restart
T4
T5
T0
Period/Position restart
T1
T0
T1
QUE_PERIOD = 4
Encoder
Output
QUE_POS_RST
QUE_CNT_RST
Field Counter
QUE_POS
(Channel)
MUX_OUT_CH
1 2 3 4 0 1 2 3 4 0 1 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 3 4 0 1 2 3 4 0
Q2 (2)
Q3 (3)
0
1
Q4 (0)
2
Q5 (1)
Q6 (2) Q0 (0)
3
0
Q1 (1)
1
Q2 (2) 0
Q1 (1)
0
1
Q2 (2)
0
Fig 24 The illustration of QUE_POS_RST and QUE_CNT_RST
For external triggering mode, the request of channel switching comes from the EXT_TRIG
(1x59) register or TRIGGER pin that is controlled by the PIN_TRIG_MD (1x56) register. Like
internal triggering mode, writing “1” to the QUE_POS_RST register can reset the queue position
in external triggering mode.
For interrupt triggering, host can request the channel switching at anytime via the INTR_REQ
(1x07, 1x59) register. The switching channel is defined by the INTR_CH (1x07 for display path)
or MUX_WR_CH (1x59 for record path) registers. Because the interrupted trigger has a priority
over internal or external triggering in record path, the channel defined by the MUX_WR_CH can
be inserted into the programmed channel sequence immediately.
The TW2834 also provides various switching types as odd field, even field or frame switching
via the MUX_FLD (1x06, 1x56) register. For MUX_FLD = “0”, it is working as field switching
mode with only odd field, but with only even field for MUX_FLD = “1”. For MUX_FLD = “2” or “3”,
it is working as frame switching with both odd and even field. But in the frame record mode (it
will be covered in “Frame Record Mode” section, page 55), the switching type is defined by the
FRAME_FLD (1x01, 1x51) register.
Actually the channel switching is executed just before vertical sync of video output in field
switching mode or before vertical sync of only odd field in frame switching mode. So all registers
for switching should be set before that timing. Otherwise, the control values will be applied to
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TW2834 Video Controller
Preliminary
the next field or frame. For the reference timing of switching, the TW2834 provides the LINK pin
whose represents the field transition with “1” for even field.
Likewise, the switching channel information is updated just before vertical sync of video output
in field switching or before vertical sync of only odd field in frame switching mode. Basically it
takes 4 field duration to display the switching channel from any triggering (field or frame). The
host can read the current switching channel information through the MUX_OUT_CH (1x08,
1x6E) register. The TW2834 also support external pin output for this channel information with
MPPDEC pin via the MPPSET (1x50) register. The switching channel information can also be
discriminated by the channel ID in the video stream.
The illustration of channel switching is shown in the Fig 25 and Fig 26.
T0
Triggering
T1
T2
T3
T0
T1
T2
Encoder
Output
Vertical Vertical
Blank
Active
LINK Pin
INTR_REQ
QUE_POS
1
2
3
0
1
2
3
MUX_OUT_CH
2
3
0
1
2
3
0
Video
output
Mux output delay = 4 Fields
Fig 25 The illustration of switching sequence when QUE_SIZE = 3, QUE_PERIOD = 1
Switch interrupt
Triggering is delayed due to switch interrupt
switch interrupt is inserted between programmed triggering
Triggering
T0
I3 T1
T2
I1
T3
T0
T1
T2
Encoder
output
INTR_REQ
Vertical Vertical
Blank
Active
QUE_POS
MUX_OUT_CH
1
2
2
3
Mux output delay = 4 Fields
3
0
0
3
Interrupt
Output
1
1
2
1
2
3
3
0
Interrupt
Output
Fig 26 The interrupted switching sequence when QUE_SIZE = 3, QUE_PERIOD = 1
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TW2834 Video Controller
Preliminary
The TW2834 supports the skip function of the switching queue for switch mode in record path.
In single chip application, the auto skip function of the switching queue can be supported if the
MUX_SKIP_EN (1x5B) register is “1” and the NOVID_MODE is “1” or “3”. But in the chip-to-chip
cascaded application, the skip function should be forced with the MUX_SKIP_CH (1x5C, 1x5D)
register because the switching queue for whole channels is located in the lowest slaver device
but cannot get the no-video information from the other chips.
The QUAD MUX function in chip-to-chip cascade application will be covered in the “Chip-toChip Cascade Operation (page 72)”.
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TW2834 Video Controller
Preliminary
Channel Attribute
The TW2834 provides various channel attributes such as channel enable, boundary selection,
blank enable, freeze, horizontal/vertical mirroring for both display and record path. As special
feature, the TW2834 supports the last image capture function, save/recall function, image
enhancement and dummy channel display function for display path. For last image capture
mode, channel can be blanked or boundary can be blinked automatically on no-video state.
Background Control
Summation of all active channel regions can be called as active region and the rest region
except active region is defined as background region. The TW2834 supports background
overlay and the overlay color is controlled via the BGDCOL (1x0F, 1x5F) register.
Boundary Control
The TW2834 can overlay channel boundary on each channel region using the BOUND (1x11,
1x13, 1x19, 1x1B, 1x21, 1x23, 1x29, 1x2B for display path, 1x61, 1x64, 1x67, 1x6A for record
path) register and it can be blinked via the BLINK (1x11, 1x13, 1x19, 1x1B, 1x21, 1x23, 1x29,
1x2B for display path, 1x61, 1x64, 1x67, 1x6A for record path) register when BOUND is high.
The boundary color can be selected through the BNDCOL (1x0F, 1x5F) register. The blink
period can be also controlled through the TBLINK (1x02, 1x52) register.
Blank Control
Each channel can be blanked with specified color using the BLANK (1x11, 1x13, 1x19, 1x1B,
1x21, 1x23, 1x29, 1x2B for display path, 1x61, 1x64, 1x67, 1x6A for record path) register and
the blank color can be specified via the BLKCOL (1x0F, 1x3F) register.
Freeze Control
Each channel can capture last 4 field images whenever freeze function is enabled and display 1
field image out of the captured 4 field images using the FRZ_FLD (1x0F, 1x3F) register. The
freeze function can be enabled or disabled independently for each channel via the FREEZE
(1x11, 1x13, 1x19, 1x1B, 1x21, 1x23, 1x29, 1x2B for display path, 1x61, 1x64, 1x67, 1x6A for
record path) register.
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TW2834 Video Controller
Preliminary
Last Image Capture
When video loss has occurred or gone, the TW2834 provides 4 kinds of indication such as
bypass of incoming video, channel blank, capture of last image, and capture of last image with
blinking channel boundary depending on the NOVID_MODE (1x05, 1x55) register. This function
is working automatically on video loss. The capturing last image is same as freeze function
described above. User can select 1 field image out of captured 4 filed images via the FRZ_FLD
(1x0F, 1x5F) register which is shared with freeze function.
Horizontal / Vertical Mirroring
The TW2834 supports image-mirroring function for horizontal and/or vertical direction. The
horizontal mirroring is achieved via the H_MIRROR (1x11, 1x13, 1x19, 1x1B, 1x21, 1x23, 1x29,
1x2B for display path, 1x61, 1x64, 1x67, 1x6A for record path) register and the vertical mirroring
is attained via the V_MIRROR (1x11, 1x13, 1x19, 1x1B, 1x21, 1x23, 1x29, 1x2B for display path,
1x61, 1x64, 1x67, 1x6A for record path) register. It is useful for a reflection image in the
horizontal and vertical direction.
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TW2834 Video Controller
Preliminary
Display Path Control
The TW2834 can save images in external memory and recall them to display. This function can
be working in display path only because the external memory can be extended from 16M to
512M bits only in display path. The TW2834 also supports the special filter to enhance image
quality in display path for non-realtime video display such as recalled image from saving images
and playback with multiplexed video source. The TW2834 provides high performance 2X zoom
function in the vertical and horizontal direction. The TW2834 supports any kind of picture
configuration for display path with variable picture size, position and pop-up control. The
TW2834 also provides a dummy channel function for pseudo 8ch application.
Save and Recall Function
The save/recall function can be working independently for each channel and the number of the
saved images depends on the extended memory capability, picture size and field type. The
TW2834 can save image only in live channel so that it cannot be saved in freezing channel. If
channel is working on strobe operating mode, this channel can be saved with new strobe
command. For switch operating mode, the channel can be saved only on switching time
because this channel can be updated at this moment.
To save image, several parameters should be controlled that are the SAVE_FLD, SAVE_HID,
SAVE_REQ (1x03) and SAVE_ADDR (1x02) registers. The SAVE_FLD determines field or
frame type for image to be saved. Even though the channel to be saved is hidden by upper
layer picture, it can be saved using the SAVE_HID register that makes no effect on current
display. The saving function is requested by writing “1” to the SAVE_REQ register and this
register will be cleared when saving is done. Before it is cleared, the TW2834 cannot accept
new saving request. The SAVE_ADDR register defines address where an image will be saved.
Because 4M bits is allocated for each 1 field image, SAVE_ADDR unit is 4M bits and can have
range 0 ~ 127 for 512M bits. The first 0~ 3 addresses are reserved for normal operation so that
it cannot be used for saving function.
To recall the saved video image, several parameters are required such as RECALL_FLD (1x03),
RECALL_EN (1x11, 1x13, 1x19, 1x1B, 1x21, 1x23, 1x29, 1x2B) and RECALL_ADDR (1x12,
1x14, 1x1A, 1x1C 1x22, 1x24, 1x2A, 1x2C) registers. If the RECALL_EN is “1”, the TW2834
recalls the saved image that is located at RECALL_ADDR in external memory and displays it
just like incoming video. The RECALL_FLD register determines 1 field or 1 frame mode to
display. The following Fig 27 illustrates the relationship between external SDRAM size and
SAVE_ADDR / RECALL_ADDR.
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TW2834 Video Controller
SAVE_ADDR
RECALL_ADDR
16M
0~3
Reserved
SDRAM Size
64M
4 ~ 15
64M
Preliminary
128M
16 ~ 31
256M
512M
64 ~ 127
32 ~ 63
128M
256M
512M
Save Examples for Each Save Address with 4M Size
In case of Full Image, 1 Picture can be saved
In case of CIF Image, 4 Picture can be saved
CH0
CH1
CH2
CH3
CH0
Fig 27 The relationship between SDRAM size and SAVE_ADDR / RECALL_ADDR
Image Enhancement
In non-realtime video such as freeze image, recalled image from saving images and playback
video which records multi-channel video using field switching, so many line flicker noise can be
found in image because it displays same field image for both odd and even field. The
embedded filter in the TW2834 can remove effectively this line flicker noise and be enabled via
the ENHANCE (1x11, 1x13, 1x19, 1x1B, 1x21, 1x23, 1x29, 1x2B) register for each channel.
This filter coefficient can be controlled via the FR_EVEN_OS and FR_ODD_OS (1x0B) register.
Zoom Function
The TW2834 supports high performance 2X zoom function in the vertical and horizontal
direction for display path. The zoom function can be working in any operation mode such as live,
strobe and switch mode. Conventional system also has zoom function, but it has a very poor
quality due to line flicker noise even though interpolation filter is adapted. The TW2834 provides
high quality zoom characteristics using high performance interpolation filter and image
enhancement technique. When zoom is executed, the image enhancement is operated
automatically and the filter coefficient can be controlled via the ZM_EVEN_OS and
ZM_ODD_OS (1x0B) register.
The zoomed region will be defined with the ZOOMH (1x0D) and ZOOMV (1x0E) registers and
can be displayed depending on the ZMBNDCOL, ZMBNDEN, ZMAREAEN, ZMAREA (1x0C)
register. The zoom operation is enabled via the ZMENA (1x0C) register.
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TW2834 Video Controller
Preliminary
Picture Size and Popup Control
Each channel region can be defined using its own PICHL (1x30, 1x34, 1x38, 1x3C), PICHR
(1x31, 1x35, 1x39, 1x3D), PICVT (1x32, 1x36, 1x3A, 1x3E), and PICVB (1x33, 1x37, 1x3B,
1x3F) register. If more than 2 channels have same region, there will be a conflict of what to
display for that area. Generally the TW2834 defines that the channel 0 has priority over channel
3. So if a conflict happens between more than 2 channels, the channel 0 will be displayed first
as top layer and then channel 1 and 2 and 3 are hidden beneath.
The TW2834 also provides a channel pop-up attribute via the POP_UP (1x10, 1x18, 1x20,
1x28) register to give priority for another display. If a channel has pop-up attribute, it will be
displayed as top layer. This feature is used to configure PIP (Picture-In-Picture) or POP
(Picture-Out-Picture). The following Fig 28 shows the channel definition and priority for display
path.
H=0
H = 180
PICHL1
PICVT0
V=0
PICVB0
PICVT1
POP_UP2 = 0
POP_UP0 = 0
POP_UP1 = 1
PICHL0
PICHR0
V = 120/144
Fig 28 The channel position and priority in display path
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TW2834 Video Controller
Preliminary
Dummy Channel Function
The TW2834 supports additional 4 dummy channel controllers to display up to 8 channel videos
in display path for non-realtime application. That is, this dummy channel is useful to implement
low cost and high feature application system such as pseudo 8-channel QUAD system.
The TW2834 has 4 main channel controllers as described before and each main channel has its
own corresponding dummy channel. The dummy channel has input source selection and popup attribute in common with the main channel, but has its own attributes such as boundary,
blank, enhancement, recall and so on.
To use dummy channel function, dummy channel region should be defined in the DMPICHL
(1x40, 1x44, 1x48 and 1x4C), DMPICHR (1x41, 1x45, 1x49 and 1x4D), DMPICVT (1x42, 1x46,
1x4A and 1x4E), and DMPICVB (1x43, 1x47, 1x4B and 1x4F) registers and dummy channel
should be enabled using the DMCH_EN (1x10, 1x18, 1x20 and 1x28) register. The updated
input selection can be controlled via the DMCH_PATH (1x10, 1x18, 1x20 and 1x28) register. If
the DMCH_PATH is “1”, the dummy channel will be updated, but if DMCH_PATH is “0”, the
main channel will be updated. So the updated input selection should be defined before update
such as during vertical blanking time or between completed strobe and new strobe.
This dummy channel can also be used to display 8 split channel for playback input with
multiplexed or dual page video format. For playback application using auto cropping and auto
strobe mode, the updated input selection is controlled automatically from channel ID decoder
when dummy channel is enabled.
The following Fig 29 shows pseudo 8-channel operation using dummy channel function, strobe
operating mode and internal analog switch.
V=0
CH 0-0
CH 1-0
CH 2-0
Background
CH 3-0
V = 120/144
CH 1-1
CH 0-1
CH 2-1
CH 3-1
H=0
H = 180
Fig 29 Pseudo 8 channel operation
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TW2834 Video Controller
Preliminary
Record Path Control
The TW2834 supports 4 record modes such as normal record mode, frame record mode, DVR
record mode and DVR frame record mode. The DVR record mode and DVR frame record mode
generate continuous video stream for each channel and transfer it to compression part (MJPEG or MPEG) so that they are very useful for DVR application. The frame record mode can
be used to record each channel with full vertical resolution. The record mode is selected via the
DIS_MODE and FRAME_OP (1x51) register. If the FRAME_OP is “0”, the DIS_MODE = “0”
stands for normal record mode and the DIS_MODE = “1” represents DVR record mode. If the
FRAME_OP is “1”, the DIS_MODE = “0” stands for frame record mode and the DIS_MODE =
“1” represents DVR frame record mode.
The TW2834 support high performance free scaler for vertically and horizontally in display path,
but has the size and position limitation such as Full / Quad / CIF in record path.
The TW2834 can provide various record formats with various record modes (normal/frame/DVR
/DVR frame), operation modes (live/strobe/switch) and respective size/position definition. Many
illustration and detail description is covered in the application note.
The TW2834 also supports four channel real-time record mode with full D1 format. In this case,
the external SDRAM in record path should not be used so that four channel full D1 data can be
output though the SDRAM interface pin.
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TW2834 Video Controller
Preliminary
Normal Record Mode
Each channel position and size can be defined using its own PIC_SIZE (1x6C), and PIC_POS
(1x6D) register. The channel size is defined via the PIC_SIZE register such as “0” for
Horizontal/Vertical half size (QUAD), “1” for Horizontal full size and Vertical half size, “2” for
Horizontal half size and Vertical full size, and “3” for Horizontal/Vertical full size. The channel
position is defined via the PIC_POS register such as “0” for no Horizontal/Vertical offset, “1” for
Horizontal half picture offset, “2” for Vertical half picture offset and “3” for Horizontal/Vertical half
picture offset. The channel size and location should be defined within the full picture size (i.e.
PIC_SIZE = “3” & PIC_POS = “2” is not allowed).
The horizontal full size of picture is controlled via the SIZE_MODE (1x51) register such as “0”
for 720 pixels, “1” for 702 pixels, and “2” for 640 pixels. Likewise, the vertical full size is selected
by the SYS5060 (1x00) register such as “0” for 240 lines and “1” for 288 lines.
If more than 2 channels have same region, there will be a conflict of what to display for that area.
Generally the TW2834 defines that the channel 0 has priority over channel 3. So if a conflict
happens between more than 2 channels, the channel 0 will be displayed first as top layer and
then the channel 1 and 2 and 3 are hidden beneath. The TW2834 also provides a channel popup attribute via the POP_UP (1x60, 1x63, 1x66, and 1x69) register to give priority for another
display. If a channel has pop-up attribute, it will be displayed as top layer. The following Fig 30
shows the example of the channel position and size control in normal record mode.
Horizontal Direction (H)
Vertical Direction (V)
PIC_SIZE = 0
PIC_POS = 0
PIC_SIZE = 0
PIC_POS = 1
CH 0
CH 1
PIC_SIZE = 0
PIC_POS = 2
PIC_SIZE = 0
PIC_POS = 3
CH 2
CH 3
Fig 30 The channel position and size control in normal record mode
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TW2834 Video Controller
Preliminary
Frame Record Mode
The frame record mode is similar to normal record mode except that the definition of picture size
is extended to frame area and only one field data can be output in 1 frame. The odd or even
field selection is controlled via the FRAME_FLD (1x51) register. Like normal record mode, each
channel position and size can be defined using its own PIC_SIZE (1x6C), and PIC_POS (1x6D)
register. The channel size is defined via the PIC_SIZE register such as “0” for Horizontal half
size and Vertical full size, “1” for Horizontal/Vertical full size, but “2” or “3” is not allowed. That is,
the channel size for vertical direction supports only one field size. The channel position is
defined via the PIC_POS register such as “0” for no Horizontal/Vertical offset, “1” for Horizontal
half picture offset, “2” for Vertical 1 field offset, and “3” for Horizontal half picture offset and
Vertical 1 field offset. The channel size and location should be defined within the full picture size.
In frame record mode, the TW2834 also supports the full operation mode such as live, strobe or
switch operation and provides a pop-up attribute via the POP_UP register. The Fig 31 shows
the example of the channel position and size control in frame record mode.
N o rm a l R e c o rd M o d e (Q u a d )
(P IC _ S IZ E = 0 )
F ra m e R e c o rd M o d e (F ra m e -Q u a d )
(P IC _ S IZ E = 0 )
V e r t ic a l B la n k i n g
V e r t ic a l B la n k i n g
0
2 4 0 /2 8 8
P IC _ P O S = 2
P IC _ P O S = 1
Output Data of Odd Field
P IC _ P O S = 0
Output Data of Odd Field
0
P IC _ P O S = 3
2 4 0 /2 8 8
P IC _ P O S = 0
P IC _ P O S = 1
P IC _ P O S = 2
P IC _ P O S = 3
Output Data of Even Field
P IC _ P O S = 0
P IC _ P O S = 1
V e r t ic a l B la n k i n g
Output Data of Even Field
V e r t ic a l B la n k i n g
P IC _ P O S = 2
4 8 0 /5 7 6
P IC _ P O S = 3
4 8 0 /5 7 6
V id e o In p u t fo r E a c h C h a n n e l
S c a le r a tio fo r H o riz o n ta l : 1 /2
S c a le r a tio fo r V e rtic a l : 1 / 2
V id e o In p u t fo r E a c h C h a n n e l
S c a le r a tio fo r H o riz o n ta l : 1 /2
S c a le r a tio fo r V e r tic a l : 1
Fig 31 The channel position and size control in frame record mode
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TW2834 Video Controller
Preliminary
DVR Normal Record Mode
The DVR normal record mode outputs the continuous video stream for compression part (MJPEG or MPEG) in DVR application. Like normal record mode, each channel position and size
can be defined using its own PIC_SIZE (1x6C), and PIC_POS (1x6D) register.
The channel size is defined via the PIC_SIZE register such as “0” for Horizontal/Vertical half
size (QUAD), “1” for Horizontal full size and Vertical half size, “2” for Horizontal half size and
Vertical full size, and “3” for Horizontal/Vertical full size. The channel position is defined via the
PIC_POS register such as “0” for no Vertical offset, “1” for Vertical 1/4 picture offset, “2” for
Vertical 1/2 picture offset and “3” for Vertical 3/4 picture offset. The channel size and location
should be defined within the full picture size. In DVR normal record mode, the TW2834 also
supports the full operation mode such as live, strobe or switch operation and provides a pop-up
attribute via the POP_UP register. But the channel boundary is not supported in DVR normal
record mode. The following Fig 32 shows the example of the channel position and size control
in DVR normal record mode.
DVR Normal Record Mode (Quad)
(PIC_SIZE = 0)
Normal Record Mode (Quad)
(PIC_SIZE = 0)
0
Pixels
360
0
720
00
Pixels
360
720 PIC_POS
00
Lines
60/72
120/144
60/72
PIC_POS = 0
PIC_POS = 1
01
120/144
10
180/216
180/216
11
240/288
PIC_POS = 2
PIC_POS = 3
240/288
Output Video is scaled to Quad
(360 pixels X 120 Lines / Ch)
Vertical is divided to 2
Horizontal is divided to 2
Odd line
Even line
Output Video is scaled to Quad
(720 pixels X 60 Lines / Ch)
Vertical is divided to 4 region
Fig 32 The channel position and size control for DVR normal record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
DVR Frame Record Mode
The DVR frame record mode is the combination of frame record mode and DVR normal record
mode. The odd or even field selection is controlled via the FRAME_FLD (1x51) register like
frame record mode. The TW2834 also supports the full operation mode such as live, strobe or
switch operation, but the channel boundary is not supported in DVR frame record mode. The
following Fig 33 shows the example of DVR frame record mode.
Frame Record Mode (Frame-Quad)
(PIC_SIZE = 0)
Pixels
360
0
DVR Frame Record Mode (Frame-Quad)
(PIC_SIZE = 0)
720
Vertical Blanking (Odd)
0
Lines
120/144
PIC_POS = 0
PIC_POS = 1
240/288
Vertical Blanking (Even)
360/432
480/576
720
Vertical Blanking (Odd)
0
240/288
Pixels
360
0
PIC_POS = 2
PIC_POS = 3
480/576
PIC_POS = 0
PIC_POS = 1
Vertical Blanking (Even)
PIC_POS = 2
PIC_POS = 3
Odd line
Even line
Output Video is scaled to Frame Quad
(720 pixels X 120 Lines / Ch)
Vertical is divided to 4
Horizontal is divided to 1
Output Video is scaled to Frame Quad
(360 pixels X 240 Lines / Ch)
Vertical is divided to 2
Horizontal is divided to 2
Fig 33 The channel position and overlay for DVR frame record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Realtime Record/Playback Mode
The TW2834 supports 4 channel real-time record output with full D1 or scaled format. In this
case, the external SDRAM in record path should not be used so that four channel full D1 data
can be output with 54MHz ITU-R BT 656 format though the SDRAM interface pins such as
DATAY[15:0], ADDRY [10:0], BA0Y, WEBY, RASBY, CASBY, and DQMY pin. The I/O of
SDRAM Interface pins are controlled via the MEM_OP_EN (1x55) register such as “0” for 4
channel digital output mode and “1” for normal operation mode. The real-time record output
format can be selected via the DEC_BYP_EN (1xBB) register such as “1” for scaled display
output mode, “2” for scaled record output mode, and “3” for full D1 output mode. Four channel
real-time record output is synchronous with each video decoder timing. Each channel H/V/F
signal can be monitored through the MPPDEC pins via the control of the MPPSET (1x50)
register. The following Fig 34 shows the example of 4 channel real-time record / playback
application.
MCLKY
VDOUTX
VIN0
0~3
Input
2
CLK27ENCY
CLK27ENCX
ADDRY[10:3]
4 Record Input
ADDRY[2:0]…DQM
VIN1
1
VIN2
PBCLK
PBIN
TW 2834
VIN3
Backend
Processor
BA1X
VDOUTY
4 Playback Output
ADDRX[12]
DATAY[15:8]
ADDRX[11]
DATAY[7:0]
4 Ch Display
Full D1 Capture
2
1
0
1
0
2
3
1
2
3
Fig 34 The example of 4 channel record connection with 54MHz time multiplexing
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Playback Path Control
The TW2834 supports the playback function for variable record mode input such as normal
record mode, frame record mode, DVR normal record mode, and DVR frame record mode. The
TW2834 also supports auto cropping and auto strobe function for playback input with auto
channel ID decoding.
The TW2834 provides various playback functions for normal record mode input. If the channel
operation mode is live mode (FUNC_MODE = “0”), the playback input can be bypassed in
display path, but the auto cropping function from the channel ID decoder is available to separate
each channel from the multi-channel format such as QUAD (Auto cropping function is described
in “Cropping Function” section, page 26).
The TW2834 supports not only auto cropping function but also auto strobe function for playback
input through auto channel ID decoder. The auto strobe function implies that the selected
channel by the PB_CH_NUM (1x16, 1x1E, 1x26, 1x2E) register is updated automatically from
the playback input of the time-multiplexed full D1 or quad format via auto channel ID decoder.
If the channel operation mode is strobe mode (FUNC_MODE = “1”), the auto strobe function is
used to update the channel automatically. The TW2834 also supports event strobe mode using
event information in auto channel ID. It makes the channel updated whenever event information
in auto channel ID is detected. The event strobe mode can be enabled via the EVENT_PB
(1x16, 1x1E, 1x26, 1x2E) register. The auto strobe function can also be used to display pseudo
8-channel with dummy channel for playback input of the dual page or pseudo 8-channel MUX
using analog switch.
The TW2834 also provides an anti-rolling function for picture configuration change in playback
application via the PB_STOP (1x16, 1x1E, 1x26, 1x2E) register. If the PB_STOP is set to high
in strobe operation mode (FUNC_MODE = “1”), the channel is not updated until the PB_STOP
is set to low after picture configuration change.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Normal Record Mode
The following Fig 35 shows the examples of playback function for normal record mode using
cropping, scaling and repositioning.
Playback Input (QUAD)
Display Path Output
1. Bypass (1Ch)
CH0
CH1
CH2
CH0
CH3
CH2
2. Bypass + Scaling (1Ch)
CH0
CH1
CH2
CH3
CH1
CH2
(Live)
CH3
CH1
CH2
CH3
CH1
(Live)
CH3
CH1
(Live)
CH3
(Live)
CH2
(Live)
CH3
(Live)
5. Crop + Reposition + Scaling
(3Ch)
4. Crop + Reposition (4Ch)
CH1
3. Bypass + Crop (1Ch)
CH2
6. Crop + Reposition +
Scaling + Popup (3Ch)
CH3
CH3
CH0
(Live)
CH0
(Live)
CH0
CH1
CH2
Fig 35 The examples of the playback function for normal record mode
The following Fig 36 shows the various examples for auto cropping and strobe function.
Playback Input
1. Dual Page
Display Path Output
Bypass (1Ch)
CH0
CH1
CH4
CH5
CH0
CH1
CH2
CH3
CH6
CH7
CH2
CH3
2. 16Ch Quad-MUX
Bypass (1Ch)
CH0
CH0
CH1
CH2
CH3
CH2
CH1
CH3
CH4
CH6
CH5
CH7
3. Switch mode
Strobe (1Ch)
Scaling + Strobe (1Ch)
CH0 CH1
CH2 CH3
CH1
(Live)
CH2
CH3
(Live) (Live)
Scaling + Strobe (1Ch)
CH4 CH5
CH6 CH7
CH1
(Live)
CH2
CH3
(Live) (Live)
Strobe + Scale (1Ch)
Scaling + Strobe
(1Ch)
CH0 CH1 CH4 CH5
CH1
4. Pseudo-8Ch MUX
CH0
Strobe (1Ch)
CH0
CH1
Crop + Strobe (1Ch)
CH1
CH2
CH2
CH3
(Live) (Live)
CH2
CH3
(Live) (Live)
CH3
CH0
Crop + Strobe (1Ch)
Crop + Strobe (4Ch)
CH2 CH3 CH6 CH7
CH5
CH0
CH0
CH4
CH0
CH1
(Live)
CH1
CH2
CH2
CH3
(Live) (Live)
CH3
CH0
CH0
Crop + Strobe (2Ch)
CH1
Crop + Scale + Strobe
(1Ch)
CH0
CH1
(Live)
CH2
CH3
(Live) (Live)
CH2
CH3
(Live) (Live)
Crop + Strobe (1Ch)
Crop + Scale + Strobe
(1Ch)
CH0
CH0
Crop + Strobe (4Ch)
CH1
(Live)
CH0
CH0
Crop + Strobe (1Ch)
CH4
CH2
CH3
(Live) (Live)
CH1 CH2 CH3
CH0
CH4
CH5 CH6 CH7
Crop + Strobe + scale
(4Ch)
CH1 CH2 CH3
CH0
(Live)
Crop + Scale + Strobe
(4Ch)
CH1
CH3
CH2
CH1
CH2
CH3
(Live) (Live)
CH3
CH1 CH2 CH3
CH2
CH1
CH2
Crop + Scale + Strobe
(4Ch)
CH1 CH2 CH3
CH0
CH0
CH3
CH0
CH0
CH0
Crop + Scale + Strobe
(4Ch)
CH1
(Live)
CH0
Crop + Scale + Strobe
(4Ch)
CH4
CH1 CH2 CH3
CH0
CH5 CH6 CH7
Fig 36 The example of auto strobe function for normal record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Frame Record Mode
The TW2834 supports the playback function for playback input of frame record mode. The
playback input of frame record mode is formed with 1 frame so that the vertical lines of each
playback channel have twice as many as the normal record mode. So if the displayed channel
size is half size of the playback input in vertical direction, the playback input can be separated
into two (odd/even) fields according to the line numbers such as odd line for odd field and even
line for even field. With this conversion, the vertical resolution of the playback input can be
enhanced compared with simple half vertical scaling of the playback input. This mode can be
enabled via the FIELD_OP (1x76) register. The following Fig 37 shows the illustration of this
conversion from frame record mode to normal display mode in playback application.
0
Frame Record Mode (Frame-Quad)
(Play back Input)
Pixels
0
360
720
Vertical Blanking (Odd)
Normal Display Mode (Quad)
Pixels
360
Vertical Blanking (Odd)
0
CH0 (Odd Line)
0
720
C
H
0
n
ve
(E
120/144
CH 0
CH
CH 33
Lines
)
ne
Li
240/288
CH 0
CH 1
Vertical Blanking (Even)
CH 22
240/288 CH
0
360/432
480/576
CH 2
CH 3
480/576
Input Video is Frame Quad
(360 pixels X 240 Lines / Ch)
Vertical is divided to 2
Horizontal is divided to 2
CH
CH 11
Vertical Blanking (Even)
CH 0
CH 3
CH 2
CH 1
Output Video is divided to Odd/Even
(360 pixels X 120 Lines / Ch * 2 Field)
Odd Line Data go to Odd Field.
Even Line Data go to Even Field.
Fig 37 The conversion from frame record mode to normal display mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
The following Fig 38 shows the various examples of auto cropping and strobe function for
playback input of frame record mode.
P la yb a c k In p u t
(F ra m e R e c o rd M o d e )
CH0
CH1
D is p la y P a th O u tp u t
2 . S tro b e (2 C h )
1 . S tro b e (2 C h )
CH0
CH1
CH0
4 . S tro b e + S ca le + C ro p (1 C h )
CH2
CH3
CH1
CH1
(LIV E )
CH2
(L IV E )
CH3
(LIV E )
CH0
CH2
CH2
(L IV E )
CH3
(L IV E )
CH3
5 . C ro p + S c a le + S tro b e (4 C h )
CH1
3 . S tro b e + S c a le (2 C h )
6 . C ro p + S ca le + S tro be (1 C h )
CH2
CH1
(L IV E )
CH3
CH0
CH1
Fig 38 The examples of the playback function for frame record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
DVR Normal Record Mode
If the playback input is the DVR normal record mode, it cannot be displayed directly because it
is special mode not for display but for record to compression part. The TW2834 supports the
conversion from this DVR normal record mode to normal display mode via the DVR_IN (1x76)
register. For auto cropping function of the playback with this mode, the PB_CROP_MD (0x38)
register should be set into “1” to crop the 1/4 vertical picture size (Please refer to “Cropping
Function” section in Page 26). The auto strobe function and all channel attributes can also be
supported, but the scaling function cannot be supported in this mode. The following Fig 39
shows the illustration of conversion from DVR normal record mode to normal display mode in
playback application.
0
0
DVR Record Mode In Quad Size
(Play back Input)
Pixels
360
Normal Display Mode In Quad Size
0
720
Pixels
360
720
0
Lines
Lines
60/72
120/144
120/144
180/216
240/288
240/288
Odd line
Even line
Input Video is DVR display mode.
(720 pixels X 60 Lines / Ch)
Vertical is divided to 4 region
Output Video is Monitor display mode
(360 pixels X 120 Lines / Ch)
No scaling & DVR_IN = “1”
(Odd/Even Line is gathering to 1 region)
Fig 39 The conversion from DVR normal record mode to normal display mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
DVR Frame Record Mode
The TW2834 also provides the conversion from DVR frame record mode to normal display
mode using combination of frame record mode and DVR normal record mode via the DVR_IN
and FIELD_OP (1x76) register. Likewise, the auto strobe function and all channel attributes can
also be supported, but the scaling function cannot be supported in this mode. The following Fig
40 shows the illustration of conversion from DVR frame record mode to normal display mode in
playback application.
Frame Record Mode (Frame-Quad)
(Play back Input)
Pixels
360
0
Normal Display Mode (Quad)
720
Pixels
360
0
Vertical Blanking (Odd)
0
Left Half Line
0
gh
Ri
tH
CH 0
alf
120/144
720
Vertical Blanking (Odd)
120/144
CH 0
CH 1
Lin
Lines
e
240/288
CH 1
240/288
Vertical Blanking (Even)
CH 2
CH 3
Vertical Blanking (Even)
0
360/432
CH 2
120/144
480/576 CH 3
Input Video is Frame Quad
(720 pixels X 120 Lines / Ch)
Vertical is divided to 4
Horizontal is divided to 1
240/288
CH 0
CH 1
CH 2
CH 3
Output Video is divided to Odd/Even
(360 pixels X 120 Lines / Ch * 2 Field)
Left Half Line Data go to Odd Field.
Right Half Line Data go to Even Field.
Fig 40 The conversion from DVR frame record mode to normal display mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Real-time Record/playback Mode
The TW2834 provides 4 channel playback input in real-time 4 channel full D1 record application.
This mode supports ITU-R BT. 656 interface with 27MHz through the PBIN, DATAY, VDOUTY
pins for 4 playback inputs. The DATAY[15:0] pins are used for playback input 2 and 3 via the
DEC_BYP_EN (1xBB) register such as “0” for normal operation mode, and “1/2/3” for playback
input mode. The VDOUTY pins are used for playback input 1 via the VDOUTY_MODE (1x8C)
register. The ADDRX [12:11] and BA1X pin can be used for 4ch playback clock input via the
ADDR_OUT_EN (1x05) register.. In this case, the Save/Recall function of display path cannot
be supported because the extended SDRAM pin interface is shared for it. The following Fig 41
shows the example of 4 channel real-time record/playback application.
2
VDOUTX
CLK27ENCY
CLK27ENCX
ADDRY[10:3]
VIN0
0~3
Input
4 Record Input
ADDRY[2:0]…DQM
VIN1
1
VIN2
PBCLK
PBIN
TW2834
VIN3
Backend
Processor
BA1X
VDOUTY
4 Playback Output
ADDRX[12]
DATAY[15:8]
ADDRX[11]
DATAY[7:0]
4 Ch Display
Full D1 Capture
2
1
0
1
0
2
3
1
2
3
Fig 41 The example of 4 channel real-time record/playback application
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Real-time Record/Spot Mode
The TW2834 provides 4 channel realtime record output, 1 channel spot output, 1 channel
display output and 1 channel playback input simultaneously. In this mode the SDRAM interface
for Y path are used for spot output with normal operation and the VDOUTX pins are used for
output interface of display and spot data with 54MHz ITU-R BT 656 format. The VDOUTY pins
are used for real-time record output interface of channel 2/3 via the BYPASS_Y (1x83) register
of “11b” value and CCIR_IN_SEL (1x80) register of “2, 3” value. The MPPDEC pins are used for
real-time record output interface of channel 0/1 via the BYP_MPP (1xBB) register of “1” value,
MPPSET_X register of “8” value and MPPSET_Y (1x 50) register of “9” value.
In this mode, the TW2834 support independent 2 analog output for display and spot, but
provides only 1 playback input interface through the PBIN pins and cannot be extended to 8/16
application because MPPDEC pins are used for real-time record output interface.
The following Fig 42 shows the example of 4 channel real-time record/spot application.
2
VDOUTX
VIN0
0~3
Input
Display + Spot
CLK27ENCY
CLK27ENCX
VIN1
1
TW 2834
VIN2
VDOUTY
VIN3
PBCLK
PBIN
4 Ch Display/Spot
2
1
0
2
3
Backend
Processor
4 Record Input
MPPDEC
4 Playback Output
Full D1 Record
1
0
1
2
3
0
1
2
Fig 42 The example of 4 channel real-time record/spot application
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Channel ID Encoder
The TW2834 supports the channel ID encoding to detect the picture information in video stream
for Y path. The TW2834 has two kinds of channel ID such as User channel ID and Auto channel
ID. The User channel ID is used for customized information such as system information and
date. The Auto channel ID is employed for automatic identification of picture configuration. The
Auto channel ID includes the channel number with cascade stage, analog switch, event, region
enable and field/frame mode information. The TW2834 also supports both analog and digital
type channel ID during VBI period.
Channel ID Information
The channel ID can be composed of 16 byte User channel ID and 4 byte Auto channel ID. The
User channel ID is defined by user and may be used for system information, date and so on.
The Auto channel ID is used to identify the current picture configuration. Basically the Auto
channel ID has 4 byte data that contains 4 region channel information in one picture such as
QUAD split image. That is, each region has 1 byte channel information. The Auto channel ID
format is described in the following Table 4.
Table 4 The Auto channel ID information
Function
Bit
Name
7
REG_EN
6
EVENT
5
FLDMODE
Sequence Unit (0 : Frame, 1 : Field)
4
ANAPATH
Analog switch information
[3:2]
CASCADE
Cascade Stage Information
[1:0]
VIN_PATH
Video Input Path Number (depending on DEC_PATH_Y)
Region Enable Information
New Event Information
The REG_EN is used to indicate whether the corresponding 1/4 region is active or blank region.
The EVENT is used to denote the update information of each channel in live, strobe or switch
operation. Especially the EVENT information is very useful for switch operation or non-realtime
application such as pseudo 8ch or dual page mode because each channel can be updated
whenever EVENT is detected. The FLDMODE is used to denote the sequence unit such as
frame or field. The ANAPATH is used to identify the analog switch information in the channel
input path. The ANAPATH information is required for non-realtime application such as pseudo
8ch, dual page or pseudo 8channel MUX application using analog switch. The CASCADE is
used to indicate the cascade stage of channel in chip-to-chip cascade application. The
VIN_PATH information is used to indicate the video input path of channel.
Four bytes of Auto channel ID can be distinguished by its order. The first byte of Auto channel
ID defines the left top region configuration. Likewise the second byte defines the right top, the
third byte defines the left bottom and the fourth byte defines the right bottom region
configuration in one picture.
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TW2834 Video Controller
Preliminary
The following Fig 43 shows the example of Auto channel ID.
QUAD Frame
CIF + QUAD (Frame)
Auto Channel ID
CH0
CH0
CH1
CH1
A1 = “1100_0001
CH2
CH2
CH3
CH3
A2 = “1100_0010
A3 = “1100_0011
QUAD (DVR, Frame)
CH3
CH3
CH2
CH2
CH0
CH0
CH1
CH1
CH3
CH3
CH2
CH2
CH0
CH0
CH1
CH1
CH2
CH2
A0 = “1100_0000
CIF (Odd Field)
Auto Channel ID
Auto Channel ID
A0 = “1100_0000
A0 = “1110_0001
A1 = “1100_0010
CH0
CH0
CH3
CH3
A0 = “1100_0011
CH1
CH1 CH1
CH1
A1 = “1100_0010
A2 = “1100_0000
A3 = “1100_0001
A1 = “1110_0010
A2 = “1110_0001
A3 = “1100_0011
A3 = “1110_0010
CIF (Even Field)
Auto Channel ID
Auto Channel ID
A0 = “1100_0000
A0 = “1110_0000
A1 = “1100_0010
CH2
CH2 CH2
CH2
CH2
A2 = “1100_0000
CIF + DVR Frame
Auto Channel ID
CH1
CH0
CH3
A1 = “1110_0011
A2 = “1100_0010
A2 = “1110_0000
A3 = “1100_0011
A3 = “1110_0011
Fig 43 The example of Auto channel ID
These information of encoded channel ID can be readied via AUTO_CHID0 ~ AUTO_CHID3
(1xE0 ~ 1xE3) register and updated at the beginning of each field.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Analog Type Channel ID in VBI
The TW2834 supports the analog type channel ID during VBI period. The analog channel ID
has max 8 lines whose line width can be controlled by the VIS_LINE_WIDTH (1xC4) register
and each line has 2 bytes channel information. The H/V start position of analog channel ID is
controlled by the VIS_LINE_OS (1xC4) register for vertical direction with 1 line unit and
VIS_H_OS (1xC2) register for horizontal direction with 2 pixels unit. The pixel width of each bit
is controlled by the VIS_PIXEL_WIDTH (1xC3) register with 1 pixel unit. The magnitude of each
bit is defined by the VIS_HIGH_VAL (1xC5) and the VIS_LOW_VAL (1xC6) register. The analog
channel ID can be enabled independently for each path via the VIS_ENA (1xC1) register. The
following Fig 44 shows the illustration of analog channel ID.
Video Output
H
V
VIS_LINE_OS
VIS_LINE_WIDTH
F
Analog Channel ID Format 1
Horizontal Active Period
Run-In Clock
A0 = 11000000
A1 = 11000001
VIS_HIGH_VAL
VIS_LOW_VAL
1
VIS_H_OS
1
0
0
0
0
0
0
VIS_PIXEL_WIDTH
P0 1
1
0
0
0
0
0
1
P1
Parity
Parity
Auto channel ID (A#) : Odd parity
User channel ID (U#) : Even parity
Channel ID Type of each line can be detected with parity bit type.
Analog Channel ID Format 2 (Mixed Format)
Auto Channel ID (2 bytes)
A0 = 11000000,1
1st
User Channel ID (2 Bytes)
A1 = 11000001,0
2 Bytes are auto channel ID which has odd parity and
2nd
U0 = 11000000,0
U1 = 11000001,1
2 Bytes is user channel ID which has even parity.
Fig 44 The illustration of analog channel ID
The analog channel ID consists of run-in clock, data and parity bit. The run-in clock insertion is
enabled via the VIS_RIC_EN (1xC0) register. The format of analog channel ID is selected via
the VIS_MIX_EN (1xC1) register which indicates the analog channel ID format 1 with “0” value
and analog channel ID format 2 with “1” value. For analog channel ID format 1, the channel ID
has 2 bytes per line and the Auto/User channel ID can be selected via the VIS_SEL (1xC1)
register with 2 line unit. For analog channel ID format 2, the channel ID has 4 bytes per line and
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
each line has both 2 byte Auto channel ID and 2 byte User channel ID. Each byte of channel ID
has a parity bit and the kind of channel ID can be detected with this parity type. That is, the odd
parity type is used for Auto channel ID and even parity for User channel ID. Therefore, the parity
type should be same for 2 bytes of channel ID.
The TW2834 supports a robust error detection mode via the VIS_EC_EN (1xC1) register. In this
case, the Auto channel ID occupies 4 lines that consist of first 2 lines for normal channel ID and
next 2 lines for inverted channel ID.
Digital Type Channel ID in VBI
The TW2834 also provides the digital type channel ID during VBI period. It’s useful for DSP
application because the channel ID can be inserted in just 1 line with special format. The digital
channel ID is located after analog channel ID line. The digital channel ID can be enabled via the
VIS_CODE_EN (1xC1) register.
The digital channel ID is inserted in Y data in ITU-R BT.656 stream and composed of ID # and
channel information. The ID # indicates the index of digital type channel ID including the Start
code, Auto/User channel ID and End code. The ID # has 0 ~ 63 index and each 1 byte channel
information is divided into 2 bytes with 4 LSB to take “50h” offset against ID # for discrimination.
The Start code is located in ID# 0 ~ 1 and the Auto channel ID is situated in ID# 2 ~ 9. The User
channel ID is located in ID # 10 ~ 41 and the inverted Auto channel ID is situated in ID # 42 ~
49 only when VIS_EC_EN = “1”. The End code occupies the others. The digital channel ID is
repeated more than 5 times during horizontal active period. The following Fig 45 shows the
illustration of the digital channel ID.
Timing Format
Digital Channel ID (1 Line)
H
V
Analog Channel ID (Max 8 Lines)
F
Video Output
Digital Channel ID
Horizontal Active Period (1440 Pixel)
SAV
P0
P1
P2
P1440EAV
P3
FFh 00h 00h XYh 00h 00h 00h 5Fh 00h 01h 00h 50h 00h 02h 00h 5Ch 00h 03h 00h 50h
Cb
Y
Cr
SAV
00h 3Eh 00h 50h 00h 3Fh 00h 50h 00h 00h
Y
st
1 Start Code
2
nd
st
Start Code
1 Auto Channel ID 2
nd
Auto Channel ID
63th End Code
64th End Code
Full Ch Id Set = 256 Pixels
00h ID #
00h
Repeated Again
Data
Digital Channel ID Format
Id #
0
1
2
~
Data
5Fh
50h
{0101, A0_MSB}
~
description
Start Code
9
10
{0101, A3_LSB} {0101, U0_MSB}
Auto Channel ID (4 Bytes)
~
41
42
~
49
~
{ 0101, U15_LSB}
{0101, !A0_MSB}
~
{0101, !A3_LSB}
User Channel ID (16 Bytes)
50
Inverted Auto Channel ID (Option)
Or End Code {0101, 0000}
--
63
{0101, 0000}
End Code
Fig 45 The illustration of the digital channel ID in VBI period
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Digital Type Channel ID in Channel Boundary
The TW2834 also support the extra type of the digital channel ID in horizontal boundary for
each channel. This information can be used for very easy memory management of each
channel because this digital channel ID information includes not only the channel information
but also line number of picture. The Auto channel ID format is described in the following Table 5.
Table 5 The digital channel ID information in active area
Name
Function
Bit
[15:7]
LINENUM
6
FIELD
Active Line number
5
REG_EN
Region Enable Information
Field Polarity Information
4
ANAPATH
Analog switch information
[3:2]
CASCADE
Cascade Stage Information
[1:0]
VIN_PATH
Video Input Path Number (depending on DEC_PATH_Y)
This digital channel ID is enabled in the horizontal active area by setting “1” to the CH_START
(1x55) register. The following Fig 46 shows the digital channel ID in the horizontal active area.
Video Output
0
Line #
CH 1
Digital Data for
Channel ID
SAV
Horizontal Active Period
P0
P1
P2
P3
FFh 00h 00h XYh 21h 01h 23h 01h
Cb
SAV
No channel Area
CH 2
23h
Y
Cr
Y
CH 1 Start Code
Channel 1 Data
P0
P1
P2
P3
22h 01h 23h 01h
Cb
Y
Cr
Y
CH 2 Start Code
00h
Data { Linenum[8], ENC_FIELD, VALID, ANA_PATH, CASCADE(2 Bit), VIN_PATH(2Bit) }
00h
Linenum[7:0]
Channel 2 Data
P0
P1
P2
P3
Blank Data
EAV
00h 01h 23h 01h
Cb
Y
Cr
Y
No video Start Code
Fig 46 The digital channel ID format in the horizontal active area
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Chip-to-Chip Cascade Operation
The TW2834 supports chip-to-chip cascade connection up to 4 chips for 16-channel application
and also provides the independent operation for display and record path. That is, the display
path can be operated with cascaded connection even though the record path is working in
normal operation. Likewise, the cascade connection of record path is limited within 4 chips while
the infinite cascade connection of display path can be supported for more than 16-channel
application. For the record path in cascade connection, the TW2834 supports the switch
operation mode with switching queue for full D1 multiplexing output or the auto strobe operation
mode with QUAD_MUX queue for QUAD multiplexing output.
Channel Priority Control
When 2 channels are overlapped in chip-to-chip cascade operation for display path, there is a
priority with the following order such as popup attributed channel of master device, popup
attributed channel of slaver device, non-popup attributed channel of master device and nonpopup attributed channel of slaver device. Using this popup attribute, the TW2834 can
implement the channel overlay such as PIP, POP, and full D1 format channel switching in chipto-chip cascade connection.
For QUAD multiplexing record output in chip-to-chip application, the popup priority of the
channel is controlled via the QUAD_MUX queue. The QUAD_MUX operation is enabled via the
POS_CTL_EN (1x70) register and the operation mode should be set into strobe operation
(FUNC_MODE = “1”). If the POS_CTL_EN is “0”, the channel position is defined via the
PIC_POS (1x6D) register and the priority from top to bottom layer is controlled by the popup
attribute like the display path. If the POS_CTL_EN is “1”, the channel position and priority is
controlled by the pre-defined queue or interrupt.
The TW2834 supports the interrupt triggering via the POS_INTR (1x70), POS_CH (1x73, 1x74)
register and also provides the internal or external triggering mode for the QUAD_MUX operation.
The triggering mode is selected via the POS_TRIG_MODE (1x70) register such as “0” for
external trigger mode and “1” for internal trigger mode.
The QUAD_MUX queue size can be defined by the POS_QUE_SIZE (1x71) register. To change
the channel popup sequence in internal queue, the POS_QUE_WR (1x75) register should be
set to “1” after defining the queue address with the POS_QUE_ADDR (1x75) register and the
channel number with the POS_CH (1x73, 1x74) register. The POS_QUE_WR register will be
cleared automatically after updating queue. The QUAD_MUX queue is shared with the normal
switching queue so that the maximum queue size for QUAD_MUX is 32 (=128/4) depth.
The QUAD_MUX switching period can be defined via the POS_QUE_PERIOD (1x72) register
that has 1 ~ 1024 period range in the internal triggering mode. The switching period unit is
controlled via the POS_FLD_MD (1x71) register as field or frame. If switching period unit is
frame, switching will occur at the beginning of odd field. The internal field counter can be reset
at anytime using the POS_CNT_RST (1x75) register that will be cleared automatically after
reset. To reset an internal queue position, the POS_CNT_RST (1x75) register should be set to
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Q4
Q5
Q6
POS_INTR
POS_CH
Q2
Q1
Queue
Read/Write
Control
Q0
Popup/position
Interrupt
Detector
Popup/position
Arbitration
POS_TRIG_MODE
POS_POS_RST
Q3
Internal
Queue
Q7
POS_RST
POS_SIZE = 7
POS_CH
POS_ADDR
“1” and will be cleared automatically after set to “1”. The structure of QUAD_MUX switching
operation is shown in the following Fig 47.
Internal
Field
Counter
External
Triggering
Detector
Popup/position
Operation
Control
POS_PERIOD
POS_CNT_RST
POS_TRIG
POS_OUT_CH
Fig 47 The structure of QUAD_MUX switching operation when POS_SIZE = 7
For QUAD_MUX switching operation by field unit, the TW2834 supports an auto strobe mode
for channel to be updated automatically with specific field data. The STRB_FLD (1x04, 1x54)
register is used to select specific field data in strobe mode and the STRB_AUTO (1x07, 1x57)
register is used to update it automatically.
The QUAD_MUX operation has several limitations. The first is that the channel region should
not be overlapped with other channel region via the PIC_SIZE and PIC_POS register. The
second is that the channel position and popup property in live or strobe operation mode can be
controlled by the popup/position control. But the channel position and priority in switch operation
mode is determined by the QUAD_MUX queue. The third is that the POS_CH register in
QUAD_MUX queue should be set as the following sequence that is the left top, right top, left
bottom and right bottom position in the picture. The POS_CH register includes the cascade
stage and channel number information.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
120 CIF/Sec Record Mode
For chip-to-chip cascade connection, the MPPDEC and TRIGGER and LINK pin in master chip
should be connected to VDOUTX and VSENC and HSENC pin in slaver chips. So the VDOUTX
and VSENC and HSENC output pin is only available in master device when cascaded.
The TW2834 has several registers for cascade operation such as the LINK_EN, LINK_NUM
and LINK_LAST (1x00) register. For lowest slaver chip, both LINK_LAST_X and LINK_LAST_Y
should be set to “1”. To receive the cascade data from slaver chip, either LINK_EN_X or
LINK_EN_Y should be set to “1”. To transfer the cascade data properly among the chips, the
LINK_NUM should be set properly in accordance with its order. In 120 CIF/Sec record mode,
the TW2834 transfers all information of slaver chips to master chip including video data, zoom
factors, switching information and 2D box except overlay information such as single box, mouse
pointer and OSD information. Therefore, the master chip should be controlled for overlay and
the lowest slaver chip should be controlled for the others such as video data, zoom and
switching. The information of switching channel can be taken from master chip via the channel
ID in video stream or by reading the MUX_OUT_CH (1x08, 1x6E) register. The information of
switching channel can also be taken from the lowest slaver chip via the MPPDEC pins. The
following Fig 48 illustrates the cascade connection for 120 CIF/Sec record mode.
4
Display
(16ch Split)
Record
(16ch MUX)
5
time
0~3
Input
PB Input
5
Master
VIN0
VIN1
VIN2
VIN3
4
VDOUTX
(LINK_NUM =0)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0, VDOUTY
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
5
4 1 9 7
0 10 13 6
14 2 3 12
8 11 5 15
12 8
5
Slave1
VSENC
VDOUTX
HSENC
4
(LINK_NUM=1)
(LINK_LAST_X=0,
LINK_EN_X=1) VDOUTY
(LINK_LAST_Y=0,
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
Pop_up
time
3
VIN0
VIN1
VIN2
VIN3
13
12
13
8 4
9 5
0
1
1410
1511
6 2
7 3
switch
3
4~7
Input
3
Record
(Quad MUX)
X
9
10 13
14
8 11
5
12 8
7
6
12
15
5
5
128
13
139
4 4
5 5
1410
1511
6 6
7 7
Pop_up
switch
2
time
2
8~11
Input
VIN0
VIN1
VIN2
VIN3
Slave2
VSENC
12 8
9
10 13
VDOUTX
(LINK_NUM=2)
HSENC
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0, VDOUTY
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
X
14
8 11
12
8
8
13
12
15
8 8
14 10
switch
13
9 9
8
9
15 11
10
11
10
11
Pop_up
1
time
1
12~15
Input
VIN0
VIN1
VIN2
VIN3
Slave3
VSENC
VDOUTX
(LINK_NUM=3)
HSENC
(LINK_LAST_X=1,
LINK_EN_X=1)
VDOUTY
(LINK_LAST_Y=1,
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
12 12
12 12
13
13
14
X
12
15
switch
switch
12
14
12 12
14 14
13
12
15
14
13 13
15 15
13
15
Pop_up
Fig 48 The cascade connection for 120 CIF /sec record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
240 CIF/Sec Record Mode
The TW2834 supports 240 CIF/Sec record mode in the chip-to-chip cascade connection. In this
case, the display path is composed of 4 chip cascade stage, but the record path consists of 2
chip cascade stage. That is, two lowest slaver chips for record path should be set with the
LINK_LAST_Y = “1” and the information of switching channel can be taken from two master
chips for record path by reading the MUX_OUT_CH (1x6E) register. The following Fig 49
illustrates the cascade connection for 240 CIF/Sec record mode.
4
Display
(16ch Split)
Record (8ch MUX)
6
Record (Quad MUX)
time
0~3
Input
PB Input
6
Master
VIN0
VIN1
VIN2
VIN3
4
VDOUTX
(LINK_NUM =0)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0, VDOUTY
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
6
4 1 9 7
0 10 13 6
14 2 3 12
8 11 5 15
4
2
switch
3
VSENC
VDOUTX
HSENC
(LINK_NUM=1)
(LINK_LAST_X=0,
LINK_EN_X=1) VDOUTY
(LINK_LAST_Y=1,
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
4
Slave1
VIN0
VIN1
VIN2
VIN3
X
3
switch
9
10 13
14
8 11
5
4
7
6
12
15
4
switch
5
5
switch
2
5
2
8~11
Input
PB Input
5
VIN0
VIN1
VIN2
VIN3
Slave2
VSENC
5
14
8 11
Slave3
VSENC
VDOUTX
(LINK_NUM=3)
HSENC
(LINK_LAST_X=1,
LINK_EN_X=1)
VDOUTY
(LINK_LAST_Y=1,
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
X
5 5
4 4
5 5
6 6
7 7
6 6
7 7
Pop_up
14
switch
Pop_up
Record (Quad MUX)
13
8
12
14 10
14
9
8
15 11
10
13
15
9
11
Pop_up Pop_up
time
12 12
13 13
14
13
14
Pop_up Pop_up
12
13 9
switch
1
VIN0
VIN1
VIN2
VIN3
switch
12
15
1
12~15
Input
5
0 4
1 5
0
1
7 3
6 2
7 3
6 2
4 4
6
Record (8ch MUX)
time
12 8
9
10 13
VDOUTX
(LINK_NUM=2)
HSENC
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0, VDOUTY
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
6
time
3
4~7
Input
4
5
12
15
switch
switch
switch
12
14
12 12
14 14
Pop_up
13
12
15
14
13 13
15 15
13
15
Pop_up
Fig 49 The cascade connection for 240 CIF/sec record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
480 CIF/Sec Record Mode
The TW2834 also supports 480 CIF/Sec record mode in the chip-to-chip cascade connection. In
this case, the display path is composed of 4 chip cascade stage, but the record path has no
cascade connection. Even though the record path has no cascade connection, the LINK_NUM
should be set properly in accordance with its cascade order for correct channel number in
channel ID and the LINK_EN_Y should be set to “0” or the LINK_LAST_Y should be set to “1”.
The TW2834 transfers the slaver chip information to master chip such as zoom control and 2D
box only for display path and the information of the switching channel for record path can be
taken from each chip by reading for the MUX_OUT_CH (1x6E) register. The TW2834 also
provides the channel ID encoding for each chip. The following Fig 50 illustrates cascade
connection for 480 CIF/Sec record mode.
4
8
Display (16ch Split)
0~3 Input
PB Input
8
VIN0
VIN1
VIN2
VIN3
Master
4
VDOUTX
(LINK_NUM=0)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0, VDOUTY
PBIN
LINK_EN_Y=0)
LINK
TRIGGER
MPPDEC
4 1 9 7
0 10 13 6
14 2 3 12
8 11 5 15
8
time
Record (4ch MUX or QUAD)
0 1
2 3
0
1
2
3
3
3
7
Record (4ch MUX or QUAD)
time
4~7 Input
PB Input
7
VIN0
VIN1
VIN2
VIN3
Slave1
VSENC
VDOUTX
(LINK_NUM=1)
HSENC
(LINK_LAST_X=0,
LINK_EN_X=1) VDOUTY
(LINK_LAST_Y=0,
PBIN
LINK_EN_Y=0)
LINK
TRIGGER
MPPDEC
4
7
9
10 13
14
8 11
5
7
6
12
15
5 7
4 6
4
5
6
7
2
6
2
Record (4ch MUX or QUAD)
time
8~11 Input
PB Input
6
VIN0
VIN1
VIN2
VIN3
Slave2
VSENC
VDOUTX
(LINK_NUM=2)
HSENC
(LINK_LAST_X=0,
LINK_EN_X=1) VDOUTY
(LINK_LAST_Y=0,
PBIN
LINK_EN_Y=0)
LINK
TRIGGER
MPPDEC
9
10 13
14
12
8 11
15
6
8 9
10 11
8
9
10
11
1
1
5
Record (4ch MUX or QUAD)
time
12~15 Input
PB Input
5
VIN0
VIN1
VIN2
VIN3
Slave3
VSENC
VDOUTX
(LINK_NUM=3)
HSENC
(LINK_LAST_X=1,
LINK_EN_X=1) VDOUTY
(LINK_LAST_Y=1,
PBIN
LINK_EN_Y=0)
LINK
TRIGGER
MPPDEC
13
5
14
12
15
15 12
13 14
12
13
15
14
Fig 50 The cascade connection for 480 CIF/Sec record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Realtime Record Mode
The TW2834 also supports the real-time record mode in chip-to-chip cascade connection. In
this case, the TW2834 use the SDRAM interface pin of record path for real-time record and
playback interface. Like 480 CIF/Sec record mode, the record path has no cascade connection
but the display path can be extended with more than 4 chip cascade stage (It will be described
in the next “Infinite Cascade Mode for Display Path” section, page78). In real-time record mode,
the TW2834 does not support the channel ID encoding because there is no need of channel ID
insertion for independent full channel recording. The Fig 51 shows the example of real-time
record mode.
16 Ch Display
Full D1 Capture
4
0~3
Input
8
4 PB
Input
VIN0
VIN1
VIN2
VIN3
Master
PBIN
VDOUTY
DATAY[15:8]
DATAY[7:0]
TRIGGER
(LINK_NUM=0)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0,
LINK_EN_Y=0)
VSENC
VDOUTX
4
HSENC
ADDRY[10:3]
4 D1
Output
ADDRY..DQ M
LINK
MPPDEC
8
7
11
14
9
8
3
4
2
0 6
13 1
10 12
5 15
7
11
14
9
8
6
4
13
10 12
5 15
8
0
1
2
3
7
4
5
6
7
6
8
9
10
11
5
12
13
14
15
3
3
4~7
Input
7
4 PB
Input
VIN0
VIN1
VIN2
VIN3
Slave1
PBIN
VDOUTY
DATAY[15:8]
DATAY[7:0]
TRIGGER
(LINK_NUM=1)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0,
LINK_EN_Y=0)
VSENC
VDOUTX
HSENC
ADDRY[10:3]
ADDRY..DQ M
4 D1
Output
7
LINK
MPPDEC
2
2
8~11
Input
6
4 PB
Input
VIN0
VIN1
VIN2
VIN3
Slave2
PBIN
VDOUTY
DATAY[15:8]
DATAY[7:0]
TRIGGER
(LINK_NUM=2)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0,
LINK_EN_Y=0)
8
VSENC
VDOUTX
HSENC
ADDRY[10:3]
ADDRY..DQ M
4 D1
Output
11
14
9
6
13
10 12
15
LINK
MPPDEC
1
1
12~15
Input
5
4 PB
Input
VIN0
VIN1
VIN2
VIN3
Slave3
PBIN
VDOUTY
DATAY[15:8]
DATAY[7:0]
TRIGGER
(LINK_NUM=3)
(LINK_LAST_X=1,
LINK_EN_X=1)
(LINK_LAST_Y=1,
LINK_EN_Y=0)
VSENC
VDOUTX
HSENC
ADDRY[10:3]
ADDRY..DQ M
13
4 D1
Output
5
14
12
15
LINK
MPPDEC
Fig 51 The cascade connection for real-time record mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Infinite Cascade Mode for Display Path
In normal cascade connection, the master chip has LINK_NUM = “0” and the lowest slaver chip
has LINK_NUM = “3”. The master chip can output both display and record path, but the slaver
device can output only record path. To implement more than 16 channel application, the
TW2834 also provides the infinity cascade connection for display path. That is, the video data
and popup information can be transferred to next cascade chip even though the master chip is
set with LINK_NUM = “0” and the slaver chip with LINK_NUM = “3” for display path. This mode
can be enabled via the T_CASCADE_EN (1xBA) register.
The following Fig 52 illustrates the multiple cascade connection for display path. In this example,
the display path in the last master chip can output 32 channel video and the record path can
implement “480 CIF/sec” with lower 4 chips and “120 CIF/sec” with upper 4 chips
0~3
Input
PB Input
7
4
Master
VIN0
VIN1
VIN2
VIN3
4
VDOUTX
(LINK_NUM =0)
(LINK_LAST_X=0,
LINK_EN_X=1)
(LINK_LAST_Y=0, VDOUTY
PBIN
LINK_EN_Y=1)
LINK
MPPDEC
TRIGGER
7
Display
(multi-ch Split)
Capture (16ch MUX)
7
time
0 1 2 3 4 5 6 7
3
8 9 A BCDE F
4
4
B
D
0
0 1 2 3 4 5 6 7
3
timeCapture (4ch MUX)
3
Video
Input
Middle
Slave3
5
0 8
1 9
C
D
6 2
7 3
A
B
E
F
8 9 A BCDE F
Middle Slave1/2
VIN0
VIN1
VIN2
VIN3
Capture (Quad or
QUAD MUX)
VSENC
VDOUTX
HSENC
(LINK_NUM=3)
(LINK_LAST_X=0, VDOUTY
LINK_EN_X=1)
PBIN
(LINK_LAST_Y=1,
LINK
TRIGGER LINK_EN_Y=1)
MPPDEC
X
C
CDE F
C
C
D
D
0 1 2 3 4 5 6 7
Capture (Quad)
C C
D
C CD D D
E E
F
E EF F F
8 9 A BCDE F
2
switch
Video
Input
PB Input
6
Middle
Master
VIN0
VIN1
VIN2
VIN3
2
VSENC
VDOUTX
HSENC
(LINK_NUM=0)
(LINK_LAST_X=0,
LINK_EN_X=1) VDOUTY
PBIN
(LINK_LAST_Y=0,
LINK
LINK_EN_Y=1)
MPPDEC
TRIGGER
Capture (4ch MUX)
time
6
0
6
1
2
Pop_up
Capture (Quad)
0 0
3
1
0 1 2 3 4 5 6 7
0
2 2
2
8 9 A BCDE F
1 1
0
3 3
2
1
3
1
3
Middle Slave1/2
1
Video
Input
PB Input
5
VIN0
VIN1
VIN2
VIN3
Lowest
Slave3
C
VSENC
HSENC
VDOUTX
(LINK_NUM=3)
(LINK_LAST_X=1,
VDOUTY
LINK_EN_X=1)
(LINK_LAST_Y=1,
LINK
LINK_EN_Y=1) MPPDEC
TRIGGER
Capture (4ch MUX)
time
5
1
D
E
F
C
5
Capture (Quad)
C C
D D
D
C
D
E
F
E E
F F
E
F
C
PBIN
CDE F
Fig 52 Infinite cascade mode for display path
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
OSD (On Screen Display) Control
The TW2834 provides various overlay layers such as character/bitmap overlay, box overlay and
Font Data
Display
RAM
Font
RAM
Character
Overlay
Mouse
Overlay
VOSD_X
VVID_X
VVID_Y
Character
Overlay
Display
RAM
Font
RAM
Character Data
Font Data
Mouse
Overlay
VOSD_Y
To Video Encoder
VOUT_Y
Character Data
Single Box Overlay
MOTION
RESULT
Chip-to-Chip Cascade
& Path Overlay
VOUT_X
2D Box Overlay
From Video Control Part
mouse pointer that can be overlaid on display and record path independently. The following Fig
53 shows the overlay block diagram.
Fig 53 Overlay block diagram
The font data can be downloaded from host and supported up to 128 fonts * 2 fields * 16 pages.
The TW2834 supports 16 programmable single boxes and four 2D arrayed boxes that are
programmable for size, position and color.
Dual analog video outputs and dual digital video outputs can enable or disable a character and
mouse pointer respectively. The overlay priority of OSD layer is shown in Fig 54. The various
OSD overlay function is very useful to build GUI interface.
P ointer Layer
C haracter Layer
S ingle B ox Layer
2D B ox Layer
V ideo Layer
Fig 54 The overlay priority of OSD layer
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Character/Bitmap Overlay
The TW2834 has character overlay function for display and record path independently. Each
character overlay function block consists of a font RAM, a display RAM and an overlay control
block. A font RAM stores font data that can be downloaded from host at anytime. A display RAM
stores index, position and attributes of character to be displayed. Character size can be defined
as 8~16 dots for 360 pixel rate and 16 ~ 32 dots for 720 pixel rate in the horizontal and 10 ~ 16
lines in the vertical direction.
Bitmap data can also be downloaded from host like character. That is, Bitmap is almost same
as character except the control of class 0 color. A character type has a blank for class 0 color in
default mode, but a bitmap color has a selectable color for it. However, if CLASS0ENA (1xA0) is
set to “1”, even a character type can have a selectable color like bitmap type. In that case, a
character type is completely same as a bitmap type. The character and bitmap types can be
selected via the FONT_TYPE bit of character attributes in display RAM.
Download Font Group
The TW2834 supports 16 pages * 2 different font groups and each font group can have 128
fonts. A font consists of several dots such as 8 (10, 12, 14, 16 in 360 dot rate and 16, 20, 24, 28,
32 in 720 dot rate) x 10 (12, 14, 16) dots. 1 dot is composed of 2 pixels x 1 video line in 360 dot
rate and 1 pixel x 1 video line in 720 dot rate. Each dot has 2 bits to define colors (class 0,
class1, class2 and class3). The TW2834 has individual font RAM for display and record path so
that the different font data can be stored. The following Fig 55 shows a font RAM structure.
FONT_WR_FLD
15
0
1
0
1
¥á
¥â
¥ã
¥ä
A
a
A
B
b
B
C
c
C
d
*
?
Group0 Group1
+
Group30 Group31
X Path (FONT_REQ_X)
15
0
1
1
0
1
@
a
2
#
b
3
$
c
4
%
d
X
!
Y
\
Z
?
Group0 Group1
¥Á 0
¥Â
¥Ã
¥Ä
X
Y
Z
…
\
¥õ
¥÷
¥ø
15
…
&
#
$
0
…
!
0
…
Font Group
^
D
…
LSB
…
…
FONT_WR_DATA = 64 Bits
1 Dot Data (2 Bits)
0 : Class 0
1 : Class 1
2 : Class 2
3 : Class 3
15
D
15
MSB
0
…
FONT_WR_LINE
CHAR_VSIZE
0
0
FONT_WR_INDEX
FONT_WR_PAGE
CHAR_HSIZE
¥Ö
¥×
¥Ø127
Group30 Group31
Y Path (FONT_REQ_Y)
Fig 55 Font RAM structure
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
The font data can be written to font RAM via FONT_WR_FLD, FONT_WR_TYPE, and
FONT_REQ (1x9A), FONT_WR_LINE, FONT_WR_PAGE (1x99), FONT_WR_DATA (1x90 ~
1x97), FONT_WR_INDEX (1x98) register. By setting “1” to FONT_REQ, font data in the
FONT_WR_DATA is transferred to font RAM addressed by FONT_WR_PAGE, FONT_WR
_FLD, FONT_WR_LINE, and FONT_WR_INDEX. The FONT_REQ register has status
information of transferring in read mode. If the FONT_REQ = “1” in read mode, it means that the
TW2834 is busy in transferring font data. In this case, additional request cannot be accepted.
The following Fig 56 shows the flow chart of transferring font data to font RAM.
Font Download Start
W rite FO NT_W R_DATA
W rite FO NT_W R_INDEX
W rite FO NT_W R_PAG E
W rite FO NT_W R_LINE
W rite FO NT_W R_FLD
W rite FO NT_W R_TYPE
Set to high FO NT_REQ
NO
FONT_REQ = “0”
?
YES
NO
END O F W RITE
?
YES
Font Download End
Fig 56 Flow chart of downloading font data
The horizontal resolution of font is defined via the FONT_WR_TYPE such as “0” for 360 dot rate
with 8~16 dot size or for 720 dot rate with 16 dot size, “1” for 720 dot rate with 20~24 dot size,
and “2” or “3” for 720 dot rate with 28~32 dot size. The FONT_WR_TYPE also determines the
available index number of font as 128 font index for “0”, 86 index for “1” and 64 index for “2” or
“3”. The TW2834 requires special font data for index 0 to define blank character that will be
discussed in following “Write Character and Select Font Group” section (page 82). The max font
page size depends on the external SDRAM size in display path and the motion data path via the
MD_PATH (2x9E) register (Please refer to “Motion Detection” section, page 32).
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TW2834 Video Controller
Preliminary
Write Character and Select Font Group
The TW2834 has independent 2 display RAM for display and record path. Each character in the
display RAM has its own attributes that include mix, blink, class 3 color, type and font index.
Additionally, each character line in the display RAM has its own attributes that contain font page,
font field, horizontal and vertical size with 12 bit width. That is, the display RAM consists of
45x29 character attributes and 29x12bit character line attributes. Actually the number of
displayed characters depends on character size. The horizontal and vertical address of the
display RAM represents character position to be displayed. The following Fig 57 shows the
structure of the display RAM.
4bit
2bit
4bit
2bit
CHAR_
CHAR_HFSIZE
VFSIZE
CHAR_PAGE
CHAR_
FLD
CHAR_VLOC (0 ~ 28)
Character Line’s Attribute
Character Line Attribute RAM
CHAR_HLOC (0 ~ 44)
CHAR_VLOC (0 ~ 28)
Character Attribute RAM
Character’s Attribute
MIX BLINK CLASS3COL TYPE
1bit
1bit
2bit
1bit
INDEX
7bit
Fig 57 The structure of the display RAM
To define the location of the displayed characters, the CHAR_PATH, CHAR_WR_MODE,
CHAR_VLOC (1x9B), and CHAR_HLOC register should be set before writing the character
attribute and character line attribute. The CHAR_PATH defines the path (display or record path)
and CHAR_VLOC defines the vertical location of the displayed character. The
CHAR_WR_MODE defines the write mode of the display RAM such as “0” for writing character
attribute, “1” for writing one character line attribute and “2” for writing all character line attributes
to reset. In case of CHAR_WR_MODE = “1” or “2”, the character attribute can be written
continuously after the character line attributes are written.
The character line attribute consists of 12bit so that 2 bytes are required to write in display RAM.
The CHAR_RD_PAGE (1x9C) register selects one of 16 font pages and CHAR_RD_FLD
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TW2834 Video Controller
Preliminary
(1x9C) register defines the font field mode. Setting “0” to the CHAR_RD_FLD makes a
character overlay function disabled. If the CHAR_FLD is set to “1” or “2”, only one font group is
displayed for both odd and even field. But by setting “3” to the CHAR_FLD, the different font
groups are displayed on odd and even field respectively so that the character resolution can be
enhanced 2 times in vertical direction. The CHAR_VF_SIZE and CHAR_HF_SIZE (1x9C)
register defines the vertical and horizontal size of font.
Likewise, the character’s attribute consists of 12bit so that 2 bytes are required to write in
display RAM. The TW2834 supports the special procedure for writing to and reading from
display RAM as shown in the Fig 58. If the character’s attributes are written continuously in the
same path and vertical location, the CHAR_HLOC value increases by 1 automatically.
Only Character Attribute Write Procedure (CHAR_MODE = 0)
Slaver address Page index Register index
Serial
Interface
Slave_addr
0x01
0x9B
Register index
Parallel
Interface
0x9B
Location to be displayed
CHAR_PATH
CHAR_VLOC
CHAR_HLOC
Location to be displayed
CHAR_PATH
CHAR_VLOC
CHAR_HLOC
1st character’s attribute
Char_1[15:8]
Char_1[7:0]
1st character’s attribute
Char_1[15:8]
Char_1[7:0]
Nth character’s attribute
Char_n[15:8]
Char_n[7:0]
Nth character’s attribute
Char_n[15:8]
Char_n[7:0]
CSB1
CSB0
Only Character Line Attribute Write Procedure (CHAR_MODE = “1” or “2”)
Slaver address Page index Register index
Serial
Interface
Slave_addr
0x01
0x9B
Register index
Parallel
Interface
0x9B
Location to be displayed
CHAR_PATH
CHAR_VLOC
CHAR_FLD CHAR_VFSIZE
CHAR_PAGE CHAR_HFSIZE
Location to be displayed
CHAR_PATH
CHAR_VLOC
CHAR_FLD CHAR_VFSIZE
CHAR_PAGE CHAR_HFSIZE
CSB1
If CHAR_MODE = “0”,
Character line attribute write procedure
are skipped.
If CHAR_MODE = “1”,
Only current character Line’s Attribute
are changed to new setting value.
If CHAR_MODE = “2”,
All of character Line’s Attribute are
changed to new setting value.
CSB0
Both Character Line and Character Attribute Write Procedure (CHAR_MODE = “1” or “2”)
Slaver address Page index Register index
Serial
Interface
Slave_addr
0x01
0x9B
Location to be displayed
CHAR_PATH
CHAR_VLOC
Register index
Parallel
Interface
0x9B
CHAR_FLD CHAR_VFSIZE
CHAR_HLOC
CHAR_PAGE CHAR_HFSIZE
Location to be displayed
CHAR_PATH
CHAR_VLOC
CHAR_FLD CHAR_VFSIZE
CHAR_HLOC
CHAR_PAGE CHAR_HFSIZE
1st character’s attribute
Char_1[15:8]
Char_1[7:0]
1st character’s attribute
Char_1[15:8]
Char_1[7:0]
CSB1
CSB0
Fig 58 Writing procedure to display RAM
The TW2834 also supports the display RAM clear function that resets all character attributes in
display RAM automatically by setting “1” to RAMCLR (1xA0). This function requires that font
data in index 0 should be blank character and the CLASS0ENA (1xA0) register should be set to
“0”. This RAM clear function takes about 100usec and the RAMCLR register will be cleared by
itself after finished.
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TW2834 Video Controller
Preliminary
Character Attribute
Each character has its own attributes in display RAM that includes mix, blink, class 3 color of
character, type and font index. The mix attribute makes character mixed with video data and
blink attribute makes character blinked with the period defined in the BLK_TIME (1xA0) register.
The class 3 color of character takes one of 4 colors defined in the CLASS3COL (1xA7 ~ 1xAA)
register. The type attribute defines one of 2 types, character or bitmap type for each character
and the font index attribute defines address of font. The mix and blink attributes can be enabled
for each class via the CHAR_MIX (1xA5), CHAR_BLK (1xA6) register for each character or
bitmap. The alpha blending for OSD is also supported with 25%, 50%, and 75% level via the
ALPHA_OSD (1xBA) register.
The TW2834 provides 16 different colors that consist of fixed 12 colors (8 colors from color bar
of 75% amplitude 100% saturation, 100% white, 50% gray, 25% gray and 75% blue) and user’s
defined 4 colors using the CLUT (1xAE ~ 1xB9) register. The class 0, 1 and 2 color of character
will be one of 16 colors via the CLASS0COL, CLASS1COL and CLASS2COL (1xAB ~ 1xAD)
registers and are applied to all of characters to be displayed. For class 3 color, 4 colors are
predefined via the CLASS3COL (1xA7 ~ 1xAA) register and each character can take one of
these 4 colors using character’s attribute as described previously. The different color selection
for each character and bitmap can be supported also.
A character type has a blank for class 0 color in default mode, but a bitmap color has a
selectable color for it. However, if the CLASS0ENA (1xA0) is set to “1”, a character type can
have a selectable color like bitmap type. Likewise, if the B_CLASS0DIS (1xA0) is set to “1”, a bit
map type can be changed to character type. However for the display RAM clear function, the
CLASS0ENA should be set into “0” because the font data of index 0 should have class 0 with
blank character.
The space between characters can be varied horizontally and vertically. The CHAR_HSPC
(1xA1, 1xA3) register defines horizontal character space that can be increased by 2 pixel and
the CHAR_VSPC (1xA1, 1xA3) register defines vertical character space that can be increased
by 1 line unit. Likewise, The TW2834 can define the horizontal and vertical delay for first starting
character. The CHAR_HDEL (1xA2, 1xA4) register defines the horizontal delay from left
boundary and the CHAR_VDEL (1xA2, 1xA4) register defines the vertical delay from top
boundary. Each unit is same as CHAR_HSPC and CHAR_VSPC unit.
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TW2834 Video Controller
Preliminary
Box Overlay
The TW2834 supports two kinds of box overlay such as 16 single boxes and 4 2-dimensional
arrayed boxes. The 2-dimensional arrayed box has two modes as table mode and motion
display mode.
Single Box
The TW2834 provides 16 single boxes that can be a flat type or 3D type using the BOX_TYPE
(2x03) register. The flat type is just simple rectangular box and 3D type looks like 3 dimension
view. Each single box has programmable location and size parameters with the BOX_HL (2x11
+ 5N, N = 0 ~ 15), BOX_HW (2x12 + 5N, N = 0 ~ 15), BOX_VT (2x13 + 5N, N = 0 ~ 15) and
BOX_VW (2x14 + 5N, N = 0 ~ 15) registers. The BOX_HL is the horizontal location of box with
2 pixel unit and the BOX_HW is the horizontal size of box with 4 pixel unit. The BOX_VT is the
vertical location of box with 1 line unit and the BOX_VW is the vertical size of box with 2 line unit.
There are some definitions about single box as shown in the Fig 59.
BOX_HL
BOX_HW
Outer Boundary
Inner Boundary
0
BOX_VT
Plane Area
Flat Type
BOX_VW
(BOX_TYPE = 0)
3D Type
(BOX_TYPE = 1)
BOX_IBND = 1
BOX_OBND = 1
BOX_IBND = 0
BOX_OBND = 1
Fig 59 The structure of Single box
The BOX_PLNEN (2x10 + 5N, N = 0 ~ 15) register enables each plane color and its color is
defined by the BOX_PLNCOL (2x05 ~ 2x0C) register as described in character color section.
Actually the TW2834 provides total 16 different colors that consist of fixed 12 colors (8 colors
from color bar and 100%, 50%, 25% gray and 75% blue) and user’s defined 4 colors using
CLUT (1xAE ~ 1xB9) register. This color table is used in common with plane color for single box
and character color. For the box plane, luminance level can be controlled through the
BOX_IBND (2x10 + 5N, N = 0 ~ 15) register when the BOX_EMP (2x03) register = ‘1”. The
BOX_IBND = “1” makes luminance level of plane down by 20IRE and “0” makes up by 20IRE.
The each box plane can be mixed with video data via the BOX_PLNMIX (2x10 + 5N, N = 0~15)
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TW2834 Video Controller
Preliminary
register. The alpha blending level is controlled as 25%, 50%, and 75% via the ALPHA_BOX
(2x03) register. The BOX_EN (2x10 + 5N, N = 0~15) register determines the boxes to be
displayed for each path.
The color of box boundary is defined by the BOX_TYPE (2x03), BOX_OBND (2x10 + 5N, N =
0~15), BOX_IBND (2x10 + 5N, N = 0~15) and BOX_BNDCOL (2x04) registers as described in
the Table 6.
Table 6 The Color of Single Box Boundary
Control Register
Boundary
Color Description
BOX_TYPE BOX_OBND BOX_IBND
0
X
1
X
X
0
X
1
0
X
1
0
1
1
0
X
1
0
Outer
0
(Flat Type)
Inner
Left &
Top
Outer
Right &
Bottom
1
(3D Type)
Left &
Top
Inner
Right &
Bottom
1
1
0
X
1
0
1
1
0
X
1
0
1
1
Register
BOX_
BNDCOL
[7:4]
BOX_
BNDCOL
[3:0]
BOX_
BNDCOL
[7:6]
BOX_
BNDCOL
[5:4]
BOX_
BNDCOL
[3:2]
BOX_
BNDCOL
[1:0]
Color
Outer Boundary off
0~10 : 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 IRE Gray
11~14 : User defined Color (1xAE ~ 1xB9).
15 : Same as plane color with 20IRE down of luminance
Inner Boundary off
0~10 : 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 IRE Gray
11~14 : User defined Color (1xAE ~ 1xB9).
15 : Same as plane color with 20IRE up of luminance
Boundary off
0~3 : 90, 80, 70, 60 IRE Gray
0~3 : 0, 10, 20, 30 IRE Gray
Boundary off
0~3 : 0, 10, 20, 30 IRE Gray
0~3 : 90, 80, 70, 60 IRE Gray
Boundary off
Same as inner area
0~3 : 30, 40, 50, 60 IRE Gray
Boundary off
0~3 : 30, 40, 50, 60 IRE Gray
0~3 : 70, 60, 50, 40 IRE Gray
In case that several boxes have same region, there will be a conflict of what to display for that
region. Generally the TW2834 defines that the box 0 has priority over box 15. So if a conflict
happens between more than 2 boxes, the box 0 will be displayed first as top layer and box 1 to
box 15 are hidden beneath that are not supported for pop-up attribute unlike channel display.
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TW2834 Video Controller
Preliminary
2Dimensional Arrayed Box
The TW2834 supports 4 2D arrayed boxes that have programmable cell size up to 16x16. The
2D arrayed box is useful to make a table menu or display motion detection result for analog
input. The 2D arrayed box mode is selected via the 2DBOX_MODE (2x60, 2x68, 2x70, 2x78)
register. Each 2D arrayed box can be displayed on each path by the 2DBOX_EN (2x60, 2x68,
2x70, 2x78) register.
The 2DBOX_HNUM and 2DBOX_VNUM (2x66, 2x6E, 2x76, 2x7E) registers define the number
of row and column cells. For each 2D arrayed box, the horizontal location of left top for 2D box
is defined by the 2DBOX_HL (2x62, 2x6A, 2x72, 2x7A) register with 2 pixel step and the vertical
location of left-top is defined by the 2DBOX_VT (2x64, 2x6C, 2x74, 2x7C) register with 1 line
step. The vertical size of each cell is defined by the 2DBOX_VW (2x65, 2x6D, 2x75, 2x7D)
registers with 1 line step and the horizontal size is defined by the 2DBOX_HW (2x63, 2x6B,
2DBOX_HW
2DBOX_HL
2x73, 2x7B) registers with 2 pixel step. So the whole size of 2D arrayed box is same as the sum
of cells in row and column. The following Fig 60 shows the 2D arrayed box of table mode.
Mask Plane
Detection Plane
Boundary
Cursor Cell
2DBOX_CUR_HP = 5
2DBOX_CUR_VP = 1
2DBOX_VT
2DBOX_VNUM = 4
2DBOX_VW
2DBOX_HNUM = 7
Fig 60 2D arrayed box in table mode
The boundary of 2D arrayed box can be enabled by the 2DBOX_BNDEN (2x60, 2x68, 2x70,
2x78) register and its color is controlled via the 2DBOX_BNDCOL (2x61, 2x69, 2x71, 2x79)
register which selects one of 4 colors such as 0% black, 25% gray, 50% gray and 75% white.
The plane of 2D arrayed box is separated into mask plane and detection plane. The mask plane
represents the cell defined by MD_MASK (2x86 ~ 2x9D, 2xA6 ~ 2xBD, 2xC6 ~ 2xDD, 2xE6 ~
2xFD) register. The detection plane represents the cell excluding the mask cells among whole
cells.
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The mask plane of 2D arrayed box is enabled by the 2DBOX_MSKEN (2x60, 2x68, 2x70, 2x78)
register and the detection plane is enabled by the 2DBOX_DETEN (2x60, 2x68, 2x70, 2x78)
register. The color of mask plane can be controlled by the 2DBOX_PLNCOL (2x61, 2x69, 2x71,
2x79) register, which selects one of 16 colors as described in character color and plane color of
single box. For DETCOL_EN (2x9E) = “0”, the color of detection plane is same as the mask
plane color, but for DETCOL_EN = “1”, its color is controlled by the DETCOL_SEL (2x9E)
register. The plane can be mixed with video data by the 2DBOX_MIX (2x60, 2x68, 2x70, 2x78)
register. The alpha blending level is controlled as 25%, 50%, and 75% via the ALPHA_2DBOX
(2x03) register.
Specially, the TW2834 provides the function to indicate cursor cell inside 2D arrayed box. The
cursor cell is enabled by the 2DBOX_CUREN (2x60, 2x68, 2x70, 2x78) register and the
displayed location is defined by the 2DBOX_CURHP and 2DBOX_CURVP (2x67, 2x6F, 2x77,
2x7F) registers. Its color is a reverse color of cell boundary. It is useful function to control motion
mask region.
The 2D arrayed box can be also used to display motion information. When the 2D arrayed box
is working in motion display mode, the mask plane of 2D arrayed box shows the mask
information according to the MD_MASK registers automatically. For the motion display mode,
an additional narrow boundary of each cell is provided to display motion detection via the
2DBOX_DETEN register and its color is a reverse cell boundary color. Even in the horizontal /
vertical mirroring mode, the video data and motion detection result can be matched via the
2DBOX_HINV and 2DBOX_VINV (2x81, 2xA1, 2xC1, 2xE1) registers.
The TW2834 has 4 2D arrayed boxes so that 4 video channels can have its own 2D arrayed
box for motion display mode. To overlay mask information and motion result on video data
properly, the scaling ratio of video should be matched with 2D arrayed box size.
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TW2834 Video Controller
Preliminary
The following Fig 61 shows 2D arrayed box of motion display mode.
Boundary
Detection Plane
Mask Plane
2DBOX_VNUM = 11
No Motion
Cell
Motion
detected
Cell
2DBOX_HNUM = 15
Fig 61 2D arrayed box in motion display mode
In case those several 2D arrayed boxes have same region, there will be a conflict of what to
display for that region. Generally the TW2834 defines that 2D arrayed box 0 has priority over
other 2D arrayed box. So if a conflict happens between more than 2 2D arrayed boxes, 2D
arrayed box 0 will be displayed first as top layer and 2D arrayed box 1, box 2, and box 3 are
hidden beneath that are not supported for pop-up attribute like channel attribute.
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Preliminary
Mouse Pointer
The TW2834 supports the mouse pointer that has attributes such as pointer enable, pointer
location, blink and sub-layer enable. The mouse pointer can be overlaid on both display and
record path independently.
The mouse pointer is located in the full screen according to the CUR_HP (2x01) register with 2
pixel step and CUR_VP (2x02) register with 1 line step. Two kinds of mouse pointer are
provided through the CUR_TYPE (2x00) register. The CUR_SUB (2x00) register determines a
pointer inside area to be filled with 100% white or to be transparent and CUR_BLINK (2x00)
register controls a blink function of mouse. Actually the CUR_ON (2x00) register enables or
disables mouse pointer for display and record path independently. The following Fig 62
describes the parameters of mouse pointer.
CUR_HP
360
0
CUR_VP
NTSC : 240
PAL : 288
Fig 62 The parameters of mouse pointer
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TW2834 Video Controller
Preliminary
Video Output
The TW2834 supports dual digital video outputs with ITU-R BT.656 format and 2 analog video
outputs with built-in video encoder at the same time. Dual video controllers described above
generate 4 kinds of video data, the display path video data with or without OSD and the record
path video data with or without the OSD. The CCIR_IN (1x80) register selects one of 4 video
data for the digital video output and ENC_IN (1x80) register selects one of 4 video data for the
analog video output as shown in Fig 63.
The TW2834 supports all NTSC and PAL standards for analog output, which can be composite,
or S-video video for both display and record path. All outputs can be operated as master mode
to generate timing signal internally or slave mode to be synchronized with external timing.
SYS5060/ENC_MODE
ENC_VSDEL/ENC_VSOFF/ENC_HSDEL/ACTIVE_HDEL/ACTIVE_VDEL
HSENC
VSENC
FLDENC
Timing Interface and Control
VVID_X
VOSD_X
VVID_Y
VOSD_Y
CCIR_OUT_X
CCIR_IN_X
2X1
MUX
656 Encoder
(X Path)
4X1
MUX
VDOUTX
CCIR_OUT_Y
CCIR_IN_Y
656 Encoder
(Y Path)
4X1
MUX
2X1
MUX
VDOUTY
DAC_OUT_YX
DAC_PD_YX
0
ENC_IN_X
Y
4X1
MUX
Y/C
Separation
Cb/Cr
+
X
Luma
8X1
MUX
CVBS
DAC_OUT_CX
Chroma
8X1
MUX
DAC_OUT_YY
FSC
Generation
0
Chroma
8X1
MUX
CVBS
DAC_OUT_CY
Luma
8X1
MUX
ENC_IN_Y
Cb/Cr
4X1
MUX
Y/C
Separation
X
+
Y
DAC
VOUTYX
DAC_PD_CX
DAC
VOUTCX
DAC_PD_YY
DAC
VOUTYY
DAC_PD_CY
DAC
VOUTCY
Fig 63 Video output selection
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Analog Video Output
The TW2834 supports analog video output using built-in video encoder, which generates
composite or S-video with 10 bit dual DAC for both display and record path. The incoming digital
video are adjusted for gain and offset according to NTSC or PAL standard. Both the luminance
and chrominance are band-limited and interpolated to 27MHz sampling rate for digital to analog
conversion. The NTSC output can be selected to include a 7.5 IRE pedestal. The TW2834 also
provides internal test color bar generation.
Output Standard Selection
The TW2834 supports various video standard outputs via the SYS5060 (1x00) and ENC_FSC,
ENC_PHALT, ENC_PED (1x89) registers as described in the following Table 7.
Table 7 Analog output video standards
Format
NTSC-M
Specification
Register
Line/Fv (Hz)
Fh (KHz)
Fsc (MHz)
SYS5060
ENC_ FSC
ENC_PHALT
525/59.94
15.734
3.579545
0
0
0
NTSC-J
ENC_PED
1
0
NTSC-4.43
525/59.94
15.734
4.43361875
0
1
0
1
NTSC-N
625/50
15.625
3.579545
1
0
0
0
625/50
15.625
4.43361875
1
1
1
PAL-BDGHI
0
1
PAL-N
PAL-M
525/59.94
15.734
3.57561149
0
2
1
0
PAL-NC
625/50
15.625
3.58205625
1
3
1
0
PAL-60
525/59.94
15.734
4.43361875
0
1
1
0
If the ENC_ALTRST (1x89) register is set to “1”, phase alternation can be reset every 8 field so
that phase alternation keeps same phase every 8 field.
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TW2834 Video Controller
Preliminary
Luminance Filter
The band of luminance signal can be selected as shown in the following Fig 64.
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
-45
0
2
4
6
8
Frequency (Hertz)
10
12
6
x 10
Fig 64 Characteristics of luminance filter
Chrominance Filter
The band of chrominance signal can be selected as shown in the following Fig 65.
0
Magnitude Response (dB)
-5
-10
-15
-20
-25
0
0.5
1
1.5
Frequency (Hertz)
2
2.5
3
6
x 10
Fig 65 Characteristics of chrominance Filter
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TW2834 Video Controller
Preliminary
Digital-to-Analog Converter
Digital video data from video encoder is converted to analog video signal by DAC (Digital to
Analog Converter). The analog video signal format can be selected for each DAC independently
via the DAC_OUT (1x81, 1x82) register. For DAC_OUT = “0”, no output is selected and for
DAC_OUT = “1”, CVBS output is selected. If the DAC_OUT is “2”, luminance output is chosen
and if the DAC_OUT is “3”, chrominance output is chosen. Each DAC can be disabled
independently to save power by the DAC_PD (1x81, 1x82) register.
A simple reconstruction filter is required externally to reject noise as shown in the Fig 66.
C
18pF
L
VDOUT
RCA JACK
1.8uH
R
C
C
75
330pF
330pF
Fig 66 Example of reconstruction filter
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TW2834 Video Controller
Preliminary
Digital Video Output
The digital output data of ITU-R BT.656 format is synchronized with CLK27ENC pin, which is
27MHz for single output or 54MHz for dual output. Each digital data of display and record path
can be output through VDOUTX and VDOUTY pin respectively on single output mode. For the
dual output mode, both display and record path output can come out through only one VDOUTX
or VDOUTY. The level of active video of ITU-R BT.656 can be limited to 1 ~ 254 level by the
CCIR_LMT (1x84) register. For digital channel ID mode, the CCIR_LMT should be set to low.
Table 8 ITU-R BT.656 SAV and EAV code sequence
50Hz (625Lines)
60Hz (525Lines)
Line
Note
Condition
From
To
Field
Vertical
523
*1
(1 )
3
EVEN
Blank
4
19
ODD
Blank
20
259
(263*1)
ODD
Active
FVH
Horizontal
EAV
F
V
1
1
SAV
260
*1
(264 )
265
ODD
Blank
266
282
EVEN
Blank
283
522
*1
(525 )
EVEN
Active
1
22
ODD
Blank
23
310
ODD
Active
311
312
ODD
Blank
313
335
EVEN
Blank
336
623
EVEN
Active
624
625
EVEN
Blank
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
1
0
1
1
SAV/EAV Code Sequence
H
First
Second
Third
Fourth
1
0xF1
0
0xEC
1
0xB6
0
0xAB
1
0x9D
0
0xFF
0x00
0x00
0x80
1
0xB6
0
0xAB
1
0xF1
0
0xEC
1
0xDA
0
0xC7
1
0xB6
0
0xAB
1
0x9D
0
0x80
1
0xB6
0
1
0xFF
0x00
0x00
0xAB
0xF1
0
0xEC
1
0xDA
0
0xC7
1
0xF1
0
0xEC
1. The number of ( ) is ITU-R BT. 656 standard. The TW2834 also supports this
standard by CCIR_STD register (1x88 Bit[6]).
The TW2834 also supports ITU-R BT.601 interface through the VDOUTX pin for Y data and
VDOUTY pin for C data.
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TW2834 Video Controller
Preliminary
Single Output Mode
For the single output mode, each digital output data in display and record path can be output at
27MHz ITU-R BT 656 interface through VDOUTX and VDOUTY pin that are synchronized with
CLK27ENCX and CLK27ENCY. The output data is selected by the CCIR_OUT (1x83) register
which selects the display path data for “0” and record path data for “1”. The timing diagram of
single output mode for ITU-R BT.656 interface is shown in the following Fig 67.
CLK27ENC
VDOUT[7:0]
FFh 00h 00h
XY
80h 10h
80h 10h FFh 00h 00h
EAV code
XY
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
SAV code
Fig 67 Timing diagram of single output mode for 656 Interface
The TW2834 also supports 13.5MHz ITU-R BT 601 interface through VDOUTX and VDOUTY
pin via the CCIR_601 (1x83) register. The output data is selected via the CCIR_OUT register
which selects the display path data for “0” and record path data for “1”. The timing diagram of
single output mode for ITU-R BT 601 interface is shown in the following Fig 68.
CLK27ENC
(13.5MHz)
VDOUTY[7:0]
FFh
00h
80h
80h
FFh
00h
Cb0
Cr0
Cb2
Cr2
VDOUTX[7:0]
00h
XY
10h
10h
00h
XY
Y0
Y1
Y2
Y3
EAV code
SAV code
Fig 68 Timing diagram of single output mode for 601 Interface
The output is synchronized with CLK27ENCX and CLK27ENCY pins whose phase and
frequency can be controlled by the ECLK_FR_X, ECLK_FR_Y, ECLK_PH_X and ECLK_PH_Y
(1x8D) registers.
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TW2834 Video Controller
Preliminary
Dual Output Mode
The TW2834 also supports dual output mode that is time-multiplexed with display and record
path data at 54MHz clock rate. The sequence is related with the CCIR_OUT (1x83) register that
the display path data precedes the record path for CCIR_OUT = “2” and the record path data
precedes the display path for CCIR_OUT = “3”.
The timing diagram of dual output mode for ITU-R BT 656 interface is illustrated in the Fig 69.
The dual output mode is useful to reduce number of pins for interface with other devices.
CLK27ENC_X
(54MHz)
CLK27ENC_Y
(27MHz)
VDOUT[7:0]
FFhFFh 00h 00h 00h 00h XY XY 80h 80h
10h 10h FFh FFh 00h 00h 00h 00h XY XY Cb0Cb0 Y0 Y0 Cr0 Cr0 Y1 Y1 Cb2Cb2 Y2 Y2
EAV code
Data output for display path
SAV code
Data output for capture path
Fig 69 Timing diagram of dual output mode for 656 Interface
The TW2834 also supports dual output mode with 13.5MHz ITU-R BT 601 interface that is
timing multiplexed to 27MHz through VDOUTX and VDOUTY pin via the CCIR_601 (1x83)
register. The sequence is determined by the CCIR_OUT register like 54MHz ITU-R BT.656
interface. The timing diagram of single output mode for ITU-R BT 601 interface is shown in the
following Fig 70.
CLK27ENC_X
(27MHz)
CLK27ENC_Y
(13.5MHz)
VDOUTX[7:0]
FFh FFh 00h 00h 80h 80h
80h 80h FFh FFh 00h 00h Cb0 Cb0 Cr0 Cr0 Cb2 Cb2 Cr2 Cr2
VDOUTY[7:0]
00h 00h XYh XYh 10h 10h
10h 10h 00h 00h XYh XYh Y0
EAV code
Data output for display path
Y0
Y1
Y1
Y2
Y2
Y3
Y3
SAV code
Data output for capture path
Fig 70 Timing diagram of dual output mode for 601 Interface
The output is synchronized with CLK27ENCX and CLK27ENCY pins whose polarity and
frequency can be controlled by the ECLK_FR_X, ECLK_FR_Y, ECLK_PH_X and ECLK_PH_Y
registers.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Timing Interface and Control
The TW2834 can be operated in master or slave mode via the ENC_MODE (1x84) register. In
master mode, the TW2834 can generate all of timing signals internally while the TW2834
receives all of timing signals from external device in slaver mode. The polarity of horizontal,
vertical sync and field flag can be controlled by the ENC_HSPOL, ENC_VSPOL and
ENC_FLDPOL (1x84) registers respectively for both master and slave mode. In slave mode, the
TW2834 can detect field polarity from vertical sync and horizontal sync via the ENC_FLD (1x84)
register or can detect vertical sync from the field flag via the ENC_VS (1x84) register.
The TW2834 provides or receives the timing signal through the HSENC, VSENC and FLDENC
pins. To adjust the timing of those pins, the TW2834 has the ENC_HSDEL (1x86), ENC_VSDEL
and ENC_VSOFF (1x85) registers which control only the related signal timing regardless of
analog and digital video output. Likewise, by controlling the ACTIVE_VDEL (1x87) and
ACTIVE_HDEL (1x88) registers, only active video period can be shifted on horizontal and
vertical direction independently. The shift of active video period produces the cropped video
image because the timing signal is not changed even though active period is moved. So this
feature is restricted to adjust video location in monitor for example. The active video data period
of analog video output is same as digital video output so that the video timing of both outputs
can be controlled in common. The detailed timing diagram is illustrated in the following Fig 71.
A C T IV E _ V D E L
Even End
L in e N u m b e r
524
O d d S ta rt
V B I F u ll I n t e rv a l
525
1
2
3
4
5
6
7
8
9
10
11
1 2 -1 7
18
19
20
A n a lo g O u tp u t
V (6 5 6 )
F (6 5 6 )
H (6 5 6 )
E N C _ V S D E L + E N C _ V S O F F (O d d )
VSENC
FLDENC
HSENC
A C T IV E _ H D E L
A n a lo g O u tp u t
A c tiv e D a t a / L i n e
L in e S ta rt
H (6 5 6 )
EN C _H SD EL
HSENC
A C T IV E _ V D E L
O dd End
E v e n S ta rt
V B I F u ll I n t e rv a l
L in e N u m b e r
262
263
264
265
266
267
268
269
270
271
272
273
274281
282
283
284
285
286
A n a lo g O u tp u t
V (6 5 6 )
F (6 5 6 )
H (6 5 6 )
E N C _ V S D E L + E N C _ V S O F F (E v e n )
VSENC
FLD EN C
HSENC
Fig 71 Horizontal and vertical timing control
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Host Interface
The TW2834 provides serial and parallel interfaces that can be selected by HSPB pin. When
HSPB is low, the parallel interface is selected, the serial interface for high. Some of the interface
pins serve a dual purpose depending on the working mode. The pins HALE and HDAT [7] in
parallel mode become SCLK and SDAT pins in serial mode and the pins HDAT [6:1] and
HCSB0 in parallel mode become slave address in serial mode respectively. Each interface
protocol is shown in the following figures.
.
Table 9 Pin assignments for serial and parallel interface
Pin Name
Serial Mode
Parallel Mode
HSPB
HIGH
LOW
HALE
SCLK
AEN
HRDB
Not Used (VSSO)
RENB
HWRB
Not Used (VSSO)
WENB
HCSB0
Slave Address[0]
CSB0
HCSB1
Not Used (VSSO)
CSB1
HDAT[0]
Not Used (VSSO)
PDATA[0]
HDAT[1]
Slave Address[1]
PDATA[1]
HDAT[2]
Slave Address[2]
PDATA[2]
HDAT[3]
Slave Address[3]
PDATA[3]
HDAT[4]
Slave Address[4]
PDATA[4]
HDAT[5]
Slave Address[5]
PDATA[5]
HDAT[6]
Slave Address[6]
PDATA[6]
HDAT[7]
SDAT
PDATA[7]
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TW2834 Video Controller
Preliminary
Serial Interface
HDAT [6:1] and HCSB0 pins define slave address in serial mode. Therefore, any slave address
can be assigned for full flexibility. The Fig 72 shows an illustration of serial interface for the case
of slave address (Read : “0x85”, Write : 0x84”).
3.3V/5V
3.3V/5V
3.3V/5V
R200
R201
R202
10K
4.7K
4.7K
U1
HSPB
HALE
HDAT[7]
TW2834
HDAT[6]
HDAT[5]
HDAT[4]
HDAT[3]
HDAT[2]
HDAT[1]
HCSB0
HDAT[0]
HCSB1
HRDB
HWRB
119
123
127
128
130
131
133
134
135
120
SCLK
SDAT
Slave Address
Read : "10000101"
Write : "10000100"
137
122
124
126
R1
10K
Fig 72 The serial interface for the case of slave address. (Read : “0x85”, Write : “0x84”)
The TW2834 has total 3 pages for registers (1 page can contain 256 registers) so that the page
index [1:0] is used for selecting page of registers. Page 0 is assigned for video decoder, Page 1
is for video controller / OSD / encoder and Page 2 is for motion detector / Box / Mouse pointer.
The detailed timing diagram is illustrated in the Fig 73 and Fig 74.
The TW2834 also supports automatic index increment so that it can read or write continuous
multi-bytes without restart. Therefore, the host can read or write multiple bytes in sequential
order without writing additional slave address, page index and index address. The data transfer
rate on the bus is up to 400K bits/s.
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TW2834 Video Controller
Start
Slave address
R/WB Ack
Preliminary
Page index
Index address
Ack
Data
Ack
Ack
Stop
“0”
SDAT
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
SCLK
Fig 73 Write timing of serial interface
Restart without stop is allowed
Start
Slave address
R/WB Ack
Page Index
Ack
Index address
Ack
Stop Start
Slave address
R/WB Ack
“0”
SDAT
MSB
LSB
Data
Ack
Data
NoAck
Stop
“1”
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
SCLK
Index Write Procedure for Read
Data Read Procedure
Fig 74 Read timing of serial interface
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Parallel Interface
In parallel interface, page of registers can be selected by CSB0 and CSB1 pins, which are
working as page index [1:0] in serial interface. Page number 0 is selected by CSB1 = “0” and
CSB0 = “0”, page number 1 is by CSB1 = “0” and CSB0 = “1”, and page number 2 is by CSB1 =
“1” and CSB0 = “0”. The TW2834 also supports automatic index increment for parallel interface.
The writing and reading timing is shown in the Fig 75 and Fig 76 respectively. The detail timing
parameters are in Table 10.
CSB0/1
Tsu(1)
Tw
Tw
Th(1)
Tcs
WENB
RENB
Tw
AEN
Index Address
PDATA
Tsu(2)
Write
Th(2)
Tsu(2)
Write
Th(2)
Tsu(2)
Th(2)
Fig 75 Write timing of parallel interface with auto index increment mode
CSB0/1
Tsu(1)
Tcs
WENB
Tw
Tw
RENB
Tw
Trd
Th(1)
Trd
AEN
Index Address
PDATA
Tsu(2)
Th(2)
Read
Td(1)
Td(2)
Read
Td(1)
Td(2)
Fig 76 Read timing of parallel interface with auto index increment mode
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TW2834 Video Controller
Preliminary
Table 10 Timing parameters of parallel interface
Parameter
Symbol
Min
CSB setup until AEN active
Tsu(1)
10
ns
PDATA setup until AEN,WENB active
Tsu(2)
10
ns
AEN, WENB, RENB active pulse width
Tw
40
ns
CSB hold after WENB, RENB inactive
Th(1)
60
ns
PDATA hold after AEN,WENB inactive
Th(2)
20
ns
PDATA delay after RENB active
Td(1)
PDATA delay after RENB inactive
Td(2)
60
ns
Tcs
60
ns
Trd
60
ns
CSB inactive pulse width
RENB active delay after AEN inactive
RENB active delay after RENB inactive
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Max
12
Units
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Interrupt Interface
The TW2834 provides the interrupt request function via an NMIRQ pin. Any video loss, motion
or blind detection will make the NMIRQ pin low until cleared via the register. Writing high to the
corresponding bit of the interrupt clear register IRQCLR_NOVID, IRQCLR_MDBD (1x7A) will
clear the interrupt request. The host can distinguish what event makes interrupt request to IRQ
pin by reading the status of IRQCLR_NOVID, IRQCLR_MDBD (1x7A) registers before clearing.
Then, the host has to read another status of DET_NOVID, DET_MOTION, DET_BLIND (1x7B,
1x7C) registers to find out whether the event is generated by video loss or video detection, or
whether it is made by motion or blind detection. To disable each interrupt, the interrupt status
also has its own mask register such as IRQENA_NOVID, IRQENA_MOTION (1x79), and
IRQENA_BLIND (1x7C) register. An illustration of the interrupt sequence is shown in the
following Fig 77.
VIN 4 blind detect
VIN 3 motion disappear
VIN 1 video loss detect
DET_NOVID, DET_MOTION
(1x7B)
00h
VIN 3 motion detect
10h
14h
DET_BLIND
(1x7C)
Status of IRQCLR
(1x7A)
VIN 1 video detect
10h
00h
F8h
F0h
00h
10h
00h
04h
00h
00h
10h
08h
00h
NMIRQ Pin output
Clear by host for IRQCLR
(1x7A)
10h
Clear by Host
04h
Clear by Host
10h
Clear by Host
08h
Clear by Host
Fig 77 Timing Diagram of Interrupt Interface
The TW2834 also provides the status of video loss, motion detection or the strobe acknowledge
for individual channel through the MPPDEC pins with the control of the MPPSET (1x50)
register.
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Preliminary
TW2834 Video Controller
Control Register
Register Map
For Video Decoder
VIN0
Address
VIN1
VIN2
VIN3
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
Techwell, Inc.
www.techwellinc.com
BIT7
BIT6
DET_FORMAT *
BIT5
BIT4
DET_COLOR *
BIT3
BIT2
LOCK_COLOR *
LOCK_GAIN *
IFMTMAN
IFORMAT
0
1
AGC
PEDEST
1
0
GNTIME
HDELAY_X [7:0]
HACTIVE_X [7:0]
HDELAY_Y [7:0]
HACTIVE_Y [7:0]
HACTIVE_Y [9:8]
HDELAY_Y [9:8]
HACTIVE_X [9:8]
0
0
HSWIDTH
VDELAY_X [7:0]
VACTIVE_X [7:0]
VDELAY_Y [7:0]
VACTIVE_Y [7:0]
HPLLMAN
HPLLTIME
VACTVE_Y [8]
VDELAY_Y [8]
FLDMODE
VSMODE
FLDPOL
HSPOL
VSPOL
HUE
SAT
CONT
BRT
IFCOMP
CLPF
ACCTIME
YPEAK_Y
YPEAK_X
YPEAK_FLT_Y
YPEAK_FLT_X
VSFLT_Y
VSFLT_X
HSFLT_Y
YBWI_X
COMBMD_X
0
0
0
YBWI_Y
COMBMD_Y
0
0
0
VSCALE_X [15:8]
VSCALE_X [7:0]
VSCALE_Y [15:8]
VSCALE_Y [7:0]
HSCALE_X [15:8]
HSCALE_X [7:0]
HSCALE_Y [15:8]
HSCALE_Y [7:0]
0
VFLT_MD_X
VBW_X
PAL_DLY_X
ODD_EN_X
0
VFLT_MD_Y
VBW_Y
PAL_DLY_Y
ODD_EN_Y
BLKEN
BLKCOL
0
LMTOUT
SW_RESET
ANA_SW
0
0
0
1
0
0
HDELAY_PB [7:0]
HACTIVE_PB [7:0]
105
BIT1
BIT0
LOCK_OFST *
LOCK_PLL *
DET_NONSTD *
DET_FLD60 *
OSTIME
HDELAY_X [9:8]
VACTVE_X [8]
1
VDELAY_X [8]
0
APCTIME
CKIL
HSFLT_X
0
0
0
0
EVEN_EN_X
EVEN_EN_Y
DEC_PATH_X
0
1
1
1
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Video Decoder
VIN0
Address
VIN1
VIN2
VIN3
0x26
0x27
0x28
0x66
0x67
0x68
0xE6
0xE7
0xE8
0xA6
0xA7
0xA8
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0xB8
0xB9
0xBA
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
Notes
1.
2.
3.
BIT7
BIT6
BIT5
PB_SCLFLT_EN
PB_SYNC_EN
VACTIVE_PB [8]
VSFLT_PB1
VSFLT_PB3
MAN_PB_CROP
PB_CROP_MD
PB_PATH_CH3
PB_FLDPOL
0
0
BIT4
BIT3
BIT2
VDELAY_PB [8]
HACTIVE_PB [9:8]
VDELAY_PB [7:0]
VACTIVE_PB [7:0]
HSFLT_PB1
VSFLT_PB0
HSFLT_PB3
VSFLT_PB2
PB_ACT_MD
PB_PATH_CH2
PB_PATH_CH1
BIT1
BIT0
HDELAY_PB [9:8]
HSFLT_PB0
HSFLT_PB2
PB_CH_EN
PB_PATH_CH0
PB_NOVID
0
0
PB_EC_656
0
0
0
0
PB_4CH_MD
0
0
U_GAIN
V_GAIN
U_OFF
V_OFF
0
0
0
0
1
0
1
ANA_CH_EN
1
0
0
0
0
0
0
0
FLDOS_3Y
FLDOS_2Y
FLDOS_1Y
FLDOS_0Y
0
0
0
0
0
0
0
0
0
0
0
0
FLD3*
FLD2*
FLD1*
FLD0*
ANA_CH3
ANA_CH2
HAV_VALID
0
AUTO_BGND
0
0
CDEL
0
0
1
1
0
0
0
1
AFIL_BYP
0
0
0
0
ADC_PWDN
0
0
0
0
FLDOS_3X
FLDOS_2X
1
1
0
PB_SDEL_EN
0
0
VAV3*
VAV2*
ANA_CH1
C_CORE
0
0
1
1
0
0
0
0
0
0
0
0
0
0
FLDOS_1X
FLDOS_0X
1
1
PB_SDEL
NOVID_MODE
VAV1*
VAV0*
ANA_CH0
Y_H_CORE
0
0
0
0
0
0
0
0
0
0
0x10*
“*” stand for read only register
VIN0 ~ VIN3 stand for video input 0 ~ video input 3.
: Modified in TW2834 RevC
Techwell, Inc.
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106
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Video Controller (Display path)
Address
CH0 CH1 CH2 CH3
1x10
1x11
1x12
1x13
1x14
1x15
1x16
1x30
1x31
1x32
1x33
1x40
1x41
1x42
1x43
1x00
1x01
1x02
1x03
1x04
1x05
1x06
1x07
1x08
1x09
1x0A
1x0B
1x0C
1x0D
1x0E
1x0F
1x18 1x20
1x19 1x21
1x1A 1x22
1x1B 1x23
1x1C 1x24
1x1D 1x25
1x1E 1x26
1x2F
1x34 1x38
1x35 1x39
1x36 1x3A
1x37 1x3B
1x44 1x48
1x45 1x49
1x46 1x4A
1x47 1x4B
Notes
1.
2.
3.
1x28
1x29
1x2A
1x2B
1x2C
1x2D
1x2E
1x3C
1x3D
1x3E
1x3F
1x4C
1x4D
1x4E
1x4F
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SYS_5060
OVERLAY
LINK_LAST_X
LINK_LAST_Y
LINK_EN_X
LINK_EN_Y
LINK_NUM
0
0
0
0
0
0
0
0
TBLINK
SAVE_ADDR
RECALL_FLD
SAVE_FLD
SAVE_HID
SAVE_REQ
0
STRB_FLD
DUAL_PAGE
STRB_REQ
NOVID_MODE
0
0
0
ADDR_OUT_EN
INVALID_MODE
MUX_MODE
0
MUX_FLD
0
0
0
0
STRB_AUTO
0
0
INTR_REQX
INTR_CH
MUX_OUT_CH0
MUX_OUT_CH1
MUX_OUT_CH2
MUX_OUT_CH3
CHID_MUX_OUT
ZM_EVEN_OS
ZM_ODD_OS
FR_EVEN_OS
FR_ODD_OS
ZMENA
0
ZMBNDCOL
ZMBNDEN
ZMAREAEN
ZMAREA
ZOOMH
ZOOMV
FRZ_FLD
BNDCOL
BGDCOL
BLKCOL
CH_EN
POP_UP
FUNC_MODE
DMCH_EN
DMCH_PATH
Reserved
RECALL_CH
FRZ_CH
H_MIRROR
V_MIRROR
ENHANCE
BLANK
BOUND
BLINK
0
RECALL_ADDR
RECALL_DM
FRZ_DM
H_MIRROR_DM
V_MIRROR_DM
ENHANCE_DM
BLANK_DM
BOUND_DM
BLINK_DM
0
RECALL_ADDR_DM
0
0
0
0
0
0
0
0
PB_AUTO_EN
0
PB_STOP
EVENT_PB
PB_CH_NUM
0
0
0
0
0
0
0
0
PICHL
PICHR
PICVT
PICVB
PICHL_DM
PICHR_DM
PICVT_DM
PICVB_DM
“*” stand for read only register
CH0 ~ CH3 stand for channel 0 ~ channel 3.
: Modified in TW2834 RevC
Techwell, Inc.
www.techwellinc.com
107
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Video Controller (Record path)
Address
CH0 CH1 CH2 CH3
1x60
1x61
1x62
1x50
1x51
1x52
1x53
1x54
1x55
1x56
1x57
1x58
1x59
1x5A
1x5B
1x5C
1x5D
1x5E
1x5F
1x63 1x66 1x69
1x64 1x67 1x6A
1x65 1x68 1x6B
1x6C
1x6D
1x6E
1x6F
1x70
1x71
1x72
1x73
1x74
1x75
1x76
1x77
1x78
1x79
1x7A
1x7B
1x7C
1x7D
1x7E
1x7F
Notes
1.
2.
3.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
MPPSET_X
MPPSET_Y
0
FRAME_OP
FRAME_FLD
DIS_MODE
0
0
SIZE_MODE
TBLINK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STRB_FLD
DUAL_PAGE
STRB_REQ
NOVID_MODE
0
CH_START
0
MEM_OP_EN
INVALID_MODE
MUX_MODE
TRIG_MODE
MUX_FLD
PIN_TRIG_MD
0
0
STRB_AUTO
QUE_SIZE
QUE_PERIOD[7:0]
QUE_PERIOD[9:8]
EXT_TRIG
INTR_REQY
MUX_WR_CH
QUE_WR
QUE_ADDR
0
Q_POS_RD_CTL
Q_DATA_RD_CTL
MUX_SKIP_EN
ACCU_TRIG
QUE_CNT_RST
QUE_POS_RST
MUX_SKIP_CH[15:8]
MUX_SKIP_CH[7:0]
CHID_MUX_OUT
FRZ_FLD
BNDCOL
BGDCOL
BLKCOL
CH_EN
POP_UP
FUNC_MODE
0
0
DEC_PATH_Y
0
FRZ_CH
H_MIRROR
V_MIRROR
ENHANCE
BLANK
BOUND
BLINK
0
0
0
0
0
0
0
0
PIC_SIZE3
PIC_SIZE2
PIC_SIZE1
PIC_SIZE0
PIC_POS3
PIC_POS2
PIC_POS1
PIC_POS0
MUX_OUT_CH0
MUX_OUT_CH1
MUX_OUT_CH2
MUX_OUT_CH3
POS_CTL_EN
POS_TRIG_MODE
POS_TRIG
POS_INTR
0
POS_RD_CTL
POS_DATA_RD_CTL
POS_PERIOD[9:8]
POS_FLD_MD
POS_SIZE
POS_QUE_PER[7:0]
POS_CH0
POS_CH1
POS_CH2
POS_CH3
POS_QUE_WR
POS_CNT_RST
POS_QUE_RST
POS_QUE_ADDR
FLD_OP
DVR_IN
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQPOL
IRQRPT
0
IRQENA_NVMD
IRQENA_MOTION
IRQ_CLEAR
IRQCLR_MDBD
DET_NOVID
DET_MOTION
IRQENA_BLIND
DET_BLIND
MCLK_FR_Y
MCLK_PH_Y
MCLK_FR_X
MCLK_PH_X
MCLK_CTL_Y
MCLK_CTL_X
MEM_INIT
0
0
0
0
0
0
1
“*” stand for read only register
CH0 ~ CH3 stand for channel 0 ~ channel 3.
: Modified in TW2834 RevC
Techwell, Inc.
www.techwellinc.com
108
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Video Output
Address
BIT7
1x80
1x81
1x82
1x83
1x84
1x85
1x86
1x87
1x88
1x89
1x8A
1x8B
1x8C
1x8D
1x8E
Notes
1.
2.
BIT6
ENC_IN_X
DAC_PD_YX
DAC_PD_YY
0
CCIR_601
ENC_MODE
CCIR_LMT
ENC_VSOFF
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
ENC_IN_Y
DAC_OUT_YX
DAC_OUT_YY
CCIR_OUT_X
ENC_VS
ENC_FLD
CCIR_IN_X
CCIR_IN_Y
DAC_PD_CX
DAC_OUT_CX
DAC_PD_CY
DAC_OUT_CY
BYPASS_Y
CCIR_OUT_Y
CCIR_FLDPOL
ENC_HSPOL
ENC_VSPOL
ENC_FLDPOL
ENC_VSDEL
ENC_HSDEL[7:0]
ENC_HSDEL[9:8]
0
ACTIVE_VDEL
0
CCIR_STD
ACTIVE_HDEL
ENC_FSC
0
0
1
ENC_PHALT
ENC_ALTRST
ENC_PED
ENC_CBW_X
ENC_YBW_X
ENC_CBW_Y
ENC_YBW_Y
0
0
ENC_BAR_X
ENC_CKILL_X
0
0
ENC_BAR_Y
ENC_CKILL_Y
ENC_HS_LINK
0
0
0
VDOUTY_MODE
HOUT
VOUT
FOUT
ECLK_FR_Y
ECLK_PH_Y
ECLK_FR_X
ECLK_PH_X
ECLK_CTL_Y
ECLK_CTL_X
“*” stand for read only register
: Modified in TW2834 RevC
For Character Overlay
Address
1x90
1x91
1x92
1x93
1x94
1x95
1x96
1x97
1x98
1x99
1x9A
1x9B
BIT7
BIT5
BIT4
FONT_WR_PAGE
FONT_REQ_Y
0
CHAR_WR_MODE
FONT_REQ_X
CHAR_PATH
0
0
0
0
CHAR_TYPE
Techwell, Inc.
www.techwellinc.com
BIT3
BIT2
BIT1
BIT0
FONT_WR_DATA[63:56]
FONT_WR_DATA[55:48]
FONT_WR_DATA[47:40]
FONT_WR_DATA[39:32]
FONT_WR_DATA[31:24]
FONT_WR_DATA[23:16]
FONT_WR_DATA[15:8]
FONT_WR_DATA[7:0]
FONT_WR_INDEX
0
1x9C
1x9D
BIT6
0
CHAR_RD_FLD
CHAR_VF_SIZE
0
0
0
109
FONT_WR_LINE
FONT_WR_TYPE
CHAR_VLOC
CHAR_RD_PAGE
CHAR_HF_SIZE
CHAR_HLOC
MIX
BLINK
CHAR_INDEX
0
FONT_WR_FLD
CLASS3_COL
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Character Overlay
Address
BIT7
1xA0
1xA1
1xA2
1xA3
1xA4
1xA5
1xA6
1xA7
1xA8
1xA9
1xAA
1xAB
1xAC
1xAD
1xAE
1xAF
1xB0
1xB1
1xB2
1xB3
1xB4
1xB5
1xB6
1xB7
1xB8
1xB9
1xBA
1xBB
1xBC
RAMCLR_X
Notes
0
0
0
1.
BIT6
BIT5
RAMCLR_Y
CHAR_VSPC_X
CHAR_VDEL_X
CHAR_VSPC_Y
CHAR_VDEL_Y
CHAR_MIX_C
CHAR_BLK_C
CLASS3COL1_C
CLASS3COL3_C
CLASS3COL1_B
CLASS3COL3_B
CLASS2COL_C
CLASS1COL_C
CLASS0COL_C
0
0
0
0
BYP_MPP
0
BIT4
BLK_TIME
BIT3
CLASS0ENA_X
0
0
0
CLUT0_Y
CLUT0_CB
CLUT0_CR
CLUT1_Y
CLUT1_CB
CLUT1_CR
CLUT2_Y
CLUT2_CB
CLUT2_CR
CLUT3_Y
CLUT3_CB
CLUT3_CR
T_CASCADE_EN
1
0
BIT2
BIT1
BIT0
CLASS0ENA_Y
B_CLASS0DIS_X
CHAR_HSPC_X
CHAR_HDEL_X
CHAR_HSPC_Y
CHAR_HDEL_Y
CHAR_MIX_B
CHAR_BLK_B
CLASS3COL0_C
CLASS3COL2_C
CLASS3COL0_B
CLASS3COL2_B
CLASS2COL_B
CLASS1COL_B
CLASS0COL_B
0
0
0
B_CLASS0DIS_Y
ALPHA_OSD
DEC_BYP_EN
0
0
: Modified in TW2834 RevC
Techwell, Inc.
www.techwellinc.com
110
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Channel ID CODEC
Address
BIT7
BIT6
BIT5
1xC0
1xC1
1xC2
1xC3
1xC4
1xC5
1xC6
1xC9
1xCA
1xCB
1xCC
1xCD
1xCE
1xCF
1xD0
1xD1
1xD2
1xD3
1xD4
1xD5
1xD6
1xD7
1xD8
1xD9
1xDA
1xDB
1xDC
1xDD
1xDE
1xDF
1xE0
1xE1
1xE2
1xE3
0
VIS_ENA
0
VIS_EC_EN
0
VIS_CODE_EN
0
0
VIS_LINE_WIDTH
0
Notes
1.
2.
AUTO_VBI_DET
VBI_EC_ON
VBI_FLD_OS
VBI_LINE_SIZE
VBI_CODE_EN
BIT4
BIT3
BIT2
0
0
VIS_RIC_EN
VIS_MIX_EN
VIS_H_OS
BIT1
BIT0
0
0
0
VBI_RD_CTL
VIS_SEL
VIS_PIXEL_WIDTH
VIS_LINE_OS
VIS_HIGH_VAL
VIS_LOW_VAL
VBI_RIC_ON
VBI_MIX_ON
VBI_PIXEL_H_OS
VAV_CHK
VBI_FLT_EN
VBI_PIXEL_HW
VBI_LINE_OS
MID_VAL
CHID_VALID *
CHID_TYPE *
VIS_MAN0 [15:8]
VIS_MAN0 [7:0]
VIS_MAN1 [15:8]
VIS_MAN1 [7:0]
VIS_MAN2 [15:8]
VIS_MAN2 [7:0]
VIS_MAN3 [15:8]
VIS_MAN3 [7:0]
VIS_MAN4 [15:8]
VIS_MAN4 [7:0]
VIS_MAN5 [15:8]
VIS_MAN5 [7:0]
VIS_MAN6 [15:8]
VIS_MAN6 [7:0]
VIS_MAN7 [15:8]
VIS_MAN7 [7:0]
AUTO_CHID0
AUTO_CHID1
AUTO_CHID2
AUTO_CHID3
“*” stand for read only register
: Modified in TW2834 RevC
Techwell, Inc.
www.techwellinc.com
111
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For Mouse Pointer
Address
BIT7
BIT6
BIT5
2x00
2x01
2x02
CUR_ON_X
CUR_ON_Y
CUR_TYPE
BIT4
BIT3
CUR_SUB
CUR_BLINK
CUR_HP [8:1]
CUR_VP [8:1]
BIT2
BIT1
BIT0
0
CUR_HP [0]
CUR_VP [0]
For Single Box
Address
BIT7
BIT6
BIT5
2x03
2x04
2x05
2x06
2x07
2x08
2x09
2x0A
2x0B
2x0C
BOX_TYPE
BOX_EMP
0
Address
B3
B4
B0
B1
B2
2x10
2x11
2x12
2x13
2x14
2x15
2x16
2x17
2x18
2x19
2x1A
2x1B
2x1C
2x1D
2x1E
2x1F
2x20
2x21
2x22
2x23
B8
B9
2x38
2x39
2x3A
2x3B
2x3C
2x3D
2x3E
2x3F
2x40
2x41
BOX_PLNCOL1
BOX_PLNCOL3
BOX_PLNCOL5
BOX_PLNCOL7
BOX_PLNCOL9
BOX_PLNCOLB
BOX_PLNCOLD
BOX_PLNCOLF
B5
B6
B7
2x24
2x25
2x26
2x27
2x28
2x29
2x2A
2x2B
2x2C
2x2D
2x2E
2x2F
2x30
2x31
2x32
2x33
2x34
2x35
2x36
2x37
B10
Address
B11
B12
B13
B14
B15
2x42
2x43
2x44
2x45
2x46
2x47
2x48
2x49
2x4A
2x4B
2x51
2x52
2x53
2x54
2x55
2x56
2x57
2x58
2x59
2x5A
2x5B
2x5C
2x5D
2x5E
2x5F
2x4C
2x4D
2x4E
2x4F
2x50
BIT7
BIT6
BIT5
BOX_EN_X
BOX_EN_Y
BOX_OBND
BIT7
BIT6
BIT5
BOX_EN_X
BOX_EN_Y
BOX_OBND
BIT4
BIT3
BIT2
BIT1
BIT0
0
ALPHA_2DBOX
ALPHA_BOX
BOX_BNDCOL
BOX_PLNCOL0
BOX_PLNCOL2
BOX_PLNCOL4
BOX_PLNCOL6
BOX_PLNCOL8
BOX_PLNCOLA
BOX_PLNCOLC
BOX_PLNCOLE
BIT4
BIT3
BIT2
BOX_IBND BOX_PLNMIX BOX_PLNEN
BOX_HL[8:1]
BOX_HW
BOX_VT[8:1]
BOX_VW
BIT4
BIT3
BIT2
BOX_IBND BOX_PLNMIX BOX_PLNEN
BOX_HL[8:1]
BOX_HW
BOX_VT[8:1]
BOX_VW
BIT1
BIT0
BOX_HL[0]
BOX_VT[0]
BIT1
BIT0
BOX_HL[0]
BOX_VT[0]
Notes 1. B0 ~ B15 stand for single box 0 to 15.
Techwell, Inc.
www.techwellinc.com
112
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For 2D Arrayed Box & Motion Detector
Address
2DB0 2DB1 2DB2 2DB3
2x60
2x61
2x62
2x63
2x64
2x65
2x66
2x67
2x68
2x69
2x6A
2x6B
2x6C
2x6D
2x6E
2x6F
2x70
2x71
2x72
2x73
2x74
2x75
2x76
2x77
2x78
2x79
2x7A
2x7B
2x7C
2x7D
2x7E
2x7F
BIT7
2DBOX_EN_X
BIT6
BIT5
2DBOX_EN_Y
2DBOX_MODE
2DBOX_PLNCOL
BIT4
2DBOX_DETEN
BIT3
BIT2
BIT1
2DBOX_MSKEN
2DBOX_MIX
2DBOX_CUREN
2DBOX_BNDCOL
2DBOX_HL[0]
2DBOX_HL[8:1]
2DBOX_HW
2DBOX_VT[8:1]
2DBOX_VW
2DBOX_VNUM
2DBOX_CURVP
2DBOX_HNUM
2DBOX_CURHP
BIT0
2DBOX_BNDEN
2DBOX_VT[0]
Notes 1. 2DB0 ~ 2DB3 stand for 2D arrayed box 0 to 3.
Techwell, Inc.
www.techwellinc.com
113
Jun, 28, 2005
Datasheet Rev. 2.0
Preliminary
TW2834 Video Controller
For 2D Arrayed Box & Motion Detector
VIN0
2x80
2x81
2x82
2x83
2x84
2x85
2x86
2x88
2x8A
2x8C
2x8E
2x90
2x92
2x94
2x96
2x98
2x9A
2x9C
2x87
2x89
2x8B
2x8D
2x8F
2x91
2x93
2x95
2x97
2x99
2x9B
2x9D
Address
VIN1 VIN2
2xA0
2xC0
2xA1
2xC1
2xA2
2xC2
2xA3
2xC3
2xA4
2xC4
2xA5
2xC5
2xA6
2xC6
2xA8
2xC8
2xAA 2xCA
2xAC 2xCC
2xAE 2xCE
2xB0
2xD0
2xB2
2xD2
2xB4
2xD4
2xB6
2xD6
2xB8
2xD8
2xBA 2xDA
2xBC 2xDC
2xA7
2xC7
2xA9
2xC9
2xAB 2xCB
2xAD 2xCD
2xAF
2xCF
2xB1
2xD1
2xB3
2xD3
2xB5
2xD5
2xB7
2xD7
2xB9
2xD9
2xBB 2xDB
2xBD 2xDD
2x9E
VIN3
2xE0
2xE1
2xE2
2xE3
2xE4
2xE5
2xE6
2xE8
2xEA
2xEC
2xEE
2xF0
2xF2
2xF4
2xF6
2xF8
2xFA
2xFC
2xE7
2xE9
2xEB
2xED
2xEF
2xF1
2xF3
2xF5
2xF7
2xF9
2xFB
2xFD
BIT7
BIT6
BIT5
MD_DIS
MD_REFFLD
2DBOX_HINV
2DBOX_VINV
MD_CELLSENS
MD_STRB_EN
MD_STRB
BIT4
BIT3
BD_CELSENS
MD_FLD
MASK_MODE
BIT2
BIT1
BIT0
BD_LVSENS
MD_ALIGN
MD_LVSENS
MD_SPEED
MD_DET_PERIOD
MD_TMPSENS
MD_SPSENS
MD_MASK[15:8]
MD_MASK[7:0]
MD_PATH
0
0
DETCOL_EN
DETCOL_SEL
Notes 1. VIN0 ~ VIN3 stand for video input 0 ~ video input 3.
Techwell, Inc.
www.techwellinc.com
114
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Recommended Value
For Video Decoder
VIN0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
Address
VIN1
VIN2
0x40
0x80
0x41
0x81
0x42
0x82
0x43
0x83
0x44
0x84
0x45
0x85
0x46
0x86
0x47
0x87
0x48
0x88
0x49
0x89
0x4A
0x8A
0x4B
0x8B
0x4C
0x8C
0x4D
0x8D
0x4E
0x8E
0x4F
0x8F
0x50
0x90
0x51
0x91
0x52
0x92
0x53
0x93
0x54
0x94
0x55
0x95
0x56
0x96
0x57
0x97
0x58
0x98
0x59
0x99
0x5A
0x9A
0x5B
0x9B
0x5C
0x9C
0x5D
0x9D
0x5E
0x9E
0x5F
0x9F
0x60
0xA0
0x61
0xA1
0x62
0xA2
0x63
0xA3
0x64
0xA4
0x65
0xA5
0x66
0xA6
0x67
0xA7
0x68
0xA8
0x36
0x37
0x38
0x39
0x3A
Techwell, Inc.
www.techwellinc.com
VIN3
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
1 CH
8’h00
C4
A5
1A
D0
1A
D0
88
20
06
F0
06
F0
00
D2
80
80
80
80
1F
00
00
00
00
FF
FF
FF
FF
FF
FF
FF
FF
07
07
00
11
00
D0
C8
00
F0
00
00
00
00
00
NTSC
4 CH
9 CH
16 CH
10
21
00
32
00
33
7F
55
3F
7F
55
3F
07
07
57
99
99
EE
EE
FF
FF
115
1 CH
8’h00
84
A5
22
D0
22
D0
88
20
05
20
05
20
0A
D2
80
80
80
82
2F
00
00
00
40
FF
FF
FF
FF
FF
FF
FF
FF
0F
0F
00
11
00
D0
E8
00
20
00
00
00
00
00
PAL
4 CH
9 CH
16 CH
10
20
C0
00
32
00
00
33
00
7F
55
3F
7F
55
3F
07
07
57
99
99
EE
EE
FF
FF
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN0
Notes
Address
VIN1
VIN2
0x3B
0x3C
0x3D
0x3E
0x3F
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0xB8
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
1.
VIN3
1 CH
00
80
80
82
82
00
A0
00
00
00
08
00
00
0A
40
3C
10
00
00
Preliminary
NTSC
4 CH
9 CH
16 CH
1 CH
00
80
80
82
82
00
A0
00
00
00
08
00
00
0A
40
3C
10
00
00
PAL
4 CH
9 CH
16 CH
: Modified in TW2834 RevC
Techwell, Inc.
www.techwellinc.com
116
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
For Video Controller
CH0
1x11
1x12
1x13
1x14
1x15
1x16
1x17
Address
CH1
CH2
1x00
1x01
1x02
1x03
1x04
1x05
1x06
1x07
1x08
1x09
1x0A
1x0B
1x0C
1x0D
1x0E
1x0F
1x10
1x18
1x20
1x28
1x19
1x21
1x1A
1x22
1x1B
1x23
1x1C
1x24
1x1D
1x25
1x1E
1x26
1x1F
1x27
1x30
1x31
1x32
1x33
1x34
1x35
1x36
1x37
1x38
1x39
1x3A
1x3B
1x3C
1x3D
1x3E
1x3F
1x40 ~ 1x4F
1x50
1x51
1x52
1x53
Techwell, Inc.
www.techwellinc.com
CH3
1x29
1x2A
1x2B
1x2C
1x2D
1x2E
1x2F
1 CH
8’h00
00
00
00
00
84
00
00
00
00
00
D7
00
00
00
A7
80
81
82
83
02
00
00
00
00
00
00
00
B4
00
78
00
B4
00
78
00
B4
00
78
00
B4
00
78
00
00
00
00
00
NTSC
4 CH
9 CH
00
5A
00
3C
5A
B4
00
3C
00
5A
3C
78
5A
B4
3C
78
00
3C
00
28
3C
78
00
28
78
B4
00
28
00
3C
28
50
117
16 CH
00
2D
00
1E
2D
5A
00
1E
5A
87
00
1E
87
B4
00
1E
1 CH
8’h80
00
00
00
00
84
00
00
00
00
00
D7
00
00
00
A7
80
81
82
83
02
00
00
00
00
00
00
00
B4
00
90
00
B4
00
90
00
B4
00
90
00
B4
00
90
00
00
00
00
00
PAL
4 CH
9 CH
00
5A
00
48
5A
B4
00
48
00
5A
48
90
5A
B4
48
90
00
3C
00
30
3C
78
00
30
78
B4
00
30
00
3C
30
60
16 CH
00
2D
00
24
2D
5A
00
24
5A
87
00
24
87
B4
00
24
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
CH0
1x61
1x62
Address
CH1
CH2
1x54
1x55
1x56
1x57
1x58
1x59
1x5A
1x5B
1x5C
1x5D
1x5E
1x5F
1x60
1x63
1x66
1x69
1x64
1x67
1x65
1x68
1x6C
1x6D
1x6E
1x6F
1x70
1x71
1x72
1x73
1x74
1x75
1x76
1x77
1x78
1x79
1x7A
1x7B
1x7C
1x7D
1x7E
1x7F
1x80
1x81
1x82
1x83
1x84
1x85
1x86
1x87
1x88
1x89
1x8A
Techwell, Inc.
www.techwellinc.com
CH3
1x6A
1x6B
1 CH
00
84
00
00
00
00
00
00
00
00
00
A7
80
81
82
83
02
00
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
00
00
F0
00
77
21
77
11
55
01
C0
10
00
0D
20
09
AA
Preliminary
NTSC
4 CH
9 CH
-
FF
E4
118
16 CH
-
1 CH
00
84
00
00
00
00
00
00
00
00
00
A7
80
81
82
83
00
00
00
00
00
00
00
00
00
00
00
00
00
FF
00
00
F0
00
77
21
77
11
55
01
C0
10
00
0D
20
4C
AA
PAL
4 CH
9 CH
FF
E4
16 CH
-
-
-
-
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
CH0
Address
CH1
CH2
1x8B
1x8C
1x8D
1x8E
1x90 ~ 1xBF
1xC0
1xC1
1xC2
1xC3
1xC4
1xC5
1xC6
1xC7
1xC8
1xC9 ~ 1xDF
CH3
1 CH
00
08
22
00
00
50
40
00
1F
E7
EB
10
00
00
00
Preliminary
NTSC
4 CH
9 CH
16 CH
1 CH
00
08
22
00
00
50
40
00
1F
E7
EB
10
00
00
00
PAL
4 CH
9 CH
16 CH
Notes 1. Blanks have the same value of 1 CH.
2. All values are Hexa format.
For Motion Detector
VIN0
2x80
2x81
2x82
2x83
2x84
2x85
Address
VIN1
VIN2
2xA0
2xC0
2xA1
2xC1
2xA2
2xC2
2xA3
2xC3
2xA4
2xC4
2xA5
2xC5
VIN3
2xE0
2xE1
2xE2
2xE3
2xE4
2xE5
NTSC
PAL
8’h17
08
6A
07
00
24
8’h17
08
6A
07
00
24
Notes 1. All values are Hexa format.
Techwell, Inc.
www.techwellinc.com
119
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Register Description
VIN
Index
0
0x00
1
0x40
2
0x80
3
0xC0
[7]
[6]
[5]
DET_FORMAT *
[4]
[3]
[2]
[1]
[0]
DET_
COLOR *
LOCK_
COLOR *
LOCK_
GAIN *
LOCK_
OFST *
LOCK_
PLL *
Notes “*” stand for read only register
DET_FORMAT Status of video standard detection for analog input.
0
PAL-B/D
1
PAL-M
2
3
4
5
6
DET_COLOR
PAL-N
PAL-60
NTSC-M
NTSC-4.43
NTSC-N
Status of color detection for analog input.
0
Color is not detected
1
Color is detected
LOCK_COLOR Status of locking for color demodulation loop.
0
Color demodulation loop is not locked
1
Color demodulation loop is locked
LOCK_GAIN
Status of locking for AGC loop.
0
AGC loop is not locked
1
AGC loop is locked
LOCK_OFST
Status of locking for clamping loop.
0
1
LOCK_PLL
Claming loop is not locked
Claming loop is locked
Status of locking for horizontal PLL.
0
Horizontal PLL is not locked
1
Techwell, Inc.
www.techwellinc.com
Horizontal PLL is locked
120
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x01
1
0x41
2
0x81
3
0xC1
[7]
[6]
IFMTMAN
[5]
Preliminary
[4]
IFORMAT
[3]
[2]
[1]
[0]
0
1
DET_
NONSTD *
DET_
FLD60 *
Notes “*” stand for read only register
IFMTMAN
Setting video standard manually with IFORMAT.
0
Detecting video standard of video input automatically (default)
1
Video standard is selected with IFORMAT
IFORMAT
Force to operate in a particular video standard when IFMTMAN = “1”
or to free-run in a particular video standard on no-video status when
IFMTMAN = “0”.
0
PAL-B/D (default)
1
2
3
4
5
PAL-M
PAL-N
PAL-60
NTSC-M
NTSC-4.43
6
NTSC-N
DET_NONSTD Status of non-standard video detection.
0
The incoming video source is standard
1
The incoming video source is non-standard
DET_FLD60
Status of field frequency of incoming video.
0
50Hz field frequency
1
60Hz field frequency
Techwell, Inc.
www.techwellinc.com
121
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x02
1
0x42
2
0x82
3
0xC2
AGC
[7]
[6]
[5]
[4]
AGC
PEDEST
1
0
[1]
GNTIME
[0]
OSTIME
Disable the AGC (default)
Enable the AGC
7.5 IRE setup level (7.5 IRE is ITU-R BT.601 code 16)
Control the time constant of gain tracking loop.
0
Slower
1
2
3
OSTIME
[2]
Control pedestal level by 7.5 IRE.
0
No pedestal level (0 IRE is ITU-R BT.601 code 16) (default)
1
GNTIME
[3]
Control the AGC function for active video.
0
1
PEDEST
Preliminary
Slow (default)
Fast
Faster
Control the time constant of offset tracking loop.
0
1
2
3
Techwell, Inc.
www.techwellinc.com
Slower
Slow (default)
Fast
Faster
122
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
Y
VIN
Index
0
0x07
1
0x47
2
0x87
3
0xC7
0
0x03
1
0x43
2
0x83
3
0xC3
0
0x07
1
0x47
2
0x87
3
0xC7
0
0x05
1
0x45
2
0x85
3
0xC5
HDELAY
Path
X
Y
[6]
[5]
[4]
[3]
[2]
[1]
[0]
HDELAY[9:8]
HDELAY[7:0]
HDELAY[9:8]
HDELAY[7:0]
This 10 bit register defines the starting location of horizontal active pixel with 1
pixel unit. The default value is decimal 32.
VIN
Index
0
0x07
1
0x47
2
0x87
3
0xC7
0
0x04
1
0x44
2
0x84
3
0xC4
0
0x07
1
0x47
2
0x87
3
0xC7
0
0x06
1
0x46
2
0x86
3
0xC6
HACTIVE
[7]
Preliminary
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
HACITIVE[9:8]
HACTIVE[7:0]
HACTIVE[9:8]
HACTIVE[7:0]
This 10 bit register defines the number of horizontal active pixel with 1 pixel unit.
The default value is decimal 720.
Techwell, Inc.
www.techwellinc.com
123
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x08
1
0x48
2
0x88
3
0xC8
HSWIDTH
[7]
[6]
0
0
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
HSWIDTH
This 6 bit register defines the width of horizontal sync output with 1 pixel unit.
The default value is decimal 32.
Techwell, Inc.
www.techwellinc.com
124
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
Y
VIN
Index
0
0x0D
1
0x4D
2
0x8D
3
0xCD
0
0x09
1
0x49
2
0x89
3
0xC9
0
0x0D
1
0x4D
2
0x8D
3
0xCD
0
0x0B
1
0x4B
2
0x8B
3
0xCB
VDELAY
[7]
[6]
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
VDELAY[8]
VDELAY[7:0]
VDELAY[8]
VDELAY[7:0]
This 9 bit register defines the starting location of vertical active with 1 line unit.
The default value is decimal 6. But VDELAY_Y value should be from 0 to
decimal 14.for 60Hz system and from 0 to decimal 9 for 50Hz system.
Path
X
Y
VIN
Index
0
0x0D
1
0x4D
2
0x8D
3
0xCD
0
0x0A
1
0x4A
2
0x8A
3
0xCA
0
0x0D
1
0x4D
2
0x8D
3
0xCD
0
0x0C
1
0x4C
2
0x8C
3
0xCC
VACTIVE
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VACTIVE[8]
VACTIVE[7:0]
VACTIVE[8]
VACTIVE[7:0]
This 9 bit register defines the number of vertical active lines with 1 line unit. The
default value is decimal 240. But VACTIVE_Y value should be greater than 240.
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Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x0D
1
0x4D
2
0x8D
3
0xCD
HPLLMAN
[7]
HPLLMAN
[5]
[4]
[3]
[2]
[1]
[0]
HPLLTIME
Setting horizontal PLL time constant with HPLLTIME.
0
1
HPLLTIME
[6]
Preliminary
Automatic horizontal tracking mode (default)
Horizontal PLL time constant is fixed with HPLLTIME
Control the time constant of horizontal PLL when HPLLMAN = “1”.
0
Slow
:
4
:
7
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:
Typical (default)
:
Fast
126
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Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x0E
1
0x4E
2
0x8E
3
0xCE
FLDMODE
[7]
[6]
FLDMODE
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
VSMODE
FLDPOL
HSPOL
VSPOL
1
0
Select the field flag generation mode.
0
1
2
3
Field flag is detected from incoming video (default)
Field flag is generated from small accumulator of detected field
Field flag is generated from medium accumulator of detected field
Field flag is generated from large accumulator of detected field
VSMODE
Control the VS and field flag timing.
0
VS and field flag is aligned with vertical sync (default)
1
VS and field flag is aligned with HS
FLDPOL
Select the FLD polarity.
0
Odd field is high (default)
1
Even field is high
HSPOL
Select the HS polarity.
0
1
VSPOL
Low for sync duration (default)
High for sync duration
Select the VS polarity.
0
Low for sync duration (default)
1
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High for sync duration
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Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x0F
1
0x4F
2
0x8F
3
0xCF
HUE
[7]
[5]
[4]
[3]
[2]
[1]
[0]
[1]
[0]
HUE
Control the hue information. The resolution is 1.4° / step.
0
:
128
:
255
VIN
Index
0
0x10
1
0x50
2
0x90
3
0xD0
SAT
[6]
Preliminary
[7]
-180°
:
0° (default)
:
180°
[6]
[5]
[4]
[3]
[2]
SAT
Control the color saturation. The resolution is 0.8% / step.
0
0%
:
:
128
:
255
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100% (default)
:
200%
128
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x11
1
0x51
2
0x91
3
0xD1
CONT
[7]
[5]
[4]
[3]
[2]
[1]
[0]
[2]
[1]
[0]
CONT
Control the contrast. The resolution is 0.8% / step.
0
:
128
:
255
VIN
Index
0
0x12
1
0x52
2
0x92
3
0xD2
BRT
[6]
Preliminary
[7]
0%
:
100% (default)
:
200%
[6]
[5]
[4]
[3]
BRT
Control the brightness. The resolution is 0.2IRE / step.
0
-25IRE
:
128
:
255
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:
0IRE (default)
:
25IRE
129
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x13
1
0x53
2
0x93
3
0xD3
IFCOMP
[7]
CLPF
[3]
[2]
ACCTIME
[1]
[0]
APCTIME
No compensation (default)
+1 dB/ MHz
+2 dB/ MHz
+3 dB/ MHz
Select the Color LPF mode.
0
550KHz bandwidth
1
750KHz bandwidth (default)
2
950KHz bandwidth
1.1MHz bandwidth
Control the time constant of auto color control loop.
0
Slower
1
Slow
2
3
APCTIME
[4]
Select the IF-compensation filter mode.
3
ACCTIME
[5]
IFCOMP
0
1
2
3
CLPF
[6]
Preliminary
Fast
Faster (default)
Control the time constant of auto phase control loop.
0
Slower
1
2
3
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Slow
Fast
Faster (default)
130
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x14
1
0x54
2
0x94
3
0xD4
YPEAK
[7]
[6]
YPEAK_Y
Preliminary
[5]
[4]
YPEAK_X
[3]
[2]
YPEAK_
FLT_Y
YPEAK_
FLT_X
[1]
[0]
CKIL
Control the luminance peaking for display and record path.
0
1
2
3
No peaking (default)
31.25%
62.5%
93.75%
YPEAK_FLT
Select the luminance peaking filter mode for display and record path.
0
4~5MHz frequency band (default)
1
2~4MHz frequency band
CKIL
Control the color killing mode.
0
Auto detection mode (default)
1
Auto detection mode
2
Color is always alive
3
Color is always killed
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Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x15
1
0x55
2
0x95
3
0xD5
VSFLT
[7]
[6]
Preliminary
[5]
VSFLT_Y
[4]
[3]
VSFLT_X
[2]
[1]
HSFLT_Y
[0]
HSFLT_X
Select the vertical anti-aliasing filter mode for display and record path.
0,1 Full bandwidth (default)
2
0.25 Line-rate bandwidth
3
0.18 Line-rate bandwidth
HSFLT
Select the horizontal anti-aliasing filter mode for display and record path.
0
1
2
3
Path
VIN
Index
0
0x16
1
0x56
X
Y
2
0x96
3
0xD6
0
0x17
1
0x57
2
0x97
3
0xD7
Full bandwidth (default)
2 MHz bandwidth
1.5 MHz bandwidth
1 MHz bandwidth
[7]
YBWI
[6]
[5]
COMBMD
[4]
[3]
[2]
[1]
[0]
HSFRM
0
0
0
0
YBWI
Select the luminance trap filter mode.
0
Narrow bandwidth trap filter mode (default)
1
Wide bandwidth trap filter mode
COMBMD
Select the adaptive comb filter mode.
0,1 Adaptive comb filter mode (default)
2
Force trap filter mode
3
Not supported
HSFRM
Select the special horizontal anti-aliasing filter mode for frame CIF display
mode that means 1/2 H scaling but full V scaling picture.
0
Disable the special horizontal anti-aliasing filter. (default)
1
Enable the special horizontal anti-aliasing filter for frame CIF display mode
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Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
Y
VIN
Index
0
0x18
1
0x58
2
0x98
3
0xD8
0
0x19
1
0x59
2
0x99
3
0xD9
0
0x1A
1
0x5A
2
0x9A
3
0xDA
0
0x1B
1
0x5B
2
0x9B
3
0xDB
VSCALE
Path
X
Y
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VSCALE[15:8]
VSCALE[7:0]
VSCALE[15:8]
VSCALE[7:0]
The 16 bit register defines a vertical scaling ratio. The actual vertical scaling
ratio is VSCALE/(2^16 – 1). The default value is 0xFFFF.
VIN
Index
0
0x1C
1
0x5C
2
0x9C
3
0xDC
0
0x1D
1
0x5D
2
0x9D
3
0xDD
0
0x1E
1
0x5E
2
0x9E
3
0xDE
0
0x1F
1
0x5F
2
0x9F
3
0xDF
HSCALE
[7]
Preliminary
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
HSCALE[15:8]
HSCALE[7:0]
HSCALE[15:8]
HSCALE[7:0]
The 16 bit register defines a horizontal scaling ratio. The actual horizontal
scaling ratio is HSCALE/(2^16 – 1). The default value is 0xFFFF.
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Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
Y
VIN
Index
0
0x20
1
0x60
2
0xA0
3
0xE0
0
0x21
1
0x61
2
0xA1
3
0xE1
VFLT_MD
VBW
[3]
PAL_DLY
[2]
[1]
ODD_EN EVEN_EN
[0]
1
Vertical poly-phase mode (default)
Additional vertical bandwidth reduction mode with VBW bits
Wide
Narrow
Narrower
Vertical scaling mode is selected in chrominance path (default)
PAL delay line mode is selected in chrominance path
Control the valid signal in ODD field.
0
Valid signal is always disabled in ODD field
1
EVEN_EN
VFLT_MD
[4]
Select the PAL delay line mode.
0
1
ODD_EN
0
[5]
Control the vertical bandwidth when VSFLT_MD = “1”.
0
Wider (default)
1
2
3
PAL_DLY
[6]
Select the additional vertical scaling filter mode.
0
1
VBW
[7]
Preliminary
Normal operation (default)
Control the valid signal in EVEN field.
0
Valid signal is always disabled in EVEN field
1
Normal operation (default)
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Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x22
1
0x62
2
0xA2
3
0xE2
BLKEN
[7]
[6]
[5]
[4]
[3]
[2]
BLKEN
BLKCOL
0
LMTOUT
SW_
RESET
ANA_SW
Blank color is disabled (default)
Blank color is enabled
Black color
Output ranges are limited to 16 ~ 239
Reset the system by software except control registers.
This bit is cleared by itself in a few clocks after enabled
0
Normal operation (default)
1
ANA_SW
DEC_PATH_X
Control the range of output level.
0
Output ranges are limited to 2 ~ 254 (default)
1
SW_RESET
[0]
Select the blank color when BLKEN = “1”.
0
Blue color (default)
1
LMTOUT
[1]
Control the blank output.
0
1
BLKCOL
Preliminary
Enable soft reset
Select the analog video input using switch.
0
VIN_A channel is selected (default)
1
VIN_B channel is selected
DEC_PATH_X Select the video input for each decoder path in display path.
0
Video input from internal video decoder on VIN0 pins (default)
1
Video input from internal video decoder on VIN1 pins
2
Video input from internal video decoder on VIN2 pins
3
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Video input from internal video decoder on VIN3 pins
135
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
0x23
1
0x63
2
0xA3
3
0xE3
Preliminary
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
1
0
0
0
1
[2]
[1]
[0]
This is reserved register.
For normal operation, the above value should be set in this register.
PBIN
Index
0
0x26
1
0x66
2
0xA6
3
0xE6
0
0x24
1
0x64
2
0xA4
3
0xE4
HDELAY_PB
[7]
[6]
[5]
[4]
[3]
HDELAY_PB[9:8]
HDELAY_PB[7:0]
This 10 bit register defines the starting location of horizontal active pixel with 1
pixel unit. The default value is decimal 0. This register is enabled only when the
PB_SYNC_EN (0x26, 0x66, 0xA6, 0xE6) = “1”.
PBIN
Index
0
0x26
1
0x66
2
0xA6
3
0xE6
0
0x25
1
0x65
2
0xA5
3
0xE5
HACTIVE_PB
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
HACTIVE_PB[9:8]
HACTIVE_PB[7:0]
This 10 bit register defines the number of horizontal active pixel with 1 pixel unit.
The default value is decimal 720. This register is enabled only when the
PB_SYNC_EN (0x26, 0x66, 0xA6, 0xE6) = “1”.
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Datasheet Rev. 2.0
TW2834 Video Controller
PBIN
Index
0
0x26
1
0x66
2
0xA6
3
0xE6
PB_SCL_EN
[7]
[6]
PB_SCL
_EN
PB_SYNC
_EN
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
Enable the independent anti-aliasing filter mode for playback input path.
For the details, the application note (page 6 ~ 13) can be referred to.
0
Disable the independent anti-aliasing filter mode for playback input path
In this case, it is controlled by anti-aliasing filter mode of VIN path (default)
1
Enable the independent anti-aliasing filter mode for playback input path
PB_SYNC_EN Enable the independent H/V sync control mode for playback input path.
0
Disable the independent H/V sync control mode for playback input path
In this case, it is controlled by H/V sync mode of VIN path (default)
1
Enable the independent H/V sync control for playback input path
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Datasheet Rev. 2.0
TW2834 Video Controller
PBIN
Index
0
0x26
1
0x66
2
0xA6
3
0xE6
0
0x27
1
0x67
2
0xA7
3
0xE7
VDELAY_PB
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
VDELAY
_PB[8]
VDELAY_PB[7:0]
This 9 bit register defines the starting location of vertical active with 1 line unit.
The default value is decimal 0. This register is enabled only when the
PB_SYNC_EN (0x26, 0x66, 0xA6, 0xE6) = “1”.
PBIN
Index
0
0x26
1
0x66
2
0xA6
3
0xE6
0
0x28
1
0x68
2
0xA8
3
0xE8
VACTIVE_PB
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
VACTIVE
_PB[8]
VACTIVE_PB[7:0]
This 9 bit register defines the number of vertical active lines with 1 line unit. The
default value is decimal 240. This register is enabled only when the
PB_SYNC_EN (0x26, 0x66, 0xA6, 0xE6) = “1”.
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
0x36
VSFLT_PB1
HSFLT_PB1
VSFLT_PB0
HSFLT_PB0
0x37
VSFLT_PB3
HSFLT_PB3
VSFLT_PB2
HSFLT_PB2
VSFLT_PB
Select the vertical anti-aliasing filter mode for playback path only when the
PB_SCL_EN = “1”.
0,1 Full bandwidth (default)
2
0.25 Line-rate bandwidth
3
0.18 Line-rate bandwidth
HSFLT_PB
Select the horizontal anti-aliasing filter mode for playback path only when the
PB_SCL_EN = “1”.
0
Full bandwidth (default)
1
2 MHz bandwidth
2
3
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1.5 MHz bandwidth
1 MHz bandwidth
139
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
0x38
MAN_PB_
CROP
PB_CROP
_MD
MAN_PB_CROP
[5]
Preliminary
[4]
PB_ACT_MD
[3]
[2]
[1]
[0]
PB_CH_EN
Select manual cropping mode for playback input
0
1
Auto cropping mode with fixed cropping position (default)
Manual cropping mode with HDELAY/HACTIVE and VDELAY/VACTIVE
PB_CROP_MD Select the cropping mode for playback input
0
Normal record mode or frame record mode (default)
1
PB_ACT_MD
Cropping for DVR record mode or DVR frame record mode input
Select the horizontal active size for playback input when MAN_PB_CROP is
low
0
720 pixels (default)
1
704 pixels
2/3 640 pixels
PB_CH_EN
Select the playback input for each channel in display path
PB_CH_EN[3:0] stand for Input 3 to 0
0
Decoder path input (default)
1
Playback path input
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
0x39
PB_PATH_CH3
[6]
[5]
Preliminary
[4]
[3]
PB_PATH_CH2
[2]
[1]
PB_PATH_CH1
[0]
PB_PATH_CH0
PB_PATH_CH Select the playback input for each playback path if PB_4CH_MD = “1”.
0
Playback input 0 from PBIN [7:0] pin (default)
1
Playback input 1 from VDOUTY [7:0] pin
2
3
Index
[7]
Playback input 2 from DATAY [15:8] pin
Playback input 3 from DATAY [7:0] pin
[6]
0x3A
[5]
[4]
[3]
[2]
PB_FLDPOL
PB_FLDPOL
[1]
[0]
PB_NOVID
Select the FLD polarity of playback input
PB_FLDPOL[3:0] stand for Input 3 to 0
0
Even field is high
1
Odd field is high
PB_NOVID
Force No-Video status to playback input
PB_NOVID[3:0] stands for Input 3 to 0
0
Bypass the playback input
1
Force No-Video status to playback input
Index
[7]
[6]
0x3B
[5]
[4]
0
[3]
[2]
[1]
[0]
PB_EC_656
0
0
PB_4CH_MD
PB_EC_656
Enable the error correction mode for SAV/EAV code of playback input
0
Enable the error correction mode
1
Bypass
PB_4CH_MD
Select 4ch playback mode
0
1
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Playback 1ch mode
Playback 4ch mode
141
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
Preliminary
[4]
0x3C
U_GAIN
[1]
[0]
[7]
[2]
[1]
[0]
:
100% (default)
:
200%
[6]
[5]
0x3D
V_GAIN
[2]
Adjust gain for U (Cb) component of VIN0 ~ VIN3.
The resolution is 0.8% / step.
0
0%
:
128
:
255
Index
[3]
U_GAIN
[4]
[3]
V_GAIN
Adjust gain for V (Cr) component of VIN0 ~ VIN3.
The resolution is 0.8% / step.
0
0%
:
:
128
:
255
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100% (default)
:
200%
142
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
Preliminary
[4]
0x3E
U_OFF
[2]
[1]
[0]
[2]
[1]
[0]
U (Cb) offset adjustment register of VIN0 ~ VIN3.
The resolution is 0.4% / step.
0
-50%
:
128
:
255
Index
[3]
U_OFF
[7]
:
0% (default)
:
50%
[6]
[5]
[4]
0x3F
[3]
V_OFF
V_OFF
V (Cr) offset adjustment register of VIN0 ~ VIN3.
The resolution is 0.4% / step.
0
-50%
:
:
128
:
255
0% (default)
:
50%
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0x77
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
0x78
1
0
1
ANA_CH_EN
ANA_CH_EN
[2]
[1]
[0]
ADC_PWDN
Enable the selectable interface of ADC output to change the analog input pin
interface. This bit is related with the ANA_CH (0xBA) register.
0
Fixed interface of ADC output (default)
1
ADC_PWDN
[3]
Selectable interface of ADC output with the ANA_CH (0xBA) register
Power down the ADC of video input.
ADC_PWDN [3:0] stands for VIN3 to VIN0.
0
Normal (default)
1
Power down
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0x79
0
0
0
0
0
0
0
0
0x7A
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0x7B
FLDOS_
3Y
FLDOS_
2Y
FLDOS_
1Y
FLDOS_
0Y
FLDOS_
3X
FLDOS_
2X
FLDOS_
1X
FLDOS_
0X
FLDOS
Remove the field offset between ODD and EVEN field. The number stands for
VIN3 to VIN0 and X, Y stand for display and record path.
0
Normal operation (default)
1
Remove the field offset between ODD and EVEN field
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0x7C
0
0
0
0
1
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
[2]
0x7D
0
0
0
0
0
PB_SDEL_EN
[1]
[0]
PB_SDEL
PB_SDEL_EN
Enable the variable parsing mode of ITU-R BT.656 data for playback input
0
Disable the variable parsing mode
1
Enable the variable parsing mode
PB_SDEL
Control the start point of active video from ITU-R BT.656 digital playback input
when PB_SDEL_EN = “1”
0
No delay
1
1ck delay of 27MHz
2
3
2ck delay of 27MHz
3ck delay of 27MHz
Index
[7]
[6]
[5]
[4]
[3]
[2]
0xB8
0
0
0
0
0
0
[1]
[0]
NOVID_MODE
NOVID_MODE Select the No Video signal generation mode
0
1
2
3
Index
[7]
0xB9
FLD3*
Notes
Slower (default)
Slow
Fast
Faster
[6]
[5]
[4]
[3]
[2]
[1]
[0]
FLD2*
FLD1*
FLD0*
VAV3*
VAV2*
VAV1*
VAV0*
“*” stand for read only register
FLD
Status of the field flag for each decoder path.
0
Odd field
1
Even field
VAV
Status of the vertical active video signal for each decoder path
0
Vertical blanking time
1
Vertical active time
Techwell, Inc.
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145
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
0xBA
[6]
ANA_CH
Index
[4]
[3]
ANA_CH2
[2]
[1]
ANA_CH1
[0]
ANA_CH0
Select the ADC output for each decoder path when ANA_CH_EN = “1”.
This register is useful to change the analog input pin interface.
0
ADC output from VIN0 (default)
1
2
3
0xF8
[5]
ANA_CH3
Preliminary
[7]
HAV_VALID
ADC output from VIN1
ADC output from VIN2
ADC output from VIN3
[6]
[5]
[4]
0
AUTO_
BGND
0
[3]
[2]
C_CORE
[1]
Y_H_CORE
HAV_VALID
Select the VALID output mode.
0
Valid data indicator only for active data (default)
1
Valid data indicator for both active data and ITU-R 656 timing codes
AUTO_BGND
Select the decoder blanking mode.
0
Manual blanking mode (default)
1
Automatic blanking mode when No-video is detected.
C_CORE
Coring to reduce the noise in the chrominance.
0
No coring
1
Coring value is within 128 +/- 1 range
2
Coring value is within 128 +/- 2 range (default)
3
Coring value is within 128 +/- 4 range
Y_H_CORE
Coring to reduce the high frequency noise in the luminance.
0
No coring
1
Coring value is within +/- 1 range
2
3
Techwell, Inc.
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[0]
Coring value is within +/- 2 range (default)
Coring value is within +/- 4 range
146
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
0xF9
0
CDEL
[6]
[5]
Preliminary
[4]
CDEL
[3]
[2]
[1]
[0]
0
0
0
0
Adjust the group delay of chrominance relative to luminance.
0
-2.0 pixel
1
-1.5 pixel
2
3
4
5
6
-1.0 pixel
-0.5 pixel
0.0 pixel (default)
0.5 pixel
1.0 pixel
7
1.5 pixel
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0xFA
0
0
1
1
1
1
0
0
0xFB
0
0
0
1
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
Index
[7]
[6]
0xFC
AFIL_BYP
[5]
[4]
AFIL_BYP
[3]
[2]
[1]
[0]
0
0
0
0
Bypass the analog anti-aliasing filter.
AFIL_BYP [3:0] stands for VIN3 to VIN0.
0
Enable the analog anti-aliasing filter (default)
1
Bypass the analog anti-aliasing filter
Techwell, Inc.
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147
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0xFD
0
0
0
0
0
0
0
0
[1]
[0]
This is reserved register.
For normal operation, the above value should be set in this register.
Index
[7]
[6]
0xFE
[5]
[4]
[3]
DEV_ID *
[2]
REV_ID *
Notes “*” stand for read only register
DEV_ID
The TW2834 product ID code is 00010.
REV_ID
The revision number
0
1
Techwell, Inc.
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BAPA2-GE
BAPA3-GE
148
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
1x00
[7]
SYS_5060
Preliminary
[6]
[5]
[4]
OVERLAY
LINK
_LAST_X
LINK
_LAST_Y
[3]
[2]
[1]
LINK_EN_X LINK_EN_Y
[0]
LINK_NUM
SYS_5060
Select the standard format for video controller.
0
60Hz, 525 line format (default)
1
50Hz, 625 line format
OVERLAY
Control the overlay between display and record path.
0
Disable the overlay (default)
1
Enable the overlay
LINK_LAST
Define the lowest slaver chip in chip-to-chip cascade operation.
0
Master or middle slaver chip (default)
1
The lowest slaver chip
LINK_EN
Control the chip-to-chip cascade operation for display and record path.
0
1
LINK_NUM
Disable the cascade operation (default)
Enable the cascade operation
Define the stage number of chip-to-chip cascade connection.
0
Master chip (default)
1
2
3
1st slaver chip
2nd slaver chip
3rd slaver chip
Path
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
X
1x01
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
X
1x02
TBLINK
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
TBLINK
Control the blink period of channel boundary.
0
Blink for every 30 fields (default)
1
Blink for every 60 fields
SAVE_ADDR
Define the save address of SDRAM.
The Unit Address has 4Mbit memory space.
0-3
Reserved for normal operation. Do not use this address.
4-15
Available address for 64M SDRAM
4-31
4-63
4-127
Path
X
Index
[7]
1x03
RECALL_
FLD
Available address for 128M SDRAM
Available address for 256M SDRAM
Available address for 512M SDRAM
[6]
[5]
SAVE_FLD
[4]
[3]
[2]
SAVE_
HID
RECALL_FLD
Select the field or frame data when recalling picture.
0
Recall frame data from SDRAM (default)
1
Recall field data from SDRAM
SAVE_FLD
Select the field or frame data to save.
0
Save frame data to SDRAM (default)
1
Save field data to SDRAM
SAVE_HID
Control the priority to save picture.
0
Save picture as shown in screen (default)
1
Save picture even though hidden by other picture
SAVE_REQ
Request to save for each channel.
SAVE_REQ[3:0] stands for channel 3 to 0
0
None operation (default)
1
Request to start saving picture
Techwell, Inc.
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[0]
SAVE_ADDR
150
[1]
[0]
SAVE_REQ
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
X
1x04
0
STRB_FLD
[4]
[3]
DUAL_PAGE
[2]
[1]
[0]
STRB_REQ
Capture first field of any field
Capture frame
Set dual page mode.
0
Normal strobe operation for each channel (default)
1
STRB_REQ
[5]
STRB_FLD
Control the field mode for strobe operation.
0
Capture odd field only (default)
1
Capture even field only
2
3
DUAL_PAGE
[6]
Preliminary
Enable dual page operation
Request strobe operation.
STRB_REQ[3:0] stands for channel 3 to 0
0
1
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None operation (default)
Request to start strobe operation
151
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
Index
1x05
[7]
[6]
NOVID_MODE
[5]
0
Preliminary
[4]
0
[3]
[2]
0
ADDR_OUT
_EN
[1]
[0]
INVALID_MODE
NOVID_MODE Select the Indication method for No-Video detected channel
0
1
2
3
Bypass (default)
Capture last image
Blanked with blank color
Capture last image and blink channel boundary
ADDR_OUT_EN Control the address pin function of display path for playback 4ch mode
0
Playback 4ch mode for ADDR_X[12:11], BA1_X Pin. (default)
1
Normal mode for ADDR_X[12:11], BA1_X Pin.
INVALID_MODE Indication mode for no channel area
In horizontal and vertical active region
0
Background layer with background color (default)
1
Y = 0, Cb/Cr = 128
2
Y/Cb/Cr = 0
3
Y/Cb/Cr = 0
In horizontal and vertical blanking region
0
Y = 16, Cb/Cr = 128 (default)
1
Background layer with background color
2
3
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Y = 0, Cb = {0, F, V, 0, Cascade, linenum[8:7]}, Cr = {0, linenum[6:0]}
Y/Cb/Cr = 0
152
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
[6]
X
1x06
MUX_MODE
0
Preliminary
[5]
[4]
MUX_FLD
[3]
[2]
[1]
[0]
0
0
0
0
[1]
[0]
MUX_MODE
Define the switch operation mode
0
Switch still mode (default)
1
Switch live mode
MUX_FLD
Select the field mode when switch still mode
0
Odd Field (default)
1
Even Field
2,3 Capture Frame
Path
Index
[7]
[6]
[5]
[4]
X
1x07
STRB_AUTO
0
0
INTR_REQX
[3]
[2]
INTR_CH
STRB_AUTO
Enable automatic strobe mode when FUNC_MODE = “1”
0
User strobe mode (default)
1
Automatic strobe mode
INTR_REQX
Request to start the interrupt switch operation in display path
0
None operation (default)
1
Request to start the interrupt switch operation in display path
INTR_CH
Channel number for interrupt switch operation
INTR_CH[3:2] represents the stage of cascaded chips for interrupt switch
operation
0
Master chip (default)
1
1st slaver chip
2
2nd slaver chip
3
3rd slaver chip
INTR_CH[1:0] represents the channel number for interrupt switch operation
0
Channel 0 (default)
1
Channel 1
2
3
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Channel 2
Channel 3
153
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
Index
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
1x08
MUX_OUT_CH0 *
MUX_OUT_CH1 *
1x09
MUX_OUT_CH2 *
MUX_OUT_CH3 *
[0]
MUX_OUT_CH0 Channel information in current field/frame for interrupt switch operation
MUX_OUT_CH1 Channel information in next field/frame for interrupt switch operation
MUX_OUT_CH2 Channel information after 2 fields for interrupt switch operation
MUX_OUT_CH3 Channel information after 3 fields for interrupt switch operation
MUX_OUT_CH [3:2] represents the stage of cascaded chips for interrupt
switch operation
0
Master chip (default)
1
2
3
1st slaver chip
2nd slaver chip
3rd slaver chip
MUX_OUT_CH [1:0] represents the channel number for interrupt switch
operation
0
Channel 0 (default)
1
Channel 1
2
Channel 2
3
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Channel 3
154
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
X
1x0A
[7]
[6]
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
CHID_MUX_OUT *
CHID_MUX_OUT
Channel ID of current field/frame in interrupt switch operation
CHID_MUX_OUT [7] represents the channel ID latch enable pulse
0->1
Rising edge for channel ID Update
1->0
Falling edge after 16 clock * 18.5 ns from rising edge
CHID_MUX_OUT [6] represents the updated picture in interrupt switch
operation
0
No Updated
1
Updated by new switching
CHID_MUX_OUT [5] represents the field mode in interrupt switch operation
0
Frame Mode
1
Field Mode
CHID_MUX_OUT [4] represents the analog switch path
0
Analog switch 0 path
1
Analog switch 1 path
CHID_MUX_OUT [3:2] represents the stage of cascaded chips for interrupt
switch operation
0
Master chip
1
1st slaver chip
2
3
2nd slaver chip
3rd slaver chip
CHID_MUX_OUT [1:0] represents the channel number for interrupt switch
operation
0
1
2
3
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Channel 0
Channel 1
Channel 2
Channel 3
155
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
X
1x0B
ZM_EVEN_OS
[6]
[5]
Preliminary
[4]
ZM_ODD_OS
[3]
[2]
FR_EVEN_OS
[1]
[0]
FR_ODD_OS
ZM_EVEN_OS Even field offset coefficient when zoom is enabled
0
No Offset
1
+ 0.25 Offset
2
3
ZM_ODD_OS
+ 0.5 Offset
+ 0.75 Offset (default)
Odd field offset coefficient when zoom is enabled
0
No Offset
1
2
3
+ 0.25 Offset (default)
+ 0.5 Offset
+ 0.75 Offset
FR_EVEN_OS Even field offset coefficient when the enhancement is enabled
0
No Offset
1
+ 0.25 Offset (default)
2
+ 0.5 Offset
3
+ 0.75 Offset
FR_ODD_OS
Odd field offset coefficient when the enhancement is enabled
0
No Offset
1
+ 0.25 Offset
2
+ 0.5 Offset
3
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+ 0.75 Offset (default)
156
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
[6]
X
1x0C
ZMENA
0
[5]
Preliminary
[4]
ZMBNDCOL
[3]
ZMENA
Enable the zoom function.
0
Disable the zoom function (default)
1
Enable the zoom function
ZMBNDCOL
Define the boundary color for zoomed area
0
0% Black
1
25% Gray
2
75% Gray (default)
3
ZMBNDEN
[2]
ZMBNDEN ZMAREAEN
[1]
[0]
ZMAREA
100% White
Enable the boundary of zoomed area.
0
Disable the boundary of zoomed area (default)
1
Enable the boundary of zoomed area
ZMAREAEN
Enable the mark of zoomed area
0
Disable the mark of zoom area (default)
1
Enable the mark of zoom area
ZMAREA
Control the effect of zoomed area.
0
10 IRE Bright up for inside of zoomed area (default)
1
20 IRE Bright up for inside of zoomed area
2
10 IRE Bright up for outside of zoomed area
3
Techwell, Inc.
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20 IRE Bright up for outside of zoomed area
157
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
X
1x0D
ZOOMH
[7]
Index
X
1x0E
ZOOMV
[5]
[4]
[3]
[2]
[1]
[0]
[1]
[0]
ZOOMH
Define the horizontal left point of zoomed area. 4 pixels/step.
0
Left end value (default)
:
:
180
Path
[6]
Preliminary
[7]
Right end value
[6]
[5]
[4]
[3]
[2]
ZOOMV
Define the vertical top point of zoom area. 2 lines/step.
0
Top end value (default)
:
:
120
:
144
Techwell, Inc.
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Bottom end value for 60Hz, 525 lines system
:
Bottom end value for 50Hz, 625 lines system
158
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
X
1x0F
FRZ_FLD
[7]
[5]
FRZ_FLD
[4]
[3]
BNDCOL
[2]
BGDCOL
[1]
[0]
BLKCOL
Select the image for freeze function or for last image capture on video loss.
0
Last image
1
Last image of 1 field before
2
3
BNDCOL
[6]
Preliminary
Last image of 2 fields before (default)
Last image of 3 fields before
Define the boundary color of channel.
0
0% Black
1
25% Gray
2
75% Gray
3
100% White (default)
Channel boundary color is changed according to this value when boundary is
blinking.
0
100% White
1
100% White
2
0% Black
3
0% Black (default)
BGDCOL
Define the background color.
0
0% Black
1
40% Gray (default)
2
3
BLKCOL
75% Gray
Blue (100% Amplitude 100% Saturation)
Define the color of the blanked channel.
0
0% Black
1
2
3
Techwell, Inc.
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40% Gray
75% Gray
Blue (100% Amplitude 100% Saturation) (default)
159
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
CH
Index
0
1x10
1
1x18
2
1x20
3
1x28
X
CH_EN
CH_EN
POP_UP
[5]
[4]
FUNC_MODE
[3]
[2]
DMCH_EN
DMCH_
PATH
[1]
[0]
RESERVED
Disable the channel (default)
Enable the channel
Enable pop-up.
0
Disable pop-up (default)
1
FUNC_MODE
[6]
Enable the channel.
0
1
POP_UP
[7]
Preliminary
Enable pop-up
Select the operation mode.
0
Live mode (default)
1
Strobe mode
2-3 Switch mode
DMCH_EN
Enable the dummy channel when the corresponding channel is enabled.
0
Disable the dummy channel (default)
1
Enable the dummy channel
DMCH_PATH
Select the main or dummy channel when dummy channel is enabled.
0
Main channel for channel input (default)
1
Dummy channel for channel input
RESERVED
The following value should be set for proper operation.
1x10 0
1x18 1
1x20 2
1x28 3
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160
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
CH
Index
0
1x11
1
1x19
2
1x21
3
1x29
X
RECALL_EN
[5]
[4]
[3]
FREEZE H_MIRROR V_MIRROR ENHANCE
[2]
[1]
[0]
BLANK
BOUND
BLINK
Disable the recall function (default)
Enable the recall function
Enable the freeze function of main channel.
0
Normal operation (default)
1
H_MIRROR
RECALL_
EN
[6]
Enable the recall function of main channel.
0
1
FREEZE
[7]
Preliminary
Enable the freeze function
Enable the horizontal mirroring function of main channel.
0
Normal operation (default)
1
Enable the horizontal mirroring function
V_MIRROR
Enable the vertical mirroring function of main channel.
0
Normal operation (default)
1
Enable the vertical mirroring function
ENHANCE
Enable the image enhancement function of main channel.
0
Normal operation (default)
1
Enable the image enhancement function
BLANK
Enable the blank of main channel.
0
Disable the blank (default)
1
Enable the blank
BOUND
Enable the channel boundary of main channel.
0
1
BLINK
Disable the channel boundary
Enable the channel boundary (default)
Enable the boundary blink of main channel when boundary is enabled.
0
Disable the boundary blink (default)
1
Techwell, Inc.
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Enable the boundary blink
161
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
CH
Index
0
1x12
1
1x1A
2
1x22
3
1x2A
[7]
[6]
Preliminary
[5]
[4]
0
[3]
[2]
[1]
[0]
RECALL_ADDR
RECALL_ADDR Define the recall address for main channel.
0-3
4-15
4-31
4-63
4-127
Techwell, Inc.
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Reserved address. Do not use this value
Available address for 64M SDRAM
Available address for 128M SDRAM
Available address for 256M SDRAM
Available address for 512M SDRAM
162
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
CH
Index
0
1x13
1
1x1B
2
1x23
3
1x2B
RECALL_DM
RECALL
_DM
[6]
[5]
[4]
[3]
FREEZE H_MIRROR V_MIRROR ENHANCE
_DM
_DM
_DM
_DM
[2]
[1]
[0]
BLANK
_DM
BOUND
_DM
BLINK
_DM
Enable the recall function of dummy channel.
0
1
FREEZE_DM
[7]
Preliminary
Disable the recall function (default)
Enable the recall function
Enable the freeze function of dummy channel.
0
Normal operation (default)
1
Enable the freeze function
H_MIRROR_DM Enable the horizontal mirroring function of dummy channel.
0
Normal operation (default)
1
Enable the horizontal mirroring function
V_MIRROR_DM Enable the vertical mirroring function of dummy channel.
0
Normal operation (default)
1
Enable the vertical mirroring function
ENHANCE_DM Enable the image enhancement function of dummy channel.
0
Normal operation (default)
1
Enable the image enhancement function
BLANK_DM
Enable the blank of dummy channel.
0
Disable the blank (default)
1
Enable the blank
BOUND_DM
Enable the channel boundary of dummy channel.
0
1
BLINK_DM
Disable the channel boundary
Enable the channel boundary (default)
Enable the boundary blink of dummy channel when boundary is enabled.
0
Disable the boundary blink (default)
1
Techwell, Inc.
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Enable the boundary blink
163
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
CH
Index
0
1x14
1
1x1C
2
1x24
3
1x2C
[7]
[6]
Preliminary
[5]
[4]
0
[3]
[2]
[1]
[0]
RECALL_ADDR_DM
RECALL_ADDR_DM Define the recall address for dummy channel.
0-3
4-15
4-31
4-63
4-127
Path
X
CH
Index
0
1x15
1
1x1D
2
1x25
3
1x2D
Reserved address. Do not use this value
Available address for 64M SDRAM
Available address for 128M SDRAM
Available address for 256M SDRAM
Available address for 512M SDRAM
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
Techwell, Inc.
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164
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
CH
Index
[7]
0
1x16
PB_AUTO
_EN
1
1x1E
0
2
1x26
0
3
1x2E
0
Preliminary
[6]
[5]
[4]
0
PB_STOP
EVENT
_PB
[3]
[2]
[1]
[0]
PB_CH_NUM
PB_AUTO_EN Enable the auto strobe and auto cropping function for playback input
0
Disable the auto strobe/cropping function (default)
1
Enable the auto strobe/cropping function
PB_STOP
Disable the auto strobe operation for playback input
0
Normal operation (default)
1
Disable the auto strobe operation for playback input
EVEN_PB
Enable the event strobe function for playback input
0
Disable the event strobe function for playback input
1
Enable the event strobe function for playback input
PB_CH_NUM
Select the channel number from playback input for display
PB_CH_NUM[3:2] represents the stage of cascaded chips
0
Master chip
1
1st slaver chip
2
2nd slaver chip
3
3rd slaver chip
PB_CH_NUM[1:0] represents the channel number
0
Channel 0
1
Channel 1
2
Channel 2
3
Channel 3
Path
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
X
1x2F
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
CH
Index
0
1x30
1
1x34
2
1x38
3
1x3C
0
1x40
1
1x44
2
1x48
3
1x4C
PICHL
[7]
[6]
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
[2]
[1]
[0]
PICHL
PICHL_DM
Define the horizontal left position of channel
0
Left end (default)
:
:
180 Right end
Path
X
PICHR
CH
Index
0
1x31
1
1x35
2
1x39
3
1x3D
0
1x41
1
1x45
2
1x49
3
1x4D
[7]
[6]
[5]
[4]
[3]
PICHR
PICHR_DM
Define the horizontal right position of channel region
0
Left end (default)
:
:
180 Right end
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
X
CH
Index
0
1x32
1
1x36
2
1x3A
3
1x3E
0
1x42
1
1x46
2
1x4A
3
1x4E
PICVT
[7]
[6]
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
[2]
[1]
[0]
PICVT
PICVT_DM
Define the vertical top position of channel region.
0
Top end (default)
:
:
120 Bottom end for 60Hz system
:
:
144 Bottom end for 50Hz system
Path
X
PICVB
CH
Index
0
1x33
1
1x37
2
1x3B
3
1x3F
0
1x43
1
1x47
2
1x4B
3
1x4F
[7]
[6]
[5]
[4]
[3]
PICVB
PICVB_DM
Define the vertical bottom position of channel region.
0
Top end (default)
:
:
120 Bottom end for 60Hz system
:
:
144 Bottom end for 50Hz system
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1x50
MPPSET_X
MPPSET_Y
[5]
Preliminary
[4]
[3]
MPPSET_X
[2]
[1]
[0]
MPPSET_Y
Select the function for MPPDEC_X[3:0] pins.
Select the function for MPPDEC_Y[3:0] pins.
For the following 0~5 value, MPPDEC0 ~ MPPDEC3 data comes from VIN0 ~
VIN3 and for 6~F value, comes from CH0 ~ CH3.
0
1
2
Input Mode (default)
Horizontal sync
Vertical sync
3
4
5
6
Field flag
Video loss
Motion detection
Blind detection
7
8
9
A
B
Strobe acknowledge of display path
Strobe acknowledge of record path
Not supported
Not supported
LSB 4 bits of Channel ID information in record path for switch mode
C
[3:2] Stage of cascaded chips
[1:0] Video input path
MSB 4 bits of Channel ID information in record path for switch mode
[3] Channel ID Latch Enable Pulse
[2] New switching Information
D
E
F
[1] Switch mode for Field or Frame
[0] Analog Switch Path Information
Not supported
Channel Information of Queue in record path for switch mode
[3:2] Stage of cascaded chips
[1:0] Channel number
Encoder Timing
[3] HSENC
[2] VSENC
[1] FLDENC
[0]
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LINK
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
1x51
FRAME_OP
[7]
0
[6]
[5]
[4]
[3]
[2]
FRAME_OP
FRAME_
FLD
DIS_MODE
0
0
[1]
[0]
SIZE_MODE
Select the frame operation mode for record path.
0
1
DIS_MODE
Preliminary
Normal operation mode (Default)
Frame operation mode
Select the record mode depending on FRAME_OP.
When FRAME_OP = 0
0
1
Normal record mode (Default)
DVR normal record Mode
When FRAME_OP = 1
0
1
FRAME_FLD
Select the displayed field when FRAME_OP = “1”.
0
Odd field is displayed (default)
1
SIZE_MODE
Frame record mode
DVR frame record mode
Even field is displayed
Select the active pixel size per line
0
720 pixels (default)
1
704 pixels
2
3
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640 pixels
640 pixels
169
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Path
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Y
1x52
TBLINK
0
0
0
0
0
0
0
TBLINK
Control the blink period of channel boundary.
0
Blink for every 30 fields (default)
1
Blink for every 60 fields
Path
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Y
1x53
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
Techwell, Inc.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
Y
1x54
0
STRB_FLD
[4]
[3]
DUAL_PAGE
[2]
[1]
[0]
STRB_REQ
Capture first field of any field
Capture frame
Set dual page mode.
0
Normal strobe operation for each channel (default)
1
STRB_REQ
[5]
STRB_FLD
Control the field mode for strobe operation.
0
Capture odd field only (default)
1
Capture even field only
2
3
DUAL_PAGE
[6]
Preliminary
Enable the dual page operation
Request strobe operation.
STRB_REQ[3:0] represents the channel 3 to 0
0
1
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None operation (default)
Request to start strobe operation
171
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
1x55
[7]
[6]
NOVID_MODE
[5]
0
Preliminary
[4]
CH_START
[3]
[2]
0
MEM_OP_
_EN
[1]
[0]
INVALID_MODE
NOVID_MODE Select the indication method for no video detected channel
0
1
2
3
Bypass (default)
Capture last image
Blanked with blank color
Capture last image and blink channel boundary
CH_START
Enable the digital channel ID in horizontal boundary of channel
0
Disable the digital channel ID in horizontal boundary (default)
1
Enable the digital channel ID in horizontal boundary
MEM_OP_EN
Disable 4 channel record output mode
0
Enable 4 channel record output mode (default)
1
Disable 4 channel record output mode
INVALID_MODE No channel area indication
In horizontal and vertical active region
0
Background layer with background color (default)
1
Y = 0, Cb/Cr = 128
2
Y/Cb/Cr = 0
3
Y/Cb/Cr = 0
In horizontal and vertical blanking region
0
Y = 16, Cb/Cr = 128 (default)
1
Background layer with background color
2
Y = 0, Cb = {0, F, V, 0, Cascade, linenum[8:7]}, Cr = {0, linenum[6:0]}
3
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Y/Cb/Cr = 0
172
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
[7]
[6]
Preliminary
[5]
1x56 MUX_MODE TRIG_MODE
[4]
MUX_FLD
[3]
[2]
[1]
[0]
PIN_TRIG_MD
0
0
MUX_MODE
Define the switch mode.
0
Switch channel with still picture (default)
1
Switch channel with live picture
TRIG_MODE
Define the switch trigger mode.
0
MUX with external trigger from host (default)
1
MUX with internal trigger
MUX_FLD
Control the capturing field for switch operation.
0
Capture odd field only (default)
1
Capture even field only
2
Capture frame
3
Capture frame
PIN_TRIG_MD Select the triggering input when external trigger mode
0
Triggering by EXT_TRIG register
1
Triggering by positive edge of TRIGGER pin
2
3
Path
Index
[7]
Y
1x57
0
QUE_SIZE
Triggering by negative edge of TRIGGER pin
Triggering by both positive and negative edge of TRIGGER pin
[6]
[5]
[4]
[3]
[2]
[1]
[0]
QUE_SIZE
Define the actual using queue size.
0
Queue size = 1 (default)
:
:
127 Queue size = 128
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
[7]
[6]
[5]
1x58
1x59
Preliminary
[4]
[3]
[2]
[1]
[0]
QUE_PERIOD [7:0]
QUE_PERIOD [9:8]
EXT_TRIG INTR_REQY
MUX_WR_CH
QUE_PERIOD Trigger period for internal trigger mode.
0
:
1023
Trigger period = 1 field (default)
:
Trigger period = 1024 fields
EXT_TRIG
Make trigger when TRIG_MODE = “0”.
0
None operation (default)
1
Request to start MUX with external trigger mode
INTR_REQY
Request to start the switch operation with interrupt in record path
0
1
MUX_WR_CH
None operation (default)
Request to start the switch operation with interrupt
Channel number to be written in internal MUX queue or in interrupt trigger.
MUX_WR_CH[3:2] stands for stage of cascaded chips
0
1
2
3
Master chip (default)
1st slaver chip
2nd slaver chip
3rd slaver chip
MUX_WR_CH[1:0] stands for channel number
0
Channel 0 (default)
1
Channel 1
2
Channel 2
3
Channel 3
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
[7]
Y
1x5A
QUE_WR
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
QUE_WR
Control to write internal queue data.
0
None operation (default)
1
Request to start writing QUE_CH in internal queue of QUE_ADDR
QUE_ADDR
Define the queue address.
0
1st queue address (default)
:
:
127 128th queue address
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[0]
QUE_ADDR
175
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
1x5B
Y
[7]
[6]
0
Q_POS_RD
_CTL
[5]
Preliminary
[4]
Q_DATA_RD_CTL
[3]
1x5C
MUX_SKIP_CH[15:8]
1x5D
MUX_SKIP_CH[7:0]
Q_POS_RD_CTL
0
1
Q_DATA_RD_CTL
0
[2]
[1]
[0]
MUX_SKIP
QUE_CNT_ QUE_POS_
ACCU_TRIG
_EN
RST
RST
Control the read mode of the QUE_ADDR
Current queue address of internal queue (default)
Written value into the QUE_ADDR
Control the read mode of the MUX_WR_CH
Current queue data of internal queue (default)
1
Written value into the MUX_WR_CH
2,3 Queue data at the QUE_ADDR
MUX_SKIP_EN Enable the switch skip mode
0
Disable the switch skip mode
1
ACCU_TRIG
Enable the switch skip mode
Adjust the switch timing in external triggering via the TRIGGER pin
0
Output is delayed in 4 fields from triggering (default)
1
Output is matched with triggering
QUE_CNT_RST Reset the internal field counter to count queue period.
0
None operation (default)
1
Reset the field counter
QUE_POS_RST Reset the queue address.
0
None operation (default)
1
Reset the queue address and restart address
MUX_SKIP_CH Define the switch skip channel
MUX_SKIP_CH[15:0] stands for channel 15 ~ 0 including cascaded chip
0
Normal operation (default)
1
Skip channel
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Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
Y
1x5E
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
CHID_MUX_OUT *
Notes “*” stand for read only register
CHID_MUX_OUT
Channel ID of current field/frame in switch operation
CHID_MUX_OUT [7] represents the channel ID latch enable pulse
0->1
1->0
Rising edge for updating the channel ID
Falling edge after 16 clock * 18.5 ns from rising edge
CHID_MUX_OUT [6] represents Updated Picture in switch operation
0
No Updated
1
Updated by New Switching
CHID_MUX_OUT [5] represents the field mode in switch operation
0
Frame mode
1
Field mode
CHID_MUX_OUT [4] represents analog switching path
0
Analog switching 0 path
1
Analog switching 1 path
CHID_MUX_OUT [3:2] represents the stage of cascaded chip for switch
operation
0
Master chip
1
1st slaver chip
2
3
2nd slaver chip
3rd slaver chip
CHID_MUX_OUT [1:0] represents the channel number for switch operation
0
Channel 0
1
2
3
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Channel 1
Channel 2
Channel 3
177
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
Y
1x5F
FRZ_FLD
[7]
[5]
FRZ_FLD
[4]
[3]
BNDCOL
[2]
BGDCOL
[1]
[0]
BLKCOL
Select the image with freeze function or with last capture on video loss.
0
Last image
1
Last image of 1 field before
2
3
BNDCOL
[6]
Preliminary
Last image of 2 fields before (default)
Last image of 3 fields before
Define the boundary color of channel.
0
0% Black
1
25% Gray
2
75% Gray
3
100% White (default)
Channel boundary color is changed according to this value when boundary is
blinking.
0
100% White
1
100% White
2
0% Black
3
0% Black (default)
BGDCOL
Define the background color.
0
0% Black
1
40% Gray (default)
2
3
BLKCOL
75% Gray
Blue (100% Amplitude 100% Saturation)
Define the color for blanked channel.
0
0% Black
1
2
3
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40% Gray
75% Gray
Blue (100% Amplitude 100% Saturation) (default)
178
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
CH
Index
0
1x60
1
1x63
2
1x66
3
1x69
Y
CH_EN
CH_EN
POP_UP
[5]
[4]
[3]
[2]
[1]
[0]
FUNC_MODE
0
0
DEC_PATH_Y
Disable the channel (default)
Enable the channel
Enable pop-up.
0
Disable pop-up (default)
1
FUNC_MODE
[6]
Enable the channel.
0
1
POP_UP
[7]
Preliminary
Enable pop-up
Select the operation mode.
0
Live mode (default)
1
Strobe mode
2-3 Switch mode
DEC_PATH_Y Select the video input for each channel.
0
Video input from internal video decoder on VIN0 pins (default)
1
2
3
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Video input from internal video decoder on VIN1 pins
Video input from internal video decoder on VIN2 pins
Video input from internal video decoder on VIN3 pins
179
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
CH
Index
0
1x61
1
1x64
2
1x67
3
1x6A
Y
FREEZE
[5]
[4]
[3]
FREEZE H_MIRROR V_MIRROR ENHANCE
[2]
[1]
[0]
BLANK
BOUND
BLINK
Normal operation (default)
Enable the freeze function
Enable the horizontal mirroring function of main channel.
0
Normal operation (default)
1
V_MIRROR
0
[6]
Enable the freeze function of main channel.
0
1
H_MIRROR
[7]
Preliminary
Enable the horizontal mirroring function
Enable the vertical mirroring function of main channel.
0
Normal operation (default)
1
Enable the vertical mirroring function
ENHANCE
Enable the image enhancement function of main channel.
0
Normal operation (default)
1
Enable the image enhancement function
BLANK
Enable the blank of main channel.
0
Disable the blank (default)
1
Enable the blank
BOUND
Enable the channel boundary of main channel.
0
Disable the channel boundary
1
Enable the channel boundary (default)
BLINK
Enable the boundary blink of main channel when boundary is enabled.
0
1
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Disable the boundary blink (default)
Enable the boundary blink
180
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
CH
Index
0
1x62
1
1x65
2
1x68
3
1x6B
Preliminary
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
Path
Index
Y
1x6C
PIC_SIZE
[7]
[6]
PIC_SIZE3
[5]
[4]
PIC_SIZE2
[3]
[2]
PIC_SIZE1
[1]
[0]
PIC_SIZE0
Define the channel size when normal record mode or DVR normal record
mode
0
1
2
3
QUAD size
Full size for horizontal and Half size for vertical size
Half size for horizontal and Full size for vertical size
Full size
When Frame record mode or DVR frame record mode
0
CIF size (Half size for horizontal and Full size for vertical size)
1
Full size in frame record mode or DVR frame record mode
2/3 Not Available
Techwell, Inc.
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181
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
Y
1x6D
PIC_POS
[7]
[6]
PIC_POS3
[5]
Preliminary
[4]
[3]
PIC_POS2
[2]
[1]
PIC_POS1
[0]
PIC_POS0
Define the channel start position
When Normal record mode
0
No offset for both horizontal and vertical direction
1
2
3
Half offset for horizontal and no offset for vertical direction
No offset for horizontal and half offset for vertical direction
Half offset for horizontal and half offset for vertical direction
When Frame record mode
0
1
2
3
No offset for both horizontal and vertical direction
Half offset for horizontal and no offset for vertical direction
No offset for horizontal and field offset for vertical direction
Half offset for horizontal and field offset for vertical direction
When DVR normal record mode
0
No offset for both horizontal and vertical direction
1
1/4 Quarter offset for vertical direction
2
Half offset for vertical direction
3
3/4 Quarter offset for vertical direction
When DVR Frame record mode
0
No offset for both horizontal and vertical direction
1
Half offset for vertical direction
2
3
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Field offset for vertical direction
Field and half offset for vertical direction
182
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
1x6E
MUX_OUT_CH0 *
MUX_OUT_CH1 *
1x6F
MUX_OUT_CH2 *
MUX_OUT_CH3 *
[0]
MUX_OUT_CH0 Channel Information in current field/frame for switch operation
MUX_OUT_CH1 Channel Information in next field/frame for switch operation
MUX_OUT_CH2 Channel Information after 2 fields for switch operation
MUX_OUT_CH3 Channel Information after 3 fields for switch operation
MUX_OUT_CH [3:2] represents the stage of cascaded chips
0
1
2
3
Master chip (default)
1st slaver chip
2nd slaver chip
3rd slaver chip
MUX_OUT_CH [1:0] represents the channel number
0
Channel 0 (default)
1
Channel 1
2
Channel 2
3
Channel 3
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
[7]
1x70
POS_CTL
_EN
POS_CTL_EN
[5]
[4]
POS_TRIG
POS_TRIG POS_INTR
_MODE
[3]
[2]
0
POS_RD
_CTL
[1]
[0]
POS_DATA_RD_CTL
Enable the position/popup control
0
1
POS_TRIG_MODE
0
1
POS_TRIG
[6]
Preliminary
Disable the position/popup control (default)
Enable the position/popup control
Select the position/popup trigger mode
External trigger mode (default)
Internal trigger mode
Request the external trigger on external trigger mode
0
None Operation (default)
1
Request to start position/popup control in external trigger mode
POS_INTR
Request to start position/popup control with interrupt
0
None Operation (default)
1
Request to start position/popup control with interrupt
INTR_REQ
Request interrupt MUX
0
None operation (default)
1
Request to start MUX with interrupt
1
Request to start position/popup control with interrupt
POS_RD_CTL Control the read mode for the POS_QUE_ADDR
0
Current queue address for internal position/popup queue (default)
1
Written value into the POS_QUE_ADDR
POS_DATA_RD_CTL Control the read mode for the POS_CH
0
Current Queue Data for Internal Queue (default)
1
Written POS_CH value
2
Queue Data of the POS_QUE_ADDR
3
Queue Data of the POS_QUE_ADDR
Techwell, Inc.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Y
Index
1x71
[7]
[6]
[5]
POS_QUE_PER[9:8]
Preliminary
[4]
[3]
POS_FLD_
MD
1x72
[2]
[1]
[0]
[1]
[0]
POS_QUE_SIZE
POS_QUE_PER [7:0]
POS_QUE_SIZE
0
Select the position/popup queue size
Queue size = 1 (default)
:
:
Queue size = 32
31
POS_FLD_MD Select the position/popup queue period unit
0
Frame (default)
1
Field
POS_QUE_PER Trigger period for internal trigger mode.
0
Trigger period = 1 field or frame (default)
:
:
1023
Path
Y
Index
[7]
Trigger period = 1024 fields or frames
[6]
[5]
[4]
[3]
[2]
1x73
POS_CH0
POS_CH1
1x74
POS_CH2
POS_CH3
POS_CH
Define the channel for each region
POS_CH0 stands for No offset region of both H/V
POS_CH1 stands for half offset of H
POS_CH2 stands for half offset of V
POS_CH3 stands for half offset of both H/V
POS_CH [3:2] stands for the order of cascade chips
0
Master chip (default)
1
1st slaver chip
2
2nd slaver chip
3
3rd slaver chip
POS_CH [1:0] stands for the channel number
0
Channel 0 (default)
1
Channel 1
2
Channel 2
3
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Channel 3
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Path
Y
Index
[7]
[6]
[5]
1x75
POS_QUE
_WR
POS_CNT
_RST
POS_QUE
_RST
Preliminary
[4]
[3]
[2]
[1]
[0]
POS_QUE_ADDR
POS_QUE_WR Control to write internal position queue data
0
1
None operation (default)
Write data into the POS_CH register at the POS_QUE_ADDR
POS_CNT_RST Reset the internal field counter to count queue period for position queue.
0
None operation (default)
1
Reset the field counter
POS_QUE_RST Reset the queue address for position queue.
0
None operation (default)
1
POS_QUE_ADDR
0
31
Index
[7]
Reset the queue address and restart address
Define the queue address.
1st queue address (default)
:
:
32nd queue address
[6]
1x76
[5]
[4]
[3]
[2]
FLD_OP
[0]
DVR_IN
FLD_OP
Enable Field to Frame Conversion mode.
FLD_OP[3:0] stands for the channel 3 to channel 0
0
Normal operation (default)
1
Enable Field to Frame Conversion mode
DVR_IN
Enable DVR to Normal Conversion mode.
DVR_IN[3:0] stand for the channel 3 to channel 0
0
Normal operation (default)
1
[1]
DVR to Normal Conversion mode
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1x77
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
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TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1x78
0
0
0
0
0
IRQPOL
IRQRPT
0
IRQPOL
Select the IRQ polarity.
0
Active high (default)
1
Active low
IRQRPT
Select the IRQ mode.
IRQ pin maintains the state “1” until the interrupt request is cleared (default)
Interrupt request is repeated with 5msec period via IRQ pin when interrupt is
not cleared in long time.
Index
[7]
[6]
1x79
[5]
[4]
[3]
IRQENA_NOVID
[2]
[1]
[0]
IRQENA_MOTION
IRQENA_NOVIDInterrupt enable for corresponding video-loss detection.
IRQENA_NOVID[3:0] stand for VIN3 to VIN0.
0
Interrupt is disabled (default)
1
Interrupt is enabled
IRQENA_MOTION Interrupt enable for corresponding motion detection.
IRQENA_MOTION [3:0] stand for VIN3 to VIN0.
0
Interrupt is disabled (default)
1
Index
[7]
Interrupt is enabled
[6]
1x7A
[5]
[4]
[3]
IRQCLR_NOVID
[2]
[1]
[0]
IRQCLR_MDBD
IRQCLR_NOVID Setting “1” to clear interrupt request for corresponding video-loss detection.
This bit is cleared by itself in a few clocks after setting “1”.
IRQCLR_NOVID [3:0] stand for VIN3 to VIN0.
IRQCLR_MDBD Setting “1” to clear interrupt request for corresponding motion and blind
detection. This bit is cleared by itself in a few clocks after setting “1”.
IRQENA_MD_BD [3:0] stand for VIN3 to VIN0.
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1x7B
[5]
Preliminary
[4]
[3]
DET_NOVID *
[2]
[1]
[0]
DET_MOTION *
Notes “*” stand for read only register
DET_NOVID
Status of video loss detection.
DET_NOVID[3:0] stand for VIN3 to VIN0.
0
1
Video is alive
Video loss is detected
DET_MOTION Status of motion detection.
DET_MOTION[3:0] stand for VIN3 to VIN0.
0
1
Index
[7]
No motion
Motion is detected
[6]
1x7C
[5]
[4]
[3]
[2]
[1]
[0]
DET_BLIND *
IRQENA_BLIND
Notes “*” stand for read only register
IRQENA_BLIND Interrupt enable for corresponding blind detection.
IRQENA_BLIND[3:0] stand for VIN3 to VIN0.
0
Interrupt is disabled (default)
1
Interrupt is enabled
DET_BLIND
Status of blind detection.
DET_BLIND[3:0] stand for VIN3 to VIN0.
0
No blinded video
1
Blind video is detected
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1x7D
[6]
MCLK_FR_Y
MCLK_FR_X
MCLK_FR_Y
Preliminary
[5]
[4]
MCLK_PH_Y
0
[3]
[0]
0
[1]
[0]
27 MHz
27 MHz
27 MHz
MCLK_PH_X
Control the clock phase of the CLK54MEMX pin
MCLK_PH_Y
Control the clock phase of the CLK54MEMY pin
0
None operation (default)
1
Phase Inverting
[7]
[6]
1x7E
[5]
[4]
[3]
MCLKDEL_Y
MCLKDEL_X
MCLKDEL_Y
[1]
MCLK_PH_X
Control the clock frequency of the CLK54MEMX Pin
Control the clock frequency of the CLK54MEMY Pin
0
54 MHz (default)
1
2
3
Index
[2]
MCLK_FR_X
[2]
MCLKDEL_X
Control the clock delay of the CLK54MEMX pin
Control the clock delay of the CLK54MEMY pin
The delay can be controlled by 1ns.
The default value is 0.
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1x7F
MEM_INIT
0
1
0
0
0
0
1
MEM_INIT
Initialize operation mode of SDRAM.
This is cleared by itself after setting “1”.
0
None operation (default)
1
Request to start initializing operation mode of SDRAM
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
1x80
ENC_IN
[7]
[6]
ENC_IN_X
[4]
ENC_IN_Y
[3]
[2]
CCIR_IN_X
[1]
[0]
CCIR_IN_Y
Select the video data input of video encoder for analog output.
0
Display path video data without OSD and mouse overlay (default)
1
Display path video data with OSD and mouse overlay
2
3
CCIR_IN
[5]
Preliminary
Record path video data without OSD and mouse overlay
Record path video data with OSD and mouse overlay
Select the video data input of ITU-R BT 656 encoder for digital output.
0
Display path video data without OSD and mouse overlay (default)
1
2
3
Display path video data with OSD and mouse overlay
Record path video data without OSD and mouse overlay
Record path video data with OSD and mouse overlay
When realtime output mode for VDOUTY Pin (1x83, BYPASS_Y = 11b),
Select the video data output of VDOUTY Pin.
When Timing Multiplexed with 54MHz via CCIR_OUT_SEL_Y[1] = 1
0/1 Video Input 0/1
2/3 Video Input 2/3
When 27MHz output mode via CCIR_OUT_SEL_Y[1] = 0
0
Video Input 0
1
Video Input 1
2
Video Input 2
3
Video Input 3
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
1x81
DAC_PD_YX
DAC_OUT_YX
DAC_PD_CX
DAC_OUT_CX
1x82
DAC_PD_YY
DAC_OUT_YY
DAC_PD_CY
DAC_OUT_CY
DAC_PD
[6]
[4]
[3]
[2]
[1]
[0]
Enable the power down of DAC.
0
1
DAC_OUT
[5]
Normal operation (default)
Enable power down of DAC
Define the analog video format.
DAC_OUT[2] represents the selected path for output.
0
Display path (default)
1
Record path
DAC_OUT[1:0] represents the selected mode for output.
0
1
2
3
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No Output (default)
CVBS
Luminance
Chrominance
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1x83
0
CCIR_601
[5]
Preliminary
[4]
CCIR_OUT_X
[3]
[2]
BYPASS_Y
CCIR_601
Define the digital data output format.
0
ITU-R BT.656 mode (default)
1
ITU-R BT.601 mode
BYPASS_Y
Define the digital data output format for VDOUTY Pin.
0
Normal Operation (default)
1
Reserved
2
Reserved
3
CCIR_OUT
[1]
[0]
CCIR_OUT_Y
Decoder Data Bypass for Realtime Output
Define the mode of ITU-R BT.656 digital output.
The default value is “0” for CCIR_OUT_X, but “1” for CCIR_OUT_Y.
When ITU-R BT.656 is selected (CCIR_601 = 0)
0
Display path video data with single output mode (27MHz)
1
Record path video data with single output mode (27MHz)
2
Display and Record path video data with dual output mode (54MHz)
3
Record and Display path video data with dual output mode (54MHz)
When ITU-R BT.601 is selected (CCIR_601 = 1)
0
Display path video data with single output mode (13.5MHz)
1
Record path video data with single output mode (13.5MHz)
2
Dual output mode with Display and Record path video data (27MHz)
3
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Dual output mode with Record and Display path video data (27MHz)
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1x84
ENC_
MODE
ENC_MODE
[6]
CCIR_LMT
[2]
[1]
[0]
ENC_FLD
ENC_
HSPOL
ENC_
VSPOL
ENC_
FLDPOL
Slave mode operation (default)
Master mode operation
Data range is limited to 16 ~ 235 code
Define the vertical sync detection type.
0
Detect vertical sync from VSENC pin (default)
1
ENC_FLD
[3]
CCIR_
FLDPOL
Control the data range of ITU-R BT 656 output.
0
Data range is limited to 1 ~ 254 code (default)
1
ENC_VS
ENC_VS
[4]
Define the operation mode of video encoder.
0
1
CCIR_LMT
[5]
Preliminary
Detect vertical sync from combination of HSENC and FLDEN pins
Define the field polarity detection type
0
Detect field polarity from FLDENC pin (default)
1
Detect field polarity from combination of HSENC and VSENC pins
CCIR_FLDPOL Control the field polarity of ITU-R BT 656 output.
0
High for even field (default)
1
High for odd field
ENC_HSPOL
Control the horizontal sync polarity.
0
Active low (default)
1
Active high
ENC_VSPOL
Control the vertical sync polarity.
0
1
Active low (default)
Active high
ENC_FLDPOL Control the field polarity.
0
Even field is high (default)
1
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Odd field is high
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TW2834 Video Controller
Index
1x85
[7]
[6]
[5]
ENC_VSDEL
[3]
[2]
[1]
[0]
ENC_VSDEL
Compensate the field offset for first active video line.
0
Apply same ENC_VSDEL for odd and even field (default)
1
Apply {ENC_VSDEL+1} for odd and ENC_VSDEL for even field
2
3
Apply ENC_VSDEL for odd and {ENC_VSDEL +1} for even field
Apply ENC_VSDEL for odd and {ENC_VSDEL +2} for even field
Control the line delay of vertical sync from active video by 1 line/step.
0
No delayed
:
32
:
63
[7]
:
32 line delay (default)
:
63 line delay
[6]
[5]
ENC_HSDEL[1:0]
0
1x86
1x87
[4]
ENC_VSOFF
ENC_VSOFF
Index
Preliminary
[4]
[3]
[2]
[1]
[0]
ENC_HSDEL[9:2]
ENC_HSDEL
ACTIVE_VDEL
Control the pixel delay of horizontal sync from active video by 1/2 pixel/step.
0
No delayed
:
:
128 64 pixel delay (default)
:
:
1023255 pixel delay
ACTIVE_VDEL Control the line delay of active video by 1 line/step.
0
- 11 Lines delayed
:
:
12 0 Line delayed (default)
:
31
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:
+ 13 Lines delayed
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1x88
0
CCIR_STD
CCIR_STD
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
ACTIVE_HDEL
Select ITU-R BT656 standard format for 60Hz system.
0
240 line for odd and even field (Default)
1
244 line for odd and 243 line for even field (ITU-R BT.656 standard)
ACTIVE_HDEL Control the pixel delay of active video by 1 pixel/step.
0
- 32 Pixel delay
:
:
32
0 Pixel delay (default)
:
63
Index
[7]
1x89
:
+ 31 Pixel delay
[6]
ENC_FSC
ENC_FSC
[5]
[4]
[3]
[2]
[1]
[0]
0
0
1
ENC_
PHALT
ENC_
ALTRST
ENC_
PED
Set color sub-carrier frequency for video encoder.
0
3.57954545 MHz (default)
1
4.43361875 MHz
2
3.57561149 MHz
3
3.58205625 MHz
ENC_PHALT
Set phase alternation.
0
Disable phase alternation for line-by-line (default)
1
Enable phase alternation for line-by-line
ENC_ALTRST
Reset phase alternation for every 8 field
0
Disable phase alternation reset for every 8 field (default)
1
Enable phase alternation reset for every 8 field
ENC_PED
Set 7.5IRE for pedestal level
0
Disable 7.5 IRE for pedestal level
1
Enable 7.5 IRE for pedestal level (default)
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1x8A
[6]
ENC_CBW_X
ENC_CBW
ENC_YBW
[3]
[2]
[1]
ENC_CBW_Y
[0]
ENC_YBW_Y
1.35 MHz (default)
1.35 MHz
Control the luminance bandwidth of video encoder.
0
Narrow bandwidth
1
2
3
1x8B
[4]
ENC_YBW_X
Control the chrominance bandwidth of video encoder.
0
0.8 MHz
1
1.15 MHz
2
3
Index
[5]
Preliminary
[7]
0
Narrower bandwidth
Wide bandwidth (default)
Middle band width
[6]
[5]
[4]
0
ENC_
BAR_X
ENC_
CKILL_X
[3]
0
[2]
[1]
[0]
0
ENC_
BAR_Y
ENC_
CKILL_Y
ENC_BAR
Enable the test pattern output.
0
Normal operation (default)
1
Internal color bar with 100% amplitude 100 % saturation
ENC_CKILL
Enable the color killing function
0
Normal operation (default)
1
Color is killed
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1x8C
ENC_HS_
LINK
[6]
0
[5]
0
Preliminary
[4]
[3]
[2]
[1]
[0]
0
VDOUTY_
MODE
HOUT *
VOUT *
FOUT*
Notes “*” stand for read only register
ENC_HS_LINK Control the function of the HSENC pin.
0
Encoder Horizontal Sync (default)
1
Link pin for cascade connection
VDOUTY_MODE
0
1
Control the I/O direction of the VDOUTY pins.
Input mode for 4 ch playback input (default)
Output mode for normal application
HOUT
Horizontal sync for Encoder Timing
VOUT
FOUT
Vertical sync for Encoder Timing
Field polarity for Encoder Timing
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
1x8D
[7]
[6]
[5]
ECLK_FR_Y
ECLK_FR_X
ECLK_FR_Y
Preliminary
[4]
ECLK_PH_Y
[3]
[2]
[0]
ECLK_PH_X
Control the clock frequency of CLK27ENCX pin
Control the clock frequency of CLK27ENCY pin
0
54MHz
1
2
3
27MHz
27MHz
13.5MHz
ECLK_PH_X
Control the clock phase of CLK27ENCX pin
ECLK_PH_Y
Control the clock phase of CLK27ENCY pin
0
None operation (default)
1
None operation when clock frequency is not 13.5MHz
90 degree shift when clock frequency is 13.5MHz
2
3
Index
[1]
ECLK_FR_X
[7]
Phase Inverting
Phase Inverting when clock frequency is not 13.5MHz
270 degree shift when clock frequency is 13.5MHz
[6]
1x8E
[5]
[4]
[3]
ECLKDEL_Y
[1]
[0]
ECLKDEL_X
ECLKDEL_X
Control the clock delay of CLK27ENCX pin
ECLKDEL_Y
Control the clock delay of CLK27ENCY pin
The delay can be controlled by 1ns.
The default value is 0.
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[2]
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
Preliminary
[5]
[4]
[3]
1x90
FONT_WR_DATA[63:56]
1x91
FONT_WR_DATA[55:48]
1x92
FONT_WR_DATA[47:40]
1x93
FONT_WR_DATA[39:32]
1x94
FONT_WR_DATA[31:24]
1x95
FONT_WR_DATA[23:16]
1x96
FONT_WR_DATA[15:8]
1x97
FONT_WR_DATA[7:0]
FONT_WR_DATA
[2]
[1]
[0]
[2]
[1]
[0]
[2]
[1]
[0]
Font data for 1 line of 1 font.
The default value is 0.
Index
[7]
1x98
0
FONT_WR_INDEX
[6]
[5]
[4]
[3]
FONT_WR_INDEX
Define the font index.
0 Index 0 (default)
:
:
127 Index 127
Index
[7]
1x99
FONT_WR_PAGE
[6]
[5]
[4]
FONT_WR_PAGE
[3]
FONT_WR_LINE
Define the font page to be written.
0 Page 0 (default)
:
:
15 Page 15
FONT_WR_LINE
Define the font line to be written.
0 1st Line (default)
:
:
15 16th Line
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1x9A
FONT_
REQ_X
FONT_
REQ_Y
FONT_REQ
[5]
0
Preliminary
[4]
[3]
0
0
[2]
[1]
FONT_WR_TYPE
[0]
FONT_
WR_FLD
Request to start writing font into SDRAM.
This bit is cleared by itself after a few clocks.
0
None operation (default)
1
Request to start writing font
FONT_WR_TYPE
0
1
2
Select the font type to be written
128 index mode
85 index mode
64 index mode
FONT_WR_FLD Select the font field to be written.
0
Odd field (default)
1
Even field
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1x9B
CHAR_
PATH
CHAR_PATH
[6]
[4]
[3]
CHAR_WR_MODE
[2]
[1]
[0]
CHAR_VLOC
Select the path of the display RAM to write character attribute.
0
Write the display RAM of display path (default)
1
Write the display RAM of record path
CHAR_WR_MODE
0
1
2
3
CHAR_VLOC
[5]
Preliminary
Select the write mode of the display RAM.
Write Character Attribute
Write 1 Character Line Attribute
Write All Character Line Attribute
Write All Character Line Attribute
Define the vertical position of the displayed character.
0
1st character in the vertical direction (default)
:
:
28
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29th character in the vertical direction
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1x9C
[6]
0
0
0
[5]
Preliminary
[4]
[3]
CHAR_RD_FLD
CHAR_VF_SIZE
[2]
[1]
[0]
CHAR_RD_PAGE
CHAR_HF_SIZE
CHAR_HLOC
Notes 1. The property of 1x9C address depends on CHAR_WR_MODE value.
2. The data property of 1x9C depends on order of writing.
FONT_RD_FLD Define font field to be displayed
0
Character is not displayed (default)
1
2
3
FONT_RD_PAGE
0
15
Odd field font is used for both odd and even field
Even field font is used for both odd and even field
Both odd and even field font is used for frame display
Define the font page to be displayed
Page 0 (default)
:
:
Page 15
FONT_VF_SIZE Define the dot size of font for vertical direction
0
10 Line (default)
:
:
3
16 Line
FONT_HF_SIZE Define the horizontal pixel resolution and size of font
0
8 dots with 360 pixels resolution (default)
1
10 dots with 360 pixels resolution
2
12 dots with 360 pixels resolution
3
14 dots with 360 pixels resolution
CHAR_HLOC
4
5
6
7
8
16 dots with 360 pixels resolution
16 dots with 720 pixels resolution
20 dots with 720 pixels resolution
24 dots with 720 pixels resolution
28 dots with 720 pixels resolution
9-
32 dots with 720 pixels resolution
Define the horizontal position of displayed character.
0
1st character horizontally (default)
:
:
44
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45th character horizontally
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
[2]
1x9D
0
FONT
_TYPE
0
0
0
MIX
BLINK
[1]
[0]
CLASS3_COL
CHAR_INDEX
Notes 1. It should be written in pairs because the data of 1x9D consist of 2 bytes.
2. It is written into display RAM with CHAR_HLOC, CHAR_VLOC, and CHAR_PATH.
MIX
Enable the alpha blending
0
Disable the alpha blending
1
Enable the alpha blending with video data
BLINK
Enable the Blink
0
Disable the blink
1
Enable the blink
CLASS3_COL
Select the color of class3
0
1
2
3
CLASS3COL0 in register 1x89~1x8C
CLASS3COL1 in register 1x89~1x8C
CLASS3COL2 in register 1x89~1x8C
CLASS3COL3 in register 1x89~1x8C
FONT_TYPE
Select the font type
0
Character type
1
Bitmap type
CHAR_INDEX
Select the font index
0
1st index
:
:
127 128th index
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1xA0
RAMCLR
_X
RAMCLR
_Y
RAMCLR
[5]
Preliminary
[4]
BLK_TIME
[3]
[2]
[1]
[0]
CLASS0
ENA_X
CLASS0
ENA_Y
B_CLASS0
DIS_X
B_CLASS0
DIS_Y
Clear the display RAM.
This bit is cleared by itself after finishing display RAM clear.
0
None operation (default)
1
Request to start clearing display RAM
BLK_TIME
Select the blink period
0
1
2
3
CLASS0ENA
0.25 second (default)
0.5 second
1 sec
2 sec
Enable class 0 in character mode.
0
Disable class 0 (default)
1
Enable class 0
B_CLASS0DIS Disable class 0 in bitmap mode
0
Enable class 0 (default)
1
Disable class 0
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Path
Index
X
1xA1
Y
1xA3
CHAR_VSPC
[7]
[6]
[5]
Preliminary
[4]
[3]
CHAR_VSPC
[0]
CHAR_HSPC
No Space (default)
:
15 Lines space
CHAR_HSPC
Horizontal space in the displayed characters.
0
No space (default)
:
:
15 30 Pixels space
Path
Index
[7]
X
1xA2
Y
1xA4
[6]
[5]
[4]
[3]
CHAR_VDEL
[2]
[1]
[0]
CHAR_HDEL
Vertical offset to first displayed character.
0
No offset (default)
:
15
CHAR_HDEL
[1]
Vertical space in the displayed characters.
0
:
15
CHAR_VDEL
[2]
:
15 Lines offset
Horizontal offset to first displayed character.
0
No offset (default)
:
15
Techwell, Inc.
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:
30 Pixels offset
205
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1xA5
[5]
Preliminary
[4]
[3]
CHAR_MIX_C
CHAR_MIX_C
[1]
[0]
CHAR_MIX_B
Control the alpha blending mode with video data in character mode.
CHAR_MIX_C[3:0] stands for class 3 to 0.
0
Disable alpha blending function (default)
1
CHAR_MIX_B
[2]
Enable alpha blending function
Control the alpha blending mode with video data in bitmap mode.
CHAR_MIX_B[3:0] stands for class 3 to 0.
0
Disable alpha blending function (default)
1
Enable alpha blending function
The alpha blending Level is controlled via the ALPHA_OSD (1xBA) register.
Index
[7]
[6]
1xA6
CHAR_BLK_C
[4]
[3]
[2]
[1]
[0]
CHAR_BLK_B
Control the blink for character mode.
CHAR_BLK_C[3:0] stands for class 3 to 0.
0
1
CHAR_BLK_B
[5]
CHAR_BLK_C
Disable blink function (default)
Enable blink function
Control the blink for bitmap mode.
CHAR_BLK_B[3:0] stands for class 3 to 0.
0
1
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Disable blink function (default)
Enable blink function
206
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
1xA7
CLASS3COL1_C
CLASS 3COL0_C
1xA8
CLASS3COL3_C
CLASS 3COL2_C
1xA9
CLASS3COL1_B
CLASS 3COL0_B
1xAA
CLASS3COL3_B
CLASS 3COL2_B
1xAB
CLASS2COL_C
CLASS2COL_B
1xAC
CLASS1COL_C
CLASS1COL_B
1xAD
CLASS0COL_C
CLASS0COL_B
CLASS3COL0_C
CLASS3COL1_C
CLASS3COL2_C
CLASS3COL3_C
Color selection 0 of class 3 for character mode
Color selection 1 of class 3 for character mode
Color selection 2 of class 3 for character mode
Color selection 3 of class 3 for character mode
CLASS3COL0_B
CLASS3COL1_B
CLASS3COL2_B
CLASS3COL3_B
Color selection 0 of class 3 for bitmap mode
Color selection 1 of class 3 for bitmap mode
Color selection 2 of class 3 for bitmap mode
Color selection 3 of class 3 for bitmap mode
CLASS2COL_C
CLASS2COL_B
CLASS1COL_C
CLASS1COL_B
CLASS0COL_C
Color selection of class 2 for character mode
Color selection of class 2 for bitmap mode
Color selection of class 1 for character mode
Color selection of class 1 for bitmap mode
Color selection of class 0 for character mode
CLASS0COL_B
Color selection of class 0 for bitmap mode
Color selection table
0 White (75% Amplitude 100% Saturation) (default)
1 Yellow (75% Amplitude 100% Saturation)
2 Cyan (75 % Amplitude 100 Saturation)
3
4
5
6
7
Green (75% Amplitude 100% Saturation)
Magenta (75% Amplitude 100% Saturation)
Red (75% Amplitude 100% Saturation)
Blue (75% Amplitude 100% Saturation)
0% Black
8
9
10
11
12
100% White
50% Gray
25% Gray
Blue (75% Amplitude 75% Saturation)
Defined by CLUT0
[0]
13 Defined by CLUT1
14 Defined by CLUT2
15 Defined by CLUT3
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
1xAE
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
CLUT0_Y
1xAF
CLUT0_CB
1xB0
CLUT0_CR
1xB1
CLUT1_Y
1xB2
CLUT1_CB
1xB3
CLUT1_CR
1xB4
CLUT2_Y
1xB5
CLUT2_CB
1xB6
CLUT2_CR
1xB7
CLUT3_Y
1xB8
CLUT3_CB
1xB9
CLUT3_CR
CLUT0_Y
CLUT0_CB
Y component for user defined color 0 (default : 0)
Cb component for user defined color 0 (default : 0)
CLUT0_CR
CLUT1_Y
CLUT1_CB
CLUT1_CR
CLUT2_Y
Cr component for user defined color 0 (default : 0)
Y component for user defined color 1 (default : 0)
Cb component for user defined color 1 (default : 0)
Cr component for user defined color 1 (default : 0)
Y component for user defined color 2 (default : 0)
CLUT2_CB
CLUT2_CR
CLUT3_Y
CLUT3_CB
Cb component for user defined color 2 (default : 0)
Cr component for user defined color 2 (default : 0)
Y component for user defined color 3 (default : 0)
Cb component for user defined color 3 (default : 0)
CLUT3_CR
Cr component for user defined color 3 (default : 0)
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
1xBA
[7]
[6]
0
0
T_CASCADE_EN
0
1
ALPHA_OSD
[5]
0
Preliminary
[4]
[3]
[2]
0
T_CASCADE
_EN
0
[1]
[0]
ALPHA_OSD
Enable the infinity cascade mode for display path
Normal operation (default)
Enable the infinity cascade mode for display path
Select alpha blending mode for OSD
0
50% (default)
1
50%
2
75%
3
25%
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
1xBB
0
0
BYP_MPP
0
1
0
DEC_BYP_EN
BYP_MPP
[0]
Enable the decoder bypass mode using {MPPDEC_Y, MPPDEC_X}
0
Normal Operation (default)
1
Enable the decoder bypass mode using MPPDEC
DEC_BYP_EN Enable the decoder bypass mode using SDRAM interface of Y Path
0
Disable the decoder bypass mode (default)
1
Enable the decoder bypass mode with scaled display path
2
3
Enable the decoder bypass mode with scaled record path
Enable the decoder bypass mode with full D1
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1xBC
0
0
0
0
0
0
0
0
This is reserved register.
For normal operation, the above value should be set in this register.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
[2]
1xC0
0
0
0
VIS_RIC_EN
0
0
VIS_RIC_EN
Index
1xC1
[6]
VIS_ENA
VIS_EC
_EN
[5]
[4]
[3]
[2]
VIS_CODE
VIS_MIX_EN
_EN
[1]
[0]
VIS_SEL
Enable the Analog channel ID during vertical blanking interval
0
Disable the Analog channel ID (default)
1
VIS_EC_EN
[0]
0
Enable Run-in Clock of Analog channel ID during VBI
0
Disable Run-in Clock (default)
1
Enable Run-in Clock
[7]
VIS_ENA
[1]
Enable the Analog channel ID
Enable the error correction mode for Auto channel ID
0
Disable the error correction mode for Auto channel ID (default)
1
Enable the error correction mode for Auto channel ID
VIS_CODE_EN Enable the Digital channel ID during VBI
0
Disable the Digital channel ID (default)
1
Enable the Digital channel ID
VIS_MIX_EN
Select the Analog channel ID Format
0
Analog Channel ID Format 1 (default)
1
Analog Channel ID Format 2
VIS_SEL
Select the kind of channel ID when VIS_MIX_EN = 0
VIS_SEL[3] stand for 8th ~ 7th line among of 8 line with analog channel ID.
VIS_SEL[2] stand for 6th ~ 5th line among of 8 line with analog channel ID.
VIS_SEL[1] stand for 4th ~ 3rd line among of 8 line with analog channel ID.
VIS_SEL[0] stand for 2nd ~ 1st line among of 8 line with analog channel ID.
0
1
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Auto Channel ID
User Channel ID
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
1xC2
1xC3
Preliminary
[4]
[3]
[2]
[1]
[0]
VIS_H_OS
0
1xC4
0
0
VIS_PIXEL_WIDTH
VIS_LINE_WIDTH
VIS_LINE_OS
1xC5
VIS_HIGH_VAL
1xC6
VIS_LOW_VAL
VIS_H_OS
Horizontal start offset for Analog channel ID
0
No Offset (default)
:
:
255 255 pixels Offset
VIS_PIXEL_WIDTH Pixel width of each bit for Analog channel ID
0
1 pixel (default)
:
:
31
VIS_LINE_WIDTH
0
7
VIS_LINE_OS
32 pixels
Line width for Analog channel ID
1 line (default)
:
:
8 lines
Vertical start offset from field sync transition for Analog channel ID
0
No offset (default)
:
:
31
31 lines
VIS_HIGH_VAL Magnitude for bit “1” of Analog channel ID
VIS_LOW_VAL Magnitude for bit “0” of Analog channel ID
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1xC9
AUTO_VBI
_DET
[6]
[5]
Preliminary
[4]
[3]
[2]
VBI_CODE
VBI_EC_ON
VIS_RIC_ON VBI_MIX_ON VBI_FLT_EN
_EN
[1]
[0]
0
VBI_RD_CTL
AUTO_VBI_DET Select the Analog channel ID detection mode for playback input
0
1
VBI_EC_ON
Manual Analog channel ID detection mode (default)
Automatic Analog channel ID detection mode
Enable the error correction mode for Auto channel ID
0
Disable the error correction for Auto channel ID (default)
1
Enable the error correction for Auto channel ID
VBI_CODE_EN Enable the Digital channel ID detection mode for playback input
0
Disable the Digital channel ID detection mode (default)
1
Enable the Digital channel ID detection mode
VBI_RIC_ON
Select the Run-in clock mode for Analog channel ID
0
No Run-in Clock mode (default)
1
Run-in Clock mode
VBI_MIX_ON
Select the Analog channel ID format for playback input
0
Analog Channel ID format 1 (default)
1
Analog Channel ID format 2
VBI_FLT_EN
Select the filter mode for playback input
0
Bypass (default)
1
Enable the filter
VBI_RD_CTL
Control the read mode of channel ID for Channel ID CODEC
0
1
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Read the Written Data into VIS_MAN registers (1xD0 ~ 1xDF)
Read the encoded ID data from AUTO_CHID registers. (1xE0 ~ 1xE3)
Read the decoded ID data from VIS_MAN registers (1xD0 ~ 1xDF)
Read the decoded ID data from AUTO_CHID registers (1xE0 ~ 1xE3)
212
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Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
1xCA
1xCB
Preliminary
[4]
[3]
[2]
[1]
[0]
VBI_PIXEL_H_OS
VBI_FLD_OS
VBI_PIXEL_H_OS
VAV_CHK
VBI_PIXEL_HW
Horizontal start offset of Analog channel ID
When Manual Analog channel ID detection mode (AUTO_VBI_DET = 0)
0
No offset (Not supported in No Run-in Clock mode) (default)
:
:
255 255 pixel offset
When Auto Analog channel ID detection mode (AUTO_VBI_DET = 1)
This register notifies the detected horizontal start offset for Analog channel ID.
VBI_FLD_OS
Vertical start line offset of Analog channel ID for field polarity
0
1
2
3
VAV_CHK
Apply same VBI_LINE_OS to odd and even field (default)
Apply { VBI_LINE_OS +1} to odd and VBI_LINE_OS to even field
Apply VBI_LINE_OS to odd and {VBI_LINE_OS +1} to even field
Apply VBI_LINE_OS to odd and {VBI_LINE_OS +2} to even field
Enable the channel ID detection in vertical active period
0
Channel ID detection for VBI period only
1
Channel ID detection for VBI and vertical active period
VBI_PIXEL_HW Pixel width for each bit of Analog channel ID
0
:
31
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1 pixel (default)
:
32 pixels
213
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
1xCC
[6]
[5]
Preliminary
[4]
[3]
VBI_LINE_WIDTH
[2]
[1]
[0]
VBI_LINE_OS
1xCD
VBI_MID_VAL
1xCE
CHID_VALID *
1xCF
CHID_TYPE *
Notes “*” stand for read only register
VBI_LINE_WIDTH
Line width for Analog channel ID
When Manual Analog Channel ID detection mode (AUTO_VBI_DET = 0)
0
1 line (default)
:
:
7
8 lines
When Auto Analog channel ID detection mode (AUTO_VBI_DET = 1)
This register notifies the detected line width for Analog channel ID.
VBI_LINE_OS
Vertical start offset from field sync transition for Analog channel ID
0
No offset (default)
:
:
31 31 lines
VBI_MID_VAL
Threshold level to define bit “0” or bit “1” from Analog channel ID
CHID_VALID
Status of validity for detected channel ID
CHID_VALID[7:0] stand for 8th ~ 1st line from Analog channel ID
0
Not Valid
1
CHID_TYPE
Valid
Indicates the detected channel ID type
CHID_VALID[7:0] stand for 8th ~ 1st line from Analog channel ID
0
Auto Channel ID
1
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User Channel ID
214
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
1xD0
Preliminary
[4]
[3]
[2]
[1]
[0]
VIS_MAN0[15:8]
1xD1
VIS_MAN0[7:0]
1xD2
VIS_MAN1[15:8]
1xD3
VIS_MAN1[7:0]
1xD4
VIS_MAN2[15:8]
1xD5
VIS_MAN2[7:0]
1xD6
VIS_MAN3[15:8]
1xD7
VIS_MAN3[7:0]
1xD8
VIS_MAN4[15:8]
1xD9
VIS_MAN4[7:0]
1xDA
VIS_MAN5[15:8]
1xDB
VIS_MAN5[7:0]
1xDC
VIS_MAN6[15:8]
1xDD
VIS_MAN6[7:0]
1xDE
VIS_MAN7[15:8]
1xDF
VIS_MAN7[7:0]
1xE0
AUTO_CHID0
1xE1
AUTO_CHID1
1xE2
AUTO_CHID2
1xE3
AUTO_CHID3
Notes “*” stand for read only register
VIS_MAN
Define the User Channel ID for each line
VIS_MAN0 stand for the channel ID of 1st line for Channel ID
VIS_MAN1 stand for the channel ID of 2nd line for Channel ID
VIS_MAN2 stand for the channel ID of 3rd line for Channel ID
VIS_MAN3 stand for the channel ID of 4th line for Channel ID
VIS_MAN4 stand for the channel ID of 5th line for Channel ID
VIS_MAN5 stand for the channel ID of 6th line for Channel ID
VIS_MAN6 stand for the channel ID of 7th line for Channel ID
VIS_MAN7 stand for the channel ID of 8th line for Channel ID
Read mode depends on VBI_RD_CTL register
0
Written User Channel ID
1
AUTO_CHID
Decoded Channel ID
Auto Channel ID Data Information
For read mode, it depends on VBI_RD_CTL register
0
Encoded Auto Channel ID in record path
1
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Decoded Auto Channel ID from playback input
215
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
2x00
CUR_
ON_X
CUR_
ON_Y
CUR_
TYPE
CUR_
SUB
CUR_
BLINK
0
CUR_HP[0]
CUR_VP[0]
2x01
CUR_HP[8:1]
2x02
CUR_VP[8:1]
CUR_ON
Enable the mouse pointer.
0
1
CUR_TYPE
Disable mouse pointer (default)
Enable mouse pointer
Select the mouse type
0
Small mouse pointer (default)
1
Large mouse pointer
CUR_SUB
Control inside style of mouse pointer.
0
Transparent (default)
1
Filled with white color
CUR_BLINK
Enable blink of mouse pointer.
0
Disable blink (default)
1
Enable blink with 0.5 second period
CUR_HP
Horizontal location of mouse pointer.
0
0 Pixel position (default)
:
:
360 720 Pixels position
CUR_VP
Vertical location of mouse pointer.
0
0 Line position (default)
:
:
288 288 Line position
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Index
[7]
[6]
[5]
[4]
[3]
2x03
BOX_TYPE
BOX_EMP
0
0
ALPHA_2DBOX
BOX_TYPE
Select the single box type.
0
Flat type (default)
1
3D type
BOX_EMP
Enable the emphasis on box plane.
0
Disable the emphasis (default)
1
Enable the emphasis
[2]
[1]
[0]
ALPHA_BOX
ALPHA_2DBOX Select alpha blending mode for 2D Box
0 50% (default)
1 50%
2 75%
3
ALPHA_BOX
25%
Select alpha blending mode for Box
0 50% (default)
1 50%
2
3
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75%
25%
217
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
Preliminary
[4]
2x04
[3]
[2]
[1]
[0]
BOX_BNDCOL
BOX_BNDCOL Select the box boundary color as the following table
The default value is 0.
Control Register
Boundary
Color Description
BOX_TYPE BOX_OBND BOX_IBND
0
Outer
X
1
0
(Flat Type)
X
0
Inner
1
Left
0
X
&
1
0
Top
Outer
Right
&
Bottom
Left
1
(3D Type)
&
Top
1
1
0
X
1
0
1
1
0
0
1
0
1
1
Right
0
0
&
1
0
1
1
Inner
Bottom
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Register
BOX_
BNDCOL
[7:4]
BOX_
BNDCOL
[3:0]
BOX_
BNDCOL
[7:6]
BOX_
BNDCOL
[5:4]
BOX_
BNDCOL
[3:2]
BOX_
BNDCOL
[1:0]
218
Color
Outer Boundary off
0~10 : 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 IRE Gray
11~14 : User defined Color (1xAF ~ 1xB9)
15 : Same as plane color with 20IRE down of luminance
Inner Boundary off
0~10 : 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 IRE Gray
11~14 : User defined Color (1xAF ~ 1xB9).
15 : Same as plane color with 20IRE up of luminance
Boundary off
0~3 : 90, 80, 70, 60 IRE Gray
0~3 : 0, 10, 20, 30 IRE Gray
Boundary off
0~3 : 0, 10, 20, 30 IRE Gray
0~3 : 90, 80, 70, 60 IRE Gray
Boundary off
Same as inner area
0~3 : 30, 40, 50, 60 IRE Gray
Boundary off
0~3 : 30, 40, 50, 60 IRE Gray
0~3 : 70, 60, 50, 40 IRE Gray
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
2x05
BOX_PLNCOL1
BOX_PLNCOL0
2x06
BOX_PLNCOL3
BOX_PLNCOL2
2x07
BOX_PLNCOL5
BOX_PLNCOL4
2x08
BOX_PLNCOL7
BOX_PLNCOL6
2x09
BOX_PLNCOL9
BOX_PLNCOL8
2x0A
BOX_PLNCOLB
BOX_PLNCOLA
2x0B
BOX_PLNCOLD
BOX_PLNCOLC
2x0C
BOX_PLNCOLF
BOX_PLNCOLE
[0]
BOX_PLNCOL Define the box plane color for each box
“x” in the BOX_PLNCOLx stands for box number
Color selection table
0
White (75% Amplitude 100% Saturation) (default)
1
Yellow (75% Amplitude 100% Saturation)
2
3
4
5
6
Cyan (75 % Amplitude 100 Saturation)
Green (75% Amplitude 100% Saturation)
Magenta (75% Amplitude 100% Saturation)
Red (75% Amplitude 100% Saturation)
Blue (75% Amplitude 100% Saturation)
7
8
9
10
11
0% Black
100% White
50% Gray
25% Gray
Blue (75% Amplitude 75% Saturation)
12
13
14
15
Defined by CLUT0
Defined by CLUT1
Defined by CLUT2
Defined by CLUT3
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Box
Index
0
2x10
1
2x15
2
2x1A
3
2x1F
4
2x24
5
2x29
6
2x2E
7
2x33
8
2x38
9
2x3D
10
2x42
11
2x47
12
2x4C
13
2x51
14
2x56
15
2x5B
BOX_EN
[7]
[6]
[5]
[4]
[3]
[2]
BOX_
EN_X
BOX
_EN_Y
BOX_
OBND
BOX_
IBND
BOX_
PLNMIX
BOX_
PLN_EN
[0]
Enable the box
Enable the outer boundary.
Refer to the box boundary color in 2x04.
0
Disable (default)
1
BOX_IBND
[1]
Enable the box
0
Disable the box (default)
1
BOX_OBND
Preliminary
Enable
Enable the inner boundary.
Refer to the box boundary color in 2x04.
0
Disable the inner boundary (default)
1
Enable the inner boundary
BOX_PLNMIX
Enable alpha blending for box plane with video data.
0
Disable alpha blending (default)
1
Enable alpha blending with ALPHA_BOX register (2x03)
BOX_PLNEN
Enable the box plane
Refer to the box plane color in 2x05 ~ 2x0C.
0
Disable the box plane (default)
1
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Enable the box plane
220
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Box
Index
0
2x10
1
2x15
2
2x1A
3
2x1F
4
2x24
5
2x29
6
2x2E
7
2x33
8
2x38
9
2x3D
10
2x42
11
2x47
12
2x4C
13
2x51
14
2x56
15
2x5B
0
2x11
1
2x16
2
2x1B
3
2x20
4
2x25
5
2x2A
6
2x2F
7
2x34
8
2x39
9
2x3E
10
2x43
11
2x48
12
2x4D
13
2x52
14
2x57
15
2x5C
BOX_HL
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
BOX_
HL[0]
BOX_
HL[8:1]
Define the horizontal left location of box.
0
Left end (default)
:
:
360 Right end
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Box
Index
0
2x12
1
2x17
2
2x1B
3
2x21
4
2x26
5
2x2B
6
2x30
7
2x35
8
2x3A
9
2x3E
10
2x44
11
2x49
12
2x4E
13
2x53
14
2x58
15
2x5D
BOX_HW
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
BOX_HW
Define the horizontal size of box.
0
0 Pixel width (default)
:
:
180 720 Pixels width
Techwell, Inc.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Box
Index
0
2x10
1
2x15
2
2x1A
3
2x1F
4
2x24
5
2x29
6
2x2E
7
2x33
8
2x38
9
2x3D
10
2x42
11
2x47
12
2x4C
13
2x51
14
2x56
15
2x5B
0
2x13
1
2x18
2
2x1D
3
2x22
4
2x27
5
2x2C
6
2x31
7
2x36
8
2x3B
9
2x40
10
2x45
11
2x4A
12
2x4F
13
2x54
14
2x59
15
2x5E
BOX_VT
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
BOX_
VT[0]
BOX_
VT[8:1]
Define the vertical top location of box.
0
Vertical top (default)
:
:
288 Vertical bottom
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Box
Index
0
2x14
1
2x19
2
2x1E
3
2x23
4
2x28
5
2x2D
6
2x32
7
2x37
8
2x3C
9
2x41
10
2x46
11
2x4B
12
2x50
13
2x55
14
2x5A
15
2x5F
BOX_VW
[7]
[6]
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
BOX_VW
Define the vertical size of box.
0
0 Lines height (default)
:
:
144 288 Lines height
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
2DBox
Index
0
2x60
1
2x68
2
2x70
3
2x78
2DBOX_EN
Preliminary
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
2DBOX
_EN_X
2DBOX
_EN_Y
2DBOX
_MODE
2DBOX_
DETEN
2DBOX
_MSKEN
2DBOX
_MIX
2DBOX
_CUREN
2DBOX
_BNDEN
Enable the 2DBox
0
1
Disable the 2D box (default)
Enable the 2D box
2DBOX_MODE Define the operation mode of 2D arrayed box.
0
Table mode (default)
1
Motion display mode
2DBOX_DETEN Enable the detection plane of 2D arrayed box.
When 2DBOX_MODE = “0”
0
1
Disable the detection plane of 2D arrayed box (default)
Enable the detection plane of 2D arrayed box
When 2DBOX_MODE = “1”
0
Display the motion detection result with inner boundary
1
Display the motion detection result with plane
2DBOX_MSKEN Enable the mask plane of 2D arrayed box.
0
Disable the mask plane of 2D arrayed box (default)
1
Enable the mask plane of 2D arrayed box
2DBOX_MIX
Enable to alpha blending for 2D arrayed box plane with video data.
0
Disable to alpha blending (default)
1
Enable to alpha blending with ALPHA_2DBOX setting (2x03)
2DBOX_CUREN Enable the cursor cell inside 2D arrayed box.
0
Disable the cursor cell (default)
1
Enable the cursor cell
2DBOX_BNDEN Enable the boundary of 2D arrayed box.
0
1
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Disable the boundary (default)
Enable the boundary
225
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
2DBox
Index
0
2x61
1
2x69
2
2x71
3
2x79
[7]
[6]
[5]
Preliminary
[4]
2DBOX_PLNCOL
2DBOX_BNDCOL
0
1
2
3
[3]
[2]
[1]
[0]
2DBOX_BNDCOL
Define the color of 2D arrayed box boundary
0 % Black (default)
25% Gray
50% Gray
75% White
Define the displayed color for cursor cell and motion-detected region
0,1 75% White (default)
2,3 0% Black
2DBOX_PLNCOL
Define the color of 2D arrayed box plane.
Color selection table
0
White (75% Amplitude 100% Saturation) (default)
1
Yellow (75% Amplitude 100% Saturation)
2
3
4
5
6
Cyan (75 % Amplitude 100 Saturation)
Green (75% Amplitude 100% Saturation)
Magenta (75% Amplitude 100% Saturation)
Red (75% Amplitude 100% Saturation)
Blue (75% Amplitude 100% Saturation)
7
8
9
10
11
0% Black
100% White
50% Gray
25% Gray
Blue (75% Amplitude 75% Saturation)
12
13
14
15
Defined by CLUT0
Defined by CLUT1
Defined by CLUT2
Defined by CLUT3
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Datasheet Rev. 2.0
TW2834 Video Controller
2DBox
Index
0
2x61
1
2x69
2
2x71
3
2x79
0
2x62
1
2x69
2
2x70
3
2x77
2DBOX_HL
[7]
[6]
Preliminary
[5]
[4]
[3]
[2]
[1]
[0]
2DBOX_
HL[0]
2DBOX_HL[8:1]
Define the horizontal left location of 2D arrayed box.
0
Horizontal left end (default)
:
:
360 Horizontal right end
2DBox
Index
0
2x63
1
2x6B
2
2x73
3
2x7B
2DBOX_HW
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
2DBOX_HW
Define the horizontal size of 2D arrayed box.
0
0 Pixel width (default)
:
:
255 510 Pixels width
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
2DBox
Index
0
2x61
1
2x69
2
2x71
3
2x79
0
2x64
1
2x6C
2
2x74
3
2x7C
2DBOX_VT
[7]
[6]
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
2DBOX_
VT[0]
2DBOX_VT[8:1]
Define the vertical top location of 2D arrayed box.
0
Vertical top end (default)
:
:
240 Vertical bottom end for 60Hz system
:
:
288 Vertical bottom end for 50Hz system
2DBox
Index
0
2x65
1
2x6D
2
2x75
3
2x7D
2DBOX_VW
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
2DBOX_VW
Define the vertical size of 2D arrayed box.
0
0 Line height (default)
:
:
255 255 Lines height
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
2DBox
Index
0
2x66
1
2x6E
2
2x76
3
2x7E
[7]
[6]
[5]
Preliminary
[4]
[3]
2DBOX_HNUM
[2]
[1]
[0]
2DBOX_VNUM
2DBOX_VNUM Define the row number of 2D arrayed box.
For motion display mode, 11 is recommended.
0
1 Row
:
:
11 12 Row (default)
:
:
15
16 Rows
2DBOX_HNUM Define the column number of 2D arrayed box.
For motion display mode, 15 is recommended.
0
:
15
2DBox
Index
0
2x67
1
2x6F
2
2x77
3
2x7F
[7]
1 Column
:
16 Columns (default)
[6]
[5]
[4]
2DBOX_CURHP
[3]
[2]
[1]
[0]
2DBOX_CURVP
2DBOX_CURHP Define the horizontal location of cursor cell within 2DBOX_HNUM.
0
1st Column (default)
:
:
15 16th Column
2DBOX_CURVP Define the vertical location of cursor cell within 2DBOX_VNUM.
0
1st Row (default)
:
:
15
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16th Row
229
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
2x80
1
2xA0
2
2xC0
3
2xE0
MD_DIS
[7]
[6]
MD_DIS
MD
_REFFLD
[4]
[3]
[2]
BD_CELSENS
[1]
[0]
BD_LVSENS
Disable the motion and blind detection.
0
1
MD_REFFLD
[5]
Preliminary
Enable motion and blind detection (default)
Disable motion and blind detection
Control the updating time of reference field for motion detection.
0
Update reference field at every field (default)
1
Update reference field according to MD_SPEED
BD_CELSENS Define the threshold of cell for blind detection.
0
Low threshold (More sensitive) (default)
:
3
BD_LVSENS
:
High threshold (Less sensitive)
Define the threshold of level for blind detection.
0
Low threshold (More sensitive) (default)
:
15
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:
High threshold (Less sensitive)
230
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
2x81
1
2xA1
2
2xC1
3
2xE1
2DBOX_HINV
[7]
[6]
2DBOX
_HINV
2DBOX
_VINV
[3]
MD_FLD
[2]
[1]
[0]
MD_ALGIN
Normal operation (default)
Enable horizontal mirroring
Enable vertical mirroring
Select the field for motion detection.
0
Detecting motion for only odd field (default)
1
2
3
MD_ALGIN
[4]
Vertical mirroring for 2D arrayed box.
0
Normal operation (default)
1
MD_FLD
[5]
Horizontal mirroring for 2D arrayed box.
0
1
2DBOX_VINV
Preliminary
Detecting motion for only even field
Detecting motion for any field
Detecting motion for both odd and even field
Adjust the horizontal start position for motion detection.
0
:
15
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0 Pixel shift (default)
:
15 Pixels shift
231
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
2x82
1
2xA2
2
2xC2
3
2xE2
[7]
[6]
MD_CELSENS
[5]
Preliminary
[4]
[3]
MASK
_MODE
[2]
[1]
[0]
MD_LVSENS
MD_CELSENS Define the threshold of sub-cell number for motion detection.
0
1
2
3
Motion detected if 1 sub-cell has motion (More sensitive) (default)
Motion detected if 2 sub-cells have motion
Motion detected if 3 sub-cells have motion
Motion detected if 4 sub-cells have motion (Less sensitive)
MASK_MODE
Define the read mode of MD_MASK register.
0
Read the motion detection result (default)
1
Read the mask information
MD_LVSENS
Control the level sensitivity of motion detector.
0
More sensitive
:
:
8
Middle sensitive (default)
:
:
15
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Less sensitive
232
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
2x83
1
2xA3
2
2xC3
3
2xE3
[7]
[6]
MD_
STRB_EN
MD_STRB
[5]
Preliminary
[4]
[3]
[2]
[1]
[0]
MD_SPEED
MD_STRB_EN Select the motion detection mode
0
1
MD_STRB
Request to start motion detection on manual motion detection trigger
0
None Operation (default)
1
MD_SPEED
VIN
Index
0
2x84
1
2xA4
2
2xC4
3
2xE4
Automatic motion detection trigger
Manual motion detection trigger
Request to start for Motion Detection
Control the velocity of motion detector.
Large value is suitable for slow motion detection.
0
1
:
61
62
1 field/frame intervals (default)
2 field/frame intervals
:
62 field/frame intervals
63 field/frame intervals
63
Not supported
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
MD_DET_PERIOD
MD_DET_PERIOD
Control the Motion Monitoring Period for Motion Interrupt
0
1 field/frame intervals
:
:
255 256 field/frame intervals
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
VIN
Index
0
2x85
1
2xA5
2
2xC5
3
2xE5
[7]
[6]
[5]
Preliminary
[4]
[3]
MD_TMPSENS
[2]
[1]
[0]
MD_SPSENS
MD_TMPSENS Control the temporal sensitivity of motion detector.
0
:
15
MD_SPSENS
More Sensitive (default)
:
Less Sensitive
Control the spatial sensitivity of motion detector.
0
:
15
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More Sensitive (default)
:
Less Sensitive
234
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Row
1
Preliminary
Index
Motion Detection Mask Control for VIN
VIN0
VIN1
VIN2
VIN3
2x86
2xA6
2xC6
2xE6
2
2x88
2xA8
2xC8
2xE8
3
2x8A
2xAA
2xCA
2xEA
4
2x8C
2xAC
2xCC
2xEC
5
2x8E
2xAE
2xCE
2xEE
6
2x90
2xB0
2xD0
2xF0
7
2x92
2xB2
2xD2
2xF2
8
2x94
2xB4
2xD4
2xF4
9
2x96
2xB6
2xD6
2xF6
10
2x98
2xB8
2xD8
2xF8
11
2x9A
2xBA
2xDA
2xFA
12
2x9C
2xBC
2xDC
2xFC
1
2x87
2xA7
2xC7
2xE7
2
2x89
2xA9
2xC9
2xE9
3
2x8B
2xAB
2xCB
2xEB
4
2x8D
2xAD
2xCD
2xED
5
2x8F
2xAF
2xCF
2xEF
6
2x91
2xB1
2xD1
2xF1
7
2x93
2xB3
2xD3
2xF3
8
2x95
2xB5
2xD5
2xF5
9
2x97
2xB7
2xD7
2xF7
10
2x99
2xB9
2xD9
2xF9
11
2x9B
2xBB
2xDB
2xFB
12
2x9D
2xBD
2xDD
2xFD
MD_MASK
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
MD_MASK[15:8]
MD_MASK[7:0]
Motion Mask/Detection Cell for VIN
MD_MASK[15] is right end and MD_MASK[0] is left end of column.
Writing mode
0
1
Non-masking cell for motion detection (default)
Masking cell for motion detection
Reading mode when MASK_MODE = “0”
0
Motion is not detected for cell
1
Motion is detected for cell
Reading mode when MASK_MODE = “1”
0
Non-masked cell
1
Masked cell
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Index
2x9E
[7]
[6]
MD_PATH
MD_PATH
0
[4]
0
DETAREA
_EN
[3]
[2]
[1]
[0]
DETCOL_SEL
Display path
Record path
Enable the different color for detection plane of 2D arrayed Box
0
Same as plane color (default)
1
DETCOL_SEL
[5]
Select the path to store motion detection information
0
1
DETCOL_EN
Preliminary
Different color with the DETCOL_SEL register
Select the color for detection plane when DETCOL_EN = 1
Color selection table
0
White (75% Amplitude 100% Saturation) (default)
1
Yellow (75% Amplitude 100% Saturation)
2
Cyan (75 % Amplitude 100 Saturation)
3
Green (75% Amplitude 100% Saturation)
4
5
6
7
8
Magenta (75% Amplitude 100% Saturation)
Red (75% Amplitude 100% Saturation)
Blue (75% Amplitude 100% Saturation)
0% Black
100% White
9
10
11
12
13
50% Gray
25% Gray
Blue (75% Amplitude 75% Saturation)
Defined by CLUT0
Defined by CLUT1
14
15
Defined by CLUT2
Defined by CLUT3
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Parametric Information
DC Electrical Parameters
Parameter
Table 11 Absolute Maximum Ratings
Symbol
Min
Typ
Max
Units
V
VDDADC (measured to VSSADC)
VDDADCM
3.5
VDDDAC (measured to VSSDAC)
VDDDACM
3.5
V
VDDI (measured to VSSI)
VDDIM
3.5
V
VDDO (measured to VSSO)
VDDOM
4.6
V
Voltage on Any Digital Data Pin
(See the note below)
-
VSSO–0.5
6.0
V
Analog Input Voltage for ADC
-
VDDADCM–
0.5
VDDADCM+0.5
V
VDDDACM–
0.5
VDDDACM+0.5
V
TS
– 65
150
°C
TJ
0
125
°C
220
°C
Analog Input Voltage for DAC
Storage Temperature
Junction Temperature
Vapor Phase Soldering (15 Seconds)
TVSOL
NOTE: Long-term exposure to absolute maximum ratings may affect device reliability, and
permanent damage may occur if operate exceeding the rating. The device should be
operated under recommended operating condition.
Table 12 Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
VDDADC (measured to VSSADC)
VDDADC
2.25
2.5
2.75
V
VDDDAC (measured to VSSDAC)
VDDDAC
2.25
2.5
2.75
V
VDDI (measured to VSSI)
VDDI
2.25
2.5
2.75
V
VDDO (measured to VSSO)
VDDO
3.0
3.3
3.6
V
Maximum |VDDI – VDDADC|
0.3
V
Maximum |VDDI – VDDDAC|
0.3
V
Maximum |VDDADC – VDDDAC|
0.3
V
Maximum |VDDO – VDDADC|
1.05
V
Maximum |VDDO – VDDDAC|
1.05
V
Maximum |VDDO – VDDI|
1.05
V
2.0
V
70
°C
Analog VIN Amplitude Range
(AC coupling required)
Ambient Operating Temperature
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0.5
TA
237
0
1.0
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Parameter
Preliminary
Table 13 DC Characteristics
Symbol
Min
Typ
Max
Units
Digital Inputs
Input High Voltage (TTL)
VIH
2.0
5.5
V
Input Low Voltage (TTL)
VIL
-0.3
0.8
V
Input Leakage Current
(@VI=2.5V or 0V)
IL
±1
µA
Input Capacitance
CIN
6
pF
Digital Outputs
Output High Voltage
VOH
Output Low Voltage
VOL
High Level Output Current
(@VOH=2.4V)
IOH
5.7
Low Level Output Current
(@VOL=0.4V)
IOL
4.1
Tri-state Output Leakage Current
(@VO=2.5V or 0V)
IOZ
Output Capacitance
CO
6
pF
CA
6
pF
Analog Pin Input Capacitance
2.4
V
0.4
V
11.6
18.6
mA
6.7
8.2
mA
±1
µA
Table 14 Supply Current and Power Dissipation
Parameter
Symbol
Min
Typ
Max
Units
IDDA
200
220
mA
Digital Internal Supply Current (2.5V)
IDDI
640
700
mA
Digital I/O Supply Current (3.3V)
IDDO
27
30
mA
Total Power Dissipation
Pd
2.2
2.4
W
Analog Supply Current (2.5V)
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Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
AC Electrical Parameters
Parameter
Table 15 Clock Timing Parameters
Symbol
Min
Typ
Delay from CLK54I to CLK27ENC
Hold from CLK27ENC (27MHz) to Data
Delay from CLK27ENC (27MHz) to Data
Hold from CLK54I to Data
Delay from CLK54I to Data
Setup from PBIN to PBCLK
Hold from PBCLK to PBIN
1
2a
2b
3a
3b
4a
4b
4.7
17
Max
Units
12.5
ns
ns
ns
ns
ns
ns
ns
21
8
12
5
5
Note : Cload = 25pF.
C LK 54 I
1
C LK 27 E N C
(2 7 M H z)
2b
2a
D a ta O u tpu t
(A ) 2 7 M H z O u tpu t M o d e
C LK 54 I
1
C LK 27 E N C
(5 4 M H z)
3b
3a
D a ta O u tpu t
(B ) 5 4 M H z O u tpu t M o d e
PBCLK
4a
4b
P B _ IN
(C ) P BC LK In p u t T im in g
Fig 78 Clock Timing Diagram
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Table 16. Serial Interface Timing
Symbol
Min
Parameter
Bus Free Time between STOP and START
Typ
Max
Units
tBF
1.3
us
SDAT setup time
tsSDAT
100
ns
SDAT hold time
thSDAT
0
0.9
us
Setup time for START condition
tsSTA
0.6
us
Setup time for STOP condition
tsSTOP
0.6
us
Hold time for START condition
thSTA
0.6
Rise time for SCLK and SDAT
tR
Fall time for SCLK and SDAT
us
300
ns
tF
300
ns
Capacitive load for each bus line
CBUS
400
pF
SCLK clock frequency
fSCLK
400
KHz
Stop
Start
Start
SDA
Stop
Data
tBF
tR
tsSDAT
tF
tsSTA
thSTA
tsSTO
thSDAT
SCL
Fig 79. Serial Interface Timing Diagram
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240
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Table 17 Parallel Interface Timing Parameter
Parameter
Symbol
Min
CSB setup until AEN active
Tsu(1)
10
ns
PDATA setup until AEN,WENB active
Tsu(2)
10
ns
AEN, WENB, RENB active pulse width
Tw
40
ns
CSB hold after WENB, RENB inactive
Th(1)
60
ns
PDATA hold after AEN,WENB inactive
Th(2)
20
ns
PDATA delay after RENB active
Td(1)
PDATA delay after RENB inactive
Td(2)
60
ns
Tcs
60
ns
Trd
60
ns
CSB inactive pulse width
RENB active delay after AEN inactive
RENB active delay after RENB inactive
Typ
Max
Units
12
ns
CSB
Tsu(1)
Tw
Tw
Th(1)
Tcs
WENB
RENB
Tw
AEN
Index Address
PDATA
Tsu(2)
Write
Th(2)
Tsu(2)
Write
Th(2)
Tsu(2)
Th(2)
Fig 80 Write timing of parallel interface with auto index increment mode
CSB
Tsu(1)
Tcs
WENB
Tw
Tw
RENB
Tw
Trd
Th(1)
Trd
AEN
Index Address
PDATA
Tsu(2)
Th(2)
Read
Td(1)
Td(2)
Read
Td(1)
Td(2)
Fig 81 Read timing of parallel interface with auto index increment mode
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241
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Parameter
Preliminary
Table 18.Analog Performance Parameter
Symbol
Min
Typ
Max
Units
ADC characteristics
Differential gain
DGA
3
%
Differential phase
DpA
2
deg
Channel Cross-talk
αctA
-50
dB
Differential gain
DGD
3
%
Differential phase
DpD
2
deg
Channel Cross-talk
αctA
-50
dB
Max
Units
±6
%
DAC characteristic
Parameter
Table 19.Decoder Performance Parameter
Symbol
Min
Typ
Horizontal PLL permissible static deviation
∆fH
Color Sub-carrier PLL lock in range
∆fSC
±800
Video level tracking range
AGC
-6
18
dB
Hz
Color level tracking range
ACC
-6
30
dB
Oscillator Input
Nominal frequency
Permissible frequency deviation
Duty cycle
Techwell, Inc.
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fOSC
54
MHz
∆fOSC/fOSC
±100
ppm
dtOSC
60
%
242
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Application Schematic
VDD33
VDDAADC
220uF
C201
0.1uF
C100
C101
C102
C103
C104
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
BEAD
+ C108
47uF
Place near each device power pin(0.1uF Cap.)
VDD25
VDD25
2.5V
2.5V
BEAD
+ C202
220uF
C203
0.1uF
C105
C106
C107
0.1uF
0.1uF
0.1uF
VDD25_INT
L109
BEAD
+ C120
47uF
Place near each device power pin(0.1uF Cap.)
C1 2.2uF
C6
175
75
C4 2.2uF
181
C8
0.1uF
2
R4
75
J9
RCA JACK
1
C9
18pF
L9
1.8uH
C10
179
183
C11
330pF
R5
J10
RCA JACK
1
330pF
C12
18pF
L10
1.8uH
C13
187
189
L11
75
330F
18pF
0.1uF
L21 1uH
C21
R9
0.1uF
1.8uH
190
680
191
C22
0.1uF
192
R10
680
193
L20 1uH
C23
C17
188
196
199
1
17
28
44
73
57
84
100
113
132
140
156
13
32
52
65
92
105
125
144
161
204
VIN1A
VIN1B
VIN2A
DQMX
VIN2B
DATAX[15]
DATAX[14]
DATAX[13]
DATAX[12]
DATAX[11]
DATAX[10]
DATAX[9]
DATAX[8]
DATAX[7]
DATAX[6]
DATAX[5]
DATAX[4]
DATAX[3]
DATAX[2]
DATAX[1]
DATAX[0]
VIN3A
VIN3B
VIN4A
VIN4B
(208QFP)
VAOUTCX
VAOUTYX
194
COMPX
ISETX
VREF
L12
1.8uH
197
75
C20
R8
330pF
75
11
12
14
15
16
18
19
20
2
C19
195
330pF
CCIR 656 Output
for Display
CCIR 656 Output
for Record
VAOUTCY
R7
VDOUTX[7:0]
CLK27ENCX
22
201
202
203
205
206
207
2
3
VDOUTY[7:0]
CLK27ENCY
4
VDD33
OSC1
1
4
NC
VCC
DIP8
GND
OUT
OSC 54MHz
RESETn
8
5
7
10
8
6
72
164
166
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VAOUTYY
VDOUTX[7]
VDOUTX[6]
VDOUTX[5]
VDOUTX[4]
VDOUTX[3]
VDOUTX[2]
VDOUTX[1]
VDOUTX[0]
BA0Y
ADDRY[10]/AP
ADDRY[9]
ADDRY[8]
ADDRY[7]
ADDRY[6]
ADDRY[5]
ADDRY[4]
ADDRY[3]
ADDRY[2]
ADDRY[1]
ADDRY[0]
NMIRQ
MPPDECY[3]
MPPDECY[2]
MPPDECY[1]
MPPDECY[0]
CLK27ENCX
VDOUTY[7]
VDOUTY[6]
VDOUTY[5]
VDOUTY[4]
VDOUTY[3]
VDOUTY[2]
VDOUTY[1]
VDOUTY[0]
MPPDECX[3]
MPPDECX[2]
MPPDECX[1]
MPPDECX[0]
HSPB
CLK27ENCY
HCSB1
HCSB0
HSENC
VSENC
FLDENC
LINK
HALE
HRDB
HWRB
CLK54I
RSTB
TEST
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
VSSI
18pF
5
21
36
48
61
77
80
96
109
121
136
152
157
208
C18
RASBY
CASBY
WEBY
DATAY[15]
DATAY[14]
DATAY[13]
DATAY[12]
DATAY[11]
DATAY[10]
DATAY[9]
DATAY[8]
DATAY[7]
DATAY[6]
DATAY[5]
DATAY[4]
DATAY[3]
DATAY[2]
DATAY[1]
DATAY[0]
COMPY
185
186 VSSADAC
198 VSSADAC
VSSADAC
J12
RCA JACK
1
330pF
CLK54MEMY
DQMY
ISETY
170
174 VSSAADC
178 VSSAADC
182 VSSAADC
184 VSSAADC
VSSAADC
330pF
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
167
168
172
176
180
ADDRX[12]
ADDRX[11]
ADDRX[10]/AP
ADDRX[9]
ADDRX[8]
ADDRX[7]
ADDRX[6]
ADDRX[5]
ADDRX[4]
ADDRX[3]
ADDRX[2]
ADDRX[1]
ADDRX[0]
2
C16
BA1X
BA0X
R6
VDDADAC
C15
J11
RCA JACK
1
RASBX
CASBX
WEBX
75
C14
330pF
CLK54MEMX
PBIN[7]
PBIN[6]
PBIN[5]
PBIN[4]
PBIN[3]
PBIN[2]
PBIN[1]
PBIN[0]
TW2834
2
VIN4A
177
0.1uF
2
VIN3A
C3 2.2uF
C7
PBCLK
0.1uF
75
R3
TRIGGER
243
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
R2
2
VAOUTCX
171
173
2
VIN2A
C2 2.2uF
J7 RCA JACK
1
VAOUTYX
0.1uF
VDD33_IO
HDAT[7]
HDAT[6]
HDAT[5]
HDAT[4]
HDAT[3]
HDAT[2]
HDAT[1]
HDAT[0]
49
43
45
46
41
42
23
24
26
27
29
30
31
33
34
35
37
38
39
47
50
51
54
55
56
58
59
60
62
63
64
66
67
68
70
71
95
90
91
93
89
74
75
76
78
79
81
82
83
85
86
87
94
97
98
99
101
102
103
106
107
108
110
111
112
114
115
116
118
138
149
147
146
145
143
142
141
139
119
122
120
123
124
126
127
128
130
131
133
134
135
137
CLK54MEMX
RASBX
CASBX
WEBX
BA1X
BA0X
ADDRX[12:0]
DQMX
DATAX[15:0]
CLK54MEMY
RASBY
CASBY
WEBY
BA0Y
ADDRY[10:0]
DQMY
DATAY[15:0]
NMIRQ
MPPDECX[3]
MPPDECX[2]
MPPDECX[1]
MPPDECX[0]
MPPDECY[3]
MPPDECY[2]
MPPDECY[1]
MPPDECY[0]
HSPB
HCSB1
HCSB1
HALE
HRDB
HWRB
HDAT[7:0]
9
25
40
53
69
88
104
117
129
148
165
200
C5
75
J5 RCA JACK
1
VAOUTCY
169
R1
J3 RCA JACK
1
VAOUTYY
163
162
160
159
158
155
154
153
2
VIN1A
J1 RCA JACK
1
151
PBCLK
PBIN[7:0]
VDD25_INT
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
TRIGGER
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Place near each device power pin(0.1uF Cap.)
VDDADAC
VDDADAC
VDDADAC
VDDADAC
150
C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133
VDDAADC
VDDAADC
VDDAADC
VDDAADC
VDDAADC
VDDAADC
U1
CCIR 656 Inpuy
for Playback
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Place near each device power pin(0.1uF Cap.)
VDDADAC
L105
C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119
X Path SDRAM
Interface
+ C200
Y Path SDRAM
Interface
BEAD
VDD33_IO
L108
3.3V
Multi-purpose
Interface
L100
Micom
Interface
VDD25
2.5V
Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Package Dimension
Techwell, Inc.
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Jun, 28, 2005
Datasheet Rev. 2.0
TW2834 Video Controller
Preliminary
Revision History
Table 20 Datasheet Revision History
Product
Code
Revision
Date
Description
1.0
Mar. 04, 2005
Preliminary Specification Release
BAPA2-GE
2.0
Jun. 20. 2005
Rev C. Specification Release
BAPA3-GE
Table 21. List of Revision Point in TW2834 RevC
No.
Issue
TW2834 RevB
TW2834 RevC
1
Switching Queue
Limited switching channel order in
switching queue for 16 channel
cascade application
Free switching channel order in
switching queue for 16 channel
cascade application
2
Quad MUX
Supports Quad MUX by frame unit
Supports Quad MUX by field unit
(Page 72, 73, 153, 185)
3
Alpha Blending
Supports only half-tone
Supports the alpha blending with 25%,
50% and 75% level
(Page 84, 86, 88, 209, 217)
4
Vertical Active Line
Supports fixed 240 lines for ITU-R
BT.656 output in 60Hz system
Also supports 244 lines in odd field and
243 in even field for ITU-R BT. 656
standard in 60Hz system.
(Page 95, 195)
5
Memory Clock
Frequency
Supports only 54MHz
Supports both 54MHz and 27MHz
(Page 189)
6
Channel ID
Decoding
Supported only in VBI Period
Supported in both VBI and Vertical
active period (Page 25, 213)
7
Playback Stop
No stop mode for auto strobe in
playback input
Supports stop mode for auto strobe in
playback input (Page 59, 165)
8
Variable 656 Data
Parsing for
Playback Input
Supports fixed ITU-R BT.656 data
parsing for playback input
Supports variable ITU-R BT.656 data
parsing for playback input
(Page 145)
9
Independent
Scaling Filter and
Sync Control for
Playback Path
Controlled by the scaling filter and
sync control register of VIN path
Controlled by the independent scaling
filter and sync control register of
Playback path
(Page 136,137,138,139)
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Datasheet Rev. 2.0