ETC TW2802

TW2802/4 Multiple Video Decoder
For Security Applications
Preliminary Data Sheet from Techwell, Inc.
Information may change without notice
Disclaimer
This document provides technical information for the user. Techwell Inc. reserves the right to
modify the information in this document as necessary. The customer should make sure that
they have the most recent data sheet version. Techwell Inc. holds no responsibility for any
errors that may appear in this document. Customers should take appropriate action to ensure
their use of the products does not infringe upon any patents. Techwell Inc. respects valid
patent rights of third parties and does not infringe upon or assist others to infringe upon such
rights.
Techwell, Inc.
www.techwellinc.com
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Table of Contents
Introduction and Features ______________3
Features ___________________________3
Applications _______________________3
Block Diagram _____________________4
Pin Diagram _______________________5
Pin Description _____________________5
Analog Interface Pins _______________5
Digital Data Interface Pins ___________6
System Control Pins ________________7
Power/Ground Pins_________________7
Functional Description _________________8
Video Input Formats ________________8
Analog-to-Digital Converter __________8
Sync Processing ____________________9
Video Level Adjustment ____________9
Horizontal Sync Processing __________9
Vertical Sync Processing ____________9
Color Decoding ____________________10
Decimation Filter _________________10
Y/C Separation ___________________11
TMPSENS (Temporal Sensitivity) ____ 20
Velocity Control _________________ 21
Mask Detection Region____________ 22
Output Format ___________________ 23
ITU-R BT.656 Format ____________ 23
8-bit ITU-R BT.601 Format ________ 24
Dual ITU-R BT.656 Format in 54MHz 25
Host Interface ______________________ 26
Serial Interface ___________________ 26
Parallel Interface _________________ 27
Interrupt Interface ________________ 28
Control Register __________________
Register Map____________________
Recommended Value _____________
Register Description ______________
29
29
31
33
Parametric Information_______________ 71
DC Electrical Parameters___________ 71
AC Electrical Parameters___________ 73
Package Dimension __________________ 75
Application Information ______________ 77
Luminance Processing ______________12
Video Input Interface ______________ 77
Chrominance Processing ____________13
Chrominance Demodulation_________13
ACC (Automatic Color gain control) __14
Clamping / AGC __________________ 77
Chrominance Gain, Offset and Hue
Adjustment ______________________14
Power-Up ________________________ 77
Video Scaling and Cropping _________15
Video Scaling ____________________15
Video Output Interface ____________ 77
Application Schematic ________________ 78
Revision History_____________________ 79
Video Cropping __________________18
Motion Detector ___________________20
Sensitivity Control ________________20
LVLSENS (Level Sensitivity) ________20
SPTSENS (Spatial Sensitivity) _______20
Techwell, Inc.
www.techwellinc.com
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Introduction and Features
The TW280X includes four high quality
NTSC/ PAL video decoders, which convert
analog composite to digital component
YCbCr for security application. The TW280X
contains four 10-bit A/D and proprietary
digital gain/clamp controllers and utilizes
proprietary techniques for separating luminance & chrominance to reduce both crossluminance and cross-chrominance artifacts.
The high performance dual scalers in each
channel offer two differently scaled video
outputs with 54MHz ITU-R BT.656 format
−
Four 10-bit video CMOS analog to
digital converters
−
Proprietary architecture for locking to
weak, noisy, or unstable signals
−
High performance adaptive comb filters
for all NTSC/PAL standards
−
IF compensation filter for improvement
of color demodulation
−
PAL delay lines for correcting PAL
phase errors
−
−
−
Supports two differently scaled output
mode with 54MHz ITU-R BT.656 format
−
Supports a two-wire serial or parallel
interface
−
Low power consumption
−
128 PQFP package
VIN1A
MUX
ADC
VIN1B
Motion Detector
VIN2A
MUX
ADC
VIN2B
Motion Detector
VIN3A
MUX
ADC
VIN3B
Motion Detector
VIN4A
MUX
ADC
VIN4B
Programmable hue, saturation, contrast,
brightness and sharpness
Motion Detector
HSPB
HCSB
HALE
HRDB
HWRH
HDAT
Dual high quality horizontal and vertical
down scaler for each channel
Techwell, Inc.
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Supports the standard ITU-R BT.656 /
8bit ITU-R BT.601 format
Device Options
Device Name Features
TW2802
2 Channel Video Decoder
TW2804
4 Channel Video Decoder
Adjust video level with proprietary
automatic clamp and gain control
system
−
−
Security systems
Features
Accepts all NTSC (M/N/4.43) / PAL
(B/D/G/H/I/K/L/M/N/60) standard
formats with auto detection
Four built-in motion detectors for
security system
Applications
for security system design. Four built-in
motion detectors can also increase the
feature of security system.
−
−
Host Interface
IRQ
3
Color Decoder
with
Comb Filter
H/V Scaler
VD1[7:0]
VALID1
H/V Scaler
H/V Sync Processor
Color Decoder
with
Comb Filter
H/V Scaler
VD2[7:0]
VALID2
H/V Scaler
H/V Sync Processor
Color Decoder
with
Comb Filter
HS2
VS2
FLD2
ACTIV2
NVMD2
H/V Scaler
VD3[7:0]
VALID3
H/V Scaler
H/V Sync Processor
Color Decoder
with
Comb Filter
HS1
VS1
FLD1
ACTIV1
NVMD1
HS3
VS3
FLD3
ACTIV3
NVMD3
H/V Scaler
VD4[7:0]
VALID4
H/V Scaler
H/V Sync Processor
Clock Generator
HS4
VS4
FLD4
ACTIV4
NVMD4
CLK27O
CLK54I
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Block Diagram
VIN1A
MUX
ADC
VIN1B
Color Decoder
with
Comb Filter
MUX
ADC
VIN2B
Color Decoder
with
Comb Filter
MUX
ADC
VIN3B
Color Decoder
with
Comb Filter
MUX
ADC
VIN4B
Color Decoder
with
Comb Filter
HSPB
HCSB
HALE
HRDB
HWRH
HDAT
Host Interface
H/V Scaler
HS2
VS2
FLD2
ACTIV2
NVMD2
H/V Scaler
VD3[7:0]
VALID3
H/V Scaler
HS3
VS3
FLD3
ACTIV3
NVMD3
H/V Scaler
VD4[7:0]
VALID4
H/V Scaler
Clock Generator
IRQ
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VD2[7:0]
VALID2
H/V Sync Processor
Motion Detector
HS1
VS1
FLD1
ACTIV1
NVMD1
H/V Scaler
H/V Sync Processor
Motion Detector
VIN4A
H/V Scaler
H/V Sync Processor
Motion Detector
VIN3A
VD1[7:0]
VALID1
H/V Sync Processor
Motion Detector
VIN2A
H/V Scaler
HS4
VS4
FLD4
ACTIV4
NVMD4
CLK27O
CLK54I
4
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
TW280X
(128QFP)
Analog Pin
(4 ADC)
VD3[1]
VSS
VD3[2]
VD3[3]
VDD
VD3[4]
VD3[5]
VSS
VD3[6]
VD3[7]
VSS
VALID3
ACTIVE3
VSS
HS3
VS3
VDD
FLD3
NVMD3
VDDO
VD2[0]
VD2[1]
VSS
VD2[2]
VD2[3]
VSS
TEST
RSTB
VSS
NVMD1
FLD1
VDDO
VS1
HS1
VDD
ACTIVE1
VALID1
VSS
VD1[7]
VD1[6]
VSS
VD1[5]
VD1[4]
VSS
VD1[3]
VD1[2]
VDD
VD1[1]
VD1[0]
VDDO
NVMD2
FLD2
VSS
VS2
HS2
VSS
ACTIVE2
VALID2
VDD
VD2[7]
VD2[6]
VSS
VD2[5]
VD2[4]
IRQ
HWRB
VDDO
HRDB
HALE
VSS
HCSB
HSPB
VDDAD
VDDA
VIN1A
VIN1B
VSSA
VSSA
VIN2A
VIN2B
VDDA
VDDA
VIN3A
VIN3B
VSSA
VSSA
VIN4A
VIN4B
VDDA
VSSAD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VDD
HDAT[0]
HDAT[1]
VSS
HDAT[2]
HDAT[3]
VSS
HDAT[4]
HDAT[5]
VSS
HDAT[6]
HDAT[7]
VDD
CLK54I
CLK27O
VSS
VD4[0]
VD4[1]
VDDO
VD4[2]
VD4[3]
VSS
VD4[4]
VD4[5]
VSS
VD4[6]
VD4[7]
VSS
VALID4
ACTIVE4
VDD
HS4
VS4
VSS
FLD4
NVMD4
VDDO
VD3[0]
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Pin Diagram
Pin Description
Analog Interface Pins
Name
Number
Type
VIN1A
113
A
VIN1B
114
A
VIN2A
117
A
VIN2B
118
A
VIN3A
121
A
VIN3B
122
A
VIN4A
125
A
VIN4B
126
A
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Description
Composite video input A of Channel 1.
Must be connected through 2.2uF cap to input.
Composite video input B of Channel 1.
Must be connected through 2.2uF cap to input.
Composite video input A of Channel 2.
Must be connected through 2.2uF cap to input.
Composite video input B of Channel 2.
Must be connected through 2.2uF cap to input.
Composite video input A of Channel 3.
Must be connected through 2.2uF cap to input.
Composite video input B of Channel 3.
Must be connected through 2.2uF cap to input.
Composite video input A of Channel 4.
Must be connected through 2.2uF cap to input.
Composite video input B of Channel 4.
Must be connected through 2.2uF cap to input.
5
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Digital Data Interface Pins
Name
Number
13,14,16,17,
VD1 [7:0]
19,20,22,23
34,35,37,38,
VD2 [7:0]
40,41,43,44
55,56,58,59,
VD3 [7:0] *
61,62,64,65
76,77,79,80,
VD4 [7:0] *
82,83,85,86
VALID1
11
VALID2
32
VALID3*
53
VALID4*
74
HS1
8
HS2
29
HS3*
50
HS4*
71
VS1
7
VS2
28
VS3*
49
VS4*
70
FLD1
5
FLD2
26
FLD3*
47
FLD4*
68
ACTIVE1
10
ACTIVE2
31
ACTIVE3*
52
ACTIVE4*
73
NVMD1
4
NVMD2
25
NVMD3*
46
NVMD4*
67
Notes: * Disabled for TW2802
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Type
Preliminary
Description
O
Dual scaled video data output for channel 1.
O
Dual scaled video data output for channel 2.
O
Dual scaled video data output for channel 3.
O
Dual scaled video data output for channel 4.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Valid data indicator for channel 1.
Valid data indicator for channel 2.
Valid data indicator for channel 3.
Valid data indicator for channel 4.
Horizontal sync output for channel 1.
Horizontal sync output for channel 2.
Horizontal sync output for channel 3.
Horizontal sync output for channel 4.
Vertical sync output for channel 1.
Vertical sync output for channel 2.
Vertical sync output for channel 3.
Vertical sync output for channel 4.
Even/odd field flag output for channel 1.
Even/odd field flag output for channel 2.
Even/odd field flag output for channel 3.
Even/odd field flag output for channel 4.
Active flag output for channel 1.
Active flag output for channel 2.
Active flag output for channel 3.
Active flag output for channel 4.
Video loss or Motion detection flag for channel 1.
Video loss or Motion detection flag for channel 2.
Video loss or Motion detection flag for channel 3.
Video loss or Motion detection flag for channel 4.
6
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
System Control Pins
Name
Number
RSTB
2
CLK54I
89
CLK27O
88
TEST
1
HSPB
110
Type
I
I
O
I
I
HCSB
109
I
HALE
107
I
HRDB
106
I
HWRB
104
I
HDAT [7:0]
91,92,94,95,
97,98,100,101
I/O
IRQ
103
O
Power/Ground Pins
Name
Number
9,21,33,48,60,
VDD
72,90,102
6,24,45,
VDDO
66,84,105
3,12,15,18, 27,
30,36,39,42,51,
54,57,63,69,75,
VSS
78,81,87,93,96,
99,108
VDDA
112,119,120,127
VSSA
115,116,123,124
VDDAD
111
VSSAD
128
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Preliminary
Description
System reset.
54MHz system clock input.
27MHz Clock output.
Test pin. Connect to ground.
Select Serial/Parallel host interface.
Chip select for parallel interface.
Slaver address [0] for serial interface.
Address line enable for parallel interface.
Serial clock for serial interface.
Read enable for parallel interface.
Ground for serial interface.
Write enable for parallel interface.
Ground for serial interface.
Data bus for parallel interface.
HDAT [7] is serial data for serial interface.
HDAT [6:1] is slaver address [6:1] for serial
interface. HCSB is slaver address [0].
Interrupt request by video loss and Motion
detection
Type
Description
P
Digital power for internal logic. 2.5V.
P
Digital power for output driver. 3.3V.
G
Digital ground.
P
G
P
G
Analog power. 2.5V.
Analog ground.
Analog digital power. 2.5V.
Analog digital ground.
7
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Functional Description
Video Input Formats
The TW280X supports all NTSC/PAL standard formats and has built-in automatic standard
detection circuit. The following Table 1 shows the identified standards. Automatic standard
detection can be overridden by writing the value into the IFMTMAN and IFORMAT register
(0x01, 0x41, 0x81, 0xC1). Even in no-video status, the device can be forced to free-run in a
particular video standard mode for fast locking by programming IFORMAT register.
Table 1 Input Video Format Supported
Format
Line/Fv (Hz)
Fh (KHz)
Fsc (MHz)
NTSC-M*
NTSC-J
525/59.94
15.734
3.579545
NTSC-4.43*
525/59.94
15.734
4.43361875
NTSC-N
625/50
15.625
3.579545
PAL-BDGHI
PAL-N*
625/50
15.625
4.43361875
PAL-M*
525/59.94
15.734
3.57561149
PAL-NC
625/50
15.625
3.58205625
PAL-60
525/59.94
15.734
4.43361875
Notes: * 7.5 IRE Setup
Analog-to-Digital Converter
The TW280X contains four 10-bit Analog to Digital converters that digitizes the analog video
inputs. As the inputs are digitized at greater than two times that of the Nyquist sampling rate,
only simple external anti-aliasing LPF are needed to prevent out-of-band frequencies. Each
ADC has two analog switches that are controlled by ANA_SW (0x22, 0x62, 0xA2, 0xE2)
registers. The A/D converters can also be put into power-down mode by the ADC_PWDN
(0x78) registers.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Sync Processing
The sync processor of TW280X detects horizontal synchronization and vertical synchronization
signals in the composite. The TW280X utilizes proprietary technology for locking to weak, noisy,
or unstable signals such as those from on air signal and fast forward or backward of VCR
system.
Video Level Adjustment
A patented digital gain and clamp control circuit restores the ac coupled video signal to a fixed
dc level. The clamping circuit provides line-by-line restoration of the video pedestal level to a
fixed dc reference voltage. In no AGC mode, the gain control circuit adjusts only the video sync
gain to achieve desired sync amplitude so that the active video is bypassed regardless of the
gain control. But when AGC mode is enabled, both active video and sync are adjusted by the
gain control. The range of AGC is from –6dB to 18dB approximately.
Horizontal Sync Processing
The horizontal synchronization processing contains a sync separator, a PLL and the related
decision logic. The horizontal sync separator detects the horizontal sync by examining low-pass
filtered video input whose level is lower than a threshold. Additional logic is also used to avoid
false detection on glitches. The horizontal PLL locks onto the extracted horizontal sync in all
conditions to provide jitter free image output. In case the horizontal sync is missing, the PLL is
on free running status that matches the standard raster frequency.
Vertical Sync Processing
The vertical sync separator detects the vertical synchronization pattern in the input video
signals. The field status is determined at vertical synchronization time. When the location of the
detected vertical sync is inline with a horizontal sync, it indicates a frame start or the odd field
start. Otherwise, it indicates an even field.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Color Decoding
Decimation Filter
The digitized composite video data at 2X pixel clock rate first passes through decimation filter.
The decimation filter is required to achieve optimum performance and prevent high frequency
components from being aliased back into the video image. Fig 1 shows the characteristic of the
decimation filter.
0
Magnitude Response (dB)
-10
-20
-30
-40
-50
-60
0
2
4
6
8
Frequency (Hertz)
10
12
x 10
6
Fig 1 The Characteristic of the Decimation Filter
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10
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Y/C Separation
The adaptive comb filter is used for high quality luminance/chrominance separation from
NTSC/PAL composite video signals. The comb filter improves the luminance resolution and
reduces noise such as cross-luminance and cross-color. The adaptive algorithm eliminates
most of errors without introducing new artifacts or noise. To accommodate some viewing
preferences, additional chrominance trap filters are also available in the luminance path. Fig. 2
and Fig 3 show the frequency response of notch filter for each system NTSC and PAL.
0
Magnitude Response (dB)
-10
-20
-30
-40
-50
-60
0
1
2
3
Frequency (Hertz)
4
5
6
x 10
6
Fig. 2 The Characteristics of Luminance Notch Filter for NTSC
0
Magnitude Response (dB)
-10
-20
-30
-40
-50
-60
0
1
2
3
Frequency (Hertz)
4
5
6
x 10
6
Fig 3 The Characteristics of Luminance Notch Filter for PAL
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11
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Luminance Processing
The luminance signal is separated by adaptive comb or trap filter is then fed to a peaking circuit.
The peaking filter enhances the high frequency components of the luminance signal. Fig. 4
shows the characteristics of the peaking filter for four different gain modes. The picture contrast
and brightness adjustment is provided through CONT (0x11, 0x51, 0x91, 0xD1) and BRT (0x12,
0x52, 0x92, 0xD2) registers. The contrast adjustment range is from approximately 0 to 200
percent, and the brightness adjustment is in the range of ±25 IRE. Moreover, a high frequency
coring function is also embedded in TW280X to minimize a high frequency noise. The coring
level is adjustable through the Y_H_CORE (0xF8) register.
6
Manitude Response (dB)
5
4
3
2
1
0
0
1
2
3
4
Frequency (Hertz)
5
6
x 10
6
Fig. 4. The Characteristic of Luminance Peaking filter
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Chrominance Processing
Chrominance Demodulation
The chrominance demodulation is done by first quadrature mixing for NTSC and PAL. The
mixing frequency is equal to the sub-carrier frequency of NTSC and PAL. After the mixing, a
LPF is used to remove 2X carrier signal and yield chrominance components. The LPF
characteristic can be selected for optimized transient color performance. In case of a mistuned
IF source, IF compensation filter makes up for any attenuation at higher frequencies or
asymmetry around the color sub-carrier. The gain for the upper chrominance side band is
controlled by IFCMP_MD (0x13, 0x53, 0x93, 0xD3) register. Fig. 5 and Fig. 6 show the
frequency response of IF-compensation filter and chrominance LPF.
10
Magnitude Response (dB)
5
0
-5
-10
-15
1.5
2
2.5
3
3.5
4
Frequency (Hertz)
4.5
5
5.5
x 10
6
Fig. 5 The Characteristics of IF-compensation Filter
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
-45
0
0.5
1
1.5
2
2.5
Frequency (Hertz)
3
3.5
4
x 10
6
Fig. 6 The Characteristics of Chrominance Low Pass Filter
ACC (Automatic Color gain control)
The ACC (Automatic Color gain Control) compensates for reduced amplitudes caused by high
frequency suppression in video signal. The range of ACC is from –6dB to 30dB approximately.
For black & white video or very weak & noisy signals, the color will be off by the internal color
killing circuit. The color killer function can also be always enabled or disabled by programming
CKIL (0x14, 0x54, 0x94, 0xD4) register.
Chrominance Gain, Offset and Hue Adjustment
The color saturation can be adjusted by changing the register SAT (0x10, 0x50, 0x90, 0xD0).
The Cb and Cr gain can be also adjusted independently by programming UGAIN (0x3C) and
VGAIN (0x3D) register. Likewise, the Cb and Cr offset can be programmed through U_OFF
(0x3E) and V_OFF (0x3F) registers. Hue control is achieved with phase shift of the digitally
controlled oscillator. The phase shift can be programmed through HUE (0x0F, 0x4F, 0x8F,
0xCF) register.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Video Scaling and Cropping
The TW280X provides two methods to reduce the amount of video pixel data, scaling and
cropping. The scaling function provides video image at lower resolution while the cropping
function supplies only a portion of the video image.
Video Scaling
The TW280X includes a high quality horizontal and vertical down scaler. The video images can
be downscaled in both horizontal and vertical direction to an arbitrary size. The luminance
horizontal scaler includes an anti-aliasing filter to reduce image artifacts in the resized image
and a 32 poly-phase filter to accurately interpolate the value of a pixel. This results in more
aesthetically pleasing video as well as higher compression ratios in bandwidth-limited
applications. Fig 7 shows the frequency response of anti-aliasing filter for horizontal scaling and
Fig 8 shows the 32 poly-phase filter characteristics. Similarly, the vertical scaler also contains
an anti-aliasing filter and 16 poly-phase filter for down scaling. The filter characteristics are
shown in Fig. 9.
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
-45
0
1
2
3
4
Frequency (Hertz)
5
6
x 10
6
Fig 7 The Characteristics of Anti-aliasing filter for horizontal luminance scaling
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
0.5
0.4
Magnitude Response (dB)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.5
1
1.5
2
2.5
3
Frequency (Hertz)
3.5
4
4.5
5
x 10
6
Fig 8 The Characteristics of Group delay for horizontal luminance scaling
0
-5
Magnitude Response (dB)
-10
-15
-20
-25
-30
-35
-40
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Vertical Frequency/Line Rate
0.4
0.45
0.5
Fig. 9 The Characteristics of Anti-aliasing filter for vertical luminance scaling
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Down scaling is achieved by programming the horizontal scaling register (HSCALE) and vertical
scaling register (VSCALE). When no scaled video image, the TW280X will output the number of
pixels per line as specified by the HACTIVE register. If the number of output pixels required is
smaller than the number specified by the HACTIVE register, the 16bit HSCALE register is used
to reduce the output pixels to the desired number.
Following equation is used to determine the horizontal scaling ratio to be written into the 16bit
HSCALE register.
HSCALE = [Npixel_desired/ HACTIVE] * (2^16 – 1)
Where Npixel_desired is the desired number of active pixels per line
For example, to scale full picture (HACTIVE is 720) to CIF (360 pixels), the HSCALE value can
be found as:
HSCALE = [320/720] * (2^16 – 1) = 0x7FFF
Following equation is used to determine the vertical scaling ratio to be written into the 16bit
VSCALE register.
VSCALE = [Nline_desired / VACTIVE] * (2^16 - 1)
Where Nline_desired is the desired number of active lines per field
For example, to scale full picture (VACTIVE is 240or288) to CIF (120/144 lines), the VSCALE
value can be found as:
VSCALE = [120 / 240] * (2^16 – 1) = 0x7FFF for 60Hz
VSCALE = [144 / 288] * (2^16 – 1) = 0x7FFF for 50Hz
The scaling ratios of popular case are listed in Table 2
Table 2 HSCALE and VSCALE value for some popular video formats
Scaling
Output
Format
HSCALE
VSCALE
Ratio
Resolution
NTSC
720x480
0xFFFF
0xFFFF
1
PAL
720x576
0xFFFF
0xFFFF
NTSC
360x240
0x7FFF
0x7FFF
1/2 (CIF)
PAL
360x288
0x7FFF
0x7FFF
NTSC
180x120
0x3FFF
0x3FFF
1/4 (QCIF)
PAL
180x144
0x3FFF
0x3FFF
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Video Cropping
The cropping function allows only subsection of a video image to be output. The active video
region is determined by HDELAY, HACTIVE, VDELAY and VACTIVE register as illustrated in
Fig 10. The first active line is defined by the VDELAY register and the first active pixel is defined
by the HDELAY register. The VACTIVE register can be programmed to define the number of
active lines in a video field, and the HACTIVE register can be programmed to define the number
of active pixels in a video line.
The horizontal delay register HDELAY determines the number of pixel delays between the
horizontal reference and the leading edge of the active region. The horizontal active register
HACTIVE determines the number of active pixels to be processed. Note that these values are
referenced to the pixel number before scaling. Therefore, even if the scaling ratio is changed,
the active video region used for scaling remains unchanged as set by the HDEALY and
HACTIVE register. In order for the cropping to work properly, the following equation should be
satisfied.
HDELAY + HACTIVE < Total number of pixels per line
Where the total number of pixels per line is 858 for 60Hz and 864 for 50Hz
To process full size region, the HDELAY should be set to 32 and HACTIVE set to 720 for both
60Hz and 50Hz system.
The vertical delay register (VDELAY) determines the number of line delays from the vertical
reference to the start of the active video lines. The vertical active register (VACTIVE)
determines the number of lines to be processed. These values are referenced to the incoming
scan lines before the vertical scaling. In order for the vertical cropping to work properly, the
following equation should be satisfied.
VDELAY + VACTIVE < Total number of lines per field
Where the total number of lines per field is 262 for 60Hz and 312 for 50Hz
To process full size region, the VDELAY should be set to 7 and VACTIVE set to 240 for 60Hz
and the VDELAY should be also set to 4 and VACTIVE set to 288 for 50Hz.
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
VDELAY
VACTIVE
V reference
Preliminary
HDELAY
HACTIVE
VACTIVE * VSCALE
VACTIVE
V reference
VDELAY
H reference
HACTIVE * HSCALE
HDELAY
Cropping and Scaling
HACTIVE
H reference
Fig 10 The Effect of Cropping and Scaling Active Registers
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Motion Detector
The TW280X supports hardware motion detector for 4 channels individually. The motion
detection algorithm built in the TW280X uses difference between two luminance levels of the
adjacent two fields. Motion is detected for full screen image and each channel has 144(12x12)
mask regions, which enable or disable motion detection for that region. The motion detection
has several attributes, sensitivity and velocity of motion detector controlled by programming the
register. The Host takes the result of motion detection via IRQ or NVMD pin. Refer to the host
Interface for the detail.
Sensitivity Control
The motion detector has three sensitivity control parameters. One is level sensitivity control
parameter (LVLSENS), another is spatial sensitivity control parameter (SPTSENS), and a third
is temporal sensitivity control parameter (TMPSENS). The recommended values of sensitivity
control parameters for a proper operation are listed in Table 3
LVLSENS (Level Sensitivity)
In built-in motion detection algorithm, motion is detected when luminance level difference
between two fields is greater than the value, which is defined by LVLSENS. The smaller
LVLSENS value makes the motion detector sense more sensitively, and the larger is the
opposite. When LVLSENS is too small, the motion detector can be weak in noise.
SPTSENS (Spatial Sensitivity)
Motion detection from only luminance level difference between two fields is very weak in spatial
random noise. To remove the fake motion detection from the random noise, spatial filter is used.
SPTSENS adjusts the window size of the spatial filter to control the spatial sensitivity so that the
large SPTSENS value increases the immunity of spatial random noise.
TMPSENS (Temporal Sensitivity)
Likewise, temporal filter is used to remove the fake motion detection from the temporal random
noise. TMPSENS regulates the number of taps in the temporal filter to control the temporal
sensitivity so that the large TMPSENS value increases the immunity of temporal random noise.
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Table 3 The recommended values of sensitivity parameters for a proper operation
TMPSENS
LVLSENS
SPTSENS
More Sensitive
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
7
3
2
2
3
2
2
2
3
2
1
1
3
1
1
1
Less Sensitive
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
10
9
8
7
9
8
7
6
8
7
6
5
7
6
5
4
Velocity Control
Motion has various velocities. That is, in a fast motion an object appears and disappears rapidly
between the adjacent fields while in a slow motion it is to the contrary. As the built-in motion
detection algorithm uses the luminance level difference between two adjacent fields, a slow
motion is inferior in detection rate to a fast motion. To compensate this weakness, the
MDPERIOD parameter is used. MDPERIOD parameter adjusts the field interval in which the
luminance level is compared. Thus, for detection of a fast motion a small value is needed and
for a slow motion a large value is required. The parameter MDPERIOD value should be greater
than TMPSENS value.
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Mask Detection Region
The motion in the specific area can be ignored by the control of mask area. The full screen
image is divided into 144 (12x12) mask areas. If the mask bit in specific area is programmed
into high, the specific area is ignored in operation of motion detector, as illustrated in Fig. 11.
But for proper operation, more than 4 mask areas should be enabled in any case.
240 Lines for 60H z, 288 Lines for 50H z
720 P ixels
M ask1[0]
M ask1[1]
M ask1[2]
M ask1[3]
M ask1[4]
M ask1[5]
M ask1[6]
M ask1[7]
M ask1[8]
M ask1[9] M ask1[10] M ask1[11]
M ask2[0]
M ask2[1]
M ask2[2]
M ask2[3]
M ask2[4]
M ask2[5]
M ask2[6]
M ask2[7]
M ask2[8]
M ask2[9] M ask2[10] M ask2[11]
M ask3[0]
M ask3[1]
M ask3[2]
M ask3[3]
M ask3[4]
M ask3[5]
M ask3[6]
M ask3[7]
M ask3[8]
M ask3[9] M ask3[10] M ask3[11]
M ask4[0]
M ask4[1]
M ask4[2]
M ask4[3]
M ask4[4]
M ask4[5]
M ask4[6]
M ask4[7]
M ask4[8]
M ask4[9] M ask4[10] M ask4[11]
M ask5[0]
M ask5[1]
M ask5[2]
M ask5[3]
M ask5[4]
M ask5[5]
M ask5[6]
M ask5[7]
M ask5[8]
M ask5[9] M ask5[10] M ask5[11]
M ask6[0]
M ask6[1]
M ask6[2]
M ask6[3]
M ask6[4]
M ask6[5]
M ask6[6]
M ask6[7]
M ask6[8]
M ask6[9] M ask6[10] M ask6[11]
M ask7[0]
M ask7[1]
M ask7[2]
M ask7[3]
M ask7[4]
M ask7[5]
M ask7[6]
M ask7[7]
M ask7[8]
M ask7[9] M ask7[10] M ask7[11]
M ask8[0]
M ask8[1]
M ask8[2]
M ask8[3]
M ask8[4]
M ask8[5]
M ask8[6]
M ask8[7]
M ask8[8]
M ask8[9] M ask8[10] M ask8[11]
M ask9[0]
M ask9[1]
M ask9[2]
M ask9[3]
M ask9[4]
M ask9[5]
M ask9[6]
M ask9[7]
M ask9[8]
M ask9[9] M ask9[10] M ask9[11]
M ask10[0] M ask10[1] M ask10[2] M ask10[3] M ask10[4] M ask10[5] M ask10[6] M ask10[7] M ask10[8] M ask10[9] M ask10[10]M ask10[11]
M ask11[0] M ask11[1] M ask11[2] M ask11[3] M ask11[4] M ask11[5] M ask11[6] M ask11[7] M ask11[8] M ask11[9] M ask11[10]M ask11[11]
M ask12[0] M ask12[1] M ask12[2] M ask12[3] M ask12[4] M ask12[5] M ask12[6] M ask12[7] M ask12[8] M ask12[9] M ask12[10]M ask12[11]
Fig. 11 Motion detection mask windows
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Output Format
The TW280X supports three 8bit output formats, ITU-R BT.656, 8bit ITU-R BT.601 and Dual
ITU-R BT.656 with 54MHz data format. The output data is synchronous with rising or falling
edge of CLK27O for ITU-R BT.656 and 8bit ITU-R BT.601 format and with rising edge of
CLK54I for Dual ITU-R BT.656 with 54MHz format. The polarity of CLK27O is controlled by the
CK27O_POL register (0x3B). For Dual ITU-R BT.656 with 54MHz format, two kinds of scaled
image are time-multiplexed with 54MHz. The output formats are selected by the OUT_FMT
register (0x22, 0x62, 0xA2, 0xE2).
ITU-R BT.656 Format
In ITU-R BT.656 format, SAV and EAV sequences are inserted into the data stream to indicate
the active video time. During the blanking time, the YCbCr outputs have a value 0x00 for Y, Cr
and Cb. It is noted that the number of active pixels per line is constant in this mode regardless
of the actual incoming line length. If scaling is used, the number of active pixels per line is
constant with invalid pixel indicated by the blanking code 0x00. The output timing is illustrated in
Fig. 12. The SAV and EAV sequences are shown in Table 4. An optional set of 656 SAV/EAV
code sequence can be enabled to identify no-video status using the NOVID_656 bit (0x22,
0x62, 0xA2, 0xE2).
CLK27O
VD[7:0]
FFh
00h
00h
XY
00h
00h
00h
00h
FFh
EAV code
00h
00h
XY
00h
00h Cb0
Y0
Cr0
Y1
00h
00h
SAV code
HACIVE
VALID
Fig. 12 Timing Diagram of ITU-R BT.656 format on HSCALE = 16’h7FFF
Table 4 ITU-R 656 SAV and EAV Code Sequence
Condition
656 FVH Value
SAV/EAV Code Sequence
Field
EVEN
EVEN
EVEN
EVEN
ODD
ODD
ODD
ODD
Vertical
Horizontal
Blank
Blank
Active
Active
Blank
Blank
Active
Active
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EAV
SAV
EAV
SAV
EAV
SAV
EAV
SAV
F
1
1
1
1
0
0
0
0
V
1
1
0
0
1
1
0
0
H
1
0
1
0
1
0
1
0
First
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
23
Second
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Third
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Fourth
Normal
0xF1
0xEC
0xDA
0xC7
0xB6
0xAB
0x9D
0x80
Option
(Novideo)
0x71
0x6C
0x5A
0x47
0x36
0x2B
0x1D
0x00
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
8-bit ITU-R BT.601 Format
8-bit ITU-R BT.601 format is 8-bit YCbCr 4:2:2 data stream with additional timing information
such as syncs and field flag. The video output timing is illustrated in Fig 13 and Fig 14.
Analog
Input
Digital
Output
HS
VS
FLD
60Hz ODD Field
Analog
Input
Digital
Output
HS
VS
VSMODE = 0
VSMODE = 1
FLD
VSMODE = 0
VSMODE = 1
60Hz EVEN Field
Analog
Input
Digital
Output
HS
VS
FLD
50Hz ODD Field
Analog
Input
Digital
Output
HS
VS
VSMODE = 0
VSMODE = 1
FLD
VSMODE = 0
VSMODE = 1
50Hz EVEN Field
Fig 13 Vertical Timing for 60Hz / 50Hz Video
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
HS
Tim ing 1
VS
Tim ing 1
Tim ing 2
Tim ing 2
Tim ing 1
FLD
Tim ing 2
Tim ing 1 : 40 system clo ck(54M H z) fo r the E ven field w ith VS M O D E = 1 o r O d d field
Tim ing 2 : 1760 system clo ck(54M H z) fo r the E ven field w ith VS M O D E = 0
Fig 14 Horizontal and Vertical Timing in Video Output
Dual ITU-R BT.656 Format in 54MHz
Dual ITU-R BT.656 format in 54MHz is very useful to the security applications, which need two
independently scaled video images for display and record purpose. In the case of HSCALE_X =
16’h7FFF and HSCALE_Y = 16’hFFFF, the timing diagram of video output is illustrated in Fig
15.
CLK27O
CLK54I
VD[7:0]
FFh FFh 00h 00h 00h 00h XY XY 00h 00h
00h 00h FFh FFh 00h 00h 00h 00h XY XY 00h Cb0 00h Y0 Cb0 Cr0 Y0 Y1 Cr0 Cb2 Y1 Y2 00h Cr2 00h Y3
EAV code
HACIVE
SAV code
VALID
Data
: Scaled data output for Display purpose (X path)
Data
: Scaled data output for Record purpose (Y path)
Fig 15 Timing Diagram in Dual ITU-R BT.656 with 54MHz format
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Host Interface
The TW280X provides I2C serial and parallel interfaces that can be selected by HSPB pin.
When HSPB is low, the parallel interface is selected, the serial interface for high. Some of the
interface pins serve a dual purpose depending on the working mode. The pins HALE and
HDAT[7] in parallel mode become SCLK and SDAT pins in serial mode respectively. Each
interface protocol is shown in the following figure.
Table 5 Pin Assignment for Serial/Parallel Interface
Pin Name
Serial Mode
Parallel Mode
HSPB
HIGH
LOW
HALE
SCLK
AEN
HRDB
Not Used
RENB
HWRB
Not Used
WENB
HCSB
Slave Address[0]
CSB
HDAT[0]
Not Used
PDATA[0]
HDAT[1]
Slave Address[1]
PDATA[1]
HDAT[2]
Slave Address[2]
PDATA[2]
HDAT[3]
Slave Address[3]
PDATA[3]
HDAT[4]
Slave Address[4]
PDATA[4]
HDAT[5]
Slave Address[5]
PDATA[5]
HDAT[6]
Slave Address[6]
PDATA[6]
HDAT[7]
SDAT
PDATA[7]
Serial Interface
HDAT[6:1] and HCSB pins define slave address. Therefore, any slave address can be assigned
for full flexibility. TW2804 also supports auto index increments in write/read mode if the data are
in sequential order.
Start
SDAT
Slave address
MSB
R/WB
Ack
LSB
Index
Ack
MSB
LSB
Data
Ack
MSB
Stop
LSB
SCLK
Fig 16 Write mode in Serial Interface
Start
Slave address
R/WB
Ack
Index
Ack
Stop
Start
Slave address
R/WB
“0”
SDAT
MSB
LSB
Ack
Data
NoAck
Stop
“1”
MSB
LSB
MSB
LSB
MSB
LSB
SCLK
Fig 17 Read mode in Serial Interface
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Parallel Interface
The following figures show the write/read timing chart of parallel interface. The parallel interface
supports auto index increment after each byte of data is sent with WENB. Therefore, the host
can write multiple bytes to the slave without additional address if they are in sequential order.
The host completes the transfer cycle with CSB which is Low to High transition. Auto index
increment is also supported in read mode.
CSB
tsu(1)
th(1)
WENB
tw
RENB
tw
AEN
PDATA
th(2)
tsu(2)
th(2)
tsu(2)
Fig 18 Write mode in Parallel interface
CSB
tsu(1)
th(1)
WENB
tw
RENB
tw
AEN
PDATA
th(2)
tsu(2)
td (1)
td (2)
Fig 19 Read mode in Parallel interface
Parameter
Table 6 Parallel Interface Timing Parameter
Symbol
Min
Typ
CSB setup until AEN active
PDATA setup until AEN, WENB active
AEN, WENB, RENB active pulse width
CSB hold after WENB, RENB inactive
PDATA hold after AEN, WENB inactive
PDATA delay after RENB active
PDATA delay after RENB inactive
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tsu (1)
tsu (2)
tw
th (1)
th (2)
td (1)
td (2)
27
Max
Units
10
ns
10
ns
40
ns
60
ns
60
ns
12
ns
12
ns
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Interrupt Interface
The TW280X provides the interrupt request function via an IRQ pin. Any video loss detection or
motion detection will make the IRQ pin high until cleared via register IRQCLR (0x39) by the
host. The host processor will read the interrupt status register DET_NVMD (0x38) to find out
which channel has sensed motion or video loss. Writing high to the corresponding bit of the
interrupt clear register IRQCLR (0x39) will clear the interrupt request. Each interrupt status bit
also has its mask bit (0x3A) to disable the interrupt for that function. This sequence is described
in Fig 20.
The TW280X also provides the video loss detection or motion detection flag of individual
channel via NVMD pins. Four NVMD pins have respective channel information of motion or
M o tio n D etectio n
o n C hannel 2
M o tio n D etectio n
o n C hannel 3
N o V id eo D etectio n
o n C hannel 4
video loss so that host takes status information directly by reading these pins. Its mode is
controlled by NVMDB (0x3B) that is set “1” for video loss flag and “0” for motion detection flag.
IRQ Pin output
Status Register
0x00
Clear Register
0x80
0x00
0x80
0x04
0x02
0x04
C lear by H o st
C lear by H o st
0x00
0x02
C lear b y H ost
Fig 20 Timing Diagram of Interrupt Interface
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Datasheet Rev. 2.4
Preliminary
TW2804/TW2802 Multiple Video Decoder
Control Register
Register Map
CH1
Address
CH2 CH3
CH4
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
Mnemonic
VIDSTAT *
FORMAT
AGC_PLL
HDELAY_X
HACTIVE_X
HDELAY_Y
HACTIVE_Y
MSB_ACTV
HSWIDTH
VDELAY_X
VACTIVE_X
VDELAY_Y
VACTIVE_Y
HPLL
SYNCPOL
HUE
SAT
CONT
BRT
CFILTER
PEAKCKIL
SCLFLT
TRAP_X
TRAP_Y
VSCLMSB_X
VSCLLSB_X
VSCLMSB_Y
VSCLLSB_Y
HSCLMSB_X
HSCLLSB_X
HSCLMSB_Y
HSCLLSB_Y
VSCLCON_X
VSCLCON_Y
OUTFMT
RESERVED
SENSCTL
MPERIOD
MDMASK1
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BIT7
BIT6
BIT5
DET_FORMAT
BIT4
BIT2
LOCK_COLOR
LOCK_GAIN
0
1
PEDEST
0
GNTIME
HDELAY_X [7:0]
HACTIVE_X [7:0]
HDELAY_Y [7:0]
HACTIVE_Y [7:0]
HACTIVE_Y [9:8]
HDELAY_Y [9:8]
HACTIVE_X [9:8]
0
HSWIDTH
VDELAY_X [7:0]
VACTIVE_X [7:0]
VDELAY_Y [7:0]
VACTIVE_Y [7:0]
HPLLMAN
HPLLTIME
VACTVE_Y [8]
VDELAY_Y [8]
FLDMODE
VSMODE
FLDPOL
HSPOL
VSPOL
HUE
SAT
CONT
BRT
IFCOMP
CLPF
ACCMODE
YPEAK_Y
YPEAK_X
0
VLPF_Y
VLPF_X
HLPF_Y
YBWI_X
COMBMD_X
0
YBWI_Y
COMBMD_Y
0
VSCALE_X [15:8]
VSCALE_X [7:0]
VSCALE_Y [15:8]
VSCALE_Y [7:0]
HSCALE_X [15:8]
HSCALE_X [7:0]
HSCALE_Y [15:8]
HSCALE_Y [7:0]
0
VFLT_MD_X
VBW_X
PALDLY_X
ODD_EN_X
0
VFLT_MD_Y
VBW_Y
PALDLY_Y
ODD_EN_Y
BGND_EN
BGND_COLR
NOVID_656
LIM_16
SW_RESET
ANA_SW
1
0
0
1
0
0
LVLSENS
TMPSENS
0
MDPERIOD
MDMASK1[7:0]
IFMTMAN
AGC
DET_COLOR
BIT3
IFORMAT
29
BIT1
BIT0
LOCK_OFFSET
LOCK_HPLL
DET_NONSTD *
DET_FLD60 *
OSTIME
HDELAY_X [9:8]
VACTVE_X [8]
1
VDELAY_X [8]
0
APCMODE
CKILL
HLPF_X
EVEN_EN_X
EVEN_EN_Y
OUT_FMT
0
SPTSENS
1
1
1
09/09/2003
Datasheet Rev. 2.4
Preliminary
TW2804/TW2802 Multiple Video Decoder
CH1
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
Address
CH2 CH3
0x67
0xA7
0x68
0xA8
0x69
0xA9
0x6A 0xAA
0x6B 0xAB
0x6C 0xAC
0x6D 0xAD
0x6E 0xAE
0x6F 0xAF
0x70
0xB0
0x71
0xB1
0x72
0xB2
0x73
0xB3
0x74
0xB4
0x75
0xB5
0x76
0xB6
0x77
0xB7
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0xB8
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
Notes: ①
②
③
Mnemonic
CH4
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
*
MDMASK12
MDMASK2
MDMASK3
MDMASK34
MDMASK4
MDMASK5
MDMASK56
MDMASK6
MDMASK7
MDMASK78
MDMASK8
MDMASK9
MDMASK9A
MDMASKA
MDMASKB
MDMASKBC
MDMASKC
DET_NVMD *
IRQCLR
IRQENA
MISC
U_GAIN
V_GAIN
U_OFF
V_OFF
ADC_PWDN
RESERVED
RESERVED
FLDOFST
RESERVED
RESERVED
RESERVED
CORE
COMBCDEL
RESERVED
RESERVED
RESERVED
RESERVED
BIT7
BIT6
BIT5
BIT4
BIT3
MDMASK2[11:8]
BIT2
BIT1
BIT0
MDMASK1[11:8]
MDMASK2[7:0]
MDMASK3[7:0]
MDMASK4[11:8]
MDMASK3[11:8]
MDMASK4[7:0]
MDMASK5[7:0]
MDMASK6[11:8]
MDMASK5[11:8]
MDMASK6[7:0]
MDMASK7[7:0]
MDMASK8[11:8]
MDMASK7[11:8]
MDMASK8[7:0]
MDMASK9[7:0]
MDMASK10[11:8]
MDMASK9[11:8]
MDMASK10[7:0]
MDMASK11[7:0]
MDMASK12[11:8]
DET_NOVID4
DET_NOVID3
OE
NVMD
0
0
0
0
0
0
0
HAV_VALID
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MDMASK11[11:8]
MDMASK12[7:0]
DET_NOVID2
DET_NOVID1
DET_MOTION4
DET_MOTION3
DET_MOTION2
DET_MOTION1
IRQCLR
IRQENA
ACTIVE_MODE
0
CK27_POL
IRQPOL
IRQRPT
U_GAIN
V_GAIN
U_OFF
V_OFF
0
0
ADC_PWDN4
ADC_PWDN3
ADC_PWDN2
ADC_PWDN1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C_CORE
Y_H_CORE
CDEL
0
FLD_656
1
0
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
: Read only register
: Modified in TW2804 RevC
: Modified in TW2804 RevD
Techwell, Inc.
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30
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Recommended Value
CH1
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
Address
CH2
CH3
0x40
0x80
0x41
0x81
0x42
0x82
0x43
0x83
0x44
0x84
0x45
0x85
0x46
0x86
0x47
0x87
0x48
0x88
0x49
0x89
0x4A
0x8A
0x4B
0x8B
0x4C 0x8C
0x4D 0x8D
0x4E
0x8E
0x4F
0x8F
0x50
0x90
0x51
0x91
0x52
0x92
0x53
0x93
0x54
0x94
0x55
0x95
0x56
0x96
0x57
0x97
0x58
0x98
0x59
0x99
0x5A
0x9A
0x5B
0x9B
0x5C 0x9C
0x5D 0x9D
0x5E
0x9E
0x5F
0x9F
0x60
0xA0
0x61
0xA1
0x62
0xA2
0x63
0xA3
0x64
0xA4
0x65
0xA5
0x66
0xA6
0x67
0xA7
0x68
0xA8
0x69
0xA9
0x6A 0xAA
0x6B 0xAB
0x6C 0xAC
0x6D 0xAD
0x6E 0xAE
0x6F
0xAF
0x70
0xB0
0x71
0xB1
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CH4
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
Mnemonic
VIDSTAT
FORMAT
AGC_PLL
HDELAY_X
HACTIVE_X
HDELAY_Y
HACTIVE_Y
MSB_ACTV
HSWIDTH
VDELAY_X
VACTIVE_X
VDELAY_Y
VACTIVE_Y
HPLL
SYNCPOL
HUE
SAT
CONT
BRT
CFILTER
PEAKCKIL
SCLFLT
TRAP_X
TRAP_Y
VSCLMSB_X
VSCLLSB_X
VSCLMSB_Y
VSCLLSB_Y
HSCLMSB_X
HSCLLSB_X
HSCLMSB_Y
HSCLLSB_Y
VSCLCON_X
VSCLCON_Y
OUTFMT
RESERVED
SENSCTL
MPERIOD
MDMSKL1
MDMSKM12
MDMSKL2
MDMSKL3
MDMSKM34
MDMSKL4
MDMSKL5
MDMSKM56
MDMSKL6
MDMSKL7
MDMSKM78
MDMSKL8
FULL
8’h00
C4
A5
20
D0
20
D0
88
20
07
F0
07
F0
40
D2
80
80
80
80
1F
00
00
00
00
FF
FF
FF
FF
FF
FF
FF
FF
07
07
00
91
51
03
00
00
00
00
00
00
00
00
00
00
00
00
31
NTSC
CIF
QCIF
21
33
7F
3F
7F
3F
07
67
FULL
8’h00
84
A5
20
D0
20
D0
88
20
04
20
04
20
4A
D2
80
80
80
80
1F
00
00
40
40
FF
FF
FF
FF
FF
FF
FF
FF
0F
0F
00
91
51
03
00
00
00
00
00
00
00
00
00
00
00
00
PAL
CIF
QCIF
30
22
00
33
7F
3F
7F
3F
07
67
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH1
0x32
0x33
0x34
0x35
0x36
0x37
Address
CH2
CH3
0x72
0xB2
0x73
0xB3
0x74
0xB4
0x75
0xB5
0x76
0xB6
0x77
0xB7
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0xB8
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
CH4
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
Mnemonic
MDMSKL9
MDMSKM9A
MDMSKLA
MDMSKLB
MDMSKMBC
MDMSKLC
DET_NVMD
IRQCLR
IRQENA
MISC
U_GAIN
V_GAIN
U_OFF
V_OFF
ADC_PWDN
RESERVED
RESERVED
FLDOFST
RESERVED
RESERVED
RESERVED
CORE
COMBCDEL
RESERVED
RESERVED
RESERVED
RESERVED
FULL
00
00
00
00
00
00
00
00
FF
84
80
80
82
82
00
00
00
00
00
00
00
0A
42
3C
10
00
00
NTSC
CIF
QCIF
Preliminary
FULL
00
00
00
00
00
00
00
00
FF
84
80
80
82
82
00
00
00
00
00
00
00
0A
42
3C
10
00
00
PAL
CIF
QCIF
Note : ① Blanks : Indicate the same value as full size
: Modified in TW2804 RevC
②
: Modified in TW2804 RevD
③
Techwell, Inc.
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32
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Register Description
CH
Index
1
0x00
2
0x40
3
0x80
4
0xC0
Video Status Flag (Read only)
[7]
[6]
[5]
DET_FORMAT
DET_FORMAT
[0]
DET_COLORLOCK_COLOR LOCK_GAIN LOCK_OFST LOCK_PLL
NTSC-M
NTSC-4.43
NTSC-N
Color is not detected
Color is detected
Color demodulation loop is not locked
Color demodulation loop is locked
Status of locking for AGC loop
0 AGC loop is not locked
1
AGC loop is locked
LOCK_OFST
Status of locking for clamping loop
0 Claming loop is not locked
1 Claming loop is locked
LOCK_PLL
Status of locking for horizontal PLL
0 Horizontal PLL is not locked
1 Horizontal PLL is locked
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[1]
Status of locking for color demodulation loop
0
1
LOCK_GAIN
[2]
Status of color detection
0
1
LOCK_COLOR
[3]
Status of video standard detection
0 PAL-B/D
1 PAL-M
2 PAL-N
3 PAL-60
4
5
6
DET_COLOR
[4]
33
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x01
2
0x41
3
0x81
4
0xC1
Preliminary
Input Video Format
[7]
[6]
IFMTMAN
[5]
[4]
IFORMAT
[3]
[2]
[1]
[0]
0
1
DET_
NONSTD *
DET_
FLD60 *
Notes: * Read only register
IFMTMAN
Setting video standard manually with IFORMAT
0 Detect video standard automatically according to incoming video
1
IFORMAT
signal (default)
Video standard is selected with IFORMAT
Force the device to operate in a particular video standard when IFMTMAN
is high or to free-run in a particular video standard on no-video status when
IFMTMAN is low
0 PAL-B/D (default)
1 PAL-M
2 PAL-N
3
4
5
6
PAL-60
NTSC-M
NTSC-4.43
NTSC-N
DET_NONSTD
Status of non-standard video detection (Read only)
0 The incoming video source is standard
1 The incoming video source is non-standard
DET_FLD60
Status of field frequency of incoming video (Read only)
0
1
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50Hz field frequency
60Hz field frequency
34
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x02
2
0x42
3
0x82
4
0xC2
Preliminary
Gain and Offset Tracking
[7]
[6]
[5]
[4]
AGC
PEDEST
1
0
[3]
[2]
GNTIME
AGC
Enable the AGC
0 Disable the AGC (default)
1 Enable the AGC
PEDEST
Select the 7.5 IRE setup level, pedestal to black
0 No pedestal (default)
1 7.5 IRE setup level
GNTIME
Control the time constant of gain tracking loop
0 Slower
1 Slow (default)
2 Fast
3
OSTIME
[0]
OSTIME
Faster
Control the time constant of offset tracking loop
0 Slower
1 Slow (default)
2
3
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[1]
Fast
Faster
35
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
Index
Preliminary
Horizontal Delay Control for Path X
[7]
[6]
[5]
[4]
[3]
[2]
0x07
[0]
HDELAY[9:8]
0x03
HDELAY[7:0]
0x47
HDELAY[9:8]
0x43
HDELAY[7:0]
0x87
HDELAY[9:8]
0x83
HDELAY[7:0]
0xC7
HDELAY[9:8]
0xC3
Index
[1]
HDELAY[7:0]
Horizontal Delay Control for Path Y
[7]
0x07
0x05
0x47
0x45
0x87
0x85
0xC7
0xC5
HDELAY
[6]
[5]
[4]
[3]
[2]
[1]
[0]
HDELAY[9:8]
HDELAY[7:0]
HDELAY[9:8]
HDELAY[7:0]
HDELAY[9:8]
HDELAY[7:0]
HDELAY[9:8]
HDELAY[7:0]
This 10-bit register defines the starting location of horizontal active pixel. A
unit is 1 pixel. HDELAY1 and HDELAY2 define the different starting
location of horizontal active pixel for dual scaler output. The default value is
decimal 32.
Techwell, Inc.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
Index
Horizontal Active Control for Path X
[7]
[6]
[5]
[4]
0x07
[1]
[0]
HACITIVE[9:8]
0x84
HACTIVE[7:0]
0xC7
HACITIVE[9:8]
0xC4
HACTIVE[7:0]
Horizontal Active Control for Path Y
[7]
[6]
[5]
[4]
[3]
[2]
HACTIVE[9:8]
0x06
HACTIVE[7:0]
HACTIVE[9:8]
0x46
HACTIVE[7:0]
HACTIVE[9:8]
0x86
0xC7
[0]
HACTIVE[7:0]
0x87
0x87
[1]
HACITIVE[9:8]
0x44
0x47
[2]
HACTIVE[7:0]
0x47
0x07
[3]
HACITIVE[9:8]
0x04
Index
Preliminary
HACTIVE[7:0]
HACTIVE[9:8]
0xC6
HACTIVE[7:0]
HACTIVE
This 10-bit register defines the number of horizontal active pixel. A unit is 1
pixel. HACTIVE1 and HACTIVE2 define the different number of horizontal
active pixels for dual scaler output. The default value is decimal 720.
CH
Index
1
0x08
2
0x48
3
0x88
4
0xC8
Horizontal Sync Pulse Width Control
[7]
[6]
0
0
HSWIDTH
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[5]
[4]
[3]
[2]
[1]
[0]
HSWIDTH
This 6bit register defines the width of horizontal sync output. A unit is 1
pixel. The default value is decimal 32
37
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
Index
Preliminary
Vertical Delay Control for Path X
[7]
[6]
[5]
[4]
[3]
[2]
[1]
0x0D
VDELAY[8]
0x09
VDELAY[7:0]
0x4D
VDELAY[8]
0x49
VDELAY[7:0]
0x8D
VDELAY[8]
0x89
VDELAY[7:0]
0xCD
VDELAY[8]
0xC9
Index
[0]
VDELAY[7:0]
Vertical Delay Control for Path Y
[7]
[6]
[5]
[4]
[3]
0x0D
0x0B
VDELAY[7:0]
VDELAY[8]
VDELAY[7:0]
0xCD
0xCB
VDELAY
[0]
VDELAY[8]
0x8D
0x8B
[1]
VDELAY[7:0]
0x4D
0x4B
[2]
VDELAY[8]
VDELAY[8]
VDELAY[7:0]
This 9bit register defines the starting location of vertical active. A unit is 1
line. VDELAY1 and VDELAY2 define the different starting location of
vertical active line for dual scaler output. The default value is decimal 6.
Techwell, Inc.
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38
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
Index
Preliminary
Vertical Active Control for Path X
[7]
[6]
[5]
[4]
[3]
[2]
0x0D
[0]
VACTIVE[8]
0x0A
VACTIVE[7:0]
0x4D
VACTIVE[8]
0x4A
VACTIVE[7:0]
0x8D
VACTIVE[8]
0x8A
VACTIVE[7:0]
0xCD
VACTIVE[8]
0xCA
Index
[1]
VACTIVE[7:0]
Vertical Active Control for Path Y
[7]
[6]
[5]
[4]
0x0D
0x0C
VACTIVE
[0]
VACTIVE[7:0]
VACTIVE[8]
VACTIVE[7:0]
0xCD
0xCC
[1]
VACTIVE[8]
0x8D
0x8C
[2]
VACTIVE[7:0]
0x4D
0x4C
[3]
VACTIVE[8]
VACTIVE[8]
VACTIVE[7:0]
This 9bit register defines the number of vertical active lines. A unit is 1 line.
VACTIVE1 and VACTIVE2 define the different number of vertical active
lines for dual scaler output. The default value is decimal 240.
Techwell, Inc.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x0D
2
0x4D
3
0x8D
4
0xCD
Preliminary
Horizontal PLL Control
[7]
[6]
[5]
HPLLMAN
[4]
[3]
[2]
[1]
HPLLTIME
HPLLMAN
Set horizontal PLL time constant with HPLLTIME.
0 Automatic horizontal tracking mode (default)
1 Horizontal PLL time constant is fixed with HPLLTIME
HPLLTIME
Control the time constant of horizontal PLL when HPLLMAN is high
0 Slow
:
:
4 Typical (default)
:
7
Techwell, Inc.
www.techwellinc.com
[0]
:
Fast
40
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x0E
2
0x4E
3
0x8E
4
0xCE
Preliminary
Sync Pulse Polarity Control
[7]
[6]
FLDMODE
FLDMODE
Techwell, Inc.
www.techwellinc.com
[1]
[0]
VSMODE
FLDPOL
HSPOL
VSPOL
1
0
Field flag is generated from medium accumulator of detected field
Field flag is generated from large accumulator of detected field
(default)
VS and field flag is aligned with HS
Odd field is high (default)
Even field is high
Select the HS polarity
0 Low for sync duration (default)
1
VSPOL
[2]
Select the FLD polarity
0
1
HSPOL
[3]
Control the VS and field flag timing
0 VS and field flag is aligned with vertical sync of incoming video
1
FLDPOL
[4]
Select the field flag generation mode
0 Field flag is detected from incoming video (default)
1 Field flag is generated from small accumulator of detected field
2
3
VSMODE
[5]
High for sync duration
Select the VS polarity
0 Low for sync duration (default)
1 High for sync duration
41
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x0F
2
0x4F
3
0x8F
4
0xCF
Preliminary
Hue Control
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[1]
[0]
HUE
HUE
Control the hue information. The resolution is 1.4° / LSB.
0
-180°
:
:
128
:
255
CH
Index
1
0x10
2
0x50
3
0x90
4
0xD0
0° (default)
:
180°
Saturation Control
[7]
SAT
[6]
[4]
[3]
[2]
SAT
Control the color saturation. The resolution is 0.8% / LSB.
0
:
128
:
255
Techwell, Inc.
www.techwellinc.com
[5]
0%
:
100 % (default)
:
200 %
42
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x11
2
0x51
3
0x91
4
0xD1
Contrast Control
[7]
[6]
1
0x12
2
0x52
3
0x92
4
0xD2
[4]
[3]
[2]
[1]
[0]
[1]
[0]
Control the contrast. The resolution is 0.8% / LSB.
0
0%
:
:
128
:
255
Index
[5]
CONT
CONT
CH
Preliminary
100 % (default)
:
200 %
Brightness Control
[7]
BRT
[6]
[4]
[3]
[2]
BRT
Control the brightness. The resolution is 0.2IRE / LSB.
0
:
128
:
255
Techwell, Inc.
www.techwellinc.com
[5]
-25 IRE
:
0 (default)
:
25 IRE
43
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x13
2
0x53
3
0x93
4
0xD3
Preliminary
Color Filter Control
[7]
[6]
[5]
IFCOMP
IFCOMP
[3]
CLPF
[2]
ACCMODE
[0]
APCMODE
+2 dB/ MHz
+3 dB/ MHz
Select the Color LPF mode
0 550KHz bandwidth
1
2
3
750KHz bandwidth (default)
950KHz bandwidth
1.1MHz bandwidth
ACCMODE
Control the time constant of auto color control loop
0 Slower
1 Slow
2 Fast
3 Faster (default)
APCMODE
Control the time constant of auto phase control loop
0 Slower
1 Slow
2 Fast
3
Techwell, Inc.
www.techwellinc.com
[1]
Select the IF-compensation filter mode
0 No compensation (default)
1 +1 dB/ MHz
2
3
CLPF
[4]
Faster (default)
44
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x14
2
0x54
3
0x94
4
0xD4
Preliminary
Peaking and Color Killer Control
[7]
[6]
YPEAK_Y
YPEAK_Y
Techwell, Inc.
www.techwellinc.com
YPEAK_X
[3]
[2]
0
0
[1]
[0]
CKIL
62.5%
93.75%
Control the luminance peaking for SCALER X path
0 No peaking (default)
1
2
3
CKIL
[4]
Control the luminance peaking for SCALER Y path
0 No peaking (default)
1 31.25%
2
3
YPEAK_X
[5]
31.25%
62.5%
93.75%
Control the color killing mode
0,1 Auto detection mode (default)
2 Color is always alive
3 Color is always killed
45
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x15
2
0x55
3
0x95
4
0xD5
Preliminary
Scaler Filter Control
[7]
[6]
VLPF_Y
VLPF_Y
[1]
SCLFLT_Y
[0]
SCLFLT_X
0.18 Line-rate bandwidth
0.18 Line-rate bandwidth
2 MHz bandwidth
1.5 MHz bandwidth
1 MHz bandwidth
Select the horizontal anti-aliasing filter mode for HSCALER X
0
1
2
3
Techwell, Inc.
www.techwellinc.com
[2]
Select the horizontal anti-aliasing filter mode for HSCALER Y
0 Full bandwidth (default)
1
2
3
SCLFLT_X
VLPF_X
[3]
Select the vertical anti-aliasing filter mode for VSCALER X
0,1 Full bandwidth (default)
2 0.25 Line-rate bandwidth
3
SCLFLT_Y
[4]
Select the vertical anti-aliasing filter mode for VSCALER Y
0,1 Full bandwidth (default)
2 0.25 Line-rate bandwidth
3
VLPF_X
[5]
Full bandwidth (default)
2 MHz bandwidth
1.5 MHz bandwidth
1 MHz bandwidth
46
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x16
2
0x56
3
0x96
4
0xD6
CH
Index
1
0x17
2
0x57
3
0x97
4
0xD7
Preliminary
Trap Filter Control for Path X
[7]
YBWI
[6]
[5]
COMBMD
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
Trap Filter Control for Path Y
[7]
YBWI
[6]
[5]
COMBMD
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
YBWI
Select the luminance trap filter mode
0 Narrow bandwidth trap filter mode (default)
1 Wide bandwidth trap filter mode
COMBMD
Select the adaptive comb filter mode
0,1 Adaptive comb filter mode (default)
2 Force trap filter mode
3 Not supported
Techwell, Inc.
www.techwellinc.com
47
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
Index
Vertical Scaler Ratio Control for Path X
[7]
[6]
[5]
[4]
[3]
0x18
VSCALE[15:8]
0x19
VSCALE[7:0]
0x58
VSCALE[15:8]
0x59
VSCALE[7:0]
0x98
VSCALE[15:8]
0x99
VSCALE[7:0]
0xD8
VSCALE[15:8]
0xD9
VSCALE[7:0]
Index
Preliminary
[2]
[1]
[0]
[1]
[0]
Vertical Scaler Ratio Control for Path Y
[7]
0x1A
[6]
[5]
[4]
[3]
0x1B
VSCALE[7:0]
0x5A
VSCALE[15:8]
0x5B
VSCALE[7:0]
0x9A
VSCALE[15:8]
0x9B
VSCALE[7:0]
0xDA
VSCALE[15:8]
0xDB
VSCALE[7:0]
VSCALE
[2]
VSCALE[15:8]
The 16bit register defines a vertical scaling ratio. The actual vertical scaling
ratio is VSCALE[15:0] / (2^16 – 1). VSCALE1 and VSCALE2 define the
different vertical scaling ratio for dual scaler. The default value is 16 bit
0xFFFF.
Techwell, Inc.
www.techwellinc.com
48
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
Index
Horizontal Scaler Ratio Control for Path X
[7]
[6]
[5]
[4]
[3]
0x1C
HSCALE[15:8]
0x1D
HSCALE[7:0]
0x5C
HSCALE[15:8]
0x5D
HSCALE[7:0]
0x9C
HSCALE[15:8]
0x9D
HSCALE[7:0]
0xDC
HSCALE[15:8]
0xDD
HSCALE[7:0]
Index
Preliminary
[2]
[1]
[0]
[1]
[0]
Horizontal Scaler Ratio Control for Path Y
[7]
0x1E
[6]
[5]
[4]
[3]
0x1F
HSCALE[7:0]
0x5E
HSCALE[15:8]
0x5F
HSCALE[7:0]
0x9E
HSCALE[15:8]
0x9F
HSCALE[7:0]
0xDE
HSCALE[15:8]
0xDF
HSCALE[7:0]
HSCALE
[2]
HSCALE[15:8]
The 16-bit register defines a horizontal scaling ratio. The actual horizontal
scaling ratio is HSCALE[15:0] / (2^16 – 1). HSCALE1 and HSCALE2 define
the different horizontal scaling ratio for dual scaler. The default value is 16
bit 0xFFFF.
Techwell, Inc.
www.techwellinc.com
49
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x20
2
0x60
3
0xA0
4
0xE0
CH
Index
1
0x21
2
0x61
3
0xA1
4
0xE1
Preliminary
Vertical Scaler Control for Path X
[7]
[6]
0
VFLT_MD
[5]
[4]
VBW
[3]
PALDLY
[2]
[1]
ODD_EN EVEN_EN
[0]
1
Vertical Scaler Control for Path X
[7]
[6]
0
VFLT_MD
[5]
[4]
VBW
[3]
PALDLY
[2]
[1]
ODD_EN EVEN_EN
VFLT_MD
Select the vertical scaling filter mode
0 Vertical poly-phase filter mode is selected (default)
1 Vertical bandwidth control mode is selected with VBW bits
VBW
Control the vertical bandwidth only if VFLT_MD bit is high
0 Wider (default)
1 Wide
2 Narrow
3 Narrower
PAL_DLY
Select the PAL delay line mode
0 Normal vertical scaling operation in chroma path (default)
1 PAL delay line mode is selected in chroma path
ODD_EN
Control valid signal in ODD field
0 Valid signal is always disabled in ODD field
1 Normal operation (default)
EVEN_EN
Control valid signal in EVEN field
0
1
Techwell, Inc.
www.techwellinc.com
[0]
1
Valid signal is always disabled in EVEN field
Normal operation (default)
50
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x22
2
0x62
3
0xA2
4
0xE2
Preliminary
Output Formatter
[7]
[6]
[5]
BGNDEN BGNDCLR NOVID_656
[4]
[3]
[2]
LIM_16
SW_
RESET
ANA_SW
[1]
[0]
OUT_FMT
BGNDEN
Control the background color on/off
0 Background color is disabled (default)
1 Background color is enabled
BGNDCLR
Select the background color mode only if BGNDEN bit is high
0 Blue color mode (default)
1 Black color mode
NOVID_656
Select the optional set of 656 SAV/EAV code sequence for no-video status
0 Normal 656 SAV/EAV code sequence (default)
1 An optional set of 656 SAV/EAV code sequence for no-video status
LIM_16
Control the output range
0 Output ranges are limited to 2 ~ 254 (default)
1 Output ranges are limited to 16 ~ 239
SW_RESET
Reset the system by software except control registers.
This bit is self-clearing in a few clocks after enabled
0 Normal operation (default)
1 Enable soft reset
ANA_SW
Control the analog input channel switch
0
1
OUT_FMT
Select the output format
0 ITU-R BT.656 format (default)
1
2
3
Techwell, Inc.
www.techwellinc.com
VIN_A channel is selected (default)
VIN_B channel is selected
8bit ITU-R BT.601 format
Dual ITU-R BT.656 with 54MHz format
Not supported
51
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x23
2
0x63
3
0xA3
4
0xE3
Preliminary
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1
0
0
1
0
0
0
1
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Techwell, Inc.
www.techwellinc.com
52
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
Index
1
0x24
2
0x64
3
0xA4
4
0xE4
Preliminary
Motion Detection Sensitivity
[7]
[6]
[5]
[4]
LVLSENS
LVLSENS
[3]
[2]
[1]
TMPSENS
[0]
SPTSENS
Control the level sensitivity of motion detector (default : 3)
0 More sensitive
:
:
15 Less sensitive
TMPSENS
Control the temporal sensitivity of motion detector (default : 1)
0 More sensitive
:
:
3
SPTSENS
Control the spatial sensitivity of motion detector (default : 1)
0 More sensitive
:
3
CH
Index
1
0x25
2
0x65
3
0xA5
4
0xE5
Less sensitive
:
Less sensitive
Motion Detection Control
[7]
MDPERIOD
[6]
[5]
[4]
0
[3]
[2]
[1]
[0]
MDPERIOD
Control the velocity of motion detector (default : 3)
0 No field interval
1 1 field interval
:
:
31 31 field interval
Techwell, Inc.
www.techwellinc.com
53
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
CH
1
2
3
4
Index
Masking Motion Detection Area MASK1
[7]
[6]
[5]
[4]
[3]
0x27
[1]
[0]
MDMASK1[7:0]
0x67
MDMASK1[11:8]
0x66
MDMASK1[7:0]
0xA7
MDMASK1[11:8]
0xA6
MDMASK1[7:0]
0xE7
MDMASK1[11:8]
0xE6
MDMASK1[7:0]
Masking Motion Detection Area MASK2
[7]
0x27
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[1]
[0]
MDMASK2[11:8]
0x28
MDMASK2[7:0]
0x67
MDMASK2[11:8]
0x68
MDMASK2[7:0]
0xA7
MDMASK2[11:8]
0xA8
MDMASK2[7:0]
0xE7
MDMASK2[11:8]
0xE8
Index
[2]
MDMASK1[11:8]
0x26
Index
Preliminary
MDMASK2[7:0]
Masking Motion Detection Area MASK3
[7]
[6]
[5]
[4]
[3]
0x2A
0x29
MDMASK3[11:8]
MDMASK3[7:0]
0x6A
0x69
MDMASK3[11:8]
MDMASK3[7:0]
0xAA
0xA9
MDMASK3[11:8]
MDMASK3[7:0]
0xEA
0xE9
Techwell, Inc.
www.techwellinc.com
[2]
MDMASK3[11:8]
MDMASK3[7:0]
54
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
CH
1
2
3
4
Index
Masking Motion Detection Area MASK4
[7]
0x2A
[6]
[5]
[4]
[3]
[1]
[0]
[1]
[0]
MDMASK4[7:0]
0x6A
MDMASK4[11:8]
0x6B
MDMASK4[7:0]
0xAA
MDMASK4[11:8]
0xAB
MDMASK4[7:0]
0xEA
MDMASK4[11:8]
0xEB
MDMASK4[7:0]
Masking Motion Detection Area MASK5
[7]
[6]
[5]
[4]
[3]
0x2D
[2]
MDMASK5[11:8]
0x2C
MDMASK5[7:0]
0x6D
MDMASK5[11:8]
0x6C
MDMASK5[7:0]
0xAD
MDMASK5[11:8]
0xAC
MDMASK5[7:0]
0xED
MDMASK5[11:8]
0xEC
Index
[2]
MDMASK4[11:8]
0x2B
Index
Preliminary
MDMASK5[7:0]
Masking Motion Detection Area MASK6
[7]
0x2D
[6]
[5]
0xEE
Techwell, Inc.
www.techwellinc.com
[1]
[0]
MDMASK6[7:0]
MDMASK6[7:0]
MDMASK6[11:8]
0xAE
0xED
[2]
MDMASK6[11:8]
0x6E
0xAD
[3]
MDMASK6[11:8]
0x2E
0x6D
[4]
MDMASK6[7:0]
MDMASK6[11:8]
MDMASK6[7:0]
55
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
CH
1
2
3
4
Index
Masking Motion Detection Area MASK7
[7]
[6]
[5]
[4]
[3]
0x30
[1]
[0]
MDMASK7[7:0]
0x70
MDMASK7[11:8]
0x6F
MDMASK7[7:0]
0xB0
MDMASK7[11:8]
0xAF
MDMASK7[7:0]
0xF0
MDMASK7[11:8]
0xEF
MDMASK7[7:0]
Masking Motion Detection Area MASK8
[7]
0x30
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[1]
[0]
MDMASK8[11:8]
0x31
MDMASK8[7:0]
0x70
MDMASK8[11:8]
0x71
MDMASK8[7:0]
0xB0
MDMASK8[11:8]
0xB1
MDMASK8[7:0]
0xF0
MDMASK8[11:8]
0xF1
Index
[2]
MDMASK7[11:8]
0x2F
Index
Preliminary
MDMASK8[7:0]
Masking Motion Detection Area MASK9
[7]
[6]
[5]
[4]
[3]
0x33
0x32
MDMASK9[11:8]
MDMASK9[7:0]
0x73
0x72
MDMASK9[11:8]
MDMASK9[7:0]
0xB3
0xB2
MDMASK9[11:8]
MDMASK9[7:0]
0xF3
0xF2
Techwell, Inc.
www.techwellinc.com
[2]
MDMASK9[11:8]
MDMASK9[7:0]
56
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
CH
1
2
3
4
CH
1
2
3
4
CH
1
2
3
4
Index
Masking Motion Detection Area MASK10
[7]
0x33
[6]
[5]
[4]
[3]
[1]
[0]
[1]
[0]
MDMASK10[7:0]
0x73
MDMASK10[11:8]
0x74
MDMASK10[7:0]
0xB3
MDMASK10[11:8]
0xB4
MDMASK10[7:0]
0xF3
MDMASK10[11:8]
0xF4
MDMASK10[7:0]
Masking Motion Detection Area MASK11
[7]
[6]
[5]
[4]
[3]
0x36
[2]
MDMASK11[11:8]
0x35
MDMASK11[7:0]
0x76
MDMASK11[11:8]
0x75
MDMASK11[7:0]
0xB6
MDMASK11[11:8]
0xB5
MDMASK11[7:0]
0xF6
MDMASK11[11:8]
0xF5
Index
[2]
MDMASK10[11:8]
0x34
Index
Preliminary
MDMASK11[7:0]
Masking Motion Detection Area MASK12
[7]
0x36
[6]
[5]
0xF6
MDMASK1~12
Techwell, Inc.
www.techwellinc.com
[1]
[0]
MDMASK12[7:0]
MDMASK12[7:0]
MDMASK12[11:8]
0xB7
0xF7
[2]
MDMASK12[11:8]
0x77
0xB6
[3]
MDMASK12[11:8]
0x37
0x76
[4]
MDMASK12[7:0]
MDMASK12[11:8]
MDMASK12[7:0]
Select mask area of motion detector. An active region is divided into 12x12
mask areas as illustrated in Fig. 11. If the mask bit in specific area is
programmed into high, the specific area is ignored in operation of motion
detector. But for proper operation, more than 4 mask areas should be
enabled in any case. (default : 0x00)
57
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
No video and Motion Detection Flag (Read only)
Index
0x38
Preliminary
[7]
[6]
[5]
[4]
DET_
NOVID4
DET_
NOVID3
DET_
NOVID2
DET_
NOVID1
DET_NOVID4
Video loss is detected
Video loss is detected
Status for detection of video loss in Channel 2
0 Video is alive
1 Video loss is detected
DET_NOVID1
Status for detection of video loss in Channel 1
0 Video is alive
1 Video loss is detected
DET_MOTION4
Status for detection of motion in Channel 4
0 No motion
1 Motion is detected
DET_MOTION3
Status for detection of Motion in Channel 3
0
1
No motion
Motion is detected
Status for detection of Motion in Channel 2
0 No motion
1
Motion is detected
Status for detection of Motion in Channel 1
0 No motion
1
Techwell, Inc.
www.techwellinc.com
[0]
DET_
DET_
DET_
DET_
MOTION4 MOTION3 MOTION2 MOTION1
DET_NOVID2
DET_MOTION1
[1]
Status for detection of video loss in Channel 3
0 Video is alive
1
DET_MOTION2
[2]
Status for detection of video loss in Channel 4
0 Video is alive
1
DET_NOVID3
[3]
Motion is detected
58
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0x39
Clear Interrupt Flag
[7]
[6]
[5]
[4]
CLEAR_
NOVID4
CLEAR_
NOVID3
CLEAR_
NOVID2
CLEAR_
NOVID1
IRQCLR
Index
0x3A
Preliminary
[3]
[2]
[1]
[0]
CLEAR_
CLEAR_
CLEAR_
CLEAR_
MOTION4 MOTION3 MOTION2 MOTION1
Setting high to bits clears interrupt requests of corresponding bits. This bit
is self-clearing in a few clocks after setting high (default : 0x00)
Enable Interrupt Flag
[7]
[6]
[5]
[4]
EN_
NOVID4
EN _
NOVID3
EN_
NOVID2
EN _
NOVID1
IRQENA
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[3]
[2]
[1]
[0]
EN _
EN_
EN_
EN_
MOTION4 MOTION3 MOTION2 MOTION1
Enable the corresponding (0x38, 0x39) interrupt register bit (default : 0x00)
59
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0x3B
Preliminary
Miscellaneous Control Register
[7]
[6]
OE
NVMD
[5]
[4]
[3]
[2]
[1]
[0]
0
CK27_POL
IRQPOL
IRQRPT
ACTIVE_MODE[1:0]
OE
Control the tri-state of output pin
0 Outputs are Tri-state (default)
1 Outputs are enabled
NVMD
Select the output mode of NVMD pin
0 Video loss flag (default)
1 Motion detection flag
ACTIVE_MODE
Select the output mode of ACTIVE pin
0 HACTIVE (default)
1 VACTIVE
2 Horizontal valid pixel indicator
3 Vertical valid line indicator
CK27_POL
Select the CLK27O polarity
0 ITU-R BT.656 data outputs at the rising edge of CLK27O (default)
1 ITU-R BT.656 data outputs at the falling edge of CLK27O
IRQPOL
Select the IRQ polarity
0 Active high (default)
1 Active low
IRQRPT
Select the IRQ mode
0
1
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IRQ maintains the state until the interrupt request is cleared (default)
IRQ toggles the state at regular intervals until the interrupt request is
cleared
60
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
U Gain
[7]
[6]
[5]
0x3C
[4]
[3]
[2]
[1]
[0]
U_GAIN[7:0]
U_GAIN
Adjust gain for U (or Cb) component. The resolution is 0.8% / LSB.
0
0%
:
:
128
:
:
255
Index
Preliminary
100 % (default)
200 %
V Gain
[7]
[6]
[5]
0x3D
V_GAIN
[3]
[2]
[1]
[0]
V_GAIN[7:0]
Adjust gain for V (or Cr) component. The resolution is 0.8% / LSB.
0
0%
:
:
128
100 % (default)
:
:
255
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[4]
200 %
61
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
U Offset
[7]
[6]
[5]
0x3E
[4]
[3]
[2]
[1]
[0]
U_OFF[7:0]
U_OFF
U (or Cb) offset adjustment register. The resolution is 0.4% / LSB.
0
:
:
128
:
:
255
Index
Preliminary
-50 %
0 % (default)
50 %
V Offset
[7]
[6]
[5]
0x3F
V_OFF
[3]
[2]
[1]
[0]
V_OFF[7:0]
V (or Cr) offset adjustment register. The resolution is 0.4% / LSB.
0
-50 %
:
:
128
:
255
Techwell, Inc.
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[4]
0 % (default)
:
50 %
62
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0x78
Preliminary
ADC Power Down
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
ADC_
PWDN4
ADC_
PWDN3
ADC_
PWDN2
ADC_
PWDN1
ADC_PWDN4
Power down the ADC of channel 4
0 Normal (default)
1
ADC_PWDN3
Power down
Power down the ADC of channel 3
0 Normal (default)
1
Power down
ADC_PWDN2
Power down the ADC of channel 2
0 Normal (default)
1 Power down
ADC_PWDN1
Power down the ADC of channel 1
0 Normal (default)
1 Power down
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0x79
Preliminary
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Index
0x7A
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0x7B
Preliminary
Field Offset Control
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST FLD_OFST
_4Y
_4X
_3Y
_3X
_2Y
_2X
_1Y
_1X
FLD_OFST_4Y
Remove the field offset between ODD and EVEN for Y path of Channel 4
0 Normal operation (default)
1
FLD_OFST_4X
Remove the field offset between ODD and EVEN field
Remove the field offset between ODD and EVEN for X path of Channel 4
0 Normal operation (default)
1
Remove the field offset between ODD and EVEN field
FLD_OFST_3Y
Remove the field offset between ODD and EVEN for Y path of Channel 3
0 Normal operation (default)
1 Remove the field offset between ODD and EVEN field
FLD_OFST_3X
Remove the field offset between ODD and EVEN for X path of Channel 3
0 Normal operation (default)
1 Remove the field offset between ODD and EVEN field
FLD_OFST_2Y
Remove the field offset between ODD and EVEN for Y path of Channel 2
0 Normal operation (default)
1 Remove the field offset between ODD and EVEN field
FLD_OFST_2X
Remove the field offset between ODD and EVEN for X path of Channel 2
0
1
FLD_OFST_1Y
Remove the field offset between ODD and EVEN for Y path of Channel 1
0 Normal operation (default)
1
FLD_OFST_1X
Remove the field offset between ODD and EVEN field
Remove the field offset between ODD and EVEN for X path of Channel 1
0 Normal operation (default)
1
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Normal operation (default)
Remove the field offset between ODD and EVEN field
Remove the field offset between ODD and EVEN field
65
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0x7C
Preliminary
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Index
0x7D
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Index
0xB8
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Luma and Chroma Coring
Index
0xF8
Preliminary
[7]
[6]
[5]
[4]
[3]
HAV_VALID
0
0
0
C_CORE[1:0]
HAV_VALID
Y_H_CORE[1:0]
Valid data indicator only for active data (default)
Valid data indicator for both active data and ITU-R 656 timing codes
Coring value is within 128 +/- 1 range
Coring value is within 128 +/- 2 range (default)
Coring value is within 128 +/- 4 range
Coring to reduce the high frequency noise in the luminance
0
1
2
3
Techwell, Inc.
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[0]
Coring to reduce the noise in the chrominance
0 No coring
1
2
3
Y_H_CORE
[1]
Select VALID output mode
0
1
C_CORE
[2]
No coring
Coring value is within +/- 1 range
Coring value is within +/- 2 range (default)
Coring value is within +/- 4 range
67
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0xF9
Preliminary
Chroma Delay and Comb Filter Correlation Reference
[7]
[6]
0
CDEL
[3]
[2]
[1]
[0]
0
FLD_656
1
0
Adjust the group delay of chrominance path relative to luminance
0 -2.0 pixel
1 -1.5 pixel
7
Techwell, Inc.
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[4]
CDEL[2:0]
2
3
4
5
6
FLD_656
[5]
-1.0 pixel
-0.5 pixel
0.0 pixel (default)
0.5 pixel
1.0 pixel
1.5 pixel
Control the field polarity mode in ITU-R 656 timing codes
0 Fixed field polarity according to ITU-R 656 format (default)
1 Controllable field polarity by FLDPOL register (0x0E,0x4E,0x8E,0xCE)
68
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Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0xFA
Preliminary
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
1
1
1
1
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Index
0xFB
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
1
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Index
0xFC
Preliminary
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
Index
0xFD
Reserved
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
This control register is reserved for putting the part into test mode. For normal operation, the
above value should be set in this register.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Parametric Information
DC Electrical Parameters
Parameter
Table 7 Absolute Maximum Ratings
Symbol
Min
Typ
Max
Units
V
VDDA (measured to VSSA)
VDDAM
3.5
VDD (measured to VSS)
VDDIM
3.5
V
VDDO (measured to VSS)
VDDOM
4.6
V
Voltage on any signal pin
(See the note below)
-
VSS–0.5
VDDO+0.5
V
Analog Input Voltage
-
VSSA–0.5
VDDA+0.5
V
Storage Temperature
TS
– 65
150
°C
TJ
0
125
°C
220
°C
Junction Temperature
Vapor Phase Soldering (15 Seconds)
TVSOL
NOTE: Long-term exposure to absolute maximum ratings may affect device reliability, and
permanent damage may occur if operate exceeding the rating. The device should be
operated under recommended operating condition.
Table 8 Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
VDDA (measured to VSSA)
VDDA
2.25
2.5
2.75
V
VDD (measured to VSS)
VDDI
2.25
2.5
2.75
V
VDDO (measured to VSS)
VDDO
3.0
3.3
3.6
V
Maximum |VDDI – VDDA|
0.3
V
Maximum |VDDO – VDDA|
1.05
V
Maximum |VDDO – VDDI|
1.05
V
2.0
V
70
°C
Analog VIN Amplitude Range
(AC coupling required)
Ambient Operating Temperature
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0.5
TA
71
0
1.0
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Parameter
Table 9 DC Characteristics
Symbol
Min
Preliminary
Typ
Max
Units
Digital Inputs
Input High Voltage (TTL)
VIH
Input Low Voltage (TTL)
VIL
0.8
V
Input Leakage Current
(@VI=2.5V or 0V)
IL
±1
uA
Input Capacitance
2.0
CIN
V
6
pF
Digital Outputs
Output High Voltage
VOH
Output Low Voltage
VOL
High Level Output Current
(@VOH=2.4V)
IOH
5.7
Low Level Output Current
(@VOL=0.4V)
IOL
4.1
Tri-state Output Leakage Current
(@VO=2.5V or 0V)
IOZ
Output Capacitance
CO
6
pF
CA
6
pF
Analog Pin Input Capacitance
2.4
V
0.4
V
11.6
18.6
mA
6.7
8.2
mA
±1
uA
Table 10 Supply Current and Power Dissipation
Parameter
Symbol
Min
Typ
Analog Supply Current (2.5V)
Max
Units
IDDA
50
Digital Internal Supply Current (2.5V)
IDDI
400
mA
Digital I/O Supply Current (3.3V)
IDDO
10
mA
P
1.16
W
Total Power Dissipation
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72
mA
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
AC Electrical Parameters
Parameter
Table 11 Clock Timing Parameters
Symbol
Min
Typ
Delay from CLK54I to CLK27O
1
5
Hold from CLK27O to Data
2a
16
Delay from CLK27O to Data
2b
Hold from CLK54I to Data
3a
Delay from CLK54I to Data
3b
Max
12
Units
ns
ns
19
5
ns
ns
12
ns
CLK54I
1
CLK27O
2b
2a
Data Output
(27Mhz)
3b
3a
Data Output
(54Mhz)
Fig 21 Clock Timing Diagram
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Parameter
Preliminary
Table 12.Decoder Performance Parameter
Symbol
Min
Typ
Max
Units
Horizontal PLL
Line frequency (60Hz)
fH
15.734
KHz
Line frequency (50Hz)
fH
15.625
KHz
Permissible static deviation
∆fH
±6
%
Subcarrier PLL
Subcarrier frequency (NTSC-M)
fSC
3.579545
MHz
Subcarrier frequency (PAL-BDGHI)
fSC
4.433619
MHz
Subcarrier frequency (PAL-M)
fSC
3.575612
MHz
Subcarrier frequency (PAL-N)
fSC
3.582056
MHz
Lock in range
∆fSC
±800
AGC
-6
18
dB
ACC
-6
30
dB
Hz
AGC (Auto Gain Control)
Range
ACC (Auto Color Gain Control)
Range
Oscillator Input
Nominal frequency
Permissible frequency deviation
Duty cycle
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fOSC
54
MHz
∆fOSC/fOSC
±50
ppm
dtOSC
55
%
74
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Package Dimension
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
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Preliminary
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Application Information
Video Input Interface
TW2804 has a built-in 2:1 input MUX for software controllable input selections. This MUX can
be used to select two composite video sources. For a typical application, a video input
requires an analog low-pass filter for alias reduction. An illustration is shown in the following
application schematic.
Clamping / AGC
TW2804 has built-in clamping and AGC circuitry. The analog inputs must be AC coupled
through an external 2.2uF capacitor. Without it, no extra external component is needed for
this operation. The clamping and AGC tracking time constant can be controlled through
register setting.
Video Output Interface
All video data and sync outputs of four channels are synchronous to pin CLK27O. Therefore,
pin CLK27O should be connected to four channel interfaces for synchronizing data.
Power-Up
After power-up, TW2804 registers have unknown values. The RSTB pin must be asserted
and released to bring all registers to its default values. After reset, TW2804 data outputs are
tri-stated. The OE (0x3B) register should be written after reset to enable outputs desired.
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09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Application Schematic
75
47pF
100pF
4.7k
113
J101
RCA JACK
1
2
CH2A
R104
R103
270
75
L101
114
C105
10uH
C103
C104
R105
47pF
100pF
4.7k
2
R107
R106
270
75
L102
C107
R108
47pF
100pF
4.7k
0.1uF
2.2uF
2
L103
C111
TW2804
270
75
VIN3A
128QFP
VIN3B
C114
10uH
R109
VIN2B
C113
C106
R110
VIN2A
C108
10uH
122
J103
RCA JACK
1
0.1uF
C109
C110
R111
47pF
100pF
4.7k
2.2uF
126
VIN4A
VIN4B
C115
0.1uF
VDD
L104
BEAD
47uF/16V
C117
C118
C119
C120
C121
C122
C123
C124
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2
OSC100
+ C125
47uF/16V
C126
C127
C128
C129
C130
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1
VCC
8
DIP8
4
GND
OUT
5
R112
47uF/16V
C132
C133
C134
C135
C136
C137
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Place near each device
power pin(0.1uF Cap.)
1
CLK54I
TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+ C131
89
3
12
15
18
27
30
36
39
42
51
54
57
63
69
75
78
81
87
93
96
99
108
BEAD
OSC 54MHz
VDDO
L106
RSTB
VDDO
NC
100
VDD3.3V
34
35
37
38
40
41
43
44
32
29
28
26
31
VD2_7
VD2_6
VD2_5
VD2_4
VD2_3
VD2_2
VD2_1
VD2_0
55
56
58
59
61
62
64
65
53
50
49
47
52
VD3_7
VD3_6
VD3_5
VD3_4
VD3_3
VD3_2
VD3_1
VD3_0
76
77
79
80
82
83
85
86
74
71
70
68
73
VD4_7
VD4_6
VD4_5
VD4_4
VD4_3
VD4_2
VD4_1
VD4_0
VD1[7:0]
VALID1
HS1
VS1
FLD1
ACTIVE1
VD2[7:0]
VALID2
HS2
VS2
FLD2
ACTIVE2
VD3[7:0]
VD3_7
VD3_6
VD3_5
VD3_4
VD3_3
VD3_2
VD3_1
VD3_0
VALID3
HS3
VS3
FLD3
ACTIVE3
VD4_7
VD4_6
VD4_5
VD4_4
VD4_3
VD4_2
VD4_1
VD4_0
VALID4
HS4
VS4
FLD4
ACTIVE4
RESETB
VDDA
L105
BEAD
VD2_7
VD2_6
VD2_5
VD2_4
VD2_3
VD2_2
VD2_1
VD2_0
VALID2
HS2
VS2
FLD2
ACTIVE2
CLK27O
+ C116
VD1_7
VD1_6
VD1_5
VD1_4
VD1_3
VD1_2
VD1_1
VD1_0
VD3[7:0]
VALID3
HS3
VS3
FLD3
ACTIVE3
VD4[7:0]
125
VDD2.5V
VD1[7:0]
13
14
16
17
19
20
22
23
11
8
7
5
10
VD2[7:0]
121
CH4A
VIN1B
0.1uF
118
J102
RCA JACK
1
VIN1A
C112
2.2uF
117
CH3A
VD1_7
VD1_6
VD1_5
VD1_4
VD1_3
VD1_2
VD1_1
VD1_0
VALID1
HS1
VS1
FLD1
ACTIVE1
Analog GND
IRQ
NVMD1
NVMD2
NVMD3
NVMD4
HDAT_0
HDAT_1
HDAT_2
HDAT_3
HDAT_4
HDTV_5
HDAT_6
HDAT_7
HWRB
HRDB
HALE
HCSB
HSPB
VD4[7:0]
VALID4
HS4
VS4
FLD4
ACTIVE4
88
CLK27
103
4
25
46
67
101
100
98
97
95
94
92
91
104
106
107
109
110
HDAT[7:0]
HDAT0
HDAT1
HDAT2
HDAT3
HDAT4
HDAT5
HDAT6
HDAT7
IRQ
NVMD1
NVMD2
NVMD3
NVMD4
HDAT[7:0]
VDDO
R113
47K
To Micom
R102
111
112
119
120
127
U100
2.2uF
C101
128
115 VSSAD
116 VSSA
123 VSSA
124 VSSA
VSSA
2
C102
10uH
C100
VDDA
VDDAD
VDDA
VDDA
VDDA
VDDA
L100
270
6
24
45
66
84
105
R101
R100
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
J100
RCA JACK
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CH1A
VDDO
9
21
33
48
60
72
90
102
VDD
HWRB
HRDB
HALE
HCSB
HSPB
Digital GND
Note : Analog GND and Digital GND Plane
should be isolated
Techwell, Inc.
www.techwellinc.com
78
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Revision History
Table 13 Datasheet Revision History
Product
Code
Revision
Date
0.9
Oct / 01 / 2002
Engineering Release
1.0
Dec / 11 / 2002
(1) Update Application Schematic (P.77)
E BAHB
(2) Update Recommended Value of Control Register Map (P.31~32) (Eng RevB)
1.1
Jan / 29 / 2003
(1) Update Control Register Map (Read only description is added)
(P.29~30, P.33~34, P.58)
1.2
Feb / 04 / 2003
(1) Update Application Schematic (P.77)
E BAHB
(2) Update Recommended Value of Control Register Map (P.31~32) (Eng RevB)
1.3
Feb / 17 / 2003
(1) Update Control Register Map (Default value is added)
(P.34, P.40, P.45, P.47, P.60)
(2) Update Fig.14 (P.25)
E BAHB
(Eng RevB)
2.0
Feb / 19 / 2003
(1) Change Pin Diagram (P.5~7)
(2) Update Application Schematic (P.76)
E BAHC
(Eng RevC)
2.1
Apr / 25 / 2003
(1) Update Fig 4 and Fig 9 (P.12, P.16)
(2) Update Table 4 (P.23)
(3) Update Control Register Map & Recommended Value
(P.29~32, P.35, P.40, P.45~47, P.50~51, P.60, P.63~70)
(4) Fix FLDPOL and NVMD mode (P.41, P.60)
E BAHC
(Eng RevC)
2.2
Jul / 21 / 2003
(1) Update Fig 19 (P.27)
E BAHC
(Eng RevC)
2.3
Aug / 16 / 2003
(1) Change digital power(Pin 111) and ground pin(Pin 128) to analog
power and ground pin (P.5 ~ 7)
E BAHD
(2) Change Recommended Value of Control Register 0xFB (P.69)
(Eng RevD)
(2) Update parallel interface timing diagram (P.27)
(3) Update Application Schematic (P.77)
2.4
Sep / 09 / 2003
(1) Update Supply Current and Power Dissipation information (P.72)
E BAHD
(2) Update Application Information (P.76)
(Eng RevD)
(3) Update Application Schematic (P.77)
Nov / 11 / 2003
(1)
(2)
(3)
(4)
2.5
Techwell, Inc.
www.techwellinc.com
Description
E BAHB
(Eng RevB)
Update Fig 12 and Fig 15 (P.23, P.25)
Update Control Register Map (P.65)
Update Decoder Performance Parameter (P.74)
Update Application Schematic (P.78)
79
E BAHB
(Eng RevB)
E BAHE
(Eng RevE)
09/09/2003
Datasheet Rev. 2.4
TW2804/TW2802 Multiple Video Decoder
Preliminary
Table 14. List of Revision Point in TW2804 RevC
No.
Issue
TW2804 RevB
TW2804 RevC
1
Cross-talk
Cross-talk between adjacent input
channels
Remove cross-talk by modifying analog
circuit and changing analog pin location
2
100% amplitude,
100% saturation
Color bar pattern
Clipping the yellow and cyan pattern
Fixed by adjusting data range
3
Contrast range
Biased toward upper range
Fixed by adjusting contrast range
Not supported
Supported with Blue and Black pattern
A little aliasing noise is remained
Rejected perfectly by improving vertical
scaling filter
4
5
Background color
pattern
Vertical scaling
filter
6
IRQ polarity
Only active high is supported
Both active high and low are supported
7
Optional ITU –R
656 code set
Not supported
Optional No-video and non-valid code
set are supported
8
Peaking filter
Common mode in Scaling X & Y path
Separate mode in Scaling X & Y path
Table 15 List of Revision Point in TW2804 RevD
No.
1
Issue
ADC Linearity
TW2804 RevC
Not good in ADC linearity
TW2804 RevD
Improve ADC linearity
Table 16 List of Revision Point in TW2804 RevE
No.
Issue
TW2804 RevD
TW2804 RevE
1
ADC Linearity
Improve ADC linearity
Improve ADC linearity more
2
Field Offset
Control
Not supported
Supports the field offset control for
speeding up the field rate in analog
switching mode
Techwell, Inc.
www.techwellinc.com
80
09/09/2003
Datasheet Rev. 2.4