IRF IR21364STRPBF

Data Sheet No. PD PD60342A
November 13, 2009
IR21364(S&J)PbF
3-PHASE BRIDGE DRIVER
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Product Summary
Floating channel designed for bootstrap operation
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 11.5 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent 3 half-bridge drivers
Matched propagation delay for all channels
Cross-conduction prevention logic
Low side and High side outputs in phase with inputs.
3.3 V logic compatible
Lower di/dt gate drive for better noise immunity
Externally programmable delay for automatic fault clear
RoHS Compliant
VOFFSET
≤ 600 V
VOUT
11.5 V – 20 V
Io+ & I o(typical)
200 mA & 350 mA
tON & tOFF
(typical)
500 ns & 530 ns
Package Options
Typical Applications
•
•
•
•
3 phase bridge
driver
Topology
Motor Control
Air Conditioners/ Washing Machines
General Purpose Inverters
Micro/Mini Inverter Drivers
28-Lead SOIC
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44-Lead PLCC
w/o 12 Leads
© 2009 International Rectifier
1
IR21364(S&J)PbF
Description
The IR21364(S&J)PBF is a high voltage, high speed power MOSFET and IGBT drivers with three
independent high and low side referenced output channels for 3-phase applications. Proprietary HVIC
technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL
outputs, down to 3.3V logic. A current trip function which terminates all six outputs can be derived from an
external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An
open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred.
Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC
network connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency
applications. The floating channel can be used to drive N-channel power MOSFETs or IGBTs in the high side
configuration which operates up to 600 V.
Qualification Information
†
††
Industrial
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification
level is granted by extension of the higher Industrial
level.
Qualification Level
†††
SOIC28W
MSL3 , 260°C
(per IPC/JEDEC J-STD-020)
PLCC44
MSL3 , 245°C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
†††
Class 2
(per JEDEC standard JESD22-A114)
Human Body Model
ESD
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Machine Model
Class I, Level A
(per JESD78)
Yes
IC Latch-Up Test
RoHS Compliant
†
††
†††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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© 2009 International Rectifier
2
IR21364(S&J)PbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
Definition
VS
High side offset voltage
VB
High side floating supply voltage
VHO
High side floating output voltage
VCC
Low side and logic fixed supply voltage
VSS
Logic ground
VLO1,2,3
Min
Max
VB 1,2,3 - 25 VB 1,2,3 + 0.3
-0.3
625
VS1,2,3 - 0.3 VB 1,2,3 + 0.3
Low side output voltage
-0.3
25
VCC - 25
VCC + 0.3
-0.3
VCC + 0.3
lower of
VCC + 0.3 or
Vss+15
VCC + 0.3
VIN
Input voltage LIN, HIN, ITRIP, EN, RCIN
VSS -0.3
VFLT
FAULT output voltage
VSS -0.3
dV/dt
Allowable offset voltage slew rate
PD
RthJA
Units
V
—
50
V/ns
Package power dissipation
@ TA ≤ +25 °C
(28 lead SOIC)
—
1.6
W
(44 lead PLCC)
—
2.0
Thermal resistance, junction to
ambient
(28 lead SOIC)
—
78
(44 lead PLCC)
—
63
TJ
Junction temperature
—
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute referenced to COM. The VS & VSS offset rating are
tested with all supplies biased at a 15 V differential.
Symbol
VB1,2,3
VS 1,2,3
VCC
VHO 1,2,3
VLO1,2,3
Definition
High side floating supply voltage
High side floating supply voltage
Low side supply voltage
High side output voltage
IR21364
IR21364
Min.
Max.
VS1,2,3 +11.5
Note 1
11.5
VS1,2,3
VS1,2,3 + 20
600
20
VB1,2,3
Low side output voltage
0
VCC
VSS
Logic ground
-5
5
VFLT
FAULT output voltage
VSS
VCC
VRCIN
RCIN input voltage
VSS
VCC
Units
V
VITRIP
VIN
TA
ITRIP input voltage
VSS
VSS + 5
Logic input voltage LIN, HIN, EN
VSS
VSS + 5
-40
Ambient temperature
125
°C
Note 1: Logic operational for VS of COM -5 V to COM + 600 V. Logic state held for VS of COM -5 to COM – VBS.
(Please refer to the Design Tip DT97 -3 for more details).
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© 2009 International Rectifier
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IR21364(S&J)PbF
Static Electrical Characteristics
VBIAS (VCC, VBS 1,2,3) = 15 V, TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
VSS and are applicable to all six channels (HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM
and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.
Symbol
Definition
Min Typ Max Units
VIH
Logic “0” input voltage
—
VIL
—
0.8
Logic “1” input voltage
2.5
—
—
VEN,TH+
Enable positive going threshold
—
—
2.5
VEN,TH-
Enable negative going threshold
0.8
—
—
VIT,TH+
ITRIP positive going threshold
0.37
0.46
0.55
VIT,HYS
ITRIP hysteresis
—
0.07
—
VRCIN, TH+
RCIN positive going threshold
—
8
—
VRCIN, HYS
RCIN hysteresis
—
3
—
VOH
High level output voltage, VBIAS - VO
—
0.9
1.4
VOL
Low level output voltage, VO
—
0.4
0.6
IR21364
9.6
10.4
11.2
IR21364
8.6
9.4
10.2
IR21364
—
1
—
IR21364
9.6
10.4
11.2
IR21364
8.6
9.4
10.2
IR21364
—
1
—
—
—
50
VCCUV+
VCCUVVCCUVHY
VBSUV+
VBSUVVBSUVHY
llk
IQBS
VCC supply undervoltage positive going
threshold
VCC supply undervoltage negative going
threshold
VCC supply undervoltage hysteresis
VBS supply undervoltage positive going
threshold
VBS supply undervoltage negative going
threshold
VBS supply undervoltage
hysteresis
Offset supply leakage current
Quiescent VBS supply current
—
70
120
IQCC
ILIN+
ILINIHIN+
IHINIITRIP+
IITRIPIEN+
IEN-
Quiescent VCC supply current
Input bias current (LOUT = HI)
Input bias current (LOUT = LO)
Input bias current (HOUT = HI)
Input bias current (HOUT = LO)
“High” ITRIP input bias current
“Low” ITRIP input bias current
“High” ENABLE input bias current
“Low” ENABLE input bias current
—
—
-1
—
-1
—
-1
—
-1
0.6
100
—
100
—
3.3
—
100
—
1.3
195
—
195
—
6
—
—
—
IRCIN
RCIN input bias current
—
—
1
Io+
Output high short circuit pulsed current
120
200
—
IoRon_RCIN
Ron_FAULT
Output low short circuit pulsed current
RCIN low on resistance
FAULT low on resistance
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Test
Conditions
250
350
—
—
—
50
50
100
100
V
µA
mA
µA
Io = 20 mA
VB = VS = 600 V
VB1,2,3 = VS1,2,3 =
600 V
VIN = 0 V or 5 V
VLIN = 3.3 V
VLIN = 0 V
VHIN = 3.3 V
VHIN = 0 V
VITRIP = 3.3 V
VITRIP = 0 V
VEN = 3.3 V
VEN = 0 V
Vrcin = 0 V or 15
V
mA
Vo = 0 V,
PW ≤ 10 µs
Vo = 15 V,
PW ≤ 10 µs
Ω
I = 1.5 mA
© 2009 International Rectifier
4
IR21364(S&J)PbF
Dynamic Electrical Characteristics
Dynamic Electrical Characteristics VCC = VBS = VBIAS = 15 V, VS1,2,3 = VSS = COM, TA = 25°C and CL = 1000 pF
unless otherwise specified.
Symbol
Definition
Min
Typ
Max Units
Test Conditions
ton
Turn-on propagation delay
350
500
650
toff
Turn-off propagation delay
375
530
685
tr
tf
Turn-on rise time
Turn-off fall time
ENABLE low to output shutdown propagation
delay
ITRIP to output shutdown propagation delay
—
—
125
50
190
75
300
450
600
VIN, VEN = 0 V or 5 V
500
750
1000
VITRIP = 5 V
tEN
tITRIP
ITRIP blanking time
100
150
—
tFLT
tbl
ITRIP to FAULT propagation delay
400
600
800
tFILIN
Input filter time (HIN, LIN)
100
200
—
tfilterEn
Enable input filter time
100
200
—
Deadtime
Ton, off matching time (on all six channels)
220
—
290
—
360
75
DT matching (Hi->Lo & Lo->Hi on all channels)
pulse width distortion (pwin-pwout)
—
—
—
—
70
75
FAULT clear time RCIN: R = 2 MΩ, C = 1 nF
1.3
1.65
2
DT
MT
MDT
PM
tFLTCLR
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VIN = 0 V & 5 V
ns
VIN = 0 V or 5 V
VITRIP = 5 V
VIN = 0 V & 5 V
External dead time
>450 nsec
ms
PW input =10 µs
VIN = 0 V or 5 V
VITRIP = 0 V
© 2009 International Rectifier
5
IR21364(S&J)PbF
HIN1,2,3
LIN1,2,3
EN
ITRIP
FAULT
RCIN
HO1,2,3
LO1,2,3
Fig. 1. Input/Output Timing Diagram
LIN1,2,3
HIN1,2,
50%
50%
50%
EN
PWIN
ten
HO1,2,3
LO1,2,3
ton
t
r
PW
50
90%
HO1,2,3
LO1,2,3
10%
tof
f
90%
t
f
90%
10%
Fig. 2. Switching Time Waveforms
Fig. 3. Output Enable Timing Waveform
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IR21364(S&J)PbF
Fig. 4. Internal Deadtime Timing Waveforms
RC IN
50%
50%
IT R IP
FA U LT
50%
tflt
50%
90%
Any
Ouput
tfltclr
titrip
Fig. 5. ITRIP/RCIN Timing Waveforms
tin,fi
tin,fi
l
l
on
off
off
on
HIN/LI
on
off
high
lo
w
Fig. 6. Input Filter Function
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© 2009 International Rectifier
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IR21364(S&J)PbF
Lead Definitions
Symbol
VCC
Description
Low side supply voltage
VSS
HIN1,2,3
Logic ground
Logic inputs for high side gate driver outputs (HO1,2,3), in phase
LIN1,2,3
Logic input for low side gate driver outputs (LO1,2,3), in phase
Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, open-drain
output
Logic input to enable I/O functionality. Positive logic, i.e. I/O logic functions When ENABLE is high. No
effect on FAULT and not latched
Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and
RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time TFLTCLR, then
automatically becomes inactive (open-drain high impedance).
External RC network input used to define FAULT CLEAR delay, TFLTCLR, approximately equal to R*C.
When RCIN > 8 V, the FAULT pin goes back into open-drain high-impedance
Low side gate drivers return
High side floating supply
FAULT
EN
ITRIP
RCIN
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
High side gate driver outputs
High voltage floating supply return
Low side gate driver outputs
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© 2009 International Rectifier
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IR21364(S&J)PbF
Functional Block Diagram
VCC
VBS
ITRIP
ENAB LE
FAULT
LO1,2,3
HO1,2,3
<UVCC
15 V
15 V
15 V
15 V
X
<UVBS
15 V
15 V
15 V
X
0V
0V
>VITRIP
0V
X
5V
5V
5V
0V
0 (note 1)
high imp
high imp
0 (note 2)
high imp
0
LIN1,2,3
LIN1,2,3
0
0
0
0
HIN1,2,3
0
0
Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.
Note 2: UVCC is not latched, when VCC > UVCC, FAULT return to high impedance.
Note 3: When ITRIP <VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ VCC = 15 V)
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IR21364(S&J)PbF
Parameter Temperature Trends
Figures 7-39 provide information on the experimental performance of the IR21364 HVIC. The line plotted
in each figure is generated from actual lab data. A small number of individual samples were tested at
three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The
line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have
been connected together to illustrate the understood temperature trend. The individual data points on the
curve were determined by calculating the averaged experimental value of the parameter (for a given
temperature).
800
1000
700
800
600
Exp.
tOFF (ns)
tON (ns)
500
400
300
Exp.
600
400
200
200
100
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Fig. 8. (Toff_Ls1) Turn-off Propagation Delay
vs. Temperature
Fig. 7. (Ton_Ls1 ) Turn-on Propagation Delay
vs. Temperature
800
800
700
700
600
600
Exp.
Exp.
tOFF (ns)
tON (ns)
500
400
300
500
400
300
200
200
100
100
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 9. (Ton_Hs11) Turn-on Propagation Delay
vs. Temperature
Fig. 10. (Toff_Hs21) Turn-off Propagation
Delay vs. Temperature
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© 2009 International Rectifier
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IR21364(S&J)PbF
250
120
100
200
tF (ns)
tR (ns)
80
150
Exp.
60
100
40
50
Exp.
20
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
25
75
100
125
Fig. 12. Turn-off Fall Time vs. Temperature
100
100
80
80
MDT (ns)
MT (ns)
Fig. 11. Turn-on Rise Time vs. Temperature
60
50
Temperature (oC)
Temperature (oC)
Exp.
40
60
40
Exp.
20
20
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
25
Temperature (oC)
50
75
100
125
Temperature (oC)
Fig. 13. Ton, off matching time vs.
Temperature
Fig. 14. DT matching time vs. Temperature
100
1000
80
800
tITRIP (ns)
PM (ns)
Exp.
60
40
Exp.
600
400
200
20
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 16. ITRIP to Output Shutdown Propagation
Delay vs. Temperature
Fig. 15. Pulse Width Distortion vs.
Temperature
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© 2009 International Rectifier
11
IR21364(S&J)PbF
1200
1000
800
800
TEN (nS)
DLTon1 (ns)
1000
600
600
Exp.
400
400
Exp.
200
200
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
25
Temperature (oC)
50
75
100
125
Temperature (oC)
Fig. 17. Dead Time vs. Temperature
Figure 18. EN to Output Shutdown Time vs.
Temperature
1000
5.0
900
800
4.0
TFLTCLR (mS)
tFLT (ns)
700
Exp.
600
500
400
300
200
3.0
2.0
Exp.
1.0
100
0
-50
-25
0
25
50
75
100
125
0.0
-50
-25
0
25
Temperature (oC)
50
75
100
125
Temperature (oC)
Fig. 19. ITRIP to FAULT Indication Delay vs.
Temperature
Fig. 20. FAULT Clear Time vs. Temperature
6.0
2.5
2.0
LIN1_VTH- (V)
LIN1_VTH+ (V)
4.5
3.0
Exp.
1.5
Exp.
1.0
1.5
0.5
0.0
-50
-25
0
25
50
75
100
125
Temperature (oC)
0.0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 21. Input Positive Going Threshold vs.
Temperature
Fig. 22. Input Negative Going Threshold vs.
Temperature
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© 2009 International Rectifier
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IR21364(S&J)PbF
800
800
700
700
600
EXP.
p.
500
V IT,TH- (mV)
VIT,TH+ (mV)
600
400
300
500
Exp.
400
300
200
200
100
100
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 24. ITRIP Input Negative Going Threshold
vs. Temperature
Fig. 23. ITRIP Input Positive Going Threshold
vs. Temperature
600
1600
500
VOH_LO1 (mV)
VOL_LO1 (mV)
1200
400
300
Exp.
200
800
Exp.
400
100
0
0
-50
-25
0
25
50
75
100
125
-50
Temperature (oC)
0
25
50
75
100
125
Temperature (oC)
Fig. 25. Low Level Output Voltage vs.
Temperature
Fig. 26. High Level Output Voltage vs.
Temperature
2.5
120
100
2.0
ileak1 (µA)
80
RON,FLT (Ω)
-25
60
1.5
1.0
Exp.
40
0.5
Exp.
20
0
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
0.0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 28. Offset Supply Leakage Current vs.
Temperature
Fig. 27. FAULT Low On-Resistance vs.
Temperature
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2.0
2.0
1.5
1.5
I QCC0 (mA)
I QCC1 (mA)
IR21364(S&J)PbF
1.0
1.0
Exp.
Exp.
0.5
0.5
0.0
-50
-25
0
25
50
75
100
0.0
-50
125
-25
0
Temperature (oC)
Fig. 29. Quiescent VCC Supply Current vs.
Temperature
50
75
100
125
Fig. 30. Quiescent VCC Supply Current vs.
Temperature
80
140
70
120
60
100
50
IQBS11 (µA)
IQBS10 (µA)
25
Temperature (oC)
Exp.
40
30
80
60
Exp.
40
20
20
10
0
-50
-25
0
25
50
75
100
0
-50
125
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Fig. 31. Quiescent VBS Supply Current vs.
Temperature
Fig. 32. Quiescent VBS Supply Current vs.
Temperature
18.0
15.0
15.0
12.0
12.0
VCCUV+ (V)
VCCUV- (V)
Exp.
9.0
6.0
Exp.
9.0
6.0
3.0
0.0
-50
3.0
-25
0
25
50
75
100
125
Temperature (oC)
0.0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 34. VCC Supply Undervoltage Positive
Going Threshold vs. Temperature
Fig. 33. VCC Supply Undervoltage Negative
Going Threshold vs. Temperature
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IR21364(S&J)PbF
15.0
15.0
12.0
12.0
Exp.
VBSUV+ (V)
VBSUV- (V)
Exp.
9.0
6.0
3.0
9.0
6.0
3.0
0.0
-50
-25
0
25
50
75
100
0.0
-50
125
-25
0
Temperature (oC)
25
50
75
100
125
Temperature (oC)
Fig. 35. VBS Supply Undervoltage Negative
Going Threshold vs. Temperature
Fig. 36. VBS Supply Undervoltage Positive
Going Threshold vs. Temperature
0.5
0.0
-50
-25
0
25
50
75
100
125
0.4
-0.1
-0.2
I O- (mA)
IO+ (mA)
Exp.
Exp.
p.
0.3
0.2
-0.3
0.1
-0.4
0.0
-50
-0.5
-25
Temperature (oC)
0
25
50
75
100
125
Temperature (oC)
Fig. 37. Output High Short Circuit Pulsed
Current vs. Temperature
0
-50
-25
Fig. 38. Output Low Short Circuit Pulsed Current
vs. Temperature
0
25
50
75
100
125
Vs1_RST_domin (V)
-2
-4
-6
Exp.
-8
-10
-12
-14
Temperature (oC)
Fig. 39. Max -VS vs. Temperature
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IR21364(S&J)PbF
Case Outlines
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IR21364(S&J)PbF
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17
IR21364(S&J)PbF
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
11.90
12.10
B
3.90
4.10
C
23.70
24.30
D
11.40
11.60
E
10.80
11.00
F
18.20
18.40
G
1.50
n/a
H
1.50
1.60
28SOICW
Imperial
Min
Max
0.468
0.476
0.153
0.161
0.933
0.956
0.448
0.456
0.425
0.433
0.716
0.724
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 28SOICW
Metric
Imperial
Code
Min
Max
Min
Max
A
329.60
330.25
12.976
13.001
B
20.95
21.45
0.824
0.844
C
12.80
13.20
0.503
0.519
D
1.95
2.45
0.767
0.096
E
98.00
102.00
3.858
4.015
F
n/a
30.40
n/a
1.196
G
26.50
29.10
1.04
1.145
H
24.40
26.40
0.96
1.039
www.irf.com
© 2009 International Rectifier
18
IR21364(S&J)PbF
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR 44PLCC
Metric
Imperial
Code
Min
Max
Min
Max
A
23.90
24.10
0.94
0.948
B
3.90
4.10
0.153
0.161
C
31.70
32.30
1.248
1.271
D
14.10
14.30
0.555
0.562
E
17.90
18.10
0.704
0.712
F
17.90
18.10
0.704
0.712
G
2.00
n/a
0.078
n/a
H
1.50
1.60
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 44PLCC
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
38.4
G
34.7
35.8
H
32.6
33.1
www.irf.com
Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
1.511
1.366
1.409
1.283
1.303
© 2009 International Rectifier
19
IR21364(S&J)PbF
ORDER INFORMATION
28-Lead SOIC Tape & Reel IR21364STRPbF
44-Lead PLCC Tape & Reel IR21364JTRPbF
28-Lead SOIC IR21364SPbF
44-Lead PLCC IR21364JPbF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
© 2009 International Rectifier
20