ADVANCE INFORMATION Data Sheet PD 60178A IR1175 Synchronous Rectifier Driver Features n Provides constant and proper gate drive to power MOSFETs regardless of transformer output n Minimizes loss due to power MOSFET body drain diode conduction n Stand alone operation - no ties to primary side n Schmitt trigger input with double pulse suppression allows operation in noisy environments n High current drive capability - 2A n High speed operation - 2MHz Product Summary Vdd 5Vdc IO+/- 2A/2A Fmax 2MHz Max lead time 500nsec n Adaptable to multiple topologies (such as singleended forward, double-ended forward) Description The IR1175 is a high speed CMOS controller designed to drive N-channel power MOSFETs used as synchronous rectifiers in high current, high frequency forward converters with output voltages equal or below 5VDC. Schmitt trigger inputs with double pulse suppression allow the controller to operate in noisy environments. The circuit does not require any ties to the primary side and derives its operating power directly from the secondary. The circuit functions by anticipating transformer output transitions, then turns the power MOSFETs on or off before the transitions of the transformer to minimize body drain diode conduction and reduce associated losses. Turn on/off lead time can be adjusted to accommodate a variety of power MOSFET sizes and circuit conditions. The IR1175 also provides gate drive overlap/dead-time control via external components to further minimize diode conduction by nulling effects of secondary loop and device package inductance. Package 20 Lead Surface Mount (SSOP-20) IR1175 ADVANCE INFORMATION Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. Symbol Definition Min. Max. Vdd Supply voltage — 7 Units VDC Iin Input clamp current — +/- 10 mA DC PD Power dissipation (SSOP-20) — 400 mW Rth JC Thermal resistance (SSOP-20) junction-to-case — 28.5 °C/W RthJA Thermal resistance (SSOP-20) junction-to-ambient — 90.5 °C/W TJ Junction temperature — 150 °C TS Storage temperature -55 150 °C TL Lead temperature (soldering, 10 seconds) — 300 °C Recommended Operating Conditions Symbol Max. Units — 5 — VDC Ambient temperature -40 — 85 °C Freq Operating frequency 250 Rbias Required bias resistor (+/- 1%) Vdd TA Supply voltage operating range Min. — Typ. — 500 KHz 69.8 — KW UV Voltage at UVSET pin 1.75 — 2.25 VDC Xin Maximum voltage at X1 and X2 inputs — — 5.6 VDC Cd1/Cd2 Capacitance at pins DTIN1 and DTIN2 — — 22 pF 470 — — KW Cf 2 Definition Loop filter bypass capacitor www.irf.com IR1175 ADVANCE INFORMATION Dynamic Electrical Characteristics Vdd=5V, TA = 25 oC, Rbias = 69.8K unless otherwise specified. Symbol Definition Vdd Supply voltage operating range Iqdd Vdd quiescent current (Vin=0 or 5V, Iout=0) Freq Operating frequency Min. Typ. Max. Units 4.0 — 5.5 VDC — 3 5 mADC 100 — 2000 KHz UVSET+ UVSET positive going threshold 1.10 — 1.4 V UVSET- UVSET negative going threshold 0.8 — 1.1 V VDC Vxth+ X1/X2 Input positive going threshold — 1.4 — Vxth- X1/X2 Input negative going threshold — 1.0 — VDC Tadv Externally adjustable lead time (advance) — — 500 nsec Externally adjustable dead-time for Q1 and Q2 20 — — nsec Q1,Q2 output sink current (Vdd=5.0V, — — 2 A — — 2 A — 20 — nsec 20 — nsec Td Isink pulsed, 10 usec) Isource Q1,Q2 output source current (Vdd=5.0V, pulsed, 10 usec) tio Input to output delay (PLL bypassed, cross coupled mode) tr Gate turn-on rise time (C1=1000pf, Vdd=5V) — tf Gate turn-off fall time (C1=1000pf, Vdd=5V) — 20 — nsec Cross-over voltage (Vdd=5Vdc, DTIN shorted to — 2.5 — VDC Vtr DTOUT, C1=1000pf) Fig. 3 Rbias Required bias resistor 68 — 71 KW Vbias Voltage at Rbias pin — 1.25 — VDC -20 — 20 nsec Ichgpump Tjitter Charge pump output current (at VFLTR pin) — 50 — mADC Vchgpump Charge pump output voltage (at VFLTR pin) 1.3 1.5 1.7 VDC — 62 — KHz/ Kvco_dc www.irf.com Phase-lock loop output jitter PLL Vco DC gain 3 IR1175 ADVANCE INFORMATION Lead Definitions and Assignments Symbol Description AVDD Power - + 5 VDC to MOSFET drivers Q1 Output - gate drive for Q1 power MOSFET DTOUT1 Output - sets dead time for Q1 output - used with DTIN1 DTIN1 Input - sets dead time for Q1 - used with DTOUT1 RADV1 Output - sets lead time (advance) for Q1 VFLTR1 Output - PLL loop filter for Q1 output RVCO1 Output - sets PLL center frequency for Q1 output X1 Input - transformer input for Q1 VDD Power - +5 Vdc for internal logic UVSET Input - sets UVLO+ If this pin is pulled below 1.25VDC externally, then both Q1 and Q2 outputs will be at Vss (disabled) RBIAS Output - connected to 249K +/- 1% resistor - sets operating current AVSS Ground for logic supply (AVDD) X2 Input - transformer input for Q2 RVCO2 Output - sets PLL center frequency for Q2 output VFLTR2 Output - PLL loop filter for Q2 RADV2 Output - sets lead time (advance) for Q2 DTIN2 Input - sets dead time for Q2 - used with DTOUT2 RBIAS 11 X2 13 RVCO2 14 VFLTR2 15 RADV2 16 DTIN1 17 DTOUT1 18 Output - gate drive for Q2 power MOSFET VSS 19 Ground for MOSFET driver supply (VDD) Q2 Q2 20 VSS AVSS 12 DTOUT2 Output - sets dead time for Q2 - used with DTIN2 20 Lead SSOP 4 *VDD Q1 DTOUT2 DTIN2 RADV1 VFLTRI RVCO1 X1 AVDD UVSET 1 2 3 4 5 6 7 8 9 10 IR1175 www.irf.com ADVANCE INFORMATION IR1175 Fig. 1 Typical application circuit when supply Vout < 5.0 VDC Fig. 2 Typical application circuit when supply Vout = 5.0 VDC www.irf.com 5 IR1175 ADVANCE INFORMATION Fig. 3 Gate drive characteristics and definitions Phase Lock Loop Design Equations: 1 - Resistor to set VCO Ceter Frequency: W ) = 143 x [Vchgpump(VDC) / fvco(KHz)] x Kvco _ dc(KHz/m mA) Rvco (KW Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz Rvco = 143 x [1.5 /300] x 62 Hz/mA = 44.33 KW 2 - Small Signal gain for VCO: mA)/(7 x Rvco(KW W) Kvco_ac (KHz/Volt) = 1E3 x Kvco_dc (KHz/m Example (B): Choosing same conditions as in example A: Kvco_ac = 1E3 x 62 / (7 x 44.33) = 199.9 KHz/volt 6 www.irf.com ADVANCE INFORMATION IR1175 3 - PLL Natural frequency: ωn =2πfn(KHz)= √ Ichpump(uA) x Kvco_ac(KHz/V) / C(nF) Choose Cf such that Cf=C/16 (Minimum value for Cf=470pF) 4 - PLL Damping factor calculations: P = πE-3 x Rf (KOhms) x C(nF) x fn(KHz) Typical value for P is 0.707. (Critically damped) 5 - Advance timing: Tadv(nsec) = RADV (KOhms)*10 - 10 Where RADV is resistance from RADV1 or RADV2 to ground. Example C: RADV=10Kohms will result in Tadv=10*10 - 10 =90 nsec . 6- Dead time calculations: Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For Vdd=5 V) Where Rdt is resistance between pins DTIN1 and DTOUT1 or DTIN2 and DTOUT2. Cdt is capacitance from DTIN1 or DTIN2 to ground. Example D: Rdt=10Kohms and Cdt=22pF will result in: Td=156.8 nsec Fig. 4 PLL loop filter component definitions www.irf.com 7 IR1175 ADVANCE INFORMATION Fig. 5 IR1175 Block Diagram 8 www.irf.com ADVANCE INFORMATION IR1175 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171-0021 Tel: 8133 983 0086 IR HONG KONG: Unit 308, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2803-7380 Data and specifications subject to change without notice. 1/27/2000 www.irf.com 9