INFINEON ICE3DS01LG

Datasheet, V2.0, 15 May 2003
PWM-FF IC
ICE3DS01L
ICE3DS01LG
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
ICE3DSO1L(G)
Revision History:
2003-05-15
Datasheet
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Subjects (major changes since last revision)
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Edition 2003-05-15
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be endangered.
F3
Off-Line SMPS Current Mode Controller
with integrated 500V Startup Cell
ICE3DS01L
ICE3DS01LG
Product Highlights
P-DIP-8-6
test
• Active Burst Mode to reach the lowest
Standby Power Requirements < 100mW
• Latched Off Mode to increase Robustness
and Safety of the System
• Adjustable Blanking Window for High Load
Jumps to increase Reliability
P-DSO-8-8
Features
Description
•
The F3 Controller provides Active Burst Mode to reach the
lowest Standby Power Requirements <100mW at no load.
As during Active Burst Mode the controller is always active
there is an immediate response on load jumps possible
without any black out in the SMPS. In Active Burst Mode
the ripple of the output voltage can be reduced <1%.
Furthermore Latched Off Mode is entered in case of
Overtemperature, Overvoltage or Short Winding. If
Latched Off Mode is entered only the disconnection from
the main line can reset the Controller. Auto Restart Mode
is entered in case of failure modes like open loop or
overload. By means of the internal precise peak current
limitation the dimension of the transformer and the
secondary diode can be lower which leads to more cost
efficiency. An adjustable blanking window prevents the IC
from entering Auto Restart Mode or Active Burst Mode in
case of high Load Jumps.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Active Burst Mode for lowest Standby Power
@ light load controlled by Feedback Signal
Fast Load Jump Response in Active Burst Mode
500V Startup Cell switched off after Start Up
110kHz internally fixed Switching Frequency
Latched Off Mode for Overtemperature Detection
Latched Off Mode for Overvoltage Detection
Latched Off Mode for Short Winding Detection
Auto Restart Mode for Overload and Open Loop
Auto Restart Mode for VCC Undervoltage
User defined Soft Start
Minimum of external Components required
Max Duty Cycle 72%
Overall Tolerance of Current Limiting < ±5%
Internal Leading Edge Blanking
Soft Switching for Low EMI
Typical Application
+
Converter
DC Output
Snubber
CBulk
85 ... 270 VAC
-
VCC
HV
Startup Cell
Power
Management
CVCC
PWM Controller
Current Mode
Gate
Precise Low
Tolerance Peak
Current Limitation
CS
RSense
Control Unit
FB
Active Burst Mode
GND
Latched Off Mode
SoftS
Auto Restart Mode
CSoftS
ICE3DS01/G
Type
Ordering Code
FOSC
Package
ICE3DS01L
ES Samples available
110kHz
P-DIP-8-6
ICE3DS01LG
Q67040-S4549-A102
110kHz
P-DSO-8-8
Version 2.0
3
15 May 2003
F3
ICE3DS01L/LG
Table of Contents
Page
1
1.1
1.2
1.3
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration with P-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration with P-DSO-8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2
Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.3
3.6.3.1
3.6.3.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Version 2.0
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15 May 2003
F3
ICE3DS01L/LG
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration with P-DIP-8-6
Pin
1.2
Pin Configuration with P-DSO-8-8
Symbol
Function
Pin
Symbol
Function
1
SoftS
Soft-Start
1
SoftS
Soft-Start
2
FB
Feedback
2
FB
Feedback
3
CS
Current Sense
3
CS
Current Sense
4
HV
High Voltage Input
4
Gate
5
HV
High Voltage Input
5
HV
6
Gate
Driver Stage Output
6
N.C.
Not connected
7
VCC
Controller Supply Voltage
7
VCC
Controller Supply Voltage
8
GND
Controller Ground
8
GND
Controller Ground
Package P-DIP-8-6
Driver Stage Output
High Voltage Input
Package P-DSO-8-8
SoftS
1
8
GND
SoftS
1
8
GND
FB
2
7
VCC
FB
2
7
VCC
CS
3
6
Gate
CS
3
6
N.C.
HV
4
5
HV
Gate
4
5
HV
Figure 1
Note:
Pin Configuration P-DIP-8-6(top view)
Figure 2
Pin Configuration P-DSO-8-8(top view)
Pin 4 and 5 are shorted within the DIP
package.
Version 2.0
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F3
ICE3DS01L/LG
Pin Configuration and Functionality
1.3
Pin Functionality
SoftS (Soft Start & Auto Restart Control)
The SoftS pin combines the function of Soft Start in
case of Start Up and Auto Restart Mode and the
controlling of the Auto Restart Mode in case of error
detection. Furthermore the blanking window for high
load jumps is adjusted by means of the external
capacitor connected to SoftS.
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst
Mode of the controller.
CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
external PowerMOS. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
output is immediately switched off. Furthermore the
current information is provided for the PWMComparator to realize the Current Mode.
Gate
The Gate pin is the output of the internal driver stage
connected to the Gate of an external PowerMOS.
HV (High Voltage)
The HV pin is connected to the rectified DC input
voltage. It is the input for the integrated 500V Startup
Cell.
VCC (Power supply)
The VCC pin is the positive supply of the IC. The
operating range is between 8.5V and 21V.
GND (Ground)
The GND pin is the ground of the controller.
Version 2.0
6
15 May 2003
Figure 3
Version 2.0
FB
CSoftS
7
1.32V
4.0V
4.8V
5.4V
4.0V
21V
VCC
ICE3DS01/G
Control Unit
10pF
5k
RFB
6.5V
S1
4.4V
5k
RSoftS
C6
C5
C4
C3
C2
C1
3.25k
T1
T2
1
G2
&
G1
T3
1
G3
G5
&
&
G4
Tj >140°C
&
G11
&
G6
Active Burst
Mode
Auto Restart
Mode
Latched Off
Mode
Power-Down
Reset
Latched Off
Mode Reset
VVCC < 6V
Internal Bias
Power Management
Thermal Shutdown
Spike
Blanking
8.0us
1V
6.5V
15V
6.5V
x3.7
C9
C8
PWM
Comparator
&
G7
Soft-Start
Comparator
Current Mode
PWM OP
0.85V
0.3V
C7
Soft Start
8.5V
Undervoltage Lockout
Voltage
Reference
HV
C11
&
G10
C12
C10
FF1
S
R Q
Vcsth
1pF
&
G9
Gate
Driver
D1
10k
PWM Section
VCC
CVCC
Current Limiting
Leading
Edge
Blanking
220ns
1.66V
0.257V
1
G8
0.72
Propagation-Delay
Compensation
Spike
Blanking
190ns
Clock
Duty Cycle
max
Oscillator
Startup Cell
VCC
CS
Gate
GND
RSense
Snubber
+
Converter
DC Output
VOUT
-
2
SoftS
85 ... 270 VAC
CBulk
F3
ICE3DS01L/LG
Representative Blockdiagram
Representative Blockdiagram
Representative Blockdiagram
15 May 2003
F3
ICE3DS01L/LG
Functional Description
3
Functional Description
All values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1
Introduction
The F3 is the further development of the F2 to meet the
requirements for the lowest Standby Power at
minimum load and no load conditions. A new fully
integrated Standby Power concept is implemented into
the IC in order to keep the application design easy.
Compared to F2 no further external parts are needed to
achieve the lowest Standby Power. An intelligent
Active Burst Mode is used for this Standby Mode. After
entering this mode there is still a full control of the
power conversion by the secondary side via the same
optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage
ripple on Vout is minimized. Vout is further on well
controlled in this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore a high voltage startup cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 15V is exceeded. The external
startup resistor is no longer necessary. Power losses
are therefore reduced. This increases the efficiency
under light load conditions dramatically.
The Soft-Start capacitor is also used for providing an
adjustable blanking window for high load jumps. During
this time window the overload detection is disabled.
With this concept no further external components are
necessary to adjust the blanking window.
A new Latched Off Mode is implemented into the IC in
order to increase the robustness and safety of the
system. Latched Off Mode is only entered if very
dangerous conditions occur that damage the SMPS if
not switched off immediately. A restart of the system
can then only be done by disconnecting the AC line.
Auto Restart Mode reduces the average power
conversion to a minimum. In this mode malfunctions
are covered that could lead to a destruction of the
SMPS if no dramatically reduced power limitation is
provided over time. Once the malfunction is removed
normal operation is immediately started after the next
Start Up Phase.
The internal precise peak current limitation reduces the
costs for the transformer and the secondary diode. The
influence of the change in the input voltage on the
power limitation can be avoided together with the
integrated
Propagation
Delay
Compensation.
Therefore the maximum power is nearly independent
on the input voltage that is required for wide range
Version 2.0
8
SMPS. There is no need for an extra over sizing of the
SMPS, e.g. the transformer or PowerMOS.
3.2
Power Management
Startup Cell
HV
VCC
Power Management
Undervoltage Lockout
15V
Internal Bias
Latched Off Mode
Reset
VVCC < 6V
8.5V
Power-Down Reset
Voltage
Reference
6.5V
Auto Restart Mode
Active Burst Mode
T1
Latched Off Mode
SoftS
Figure 4
Power Management
The Undervoltage Lockout monitors the external
supply voltage VVCC. When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts
to charge the external capacitor CVCC which is
connected to the VCC pin. The VCC charge current
that is provided by the Startup Cell from the HV pin is
1.05mA. When VVCC exceeds the on-threshold
VCCon=15V the internal voltage reference and bias
circuit are switched on. Then the Startup Cell is
switched off by the Undervoltage Lockout and therefore
also the power losses are switched off caused by the
Startup Cell which is connected to the bus voltage
(HV). To avoid uncontrolled ringing at switch-on a
hysteresis is implemented. The switch-off of the
15 May 2003
F3
ICE3DS01L/LG
Functional Description
controller can only take place after Active Mode was
entered and VVCC falls below 8.5V.
The maximum current consumption before the
controller is activated is about 170µA.
When VVCC falls below the off-threshold VCCoff=8.5V the
internal reference is switched off and the Power Down
reset let T1 discharging the soft-start capacitor CSoftS at
pin SoftS. Thus it is ensured that at every startup cycle
the voltage ramp at pin SoftS starts at zero.
The internal Voltage Reference is switched off if
Latched Off Mode or Auto Restart Mode is entered.
The current consumption is then reduced to 300µA.
When Active Burst Mode is entered the internal Bias is
switched off in order to reduce the current consumption
below 1.1mA while keeping the Voltage Reference still
active as this is necessary in this mode.
In case Latched Off Mode is entered VCC needs to be
lowered below 6V to reset the Latched Off Mode. This
is done usually by disconnecting the SMPS from the
AC line.
3.3
Startup Phase
capacitor CSofts in combination with the internal pull up
resistor RSoftS determines the duty cycle until VSoftS
exceeds 4V.
In the beginning CSoftS is immediately charged up to
approx. 1V by T2. Therefore the Soft Start Phase takes
place between 1V and 4V. Above VSoftsS = 4V there is
no longer duty cycle limitation DCmax is controlled by
comparator C7 as comparator C2 blocks the gate G7
(see Figure 6).The maximum charge current in the very
first phase when VSoftS is below 1V is limited to 1.9mA.
VSoftS
max. Startup Phase
5.4V
4V
1V
max. Soft Start Phase
DCmax
t
6.5V
DC1
3.25k
RSoftS
DC2
T2
T3
SoftS
1V
t1
Figure 6
CSoftS
Soft Start
Soft-Start
Comparator
C7
&
Gate Driver
G7
C2
4V
0.85V
x3.7
t2 t
Startup Phase
By means of this extra charge stage there is no delay
in the beginning of the Startup Phase when there is still
no switching. Furthermore Soft Start is finished at 4V to
have faster the maximum power capability. The duty
cycles DC1 and DC2 are depending on the mains and
the primary inductance of the transformer. The
limitation of the primary current by DC2 is related to
VSoftS = 4V. But DC1 is related to a maximum primary
current which is limited by the internal Current Limiting
with CS = 1V. Therefore the maximum Startup Phase
is divided into a Soft Start Phase until t1 and a phase
from t1 until t2 where maximum power is provided if
demanded by the FB signal.
CS
PWM OP
Figure 5
Soft Start
During the Startup Phase a Soft Start is provided. A
signal VSoftS which is generated by the external
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15 May 2003
F3
ICE3DS01L/LG
Functional Description
3.4
PWM Section
VCC
0.72
PWM Section
Oscillator
PWM-Latch
Duty Cycle
max
1
Gate
Z1
Clock
Soft Start
Comparator
PWM
Comparator
FF1
1
G8
Gate Driver
S
R
Q
&
Figure 8
G9
Current
Limiting
Comparator
C3
Gate
Figure 7
Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external
Power Switch threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
VGate
ca. t = 130ns
PWM Section
3.4.1
Oscillator
The oscillator generates a frequency fswitch = 110kHz. A
resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.72.
3.4.2
PWM-Latch FF1
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the external Power Switch
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator, the
Current-Limit comparator or comparator C3. In case of
resetting the driver is shut down immediately.
CLoad = 1nF
5V
t
Figure 9
Gate Rising Slope
Thus the leading switch on spike is minimized. When
the external Power Switch is switched off, the falling
shape of the driver is slowed down when reaching 2V
to prevent an overshoot below ground. Furthermore the
driver circuit is designed to eliminate cross conduction
of the output stage.
3.4.3
Gate Driver
The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents and which
is equipped with a zener diode Z1 (see Figure 8) in
order to improve the control of the Gate attached power
transistors as well as to protect them against
undesirable gate overvoltages.
The Gate Driver is active low at voltages below the
undervoltage lockout threshold VVCCoff.
Version 2.0
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15 May 2003
F3
ICE3DS01L/LG
Functional Description
3.5
Current Limiting
PWM Latch
FF1
Latched Off
Mode
Current Limiting
Spike
Blanking
190ns
1.66V
C11
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
3.5.1
Leading Edge Blanking
VSense
Propagation-Delay
Compensation
Vcsth
Vcsth
C10
PWM-OP
tLEB = 220ns
Leading
Edge
Blanking
220ns
&
t
G10
C12
Figure 11
0.257V
1pF
10k
Active Burst
Mode
D1
CS
Figure 10
Current Limiting
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
external Power Switch is sensed via an external sense
resistor RSense . By means of RSense the source current
is transformed to a sense voltage VSense which is fed
into the pin CS. If the voltage VSense exceeds the
internal threshold voltage Vcsth the comparator C10
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the Power Switch in case of Current Limiting.
The influence of the AC input voltage on the maximum
output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a
short winding in the transformer or the secondary diode
is shorten. To ensure that there is no accidentally
entering of the Latched Mode by the comparator C11 a
spike blanking with 190ns is integrated in the output
path of comparator C11.
Version 2.0
Leading Edge Blanking
Each time when the external Power Switch is switched
on a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. To avoid a premature
termination of the switching pulse this spike is blanked
out with a time constant of tLEB = 220ns. During that
time there can’t be an accidentally switch off of the gate
drive.
11
3.5.2
Propagation Delay Compensation
In case of overcurrent detection the shut down of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current Ipeak which depends on
the ratio of dI/dt of the peak current (see Figure 12).
S igna l2
I S en s e
I p e ak 2
I p e ak 1
I L im it
S ig nal1
t P rop a g atio n D elay
I O ve rsh o ot2
I O v e rs ho o t1
t
Figure 12
Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
15May 2003
F3
ICE3DS01L/LG
Functional Description
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold Vcsth
and the switch off of the external Power Switch is
compensated over temperature within a wide range.
Current Limiting is now possible in a very accurate way
(see Figure 13).
E.g. Ipeak = 0.5A with RSense = 2. Without Propagation
Delay Compensation the current sense threshold is set
to a static voltage level Vcsth=1V. A current ramp of
dI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and a
propagation delay time of i.e. tPropagation Delay =180ns
leads then to an Ipeak overshoot of 12%. By means of
propagation delay compensation the overshoot is only
about 2% (see Figure 13).
with compensation
3.6
Control Unit
The Control Unit contains the functions for Active Burst
Mode, Auto Restart Mode and Latched Off Mode. The
Active Burst Mode and the Auto Restart Mode are
combined with an Adjustable Blanking Window which is
depending on the external Soft Start capacitor. By
means of this Adjustable Blanking Window an
accidentally entering of the Active Burst Mode is
avoided. Furthermore the overload detection can be
deactivated for a certain time.
3.6.1
Adjustable Blanking Window
SoftS
6.5V
without compensation
V
RSoftS
5k
1,3
1,25
VSense
1,2
4.4V
1,15
1,1
1,05
S1
1
1
&
G2
G4
0,95
0,9
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
V
2
µs
dVSense
dt
Figure 13
Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic threshold voltage Vcsth (see Figure
14). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
V OSC
C3
5.4V
Auto
Restart
Mode
&
4.8V
C4
G5
Active
Burst
Mode
m a x. D u ty C ycle
o ff tim e
V Sense
P ro p a ga tio n D e la y
1.32V
Control Unit
Figure 15
S igna l1
S ignal2
t
Version 2.0
G6
C6
t
V c s th
Figure 14
&
FB
Dynamic Voltage Threshold Vcsth
12
Adjustable Blanking Window
VSoftS is clamped at 4.4V by the closed switch S1 after
the SMPS is settled. If overload occurs VFB is
exceeding 4.8V. Auto Restart Mode can’t be entered as
the gate G5 is still blocked by the comparator C3. But
after VFB has exceeded 4.8V the switch S1 is opened
via the gate G2. The external Soft Start capacitor can
now be charged further by the integrated pull up
resistor RSoftS. The comparator C3 releases the gates
15 May 2003
F3
ICE3DS01L/LG
Functional Description
G5 and G6 once VSofts has exceeded 5.4V. Therefore
there is no entering of Auto Restart Mode possible
during this charging time of the external capacitor
CSoftS. The same procedure happens to the external
Soft Start capacitor if a low load condition is detected
by comparator C6 when VFB is falling below 1.32V.
Only after VSoftS has exceeded 5.4V and VFB is still
below 1.32V Active Burst Mode is entered. Once Active
Burst Mode is entered gate G4 is blocked to ensure
that the blanking window is only active before entering
the Active Burst Mode.
3.6.2
Active Burst Mode
The controller provides Active Burst Mode for low load
conditions at VOUT. Active Burst Mode increases
significantly the efficiency at light load conditions while
supporting a low ripple on VOUT and fast response on
load jumps. During Active Burst Mode which is
controlled only by the FB signal the IC is always active
and can therefore immediately response on fast
changes at the FB signal. The Startup Cell is kept
switched off to avoid increased power losses for the
self supply.
SoftS
6.5V
RSoftS
5k
Internal Bias
4.4V
&
G4
S1
Current
Limiting
&
C3
G10
5.4V
4.8V
C4
FB
C5
4.0V
&
G6
Active
Burst
Mode
C6
1.32V
Control Unit
Figure 16
Version 2.0
The Active Burst Mode is located in the Control Unit.
Figure 16 shows the related components.
3.6.2.1
Entering Active Burst Mode
The FB signal is always observed by the comparator
C6 if the voltage level falls below 1.32V. In that case the
switch S1 is released which allows the capacitor CSoftS
to be charged starting from the clamped voltage level
at 4.4V in normal operating mode. The gate G11 is
blocked before entering Active Burst Mode. If VSoftS
exceeds 5.4V the comparator C3 releases the gate G6
to enter the Active Burst Mode. The time window that is
generated by combining the FB and SoftS signals with
gate G6 avoids a sudden entering of the Active Burst
Mode due to large load jumps. This time window can be
adjusted by the external capacitor CSoftS.
After entering Active Burst Mode a burst flag is set
which blocks the gate G4 and the internal bias is
switched off in order to reduce the current consumption
of the IC down to ca. 1.1mA. In this Off State Phase the
IC is no longer self supplied so that therefore CVCC has
to provide the VCC current (see Figure 17).
Furthermore gate G11 is then released to start the next
burst cycle once 1.32V is again exceeded.
It has to be ensured by the application that the VCC
remains above the Undervoltage Lockout Level of 8.5V
to avoid that the Startup Cell is accidentally switched
on. Otherwise power losses are significantly increased.
The minimum VCC level during Active Burst Mode is
depending on the load conditions and the application.
The lowest VCC level is reached at no load conditions
at VOUT.
3.6.2.2
Working in Active Burst Mode
After entering the Active Burst Mode the FB voltage
rises as VOUT starts to decrease due to the inactive
PWM section. Comparator C5 observes the FB signal
if the voltage level 4V is exceeded. In that case the
internal circuit is again activated by the internal Bias to
start with switching. As now in Active Burst Mode the
gate G10 is released the current limit is only 0.257V to
reduce the conduction losses and to avoid audible
noise. If the load at VOUT is still below the starting level
for the Active Burst Mode the FB signal decreases
down to 1.32V. At this level C6 deactivates again the
internal circuit by switching off the internal Bias. The
gate G11 is released as after entering Active Burst
Mode the burst flag is set. If working in Active Burst
Mode the FB voltage is changing like a saw tooth
between 1.32V and 4V (see figure 17).
3.6.2.3
Leaving Active Burst Mode
The FB voltage immediately increases if there is a high
load jump. This is observed by comparator C4. As the
current limit is ca. 26% during Active Burst Mode a
certain load jump is needed that FB can exceed 4.8V.
At this time C4 resets the Active Burst Mode which also
&
G11
Active Burst Mode
13
15 May 2003
F3
ICE3DS01L/LG
Functional Description
blocks C12 by the gate G10. Maximum current can now
be provided to stabilize VOUT.
VFB
Entering Active
Burst Mode
4.80V
Leaving Active
Burst Mode
4.00V
3.6.3
Protection Modes
The IC provides several protection features which are
separated into two categories. Some enter Latched Off
Mode, the others enter Auto Restart Mode. The
Latched Off Mode can only be reset if VCC is falling
below 6V. Both modes prevent the SMPS from
destructive states. The following table shows the
relationship between possible system failures and the
chosen protection modes.
1.32V
VSoftS
t
Blanking Window
VCC Overvoltage
Latched Off Mode
Overtemperature
Latched Off Mode
Short Winding/Short Diode Latched Off Mode
5.40V
4.40V
VCS
1.00V
t
Overload
Auto Restart Mode
Open Loop
Auto Restart Mode
VCC Undervoltage
Auto Restart Mode
Short Optocoupler
Auto Restart Mode
3.6.3.1
Current limit level during
Active Burst Mode
Latched Off Mode
CS
Latched Off
Mode Reset
VVCC < 6V
0.257V
VVCC
t
C11
1.66V
1
Spike
Blanking
190ns
Latched
Off Mode
G3
8.5V
VCC
IVCC
t
C1
Spike
Blanking
8.0us
&
G1
21V
7.2mA
4.8V
C4
1.1mA
Voltage
Reference
Thermal Shutdown
VOUT
t
Tj >140°C
Max. Ripple < 1%
Control Unit
FB
Figure 18
Figure 17
Version 2.0
Latched Off Mode
t
The VCC voltage is observed by comparator C1 if 21V
is exceeded. The output of C1 is combined with the
output of C4 which observes FB signal if 4.8V is
14
15 May 2003
Signals in Active Burst Mode
F3
ICE3DS01L/LG
Functional Description
exceeded. Therefore the overvoltage detection is only
activated if the FB signal is outside the operating range
> 4.8V, e.g. when Open Loop happens. Therewith
small voltage overshoots of VVCC during normal
operating can not start the Latched Off Mode.
The internal Voltage Reference is switched off once
Latched Off Mode is entered in order to reduce the
current consumption of the IC as much as possible.
Latched Off Mode can only be reset by decreasing
VVCC < 6V. In this stage only the UVLO is working which
controls the Startup Cell by switching on/off at VVCCon/
VVCCoff. In this phase the average current consumption
is only 300µA. As there is no longer a self supply by the
auxiliary winding VCC drops. The Undervoltage
Lockout switches on the integrated Startup Cell when
VCC falls below 8.5V. The Startup Cell is switched off
again when VCC has exceeded 15V. As the Latched
Off Mode was entered there is no Start Up Phase after
VCC has exceeded the switch-on level of the
Undervoltage Lockout. Therefore VCC changes
between the switch-on and switch-off levels of the
Undervoltage Lockout with a saw tooth shape (see
Figure 19).
VVCC
short winding or short diode C10 is no longer able to
limit the CS signal at 1V. C11 detects then the over
current and enters immediately the Latched Off Mode
to keep the SMPS in a safe stage.
3.6.3.2
Auto Restart Mode
SoftS
6.5V
5k
RSoftS
4.4V
1
S1
G2
Voltage
Reference
C3
5.4V
&
4.8V
C4
15V
G5
FB
Auto
Restart
Mode
Control Unit
8.5V
Figure 20
IVCCStart
t
1.05mA
VOUT
Figure 19
t
Signals in Latched Off Mode
After detecting a junction temperature higher than
140°C Latched Off Mode is entered.
The signals coming from the temperature detection and
VCC overvoltage detection are fed into a spike
blanking with a time constant of 8.0µs to ensure system
reliability.
Furthermore short winding and short diode on the
secondary side can be detected by the comparator C11
which is in parallel to the propagation delay
compensated current limit comparator C10. In normal
operating mode comparator C10 keeps the maximum
level of the CS signal at 1V. If there is a failure such as
Version 2.0
15
Auto Restart Mode
In case of Overload or Open Loop FB exceeds 4.8V
which will be observed by C4. At this time S1 is
released that VSoftS can increase. If VSoftS exceeds 5.4V
which is observed by C3 Auto Restart Mode is entered
as both inputs of the gate G5 are high. In combining the
FB and SoftS signals there is a blanking window
generated which prevents the system to enter Auto
Restart Mode due to large load jumps. This time
window is the same as for the Active Burst Mode and
can therefore be adjusted by the external CSoftS.
In case of VCC undervoltage the UVLO starts a new
startup cycle.
Short Optocoupler leads to VCC undervoltage as there
is now self supply after activating the internal reference
and bias.
In contrast to the Latched Off Mode there is always a
Startup Phase with switching cycles in Auto Restart
Mode. After this Start Up Phase the conditions are
again checked whether the failure is still present.
Normal operation is proceeded once the failure mode
is removed that leads to Auto Restart Mode.
15 May 2003
F3
ICE3DS01L/LG
Electrical Characteristics
4
Electrical Characteristics
Note:
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
HV Voltage
VHV
-
500V
V
VCC Supply Voltage
VVCC
-0.3
22
V
FB Voltage
VFB
-0.3
6.5
V
SoftS Voltage
VSoftS
-0.3
6.5
V
Gate Voltage
VGate
-0.3
22
V
CS Voltage
VCS
-0.3
6.5
V
Junction Temperature
Tj
-40
150
°C
Storage Temperature
TS
-55
150
°C
Total Power Dissipation
PtotDSO8
-
0.45
W
P-DSO-8-8, Tamb < 50°C
Internally clamped at 11.5V
PtotDIP8
-
0.90
W
P-DIP-8-6, Tamb < 50°C
Thermal Resistance
Junction-Ambient
RthJADSO8
-
185
K/W
P-DSO-8-8
RthJADIP8
-
90
K/W
P-DIP-8-6
ESD Capability (incl. Pin HV)
VESD
-
3
kV
Human body model1)
1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Limit Values
min.
max.
Unit
VCC Supply Voltage
VVCC
VVCCoff
20
V
Junction Temperature of
Controller
TjCon
-25
130
°C
Version 2.0
16
Remarks
Max value limited due to thermal
shut down of controller
15 May 2003
F3
ICE3DS01L/LG
Electrical Characteristics
4.3
4.3.1
Note:
Characteristics
Supply Section
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage
and junction temperature range TJ from – 25 °C to 130 °C. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Start Up Current
IVCCstart
-
170
220
µA
VVCC =14V
VCC Charge Current
IVCCcharge1
-1.60
-1.05
-0.55
mA
VVCC = 0V
IVCCcharge2
-
-0.88
-
mA
VVCC =14V
Start Up Cell Leakage Current
IStartLeak
-
2
20
µA
VVCC>16V
Supply Current with Inactive
Gate
IVCCsup1
-
6.0
7.5
mA
Supply Current with Active Gate IVCCsup2
(CLoad=1nF)
-
7.2
8.7
mA
VSoftS = 4.4V
IFB = 0
Supply Current in
Latched Off Mode
IVCClatch
-
300
-
µA
IFB = 0
ISofts = 0
Supply Current in
Auto Restart Mode
with Inactive Gate
IVCCrestart
-
300
-
µA
IFB = 0
ISofts = 0
Supply Current in
Active Burst Mode
with Inactive Gate
IVCCburst1
-
1.1
1.3
mA
VFB = 2.5V
VSoftS = 4.4V
IVCCburst2
-
1.0
1.2
mA
VVCC = 9V
VFB = 2.5V
VSoftS = 4.4V
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
VVCCon
VVCCoff
VVCChys
14.2
8.0
-
15.0
8.5
6.5
15.8
9.0
-
V
V
V
4.3.2
Internal Voltage Reference
Parameter
Trimmed Reference Voltage
Version 2.0
Symbol
VREF
Limit Values
min.
typ.
max.
6.37
6.50
6.63
17
Unit
Test Condition
V
measured at pin FB
IFB = 0
15 May 2003
F3
ICE3DS01L/LG
Electrical Characteristics
4.3.3
PWM Section
Parameter
Symbol
Fixed Oscillator Frequency
Max. Duty Cycle
Limit Values
Unit
min.
typ.
max.
fOSC1
98
110
119
kHz
fOSC2
102
110
117
kHz
Dmax
0.67
0.72
0.77
Min. Duty Cycle
Dmin
0
-
-
PWM-OP Gain
AV
3.5
3.7
3.9
Max. Level of Voltage Ramp
VMax-Ramp
Tj = 25°C
VFB < 0.3V
-
0.85
-
V
VFB Operating Range Min Level VFBmin
0.3
0.7
-
V
VFB Operating Range Max level VFBmax
-
-
4.75
V
Feedback Pull-Up Resistor
RFB
16
20
27
kΩ
Soft-Start Pull-Up Resistor
RSoftS
39
50
62
kΩ
1)
Test Condition
CS=1V limited by
Comparator C41)
Design characteristic (not meant for production testing)
4.3.4
Control Unit
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Deactivation Level for SoftS
Comparator C7 by C2
VSoftSC2
3.85
4.00
4.15
V
VFB > 5V
Clamped VSoftS Voltage during
Normal Operating Mode
VSoftSclmp
4.23
4.40
4.57
V
VFB < 4.5V
Activation Limit of
Comparator C3
VSoftSC3
5.20
5.40
5.60
V
VFB > 5V
SoftS Startup Current
ISoftSstart
-
1.9
-
mA
VSoftS = 0V
Active Burst Mode Level for
Comparator C6
VFBC6
1.23
1.32
1.40
V
VSoftS > 5.6V
Active Burst Mode Level for
Comparator C5
VFBC5
3.85
4.00
4.15
V
After Active Burst
Mode is entered
Over Load & Open Loop
Detection Limit for
Comparator C4
VFBC4
4.62
4.80
4.98
V
VSoftS > 5.6V
Overvoltage Detection Limit
VVCCOVP
20
21
22
V
VFB > 5V
Latched Thermal Shutdown
TjSD
130
140
150
°C
guaranteed by design
Spike Blanking
tSpike
-
8.0
-
µs
Power Down Reset for Latched
Mode
VVCCPD
4.0
6.0
7.5
V
Note:
After Latched Off Mode
is entered
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
and VVCCPD
Version 2.0
18
15 May 2003
F3
ICE3DS01L/LG
Electrical Characteristics
4.3.5
Current Limiting
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
dVsense / dt = 0.6V/µs
Peak Current Limitation (incl.
Propagation Delay Time)
(see Figure 7)
Vcsth
0.950
1.000
1.050
V
Over Current Detection for
Latched Off Mode
VCS1
1.570
1.66
1.764
V
Peak Current Limitation during
Active Burst Mode
VCS2
0.232
0.257
0.282
V
VFB < 1.2V
Leading Edge Blanking
tLEB
-
220
-
ns
VSoftS = 4.4V
CS Spike Blanking for
Comparator C11
tCSspike
-
190
-
ns
CS Input Bias Current
ICSbias
-1.0
-0.2
0
µA
VCS =0V
Unit
Test Condition
4.3.6
Driver Section
Parameter
GATE Low Voltage
GATE High Voltage
Symbol
VGATElow
VGATEhigh
Limit Values
min.
typ.
max.
-
-
1.2
V
VVCC = 5 V
IGate = 5 mA
-
-
1.5
V
VVCC = 5 V
IGate = 20 mA
-
0.8
-
V
IGate = 0 A
-
1.6
2.0
V
IGate = 20 mA
-0.2
0.2
-
V
IGate = -20 mA
-
11.5
-
V
VVCC = 20V
CL = 4.7nF
-
10.5
-
V
VVCC = 11V
CL = 4.7nF
-
7.5
-
V
VVCC = VVCCoff + 0.2V
CL = 4.7nF
GATE Rise Time
(incl. Gate Rising Slope)
trise
-
150
-
ns
VGate = 2V ...9V1)
CL = 4.7nF
GATE Fall Time
tfall
-
55
-
ns
VGate = 9V ...2V1)
CL = 4.7nF
GATE Current, Peak,
Rising Edge
IGATE
-0.5
-
-
A
CL = 4.7nF2)
GATE Current, Peak,
Falling Edge
IGATE
-
-
0.7
A
CL = 4.7nF2)
1)
Transient reference value
2)
Design characteristic (not meant for production testing)
Version 2.0
19
15 May 2003
F3
ICE3DS01L/LG
Typical Performance Characteristics
Typical Performance Characteristics
8,0
186
7,5
178
174
170
166
162
158
154
150
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
7,0
6,5
6,0
5,5
5,0
4,5
4,0
3,5
3,0
105 115 125
PI-004
182
VCC Supply Current IVCCsup1 [mA]
190
PI-001
Start Up Current I VCCstart [uA]
5
-25
-15
-5
5
Junction Temperature [°C]
Figure 24
9,0
1,4
8,5
1,3
1,2
1,1
1,0
0,9
0,8
0,7
0,6
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
VCC Supply Current IVCCsup2 [mA]
1,5
0,5
0,9
0,8
0,7
0,6
45
55
65
75
85
95
105 115 125
5,0
4,5
-25 -15
-5
5
Version 2.0
25
35
45
55
65
75
85
95
105 115 125
VCC Supply Current IVCCsup2
360
340
320
300
280
260
240
220
200
-25 -15
Junction Temperature [°C]
Figure 23
15
PI-006
VCC Supply Current IVCClatch [uA]
1,0
PI-003
VCC Charge Current I VCCcharge2 [mA]
1,1
35
105 115 125
5,5
Figure 25
1,2
25
95
6,0
380
15
85
Junction Temperature [°C]
1,3
5
75
6,5
4,0
105 115 125
VCC Charge Current IVCCcharge1
-5
65
7,0
400
-15
55
7,5
1,4
-25
45
8,0
1,5
0,5
35
VCC Supply Current IVCCsup1
Junction Temperature [°C]
Figure 22
25
PI-005
Start Up Current IVCCstart
PI-002
VCC Charge Current IVCCcharge1 [mA]
Figure 21
15
Junction Temperature [°C]
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
VCC Charge Current IVCCcharge2
Figure 26
20
VCC Supply Current IVCClatch
15 May 2003
F3
ICE3DS01L/LG
16,0
380
15,8
340
320
300
280
260
240
220
200
-25 -15
-5
5
15
25
35
45
55
65
75
85
15,6
15,4
15,2
15,0
14,8
14,6
14,4
14,2
14,0
95 105 115 125
PI-010
360
VCC Turn-On Threshold VVCCon [V]
400
PI-007
VCC Supply Current IVCCrestart [uA]
Typical Performance Characteristics
-25 -15
-5
5
Figure 30
9,0
1,17
8,9
1,14
1,11
1,08
1,05
1,02
0,99
0,96
0,93
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
VCC Turn-Off Threshold VVCCoff [V]
1,20
0,90
55
65
75
85
95
105 115 125
8,7
8,6
8,5
8,4
8,3
8,2
8,1
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
VCC Supply Current IVCCburst1
Figure 31
VCC Turn-Off Threshold VVCCoff
7,0
1,11
1,08
PI-009
1,05
1,02
0,99
0,96
0,93
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
6,9
6,8
6,7
6,6
6,5
PI-012
1,14
VCC Turn-On/Off Hysteresis VVCChys [V]
1,17
VCC Supply Current IVCCburst2 [mA]
45
8,8
8,0
105 115 125
1,20
0,90
35
VCC Turn-On Threshold VVCCon
Junction Temperature [°C]
Figure 28
25
PI-011
VCC Supply Current IVCCrestart
PI-008
VCC Supply Current IVCCburst1 [mA]
Figure 27
15
Junction Temperature [°C]
Junction Temperature [°C]
6,4
6,3
6,2
6,1
6,0
-25
-15
Figure 29
Version 2.0
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
VCC Supply Current IVCCburst2
Figure 32
21
VCC Turn-On/Off Hysteresis VVCChys
15 May 2003
F3
ICE3DS01L/LG
3,90
6,58
3,86
6,56
3,82
6,54
3,78
6,50
6,48
6,46
3,74
3,70
3,66
3,62
6,44
3,58
6,42
3,54
6,40
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
3,50
105 115 125
PI-016
6,52
PWM-OP Gain AV
6,60
PI-013
Reference Voltage VREF [V]
Typical Performance Characteristics
-25 -15
-5
5
Figure 36
1,10
118
1,05
116
114
112
110
108
106
104
102
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
Max. Level Voltage Ramp VMax-Ramp [V]
120
100
0,720
0,715
0,710
0,705
55
65
75
85
95
105 115 125
Version 2.0
105 115 125
0,65
-25 -15
-5
5
15
25
35
45
55
65
75
85
Max. Level Voltage Ramp VMax-Ramp
24
23
22
21
20
19
18
17
16
-25
-15
Junction Temperature [°C]
Figure 35
95
0,70
PI-018
Feedback Pull-Up Resistor RFB [kOhm]
0,725
PI-015
Max. Duty Cycle
0,730
45
105 115 125
0,75
Figure 37
0,735
35
95
0,80
25
25
85
Junction Temperature [°C]
0,740
15
75
0,85
26
5
65
0,90
0,60
105 115 125
Oscillator Frequency fOSC1
-5
55
0,95
0,745
-25 -15
45
1,00
0,750
0,700
35
PWM-OP Gain AV
Junction Temperature [°C]
Figure 34
25
PI-017
Reference Voltage VREF
PI-014
Oscillator Frequency fOSC1 [kHz]
Figure 33
15
Junction Temperature [°C]
Junction Temperature [°C]
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
Max. Duty Cycle Dmax
Figure 38
22
Feedback Pull-Up Resistor RFB
15 May 2003
F3
ICE3DS01L/LG
5,65
58
5,60
54
52
50
48
46
44
42
40
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
5,55
5,50
5,45
5,40
5,35
5,30
5,25
5,20
5,15
105 115 125
PI-022
56
Threshold Comparator C3 V SoftSC3 [V]
60
PI-019
Soft-Start Pull-Up Resistor RSoftS [kOhm]
Typical Performance Characteristics
-25 -15
-5
5
Junction Temperature [°C]
Figure 42
1,360
4,16
1,352
4,12
4,08
4,04
4,00
3,96
3,92
3,88
3,84
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
Threshold Comparator C6 VFBC6 [V]
4,20
3,80
1,304
1,296
1,288
-25 -15
-5
5
4,36
4,32
4,28
4,24
45
55
65
75
85
Version 2.0
25
35
45
55
65
75
85
95 105 115 125
95
105 115 125
Threshold Comparator C6 VFBC6
4,12
4,08
4,04
4,00
3,96
3,92
3,88
3,84
3,80
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 41
15
PI-024
4,40
Threshold Comparator C5 VFBC5 [V]
4,44
PI-021
Clamped SoftS Voltage V SoftSclmp [V]
Figure 43
4,48
35
95 105 115 125
1,312
4,16
25
85
Junction Temperature [°C]
4,52
15
75
1,320
4,20
5
65
1,328
1,280
105 115 125
Threshold Comparator C2 VSoftSC2
-5
55
1,336
4,56
-25 -15
45
1,344
4,60
4,20
35
Threshold Comparator C3 VSoftSC3
Junction Temperature [°C]
Figure 40
25
PI-023
Soft-Start Pull-Up Resistor RSoftS
PI-020
Threshold Comparator C2 VSoftSC2 [V]
Figure 39
15
Junction Temperature [°C]
Clamped SoftS Voltage VSoftSclmp
Figure 44
23
Threshold Comparator C5 VFBC5
15 May 2003
F3
ICE3DS01L/LG
Typical Performance Characteristics
5,00
4,84
4,80
4,76
4,72
4,68
4,64
4,60
1,04
1,03
1,02
1,01
1,00
0,99
0,98
0,97
0,96
0,95
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
PI-028
4,88
PI-025
Threshold Comparator C4 VFBC4 [V]
4,92
Peak Current Limitation Vcsth [V]
1,05
4,96
105 115 125
-25 -15 -5
Figure 48
1,700
21,8
1,688
21,6
21,4
21,2
21,0
20,8
20,6
20,4
Over Current Detection VCS1 [V]
22,0
20,2
20,0
Peak Current Limitation Vcsth
1,676
1,664
1,652
1,640
1,628
1,616
1,604
1,592
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
1,580
105 115 125
-25 -15
-5
5
Junction Temperature [°C]
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
Figure 49
0,270
7,6
0,267
7,2
6,8
6,4
6,0
5,6
5,2
4,8
Peak Current Limitation VCS2 [V]
8,0
Over Current Detection VCS1
0,264
0,261
0,258
0,255
PI-030
Overvoltage Detection Limit VVCCOVP
PI-027
VCC Power Down Reset VVCCPD [V]
Figure 46
0,252
0,249
0,246
0,243
4,4
4,0
15 25 35 45 55 65 75 85 95 105 115 125
PI-029
Threshold Comparator C4 VFBC4
PI-026
Overvoltage Detection Limit VVCCOVP [V]
Figure 45
5
Junction Temperature [°C]
Junction Temperature [°C]
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
0,240
-25 -15
Figure 47
Version 2.0
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Threshold Power Down Reset VVCCPD
24
Figure 50
Peak Current Limitation VCS2
15 May 2003
F3
ICE3DS01L/LG
12,0
370
11,7
310
280
250
220
190
160
11,1
10,8
10,5
10,2
9,9
9,6
9,3
130
100
11,4
PI-034
340
Gate High Voltage VGATEhigh [V]
400
PI-031
Leading Edge Blanking tLEB [ns]
Typical Performance Characteristics
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
9,0
105 115 125
-25 -15
-5
5
Figure 54
300
280
280
260
260
240
220
200
180
160
Gate Rise Time trise [ns]
300
55
65
75
85
95
105 115 125
GATE High Voltage VGATEhigh
240
220
200
180
160
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
100
105 115 125
-25 -15
-5
5
Junction Temperature [°C]
CS Spike Blanking for C11 tCSspike
Figure 55
80
1,2
76
1,1
72
1,0
0,9
PI-033
0,8
0,7
0,6
GATE Fall Time tfall [ns]
1,3
15
25
35
45
55
65
75
85
Version 2.0
65
75
85
95
105 115 125
95
105 115 125
GATE Rise Time trise
52
40
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 53
55
56
44
5
45
60
48
-5
35
64
0,4
-15
25
68
0,5
-25
15
Junction Temperature [°C]
PI-036
Figure 52
GATE Low Voltage VGATElow [V]
45
120
120
0,3
35
140
140
100
25
PI-035
Leading Edge Blanking tLEB
PI-032
CS Spike Blanking for C11 tCSspike [ns]
Figure 51
15
Junction Temperature [°C]
Junction Temperature [°C]
GATE Low Voltage VGATElow
Figure 56
25
GATE Fall Time tfall
15 May 2003
F3
ICE3DS01L/LG
Outline Dimension
6
Outline Dimension
P-DIP-8-6
(Plastic Dual In-Line Outline)
Figure 57
P-DSO-8-8
(Plastic Dual Small Outline)
Figure 58
Dimensions in mm
Version 2.0
26
15 May 2003
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere Anstrengungen gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Quality takes on an allencompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Dazu gehört eine bestimmte
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener
Sichtweise auch über den eigenen
Arbeitsplatz hinaus – und uns ständig
zu verbessern.
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit den entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe
Leistung durch umfassende Qualität zu
beweisen.
Wir werden Sie überzeugen.
http://www.infineon.com
Published by Infineon Technologies AG
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.