IPD50N06S3L-06 OptiMOS®-T Power-Transistor Product Summary V DS 55 V R DS(on),max 6.0 mΩ ID 50 A Features • N-channel - Logic Level - Enhancement mode • Automotive AEC Q101 qualified PG-TO252-3-11 • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green package (RoHS compliant) • Ultra low Rds(on) • 100% Avalanche tested Type Package Marking IPD50N06S3L-06 PG-TO252-3-11 3N06L06 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions T C=25 °C, V GS=10 V T C=100 °C, V GS=10 V2) Value 50 Unit A 50 Pulsed drain current2) I D,pulse T C=25 °C 200 Avalanche energy, single pulse2) E AS I D=25 A 710 mJ Avalanche current, single pulse I AS 50 A Gate source voltage3) V GS ±16 V Power dissipation P tot 136 W Operating and storage temperature T j, T stg -55 ... +175 °C T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.2 55/175/56 page 1 2009-05-20 IPD50N06S3L-06 Parameter Symbol Values Conditions Unit min. typ. max. - - 1.1 minimal footprint - - 62 6 cm2 cooling area4) - - 40 Thermal characteristics2) Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA 55 - - Gate threshold voltage V GS(th) V DS=V GS, I D=80 µA 1.2 1.7 2.2 Zero gate voltage drain current I DSS V DS=55 V, V GS=0 V, T j=25 °C - 0.01 1 - 1 100 V DS=55 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=16 V, V DS=0 V - 1 100 nA Drain-source on-state resistance R DS(on) V GS=5 V, I D=37 A - 8.4 11 mΩ V GS=10 V, I D=50 A - 5.1 6 Rev. 1.2 page 2 2009-05-20 IPD50N06S3L-06 Parameter Symbol Values Conditions Unit min. typ. max. - 9400 11750 pF - 1200 1800 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 1130 1700 Turn-on delay time t d(on) - 20 - Rise time tr - 57 - Turn-off delay time t d(off) - 75 - Fall time tf - 115 - Gate to source charge Q gs - 37 50 Gate to drain charge Q gd - 27 40 Gate charge total Qg - 129 145 Gate plateau voltage V plateau - 3.9 - V - - 50 A - - 200 0.6 0.9 1.3 V - 47 - ns - 62 - nC V GS=0 V, V DS=25 V, f =1 MHz V DD=27.5 V, V GS=10 V, I D=50 A, R G=7 Ω ns Gate Charge Characteristics2) V DD=11 V, I D=50 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25 °C V GS=0 V, I F=50 A, T j=25 °C V R=27.5 V, I F=I S, di F/dt =100 A/µs 1) Current is limited by bondwire; with an R thJC = 1.1 K/W the chip is able to carry 112 A at 25°C. For detailed information see Application Note ANPS071E. 2) Defined by design. Not subject to production test. 3) Qualified at -5V and +20V. 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.2 page 3 2009-05-20 IPD50N06S3L-06 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 4 V I D = f(T C); V GS ≥ 4 V 160 60 140 120 40 I D [A] P tot [W] 100 80 60 20 40 20 0 0 0 50 100 150 200 0 50 T C [°C] 100 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 1 µs 100 10 µs 100 0.5 Z thJC [K/W] 100 µs I D [A] 1 ms 0.1 10-1 10 0.05 0.01 -2 10 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.2 10-7 single pulse page 4 2009-05-20 IPD50N06S3L-06 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = f(I D); T j = 25 °C parameter: V GS parameter: V GS 200 10 10 V 5V 6V 6V 175 150 8 5V R DS(on) [mΩ] I D [A] 125 100 4.5 V 75 8V 6 9V 4V 50 10 V 3.5 V 25 0 4 0 2 4 6 8 10 0 50 100 V DS [V] 150 200 I D [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 4 V R DS(on) = f(T j); I D = 50 A; V GS = 10 V parameter: T j 150 10 -55 °C 25 °C 175 °C 8 I D [A] R DS(on) [mΩ] 100 6 50 4 0 2 0 2 4 6 V GS [V] Rev. 1.2 -60 -20 20 60 100 140 180 T j [°C] page 5 2009-05-20 IPD50N06S3L-06 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 2.5 2.25 2 Ciss Coss 1.5 C [pF] V GS(th) [V] 104 800µA 1.75 Crss 80µA 1.25 103 1 0.75 102 0.5 -60 -20 20 60 100 140 0 180 5 10 T j [°C] 15 20 25 V DS [V] 11 Typical forward diode characteristicis 12 Typ. avalanche characteristics IF = f(VSD) I AV = f(t AV) parameter: T j parameter: T j(start) 100 103 25°C 100°C 150°C I F [A] I AV [A] 102 101 175 °C 25 °C 0.6 0.8 100 1 0 0.2 0.4 1 1.2 1.4 V SD [V] Rev. 1.2 10 1 10 100 1000 t AV [µs] page 6 2009-05-20 IPD50N06S3L-06 13 Typical avalanche Energy 14 Drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 65 1500 12.5 A 1200 60 V BR(DSS) [V] E AS [mJ] 900 25 A 600 55 50 50 A 300 45 0 0 50 100 150 -60 200 -20 20 60 100 140 180 T j [°C] T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 50 A pulsed parameter: V DD 12 V GS Qg 44 V 11 V 10 V GS [V] 8 V plateau 6 V g s(th) 4 2 Q g (th) Q sw Q gs 0 0 50 100 150 Q gate Q gd 200 Q gate [nC] Rev. 1.2 page 7 2009-05-20 IPD50N06S3L-06 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2009 All Rights Reserved. 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Rev. 1.2 page 8 2009-05-20 IPD50N06S3L-06 Revision History Version Changes Date Data Sheet version 1.1 Implementation of avalanche 07.11.2007 current single pulse Data Sheet version 1.1 07.11.2007 Update of package drawing Data Sheet version 1.1 Update of avalanche diagram 12 07.11.2007 and 13 Data Sheet version 1.1 implementation of footnote 2 for 07.11.2007 Eas specification Data Sheet version 1.2 Correction of marking and update 15.06.2009 of disclaimer Data Sheet version 1.2 15.06.2009 Correction of package name Rev. 1.2 page 9 2009-05-20