HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9 Features CAS Latency and Clock Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400B DDR400A -5 -5A 133 133 166 200 200 200 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is center-aligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst Lengths: 2, 4, or 8 • CAS Latency: (1.5), 2, 2.5, (3) • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 7.8ms Maximum Average Periodic Refresh Interval (8k refresh) • 2.5V (SSTL_2 compatible) I/O • VDDQ = 2.6V ± 0.1V / VDD = 2.6V ± 0.1V • TSOP66 package Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. dent with the Read or Write command are used to select the bank and the starting column location for the burst access. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf-clock-cycle data transfers at the I/O pins. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coinci2003-01-10, V0.9 Page 1 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Ordering Information Part Numbera Org. HYB25D256800BT(L)-5A x8 CAS-RCD-RP Clock CAS-RCD-RP Clock CAS-RCD-RP Clock Speed Latencies (MHz) Latencies (MHz) Latencies (MHz) 3-3-3 200 2.5-3-3 200 2-3-3 133 Package DDR400A 66 Pin TSOP-II HYB25D256160BT(L)-5A x16 HYB25D256800BT(L)-5 x8 HYB25D256160BT(L)-5 x16 166 DDR400B a. HYB: designator for memory components 25D: DDR-I SDRAMs at Vddq=2.5V 256: 256Mb density 400/800/160: Product variations x4, x8 and x16 B: Die revision B C/T: Package type FBGA and TSOP L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents -5: speed grade - see table Page 2 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Pin Configuration (TSOP66) VDD VDD VDD 1 66 VSS VSS VSS NC DQ0 VDDQ NC DQ0 VDDQ DQ1 2 3 4 65 64 63 DQ15 VSSQ DQ14 DQ7 VSSQ NC NC VSSQ NC 5 62 DQ13 DQ6 DQ3 VDDQ NC DQ5 VSSQ NC VDDQ NC NC VSSQ NC VDDQ NC DQ0 DQ1 DQ2 VSSQ NC NC VDDQ NC VSSQ NC DQ2 VDDQ NC VSSQ DQ3 DQ4 VDDQ DQ5 6 7 8 9 10 61 60 59 58 57 VDDQ DQ12 DQ11 VSSQ DQ10 DQ1 DQ3 DQ6 11 56 DQ9 DQ4 DQ2 VSSQ VSSQ VSSQ 12 55 VDDQ VDDQ VDDQ NC NC NC NC DQ7 NC VDDQ NC VDDQ NC VDDQ LDQS 13 14 15 16 54 53 52 51 DQ8 NC VSSQ UDQS NC NC VSSQ DQS NC NC VSSQ DQS NC VDD NC NC VDD NC NC VDD NC 17 18 19 50 49 48 NC VREF VSS NC VREF VSS NC VREF VSS 20 47 UDM DM DM 46 45 44 CK CK CK CK CK CK NC NC LDM WE CAS WE CAS WE CAS RAS RAS RAS 21 22 23 CKE CKE CKE CS NC CS NC CS NC 24 25 43 42 NC A12 NC A12 NC A12 BA0 BA1 A10/AP BA0 BA1 A10/AP BA0 BA1 A10/AP A11 A9 A8 A11 A9 A8 A0 A1 A2 A0 A1 A2 41 40 39 38 A11 A9 A8 A0 A1 A2 26 27 28 29 A7 A7 A7 30 31 37 36 A6 A5 A6 A5 A6 A5 A3 VDD A3 VDD A3 VDD 32 33 35 34 A4 VSS A4 VSS A4 VSS 16Mb x 16 32Mb x 8 64Mb x 4 2003-01-10, V0.9 Page 3 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Input/Output Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A12 Input Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. DQ Input/Output Data Input/Output: Data bus. DQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 2.6V ± 0.1V. VSSQ Supply DQ Ground VDD Supply Power Supply: 2.6V ± 0.1V. VSS Supply Ground VREF Supply SSTL_2 reference voltage: (VDDQ / 2) Page 4 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Control Logic 2 Bank2 Bank3 CK, CK DLL 2 8192 8 512 (x16) 1 16 16 Write FIFO & Drivers 1 1 8 8 8 clk clk out in Data 8 2 9 Column-Address Counter/Latch COL0 1 CK, CK DQ0-DQ7, DM DQS Input Register 1 Mask 1 16 Column Decoder 10 8 DQS Generator COL0 I/O Gating DM Mask Logic Drivers 16 Sense Amplifiers Data 8 MUX Bank0 Memory Array (8192 x 512x 16) Read Latch 8192 DQS 1 Receivers 15 Address Register A0-A12, BA0, BA1 Refresh Counter 13 13 13 Bank Control Logic Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS Command Decode Block Diagram (32Mb x 8) 8 COL0 1 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. 2003-01-10, V0.9 Page 5 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Control Logic 2 Bank2 Bank3 CK, CK DLL 2 8192 16 256 (x32) 1 32 32 Write FIFO & Drivers 1 1 16 16 16 clk clk out in Data 16 2 8 Column-Address Counter/Latch COL0 1 CK, CK DQ0-DQ15, DM DQS Input Register 1 Mask 1 32 Column Decoder 9 16 DQS Generator COL0 I/O Gating DM Mask Logic Drivers 32 Sense Amplifiers Data 16 MUX Bank0 Memory Array (8192 x 256x 32) Read Latch 8192 LDQS, UDQS 1 Receivers 15 Address Register A0-A11, BA0, BA1 Refresh Counter 13 13 13 Bank Control Logic Mode Registers Bank0 Row-Address Latch & Decoder Bank1 Row-Address MUX CKE CK CK CS WE CAS RAS Command Decode Block Diagram (16Mb x 16) 16 COL0 2 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional DQ , UDQS and LDQS signals. Page 6 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following criteria must be met: No power sequencing is specified during power up or power down given the following criteria: VDD and VDDQ are driven from a single power converter output AND VTT meets the specification AND VREF tracks VDDQ/2 or The following relationship must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200ms delay prior to applying an executable command. Once the 200ms delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any executable command. During the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 2003-01-10, V0.9 Page 7 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Register Definition Mode Register The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Page 8 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Mode Register Operation BA1 BA0 0* 0* A12 - A9 0 A8 0 A12 A11 A10 A9 A8 A7 0 A5 A4 CAS Latency Operating Mode A7 A6 A3 BT A2 Burst Length A6 - A0 Operating Mode Valid Normal operation Do not reset DLL A3 Burst Type 0 Sequential Valid Normal operation in DLL Reset 1 Interleave 0 1 0 0 0 1 Reserved - - - Reserved CAS Latency A1 A0 Address Bus Mode Register Burst Length A6 A5 A4 Latency A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 0 1 2 0 1 0 2 0 1 0 4 0 1 1 3 (optional) 0 1 1 8 1 0 0 Reserved 1 0 0 Reserved 1 0 1 1.5 (optional) 1 0 1 Reserved 1 1 0 2.5 1 1 0 Reserved 1 1 1 Reserved 1 1 1 Reserved * BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register). 2003-01-10, V0.9 Page 9 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Burst Definition Starting Column Address Order of Accesses Within a Burst Burst Length A2 A1 A0 Type = Sequential Type = Interleaved 0 0-1 0-1 1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 2 4 8 Notes: 1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 10. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS latency of 1.5 is an optional feature on this device. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Page 10 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. Required CAS Latencies CAS Latency = 2, BL = 4 CK CK Command Read NOP NOP NOP NOP NOP CL=2 DQS DQ CAS Latency = 2.5, BL = 4 CK CK Command Read NOP NOP NOP NOP NOP CL=2.5 DQS DQ Shown with nominal tAC, tDQSCK, and tDQSQ. 2003-01-10, V0.9 Don’t Care Page 11 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self refresh operation. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. I-V curves for the normal and weak drive strength are included in this document. Page 12 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Extended Mode Register Definition BA1 BA0 0* 1* A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 Operating Mode A2 A1 A0 Address Bus 0 DS DLL Extended Mode Register Drive Strength An - A3 A2 - A0 Operating Mode 0 Valid Normal Operation - - All other states Reserved A1 Drive Strength 0 Normal 1 Weak A2 0 must be set to 0 * BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register) 2003-01-10, V0.9 A0 DLL 0 Enable 1 Disable Page 13 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Commands CommandsDeselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for x16, [i = 9, j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any Page 14 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Auto Refresh Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8 ms (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 * 7.8 ms (70.2ms). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates. Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. 2003-01-10, V0.9 Page 15 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Truth Table 1a: Commands Name (Function) CS RAS CAS WE Address MNE Notes Deselect (Nop) H X X X X NOP 1, 9 No Operation (Nop) L H H H X NOP 1, 9 Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1, 3 Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1, 4 Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write 1, 4 Burst Terminate L H H L X BST 1, 8 Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1, 5 Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR / SR 1, 6, 7 Mode Register Set L L L L Op-Code MRS 1, 2 1. CKE is HIGH for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable. Truth Table 1b: DM Operation Name (Function) DM DQs Notes Write Enable L Valid 1 Write Inhibit H X 1 1. Used to mask write data; provided coincident with the corresponding data. Page 16 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Truth Table 2: Clock Enable (CKE) 1. 2. 3. 4. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. CKE n-1 CKEn Current State Previous Cycle Current Cycle Command n Self Refresh L L X Self Refresh L H Deselect or NOP Power Down L L X Power Down L H Deselect or NOP Exit Power-Down All Banks Idle H L Deselect or NOP Precharge Power-Down Entry All Banks Idle H L AUTO REFRESH Self Refresh Entry Bank(s) Active H L Deselect or NOP Active Power-Down Entry H H See “Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)” on page 18 Action n Notes Maintain Self-Refresh Exit Self-Refresh 1 Maintain Power-Down 1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock. 2003-01-10, V0.9 Page 17 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Truth Table 3: Current State Bank n - Command to Bank n (Same Bank) Current State Any Idle Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) CS RAS CAS WE Command H X X X Deselect NOP. Continue previous operation Action Notes 1-6 L H H H No Operation NOP. Continue previous operation 1-6 L L H H Active Select and activate row 1-6 L L L H AUTO REFRESH L L L L MODE REGISTER SET L H L H Read Select column and start Read burst 1-6, 10 L H L L Write Select column and start Write burst 1-6, 10 1-7 1-7 L L H L Precharge L H L H Read Deactivate row in bank(s) 1-6, 8 Select column and start new Read burst L L H L Precharge 1-6, 10 Truncate Read burst, start Precharge L H H L BURST TERMINATE 1-6, 8 BURST TERMINATE 1-6, 9 L H L H Read Select column and start Read burst 1-6, 10, 11 L H L L Write Select column and start Write burst 1-6, 10 L L H L Precharge Truncate Write burst, start Precharge 1-6, 8, 11 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according Truth Table 4. 5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 11. Requires appropriate DM masking. Page 18 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Truth Table 4: Current State Bank n - Command to Bank m (Different bank) Current State Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) CS RAS CAS WE Command H X X X Deselect NOP/continue previous operation Action Notes 1-6 L H H H No Operation NOP/continue previous operation 1-6 X X X X Any Command Otherwise Allowed to Bank m L L H H Active Select and activate row 1-6 1-6 L H L H Read Select column and start Read burst 1-7 L H L L Write Select column and start Write burst 1-7 L L H L Precharge L L H H Active Select and activate row 1-6 L H L H Read Select column and start new Read burst 1-7 L L H L Precharge L L H H Active Select and activate row 1-6 L H L H Read Select column and start Read burst 1-8 L H L L Write Select column and start new Write burst 1-7 L L H L Precharge L L H H Active Select and activate row L H L H Read Select column and start new Read burst L H L L Write Select column and start Write burst L L H L Precharge L L H H Active Select and activate row L H L H Read Select column and start Read burst 1-7,10 L H L L Write Select column and start new Write burst 1-7,10 L L H L Precharge 1-6 1-6 1-6 1-6 1-7,10 1-7,9,10 1-6 1-6 1-6 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 5. 2003-01-10, V0.9 Page 19 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Truth Table 5: Concurrent Auto Precharge From Command WRITE w/AP Minimum Delay with Concurrent Auto Precharge Support Units Read or Read w/AP 1 + (BL/2) + tWTR tCK Write ot Write w/AP BL/2 tCK 1 tCK Read or Read w/AP BL/2 tCK Write or Write w/AP CL (rounded up)+ BL/2 tCK 1 tCK To Command (different bank) Precharge or Activate Read w/AP Precharge or Activate Page 20 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Simplified State Diagram Power Applied Power On Self Refresh Precharge PREALL REFS REFSX MRS EMRS MRS Auto Refresh REFA Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Burst Stop Row Active Write Write A Write Read Read A Read Read Read A Write A Read A PRE Write A PRE PRE PRE Read A Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh 2003-01-10, V0.9 CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge Page 21 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Operating Conditions Absolute Maximum Ratings Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Rating Units -0.5 to VDDQ+ 0.5 V Voltage on Inputs relative to VSS -0.5 to +3.6 V Voltage on VDD supply relative to VSS -0.5 to +3.6 V Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 °C -55 to +150 °C Power Dissipation 1.0 W Short Circuit Output Current 50 mA Voltage on I/O pins relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Input and Output Capacitances Parameter Package Symbol Min. Max. Units Notes Input Capacitance: CK, CK TSOP CI1 2.0 3.0 pF 1 Delta Input Capacitance CK, CK TSOP CdI1 - 0.25 pF 1 Input Capacitance: All other input-only pins TSOP CI2 2.0 3.0 pF 1 Delta Input Capacitance: All other input-only pins TSOP CdI2 - 0.5 pF 1 Input/Output Capacitance: DQ, DQS, DM TSOP CIO 4.0 5.0 pF 1, 2 Delta Input/Output Capacitance : DQ, DQS, DM TSOP CdIO - 0.5 pF 1 1. These values are guaranteed by design and are tested on a sample base only. VDDQ = V DD = 2.6V ± 0.1V, f = 100MHz, TA = 25°C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) 0.2V. Unused pins are tied to ground . 2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level Page 22 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Electrical Characteristics and DC Operating Conditions (0°C £ TA £ 70°C; VDDQ = 2.6V ± 0.1V, VDD = + 2.6V ± 0.1V ) Symbol Min Max Supply Voltage 2.50 2.70 V 1, 2 I/O Supply Voltage 2.50 2.70 V 1, 2 VSS, VSSQ Supply Voltage, I/O Supply Voltage 0 0 V I/O Reference Voltage VDDQ /2-50mV VDDQ /2+50mV V 2, 3 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 2, 4 VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 2 VIL(DC) Input Low (Logic0) Voltage - 0.3 VREF - 0.15 V 2 VIN(DC) Input Voltage Level, CK and CK Inputs - 0.3 VDDQ + 0.3 V 2 VID(DC) Input Differential Voltage, CK and CK Inputs 0.36 VDDQ + 0.6 V 2, 5 VIRatio VI-Matching Pullup Current to Pulldown Current 0.71 1.4 Input Leakage Current. Any input 0V £ VIN £ VDD (All other pins not under test = 0V) -2 2 mA 2 IOZ Output Leakage Current (DQs are disabled; 0V £ Vout £ VDDQ -5 5 mA 2 IOH Output High Current, Normal Strength Driver (VOUT = 1.95 V) - 16.2 mA IOL Output Low Current, Normal Strength Driver (VOUT = 0.35 V) 16.2 mA VDD VDDQ VREF VTT II Parameter Units Notes 6 1. This is the DC voltage supplied at the DRAM and is inclusive all noise up to 10MHz. The DRAM does not generate any noise that exceeds ±150mV above 10MHz and does meet full functionality with up to ±150mV above 10MHz at the DRAM that is generated by the DRAM itself. Any noise above 10MHz at the DRAM generated from any other source than the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV. The AC and DC tolerances of the data sheet are additive. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value. 4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 5. VID is the magnitude of the difference between the input level on CK and the input level on CK 6. The ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 2003-01-10, V0.9 Page 23 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum IDD Specification and Conditions (0 °C £ TA £ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) DDR200 -8 Symbol Parameter/Condition DDR266A -7 DDR266 -7F DDR333 -6 DDR400A/B -5 Notes Unit typ. max. typ. max. typ. max. typ. max. typ. max. OperatingCurrent: onebank; active/ precharge; tRC=tRCMIN; x4/x8 IDD0 DQ, DM, andDQSinputs changingonceper clock cycle; address andcontrol inputs changingonceevery twoclock cycles x16 70 90 75 100 83 110 85 110 90 115 mA 72 95 77 105 86 115 88 115 100 120 mA x4/x8 80 100 90 110 98 120 100 120 105 125 mA x16 83 105 94 115 102 125 104 125 115 135 mA PrechargePower-DownStandbyCurrent: all banks idle; power-downmode; CKE<= VILMAX 5 7 6 8 6 8 6 9 6 9 mA 1, 2 PrechargeFloatingStandbyCurrent: /CS>= VIHMIN, all banks idle; IDD2F CKE>= VIHMIN; address andother control inputs changingonceper clock cycle, VIN = VREFfor DQ, DQSandDM. 30 35 35 40 35 40 45 55 46 56 mA 1, 2 PrechargeQuiet StandbyCurrent: /CS>=VIHMIN, all banks idle; IDD2Q CKE>= VIHMIN; address andother control inputs stable at >=VIHMINor <= VILMAX; VIN=VREFfor DQ, DQSandDM. 18 22 20 25 20 25 25 28 24 34 mA 1, 2 13 16 15 18 15 18 18 21 17 24 mA 1, 2 40 45 50 55 50 55 60 65 57 69 mA 42 50 52 60 52 60 63 70 60 74 mA 79 95 95 115 95 115 110 140 115 145 mA 89 110 107 130 107 130 124 160 140 175 mA 85 105 105 125 105 125 125 145 125 150 mA 96 120 119 140 119 140 141 165 150 180 mA 126 170 135 180 135 180 144 190 155 195 mA 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.6 2.6 mA lowpower version 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 1.25 1.30 mA x4/x8 150 210 171 225 171 225 208 270 240 280 x16 158 220 180 235 180 235 218 285 260 310 OperatingCurrent: onebank; active/read/precharge; IDD1 burst length4; Refer tothefollowingpagefor detailedtest conditions. IDD2P IDD3P 4 1, 2 1, 2 ActivePower-DownStandbyCurrent: onebank active; power-downmode; CKE<= VILMAX; VIN=VREFfor DQ, DQSandDM. ActiveStandbyCurrent: onebank active; CS>=VIHMIN; x4/x8 CKE>= VIHMIN; tRC=tRASMAX; DQ, DM, andDQSinputs IDD3N changingtwiceper clock cycle; address andcontrol inputs changing x16 onceper clock cycle OperatingCurrent: onebank active; BL2; reads; continuous burst; x4/x8 address andcontrol inputs changingonceper clock cycle; 50%of IDD4R dataoutputs changingonevery clock edge; CL2for DDR200and x16 DDR266(A), CL3for DDR333andDDR400; IOUT=0mA OperatingCurrent: onebank active; Burst =2; writes; continuous x4/x8 burst; address andcontrol inputs changingonceper clock cycle; IDD4W 50%of dataoutputs changingonevery clock edge; CL2for x16 DDR200andDDR266(A), CL3for DDR333andDDR400 IDD5 Auto-RefreshCurrent: tRC=tRFCMIN, distributedrefresh standardversion 1, 2 1, 2 1, 2 IDD6 Self-RefreshCurrent: CKE<=0.2V; external clock on OperatingCurrent: four bank; four bank interleavingwithburst IDD7 length4; Refer tothefollowingpagefor detailedtest conditions. 1, 2 1, 2, 3 mA 1, 2 1. IDDspecifications aretestedafter thedeviceis properly initializedandmeasured at 100MHz for DDR200, 133MHz for DDR266(A) and166MHz for DDR333 2. Input slewrate=1V/ns. 3. Enables on-chiprefreshandaddress counters 4. Test conditionfor typical values : VDD= 2.5V,Ta=25°C, test conditionfor maximumvalues: test limit at VDD= 2.7V,Ta=10°C Page 24 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Detailed test conditions for DDR SDRAM IDD1 and IDD7 IDD1 : Operating current : One bank operation 1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0 mA 2. Timing patterns - DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 * tCK, tRAS = 5 * tCK Setup: A0 N R0 N N P0 N Read : A0 N R0 N N P0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK Setup: A0 N N R0 N P0 N N N Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing 50% of data changing at every burst - DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK Setup: A0 N N R0 N P0 N N N Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing 50% of data changing at every burst 3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP IDD7 : Operating current: Four bank operation 1. Four banks are being interleaved with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0 mA 2. Timing patterns - DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD= 3 * tCK, Read with autoprecharge Setup: A0 N A1 R0 A2 R1 A3 R2 Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst - DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst 3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP 2003-01-10, V0.9 Page 25 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum AC Characteristics (Notes 1-6 apply to the following Tables: Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. The figure below represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level) 6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating,DDR SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC specification for DDR components AC Output Load Circuit Diagram / Timing Reference Load VTT 50W Output Timing Reference Point (VOUT) 30pF AC Operating Conditions ) (0 °C £ TA £ 70 °C; VDDQ = 2.6V ± 0.1V; VDD = 2.6V ± 0.1V) Symbol Parameter/Condition VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals VIL(AC) Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals VID(AC) Input Differential Voltage, CK and CK Inputs VIX(AC) Input Closing Point Voltage, CK and CK Inputs 1. 2. 3. 4. Min Max Unit Notes V 1, 2 VREF - 0.31 V 1, 2 VDDQ + 0.6 V 1, 2, 3 V 1, 2, 4 VREF + 0.31 0.7 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 Input slew rate = 1V/ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Page 26 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Electrical Characteristics & AC Timing - Absolute Specifications (0 °C £ TA £ 70 °C; VDDQ = 2.6V ± 0.1V; VDD = 2.6V ± 0.1V) (Part 1 of 2) Symbol tAC DDR400A -5A Parameter DQ output access time from CK/CK tDQSCK DQS output access time from CK/CK DDR400B -5 Unit Notes +0.5 ns 1-4 -0.55 +0.55 ns 1-4 Min. Max. Min. Max. -0.5 +0.5 -0.5 -0.55 +0.55 tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4 tHP Clock Half Period min (tCL, tCH) ns 1-4 tCK tCK Clock cycle time tCK min (tCL, tCH) CL = 3.0 5 10 5 10 ns 1-4 CL = 2.5 5 10 6 10 ns 1-4 CL = 2.0 7.5 10 7.5 10 ns 1-4 tDH DQ and DM input hold time 0.40 0.40 ns 1-4 tDS DQ and DM input setup time 0.40 0.40 ns 1-4 tIPW Control & Addr. input pulse width (each input) 2.2 2.2 ns 1-4,10 tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4, 10 tHZ Data-out high-impedence time from CK/CK +0.65 ns 1-4, 5 tLZ Data-out low-impedence time from CK/CK -0.65 +0.65 -0.65 +0.65 ns 1-4, 5 tDQSS Write command to 1st DQS latching transition 0.72 1.28 0.72 1.28 tCK 1-4 tDQSQ DQS-DQ skew (DQS & associated DQ signals) +0.4 +0.4 ns 1-4 tQHS Data hold skew factor +0.5 +0.5 ns 1-4 tQH DQ output hold time from DQS tDQSL,H DQS input low (high) pulse width (write cycle) +0.65 tHP-tQHS tHP-tQHS ns 1-4 0.35 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK 1-4 tMRD Mode register set command cycle time 2 2 tCK 1-4 0 0 ns 1-4, 7 tCK 1-4, 6 1-4 tWPRES Write preamble setup time tWPST Write postamble 0.40 tWPRE Write preamble 0.25 0.25 tCK 0.6 0.6 ns tIS Address and control input setup time fast slew rate tIH Address and control input hold time fast slew rate 0.60 0.40 0.60 2-4, 10,11 0.6 0.6 ns tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 40 70,000 40 70,000 ns 1-4 tRC Active to Active/Auto-refresh command period 55 55 ns 1-4 tRFC Auto-refresh to Active/Auto-refresh command period 65 65 ns 1-4 2003-01-10, V0.9 Page 27 of 29 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Electrical Characteristics & AC Timing - Absolute Specifications (0 °C £ TA £ 70 °C; VDDQ = 2.6V ± 0.1V; VDD = 2.6V ± 0.1V) (Part 2 of 2) Symbol Parameter DDR400A -5A Min. tRCD Max. DDR400B -5 Min. Unit Notes Max. Active to Read or Write delay 15 15 ns 1-4 tRP Precharge command period 15 15 ns 1-4 tRAP Active to Autoprecharge delay 15 15 ns 1-4 tRRD Active bank A to Active bank B command 10 10 ns 1-4 tWR Write recovery time 15 15 ns 1-4 tDAL Auto precharge write recovery + precharge time tCK 1-4,9 tWTR Internal write to read command delay 1 1 tCK 1-4 tXSNR Exit self-refresh to non-read command 75 75 ns 1-4 tXSRD Exit self-refresh to read command 200 200 tCK 1-4 tREFI Average Periodic Refresh Interval (8192 refresh commands per 64ms refresh period) ms 1-4, 8 7.8 7.8 1. Input slew rate >= 1V/ns for DDR400 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarilty tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac) Page 28 of 29 2003-01-10, V0.9 HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Electrical Characteristics & AC Timing for DDR400 - Applicable Specifications Expressed in Clock Cycles (0 °C £ TA £ 70 °C; VDDQ = 2.6V ± 0.1V; VDD = 2.6V ± 0.1V, DDR400A/B Symbol Parameter Units Notes 2 tCK 1-54 0.25 tCK 1-5 tCK 1-5 Min tMRD tWPRE Mode register set command cycle time Write preamble Max tRAS Active to Precharge command 8 tRC Active to Active/Auto-refresh command period 11 tCK 1-5 tRFC Auto-refresh to Active/Auto-refresh command period 13 tCK 1-5 tRCD Active to Read or Write delay 3 tCK 1-5 Precharge command period 3 tCK 1-5 tRRD Active bank A to Active bank B command 2 tCK 1-5 tWR Write recovery time 3 tCK 1-5 tDAL Auto precharge write recovery + precharge time 5 tCK 1-5 tWTR Internal write to read command delay 1 tCK 1-5 tXSNR Exit self-refresh to non-read command 10 tCK 1-5 tXSRD Exit self-refresh to read command 200 tCK 1-5 tRP 16000 1. Input slew rate = 1V/ns 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 2003-01-10, V0.9 Page 29 of 29