INFINEON TLE7182EM

Data Sheet, Rev 1.1, Sept. 2010
TLE7182EM
H-Bridge and Dual Half Bridge Driver IC
Automotive Power
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Table of Contents
Table of Contents
1
Overview 3
2
Block Diagram 4
3
3.1
3.2
Pin Configuration 5
Pin Assignment 5
Pin Definitions and Functions 5
4
4.1
4.2
4.3
4.4
General Product Characteristics 7
Absolute Maximum Ratings 7
Functional Range 8
Thermal Resistance 9
Default State of Inputs 9
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.3
5.3.1
Description and Electrical Characteristics 10
MOSFET Driver 10
Driving MOSFET Output Stages 10
MOSFET Output Stages 10
Dead Time and Shoot Through Protection 11
Bootstrap Principle 11
100% D.C. charge pumps 12
Reverse polarity protection of motor bridge 12
Sleep mode 12
Electrical Characteristics 12
Protection and Diagnostic Functions 16
Short Circuit Protection 16
SCDL Pin Open Detection 16
Vs and VDH Over Voltage Warning 16
VS Under Voltage Shutdown 16
VREG Under Voltage Warning 16
Over Temperature Warning 17
Over Current Warning 17
Passive Gxx Clamping 17
ERR Pin 17
Electrical Characteristics 19
Shunt Signal Conditioning 21
Electrical Characteristics 21
6
6.1
6.2
Application Information 23
Layout Guide Lines 25
Further Application Information 25
7
Package Outlines 26
8
Revision History 27
Data Sheet
2
Rev 1.1, 2010-09-30
TLE7182EM
H-Bridge and Dual Half Bridge Driver IC
1
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Drives 4 N-Channel Power MOSFETs
Separate control input for each MOSFET
Unlimited D.C. switch on time of Low and Highside MOSFETs
0 …95% at 20kHz & 100% Duty cycle of High Side MOSFETs
0 ... 100 % Duty cycle of Low Side MOSFETs
Additional output to drive a reverse polarity protection N-MOSFET
Current sense OPAMP
Low quiescent current mode
PG-SSOP-24
Internal shoot through protection and minimum internal dead time option
1 bit diagnosis / ERR
Over current warning based on current sense OPAMP with fixed warning level
Analog adjustable Short Circuit Protection levels via SCDL pin with open pin detection and SCD deactivation
Over temperature warning
Over voltage warning
Under voltage warning and shutdown
Green Product (RoHS compliant)
AEC Qualified
Description
The TLE7182EM is a H-bridge driver IC dedicated to control 4 N-channel MOSFETs typically forming the converter
for a high current DC motor drives in the automotive sector. It incorporates several protection features such as
over current and short circuit detection as well as under-, over voltage and over temperature diagnosis.
The TLE7182EM perfectly fits for driving 2 valves or solenoids too.
Typical applications are fans, pumps and electric power steering. The TLE7182EM is designed for a 12V power
net.
Table 1
Product Summary
Specified operating voltage
VSOP
7.0 V … 34 V
Junction temperature
Tj
-40 °C .. 150°C
Maximum output source resistance
RSou
13.5 Ω
Maximum output sink resistance
RSink
9Ω
IQVS
8 µA
1)
maximum quiescent current
1) typical value at Tj=25°CC
Type
Package
Marking
TLE7182EM
PG-SSOP-24
TLE7182EM
Data Sheet
3
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Block Diagram
2
Block Diagram
VS
VREG
Charge
pump
HS2
Charge
pump
HS1
RPP
VREG
RPP
VDH
BH1
Floating HS driver
Short circuit detection
GH1
SH1
____
ERR
SCDL
Diagnostic logic
Under voltage
Over voltage
Over current
Overtemperature
Short circuit
Reset
ENA
___
IH1
IL1
___
IH2
L
E
V
E
L
Floating LS driver
Short circuit detection
S
H
I
F
T
E
R
GL1
BH2
Floating HS driver
Short circuit detection
GH2
SH2
Input control
Shoot through
protection
dead time
Floating LS driver
Short circuit detection
IL2
GL2
SL
ISO
ISP
ISN
Shunt signal conditioning
Over current detection
GND
Figure 1
Data Sheet
Block diagram TLE7182EM
4
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
BH2
GH2
SH2
GL2
VDH
RPP
Vs
VREG
ENA
ISN
ISP
ISO
1
2
3
4
5
6
7
8
9
10
11
12
Figure 2
Pin Configuration
3.2
Pin Definitions and Functions
# of
Pins
24
23
22
21
20
19
18
17
16
15
14
13
BH1
GH1
SH1
GL1
SL
GND
SCDL
___
ERR
IL1
___
IH1
IL2
___
IH2
Symbol
Function
1
BH2
Pin for + terminal of the bootstrap capacitor of phase 2
2
GH2
Output pin for gate of high side MOSFET 2
3
SH2
Pin for source connection of high side MOSFET 2
4
GL2
Output pin for gate of low side MOSFET 2
5
VDH
Voltage input common drain high side for short circuit detection
6
RPP
charge pump output for reverse polarity protection of the motor bridge
7
VS
Pin for supply voltage
8
VREG
Output of supply for driver output stage - connect to a capacitor
9
ENA
Input pin for reset of ERR registers, active switch off of external MOSFETs and low
quiescent current mode, set HIGH to enable operation
10
ISN
Input for OPAMP + terminal
11
ISP
Input for OPAMP - terminal
12
ISO
Output of OPAMP
13
IH2
Input for high side switch 2 (active low)
14
IL2
Input for low side switch 2 (active high)
15
IH1
Input for high side switch 1 (active low)
16
IL1
Input for low side switch 1 (active high)
Data Sheet
5
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Pin Configuration
# of
Pins
Symbol
Function
17
ERR
Push pull output stage
18
SCDL
Input pin for adjustable Short Circuit Detection function and SCD deactivation
19
GND
Ground pin
20
SL
Pin for common source of lowside MOSFETs
21
GL1
Output pin for gate of low side MOSFET 1
22
SH1
Pin for source connection of high side MOSFET 1
23
GH1
Output pin for gate of high side MOSFET 1
24
BH1
Pin for + terminal of the bootstrap capacitor of phase 1
Tab
Tab
should be connected to GND
Data Sheet
6
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Conditions
Voltages
4.1.1
Supply voltage at VS
VVS
-0.3
45
V
–
4.1.2
Supply voltage at VS
VVSRP
-4.0
45
V
RVS≥10Ω
4.1.3
Voltage range at VDH
VVDH
-0.3
55
V
–
4.1.4
Voltage range at RPP
-0.3
55
V
–
4.1.5
maximum current at RPP
-25
25
mA
–
4.1.6
Voltage range at ENA
-0.3
45
V
–
4.1.7
Voltage range at SCDL
-0.3
6
V
–
4.1.8
Voltage range at IH1, IL1, IH2, IL2
-0.3
6
V
–
4.1.9
Voltage range at ERR, ISO
-0.3
6
V
–
4.1.10
Voltage range at ISP, ISN
-5.0
5.0
V
–
4.1.11
Voltage range at VREG
-0.3
15
V
–
4.1.12
Voltage range at BHx
-0.3
55
V
–
4.1.13
Voltage range at GHx
-0.3
55
V
–
4.1.14
Voltage range at GHx
-7.0
55
V
tP<1µs; f=50kHz
4.1.15
Voltage range at SHx
-2.0
45
V
–
4.1.16
Voltage range at SHx
-7.0
45
V
tP<1µs; f=50kHz
4.1.17
Voltage range at GLx
-0.3
18
V
–
4.1.18
Voltage range at GLx
VRPP
IRPP
VENA
VSCDL
VDPI
VDPO
VOPI
VVREG
VBH
VGH
VGHP
VSH
VSHP
VGL
VGLP
-7.0
18
V
tP<0.5µs;
f=50kHz
4.1.19
Voltage range at SL
-1.0
5.0
V
–
4.1.20
Voltage range at SL
VSL
VSLP
-7.0
5.0
V
tP<0.5µs;
f=50kHz;
CBS≥330nF
4.1.21
Voltage difference Gxx-Sxx
4.1.22
Voltage difference BHx-SHx
VGS
VBS
-0.3
15
V
–
-0.3
15
V
–
Temperatures
4.1.23
Junction temperature
Tj
-40
150
°C
–
4.1.24
Storage temperature
Tstg
-55
150
°C
–
4.1.25
Lead soldering temperature
(1/16’’ from body)
Tsol
–
260
°C
–
4.1.26
Peak reflow soldering temperature2)
Tref
–
260
°C
–
Ptot
–
2
W
–
VESD
–
2
kV
Power Dissipation
4.1.27
Power Dissipation (DC)
ESD Susceptibility
4.1.28
ESD Resistivity3)
Data Sheet
7
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
General Product Characteristics
Absolute Maximum Ratings (cont’d)1)
40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
4.1.29
Parameter
Symbol
CDM
VCDM
Limit Values
Min.
Max.
–
1
Unit
Conditions
kV
1) Not subject to production test, specified by design.
2) Reflow profile IPC/JEDEC J-STD-020C
3) ESD susceptibility HBM according to EIA/JESD 22-A 114B
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
4.2
Pos.
4.2.1
Functional Range
Parameter
Symbol
Specified supply voltage range
1)
Limit Values
Unit
Conditions
Min.
Max.
VVS1
7.0
34
V
–
VVS2
5.5
45
V
VVS<7V reduced
functionality
4.2.2
supply voltage range
4.2.3
Quiescent current at VS
IQVS1
–
8
µA
VVS,VVDH=12V;
ENA=Low; Tj=25°C
4.2.4
Quiescent current at VS
IQVS2
–
10
µA
VVS,VVDH<15V;
ENA=Low; Tj≤85°C
4.2.5
Quiescent current at VDH
IQVDH1
–
8
µA
VVS,VVDH=12V;
ENA=Low; Tj=25°C
4.2.6
Quiescent current at VDH
IQVDH2
–
10
µA
VVS,VVDH<15V;
ENA=Low; Tj≤85°C
4.2.7
Supply current at Vs (device
enabled)2)
IVs(1)
–
22
mA
no switching
4.2.8
Supply current at Vs (device
enabled)
IVs(2)
–
45
mA
4xQGSxfPWM≤20mA
; VVS=7.0..34V
4.2.9
D.C. switch on time of output
stages
DDC
–
∞
s
–
4.2.10
Duty cycle Highside output stage3) DHS
0
95
%
fPWM=20kHz;
continuous
operation;
CBS ≥330nF
4.2.11
Duty cycle Lowside output stage
0
100
%
–
DLS
1) operation above 34V limited by max. allowed power dissipation and max. ratings
2) Current can be higher, if driver output stages are unsupplied
3) max. limit of D.C. will increase, if fPWM or external gate charge of the MOSFETs is reduced
The PWM frequency is limited by thermal constraints and the maximum duty cycle (minimum charging time of
bootstrap capacitor).
Data Sheet
8
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
General Product Characteristics
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Pos.
4.3.1
4.3.2
Parameter
Junction to Case
Symbol
1)
Junction to Ambient
1)
RthJC
RthJA
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
–
5
K/W
–
–
35
–
K/W
2)
1) Not subject to production test, specified by design.
2) Exposed Heatslug Package use this sentence: Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural
convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner
copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first
inner copper layer.
4.4
Default State of Inputs
Table 2
Default State of Inputs (if left open)
Characteristic
State
Remark
Default state of IHx
High
High side MOSFETs off
Default state of ILx
Low
Low side MOSFETs off
Default state of ENA
Low
Output stages disabled device in sleep
mode
Default state of SCDL
OPEN
Short circuit detection deactivation &
warning
Data Sheet
9
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
5
Description and Electrical Characteristics
5.1
MOSFET Driver
5.1.1
Driving MOSFET Output Stages
The TLE7182EM incorporates 2 high side and low side output stages for 4 external MOSFETs.
Unlike other H-Bridge drivers the TLE7182EM offers 4 independent control inputs to control the MOSFETs
individually. However, the control inputs for the Highs Side MOSFETs IHx are inverted. Hence, the control inputs
for High Side IHx and Low Side MOSFETs ILx of the same half bridge can be tight together to control one half
bridge by one control signal. To avoid shoot through currents within the half bridges, a minimum dead time is
provided by the TLE7182EM. Minimum dead time is only generated, if the short circuit detection is activated.
If the TLE7182EM drives a load in between the high side MOSFET and the low side MOSFET or the driver is used
to drive 4 low side MOSFETs, the short circuit detection and the minimum dead time has to be deactivated by
pulling the SCDL pin to 5V.
For more details about the dead time please see Chapter 5.1.3.
Table 3 and Table 4 show the differed states of the output stages subject to the input conditions for activated and
deactivated shout through protection.
Table 3
ENA IL1
Truth table (shoot through active)
IH1
IL2
IH2 Lowside switch1
Highside switch1 Lowside switch2
Highside switch2
0
x
x
x
x
OFF
OFF
OFF
OFF
1
0
1
0
1
OFF
OFF
OFF
OFF
1
0
0
0
0
OFF
ON
OFF
ON
1
1
1
0
0
ON
OFF
OFF
ON
1
0
0
1
1
OFF
ON
ON
OFF
1
1
1
1
1
ON
OFF
ON
OFF
Table 4
Truth table (shoot through inactive)
ENA IL1
IH1
IL2
IH2 Lowside switch1
Highside switch1 Lowside switch2
Highside switch2
0
x
x
x
OFF
OFF
OFF
OFF
x
1
0
1
0
1
OFF
OFF
OFF
OFF
1
0
0
0
1
OFF
ON
OFF
OFF
1
1
0
0
1
ON
ON
OFF
OFF
1
0
1
0
0
OFF
OFF
OFF
ON
1
0
1
1
0
OFF
OFF
ON
ON
5.1.2
MOSFET Output Stages
The six push-pull MOSFET driver stages of the TLE7182EM are realized as separate floating blocks. This means
that the output stage is follows the individual MOSFET source voltages and so ensuring stable MOSFET driving
even in harsh electrical environment.
All 4 output stages have the same output power and thanks to the used bootstrap principle they can be switched
all up to high frequencies.
Each output stage has its own short circuit detection block. For more details about short circuit detection see
Chapter 5.2.1.
Data Sheet
10
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
VS
ENA
VDH
VREG
BHx
RPP
Voltage regulator
Charge pump
____
ERR
+
V RE G
Error logic
Reset
Power On Reset
GHx
VS C P
V DH
blanking
S CD
S CD
SHx
Level
shifter
Floating HS driver 2x
S CD
VREG
loc k /
unloc k
short circuit filter
Short Circuit
Detection Level
+
Input Logic
IH2
IH1
Shoot Through
Protection
Dead Time
GLx
-
ON / OFF
VS C P
SL
Level
shifter
ON / OFF
IL2
Floating LS driver 2x
IL1
GND
SCDL
Figure 3
Block Diagram of Driver Stages including Short Circuit Detection
5.1.3
Dead Time and Shoot Through Protection
In bridge applications it has to be assured that the external high side and low side MOSFETs are not “on” at the
same time, connecting directly the battery voltage to GND.
In TLE7182EM a minimum dead time applied. It is fixed internally and can not be programmed.
If an exact dead time of the bridge is needed, the use of the µC PWM generation unit is recommended.
In addition to this dead time, the TLE7182EM provides a locking mechanism, avoiding that both external
MOSFETs of one half bridge can be switched on at the same time. This functionality is called shoot through
protection. If the command to switch on both high and low side switches in the same half bridge is given at the
input pins, the command will be ignored. The outputs will stay in the situation like before the conflicting input.
The Shoot through protection and the dead time of the TLE7182EM will be deactivated, if a voltage of 5V is applied
at pin SCDL. The deactivation of the shoot through protection is necessary to drive valves or solenoids which are
designed in between the Lowside and Highside MOSFET of one half bridge or 4 separate low side MOSFETs.
For more detailed information how to drive valves or solenoid in between one half bridge please see Figure 7.
5.1.4
Bootstrap Principle
The TLE7182EM provides a bootstrap based supply for its high side output stages.
The bootstrap capacitors are charged by switching on the external low side MOSFETs, connecting the bootstrap
capacitor to GND. Under this condition the bootstrap capacitor will be charged from the VREG capacitor via the
integrated bootstrap diode. If the low side MOSFET is switched off and the high side MOSFET is switched on, the
bootstrap capacitor will float together with the SHx voltage to the supply voltage of the bridge. Under this condition
the supply current of the high side output stage will discharge the bootstrap capacitor. This current is specified.
Data Sheet
11
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
The size of the capacitor together with this current will determine how long the high side MOSFET can be kept on
without recharging the bootstrap capacitor.
5.1.5
100% D.C. charge pumps
100% D.C. charge pumps are implemented for each high side output stage. Therefore the high side output stages
can be switch on for an unlimited time. These integrated charge pumps can handle leakage currents which will be
caused by external MOSFETs and the TLE7182EM itself. They are not strong enough to drive a 99% duty cycle
for a longer time. the charge pumps are running when the driver is not in sleep mode and assure that the bootstrap
capacitors are charged as long as the user does not apply critical duty cycle for a longer time.
5.1.6
Reverse polarity protection of motor bridge
The TLE7182EM provides an additional RPP pin to protect motor bridge for reverse polarity. This RPP pin can
drive an additional external N-channel power MOSFET designed in between battery and the motor bridge. The
RPP pin is internally supplied by the two integrated 100% D.C. charge pumps. They are especially designed to
handle additional current which is needed to drive a the gate charge of the reverse polarity MOSFET. The
guarantied output current of the charge pumps is specified.
5.1.7
Sleep mode
If ENA pin is set to low, the ERR flag will be set to low and the output stages will be switched off.
After ENA pin is kept low for tLQM the sleep mode of the Driver IC will be activated.
In Sleep mode the complete chip is deactivated. This means the internal supply structure of the TLE7182EM will
be switched off. This mode is designed for lowest current consumption from the power net of the car. The passive
clamping is active. For details see the description of passive clamping, see Chapter 5.2.8.
The TLE7182EM will wake up, if ENA is set to high.The ENA pin is 45V compatible, so ENA can be directly be
connected to the ignition key signal KL15.
5.1.8
Electrical Characteristics
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 34V, Tj = -40 to +150°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
–
1.0
V
–
2.0
–
–
V
–
100
200
–
mV
–
320
540
770
kΩ
VVS=0V and
Control inputs
5.1.1
Low level input voltage of Ixx
5.1.2
High level input voltage of Ixx
5.1.3
Input hysteresis of Ixx
5.1.4
ILx pull-down resistor to GND
VI_LL
VI_HL
dVI
RIL
VDH=0V or open
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
RIL
IHx pull-up resistor to internal VDD RIH
Low level input voltage of ENA
VE_LL
High level input voltage of ENA
VE_HL
Input hysteresis of ENA
dVE
ENA pull-down resistor to GND
RIL
ILx pull-down resistor to GND
Data Sheet
19
32
50
kΩ
VVS or VDH >5.0V
30
–
80
kΩ
–
–
–
0.75
V
–
2.1
–
–
V
–
50
200
–
mV
–
70
125
200
kΩ
–
12
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 34V, Tj = -40 to +150°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
ILoad=-20mA
ILoad=20mA
13.5V≤VVS≤34V;
ILoad=0mA
13.5V≤VVS≤34V;
CLoad=20nF;
Min.
Typ.
Max.
RSou
RSink
VGxx1
2
–
13.5
Ω
2
–
9.0
Ω
–
11
15
V
VGxx2
–
11
13.5
V
MOSFET driver output
5.1.11
Output source resistance
5.1.12
Output sink resistance
5.1.13
High level output voltage Gxx vs.
Sxx
5.1.14
High level output voltage Gxx vs.
Sxx
D.C.=50%;
5.1.15
High level output voltage GHx vs.
SHx1)
VGHx3
–
VVS-1.5 –
V
fPWM=20kHz
7.0V<VVS<13.5V;
CLoad=20nF;
D.C.=50%;
fPWM=20kHz
5.1.16
High level output voltage GLx vs.
GND1)
VGLx3
–
VVS-0.5 –
V
7.0V<VVS<13.5V;
CLoad=20nF;
fPWM=20kHz &
D.C.=50%;
or D.C=100%
5.1.17
High level output voltage GHx vs.
SHx1)2)
VGHx4
5.0
+Vdiode
–
–
V
VVS=7.0V;
CLoad=20nF;
D.C.=95%;
fPWM=20kHz;
passive
freewheeling
5.1.18
High level output voltage GHx vs.
SHx1)
VGHx5
5.0
–
–
V
VVS=7.0V;
CLoad=20nF;
D.C.=95%;
5.1.19
High level output voltage GLx vs.
SLx1)
VGLx5
6.0
–
–
V
fPWM=20kHz
VVS=7.0V;
CLoad=20nF;
V
fPWM=20kHz
7.0V≤VVS≤13.5V;
CLoad=20nF;
D.C.=95%;
5.1.20
High level output voltage GHx vs.
SHx1)
VGHx5
10
–
–
D.C.=100%
5.1.21
High level output voltage GLx vs.
SLx1)
VGLx5
6.5
–
–
V
VVS=7.0V;
CLoad=20nF;
5.1.22
Rise time
–
250
–
ns
5.1.23
Fall time
trise
tfall
–
200
–
ns
CLoad=11nF;
RLoad=1Ω;
VVS=7V;
D.C.=100%
20-80%
Data Sheet
13
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 34V, Tj = -40 to +150°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Min.
Typ.
Max.
5.1.24
High level output voltage (in
passive clamping)1)
VGxxUV
–
–
5.1.25
Pull-down resistor at BHx to GND
RBHUVx
–
5.1.26
Pull-down resistor at VREG to GND RVRUV
5.1.27
Bias current into BHx
IBHx
Limit Values
Unit
Conditions
1.2
V
Sleep mode or
VS_UVLO
–
85
kΩ
Sleep mode or
VS_UVLO
–
–
30
kΩ
Sleep mode or
VS_UVLO
–
–
150
µA
VCBS>5V;
no switching
5.1.28
Bias current out of SHx
ISHx
–
40
–
µA
VSHx=VSL;
ENA=HIGH;
affected highside
output stage static
on;
VCBS>5V
5.1.29
Bias current out of SL
ISL
–
–
1.4
mA
0≤VSHx≤VVS+1V;
ENA=HIGH;
no switching;
VCBS>5V
Dead time & input propagation delay times
5.1.30
Min. internal dead time
tDT_MIN
0.08
0.11
0.2
µs
–
5.1.31
Dead time deviation between
channels
dtDT2
-15
–
15
%
–
5.1.32
Dead time deviation between
channels LSoff -> HS on
dtDT2
-12
–
12
%
–
5.1.33
Dead time deviation between
channels HSoff -> LS on
dtDT2
-12
–
12
%
–
5.1.34
Input propagation time (low on)
0
100
200
ns
5.1.35
Input propagation time (low off)
0
100
200
ns
CLoad=10nF;
RLoad=1Ω
5.1.36
Input propagation time (high on)
0
100
200
ns
5.1.37
Input propagation time (high off)
0
100
200
ns
5.1.38
Absolute input propagation time
difference between above
propagation times
tP(ILN)
tP(ILF)
tP(IHN)
tP(IHF)
tP(diff)
–
50
100
ns
VREG
5.1.39
VREG output voltage
VVREG
11
12.5
14
V
VVS≥13.5V;
ILoad=-35mA
5.1.40
VREG over current limitation
100
–
500
mA
–3)
5.1.41
Voltage drop between Vs and
VREG
IVREGOCL
VVsVREG
–
–
0.5
V
VVS≥7V;
ILoad=-35mA;
Ron operation
Data Sheet
14
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Description and Electrical Characteristics
Electrical Characteristics MOSFET Drivers
VS = 7.0 to 34V, Tj = -40 to +150°C all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
21
–
MHz
–
100% D.C. charge pump
5.1.42
Charge pump frequency1)
fCP
Motor bridge reverse polarity protection output
5.1.43
High level output voltage RPP vs.
VS
VRPP1
–
11
15
V
ILoad=0µA
5.1.44
High level output voltage RPP vs.
VS
VRPP2
–
11
12.5
V
ILoad≥-30µA
5.1.45
D.C. output current at RPP
IRPP1
–
-110
-150
µA
VRPP≥10V;
5.1.46
Rise time1)
–
1
2
ms
5.1.47
Rise time1)
tRPPrise
tRPPrise
–
10
20
µs
CLOAD=10nF
CLOAD=100pF
Lowside on
ENA and Low quiescent current mode
5.1.48
ENA propagation time to output
stages switched off
tPENA_H-L
–
2.0
3.0
µs
–
5.1.49
Low time of ENA signal without
clearing error register
tRST0
–
–
1.2
µs
–
5.1.50
High time of ENA signal after ENA tRST1
rising edge for error logic active
4
5.75
7
µs
–
5.1.51
go to sleep time
tsleep
310
415
540
µs
–
5.1.52
wake up time
twake
–
50
100
µs
CREG=2.2µF;
CBS=330nF
1) Not subject to production test, specified by design.
2) Vdiode is the bulk diode of the external low side MOSFET
3) normally no error flag; Error flag might by triggered by under voltage VREG caused by very high load current
Data Sheet
15
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.2
Protection and Diagnostic Functions
5.2.1
Short Circuit Protection
The TLE7182EM provides a short circuit protection for the external MOSFETs by monitoring the drain-source
voltage of the external MOSFETs.
This monitoring of the short circuit detection for a certain external MOSFET is active as soon as the corresponding
driver output stage is set to “on” and the dead time and the blanking time are expired.
The blanking time starts when the dead time has expired and assures that the switch on process of the MOSFET
is not taken into account. It is recommended to keep the switching times of the MOSFETs below the blanking time.
The short circuit detection level is adjustable in an analog way by the voltage setting at the SCDL pin. There is a
1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the
SCD circuit at 1 V drain-source voltage, the SCDL pin must be set to 1 V. The drain-source voltage limit can be
chosen between 0.2 ... 2 V.
If after the expiration of the blanking time the drain source voltage of the observed MOSFET is still higher then the
SCDL level, the SCD filter time tSCP starts to run. A capacitor is charged with a current. If the capacitor voltage
reaches a specific level (filter time tSCP), the error signal is set and the IC goes into SCDL Error Mode. If the SCD
condition is removed before the SC is detected, the capacitor is discharged with the same current. The discharging
of the capacitor happens as well when the MOSFET is switched off. It has to be considered that the high side and
the low side output of one phase are working with the same capacitor.
The Short Circuit protection of the TLE7182EM will be deactivated, if 5V is applied at pin SCDL.
5.2.2
SCDL Pin Open Detection
An integrated structure at the SCDL pin assures that in case of an open pin the SCDL voltage is pulled to a medium
voltage level. The external MOSFETs are actively switched off and an ERR flag is set. This error is self-clearing.
5.2.3
Vs and VDH Over Voltage Warning
The TLE7182EM has an integrated over voltage warning to minimize risk of destruction of the IC at high supply
voltages caused by violation of the maximum ratings. For the over voltage warning the voltage is observed at the
pin VS and VDH. If the voltage level has reached, the fixed over voltage threshold VOVW for the filter time tOV, a
warning at ERR pin is set and TLE7182EM will go in normal operation with warning.
The over voltage warning is self clearing. If the voltage at pin VS and VDH returns into the specified voltage range,
the Error register will be cleared and TLE7182EM returns to normal operation mode.
It is the decision of the user, if and how to react on the over voltage warning.
5.2.4
VS Under Voltage Shutdown
The TLE7182EM has an integrated VS Under Voltage Shutdown, to assure that the behavior of the complete IC
is predictable in all supply voltage ranges. As soon as the under voltage threshold VUVVR is reached for a specified
filter time the TLE7181EM is in VS_UVLO error mode. The error signal will be set and output stages, voltage
regulator and charge pump will be switched off so the IC will go into sleep mode. An enable is necessary to restart
the TLE7181EM.
5.2.5
VREG Under Voltage Warning
The TLE7182EM has an integrated under voltage warning detection at VREG. If the supply voltage at VREG
reaches the VREG under voltage threshold VUVVR, a warning at ERR pin is set and the TLE7182EM will go into
VREG error mode. In case of VREG error mode all output stages will actively switched off to prevent low gate
source voltages at the power MOSFETs causing high RDSon. If supply voltage at the VREG pin recovers; the
error flag will be cleared and the TLE7182EM will return in normal operation mode.
Data Sheet
16
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.2.6
Over Temperature Warning
The TLE7182EM provides an integrated digital over temperature warning to minimize risk of destruction of the IC
at high temperature. The temperature will be detected by a embedded sensor. During over temperature warning
the ERR signal is set and the TLE7182EM is in normal operation mode with warning.
The over temperature warning is self clearing. So if temperature is below Tj(PW) -dTj(OW), the warning will be cleared
and TLE7182EM returns to normal operation mode.
It is the decision of the user to react on the over temperature warning.
5.2.7
Over Current Warning
The TLE7182EM offers an integrated over current detection. The output signal of the current sense OpAmp will
be monitored. If the output signal reaches the specified voltage threshold VOCTH for a certain time, over current will
be detected. After the comparator the filter time tOC is implemented to avoid false triggering caused by overswing
of the current sense signal. The ERR pin will be set to low and the TLE7182EM will go into normal operation mode
with warning.
The error signal disappears as soon as the current decreases below the over current threshold VOCTH. The error
signal disappears as well when the current commutates from the low side MOSFET to the associated high side
MOSFET and is no longer flowing over the shunt resistor.
It is the decision of the user to react on the over current signal by modifying input patterns.
5.2.8
Passive Gxx Clamping
If VS Under Voltage shutdown is detected or the device is in Sleep Mode, a passive clamping is active as long as
the voltage at VS or VDH is higher than 3V. Even below 3V it is assured that the MOSFET driver stage will not
switch on the MOSFET actively.
The passive clamping means that the BHx and the VREG pin are pulled to GND with specified pull down resistors.
Together with the intrinsic diode of the push stage of the output stages which connect the gate output to BHx
respectively VREG, this assures that the gate of the external MOSFETs are not floating undefined.
5.2.9
ERR Pin
The TLE7182EM has a status pin to provide diagnostic feedback to the µC. The logical output of this pin is a push
pull output stage with an integrated pull-down resistor to GND (see Figure 4).
Reset of error registers and Disable
The TLE7182EM can be reset by the enable pin ENA. If the ENA pin is pulled to low for a specified minimum time,
the error registers are cleared. ERR output is still set to low. After the next rising edge at ENA pin ERR pin will be
set to high and no error condition is applied.
Data Sheet
17
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
µC
TLE718xEM
Internal
5V
internal
Error
Logic
ERR
Interface_ µC
GND
Figure 4
Structure of ERR output
Table 5
Overview of error condition
GND
ERR
Driver conditions
Driver action
Restart
High
no errors
Fully functional
–
Low
Over temperature
Warning only
Self clearing
Low
Over voltage VS/VDH
Warning only
Self clearing
Low
Over current OPAMP
Warning only
Self clearing
Low
Under voltage error VREG
All MOSFETs actively
switched off
Self clearing
Low
Under voltage shutdown based MOSFET, charge pump,
on VS
Vreg switched off
Self clearing
restart when enable high1)
Low
SCDL open pin
All MOSFETs actively
switched off
Self clearing
Low
Short circuit detection
All MOSFETs actively
switched off
Reset at ENA needed
Low
Go to sleep mode
All MOSFETs actively
switched off
immediate restart when
ENA goes high
Low
Wake up mode
start up
–
1) When SC detected, reset with ENA necessary
Table 6
Prioritization of Errors
Priority
Errors and Warnings
0
Under voltage lockout at Vs (VS_UVLO)
1
Short circuit detection error (SCD)
SCDL pin open warning (SCDLPOD)
2
Under voltage detection VREG (UV_VREG)
Over voltage detection warning (OVD)
Over temperature warning (OTD)
Over current warning (OCD)
Data Sheet
18
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.2.10
Electrical Characteristics
Electrical Characteristics - Protection and diagnostic functions
VS = 7.0 to 34V, Tj = -40 to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
Short circuit protection
5.2.1
Short circuit protection detection
level input range
VSCDL
0.2
–
2.0
V
programmed by
SCDL pin
5.2.2
Short circuit protection detection
accuracy
ASCP1
-50
–
+50
%
0.2V≤ VSCDL≤0.3V
5.2.3
Short circuit protection detection
accuracy
ASCP2
-30
–
+30
%
0.3V≤ VSCDL≤1.2V
5.2.4
Short circuit protection detection
accuracy
ASCP3
-10
–
+10
%
1.2V≤ VSCDL≤2.0V
5.2.5
Filter time of short circuit protection tSCP(off)
2.5
3.5
4.5
µs
–
5.2.6
Filter time and blanking time of
short circuit protection
4
6
8
µs
–
5.2.7
Internal pull-up resistor SCDL to 3V RSCDL
180
300
475
kΩ
–
5.2.8
SCDL open pin detection level
2.1
–
3.2
V
–
5.2.9
Filter time of SCDL open pin
detection
VSCPOP
tSCPOP
1.5
2.5
3.5
µs
–
5.2.10
SCDL open pin detection level
hysteresis1)
VSCOPH
–
0.3
–
V
–
5.2.11
Threshold voltage for deactivation
of:
- SC detection
- dead-time generation
- shoot-through protection
VSCPDIS
4.5
–
–
V
–
5.2.12
Filter time of SCD deactivation
tSCPDIS
1.0
2.0
3.1
µs
–
VOVW
34.5
36.5
38.5
V
VVS and/or VVDH
increasing
tSCPBT
Over- and under voltage monitoring
5.2.13
Over voltage warning at Vs and/or
VDH
5.2.14
Over voltage warning hysteresis for VOVWhys
Vs and/or VDH
2.1
3.1
4.1
V
–
5.2.15
Over voltage warning filter time for tOV
Vs and/or VDH
13
19
25
µs
–
5.2.16
VUVVR
Under voltage shutdown filter time tUVLO
4.5
5.0
5.5
V
VVS decreasing
–
20
–
µs
–
VUVVR
Under voltage diagnosis filter time tUVVR
5.5
6.0
6.5
V
VVS decreasing
10
–
30
µs
–
–
0.5
–
V
–
5.2.17
Under voltage shutdown at Vs
for VS1)
5.2.18
5.2.19
Under voltage warning at VREG
for VREG
5.2.20
Under voltage hysteresis at VREG VUWRhys
Data Sheet
19
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Electrical Characteristics - Protection and diagnostic functions (cont’d)
VS = 7.0 to 34V, Tj = -40 to +150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
Temperature monitoring
5.2.21
Over temperature warning
Tj(PW)
160
170
180
°C
–
5.2.22
Hysteresis for over temperature
warning
dTj(OW)
10
–
20
°C
–
VOCTH
Filter time for over current detection tOC
4.5
–
4.99
V
–
2.3
–
4.3
µs
–
4.6
–
–
V
–
–
3
µs
VVS=7V;
CLOAD=1nF;
60
100
170
kΩ
–
Over current detection
5.2.23
5.2.24
ERR pin
5.2.25
5.2.26
Over current detection level
2)
VERR
Rise time ERR (20 - 80% of internal tf(ERR)
ERR output voltage
5V)
5.2.27
Internal pull-down resistor ERR to
GND
Rf(ERR)
1) Not subject to production test, specified by design.
2) ERR pin and Reset & Enable functional between VVS=6 ... 7V, but characteristics might be out of specified range
Data Sheet
20
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
5.3
Shunt Signal Conditioning
The TLE7182EM incorporates a fast and precise operational amplifier for conditioning and amplification of the
current sense shunt signal. The gain of the OpAmp is adjustable by external resistors within a range higher than 5.
The usage of higher gains in the application might be limited by required settling time and band width.
It is recommended to apply a small offset to the OpAmp, to avoid operation in the lower rail at low currents.
The output of the OpAmp ISO is not short-circuit proof.
V DD
RREF1
TLE718xEM
R S1
ISP
R shunt
+
ISO
ISN
R S2
external
+
RREF2
-
ERR
RFB
Figure 5
VOCTH
RFB=(R REF1 ||R REF2 )
Shunt Signal Conditioning Block Diagram and Over Current Limitation
Over current warning see Chapter 5.2.7.
5.3.1
Electrical Characteristics
Electrical Characteristics - Current sense signal conditioning
VS = 7.0 to 36V, Tj = -40 to +150°C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
5.3.1
Series resistors
100
500
5.3.2
Feedback resistor
Limited by the output voltage
dynamic range
RS
Rfb
1000
Ω
–
2000
7500
–
Ω
–
5.3.3
Resistor ratio (gain ratio)
5.3.4
Steady state differential input
voltage range across VIN
Rfb/RS
VIN(ss)
5
–
–
–
–
-400
–
400
mV
–
5.3.5
Input differential voltage (ISP - ISN) VIDR
-800
–
800
mV
–
5.3.6
Input voltage (Both Inputs - GND)
(ISP - GND) or (ISN -GND)
-800
–
2000
mV
–
5.3.7
Input offset voltage of the I-DC link VIO
OpAmp, including temperature drift
–
–
+/-2
mV
5.3.8
Input bias current (ISN,ISP to GND) IIB
-300
–
–
µA
5.3.9
Low level output voltage of ISO
-0.1
–
0.2
V
RS=500Ω; VCM=0V;
VISO=1.65V;
VCM=0V; VISO=open
IOH=3mA
Data Sheet
VLL
VOL
Limit Values
21
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Electrical Characteristics - Current sense signal conditioning (cont’d)
VS = 7.0 to 36V, Tj = -40 to +150°C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Min.
Typ.
Max.
5.3.10
High level output voltage of ISO
VOH
4.75
–
5.2
5.3.11
Output short circuit current
–
Differential input resistance1)
ISCOP
RI
CCM
CMRR
5
5.3.12
100
–
–
–
80
100
1)
Limit Values
Unit
Conditions
V
IOH=-3mA
–
mA
–
–
kΩ
–
10
pF
10kHz
–
dB
–
–
dB
VIN=360mV*
5.3.13
Common mode input capacitance
5.3.14
Common mode rejection ratio at
DC
CMRR =
20*Log((Vout_diff/Vin_diff) *
(Vin_CM/Vout_CM))
5.3.15
Common mode suppression2) with CMS
CMS = 20*Log(Vout_CM/Vin_CM)
Freq =100kHz
Freq = 1MHz
Freq = 10MHz
–
dV/dt
–
10
–
V/µs
Gain≥ 5;
RL=1.0kΩ;
CL=500pF
sin(2*π*freq*t);
Rs=500Ω;
Rfb=7500Ω
62
43
23
5.3.16
Slew rate
5.3.17
Large signal open loop voltage gain AOL
(DC)
80
100
–
dB
–
5.3.18
Unity gain bandwidth1)
GBW
FM
10
20
–
MHz
RL=1kΩ; CL=100pF
–
50
–
°
Gain≥ 5;
RL=1kΩ; CL=100pF
–
12
–
dB
RL=1kΩ; CL=100pF
0.7
1.3
–
MHz
Gain=15;
RL=1kΩ;
CL=500pF;
Rs=500Ω
Gain=15;
RL=1kΩ;
CL=500pF;
0.3<VISO< 4.8V;
Rs=500Ω
1)
5.3.19
Phase margin
5.3.20
Gain margin 1)
5.3.21
Bandwidth
AM
BWG
5.3.22
Output settle time to 98%
tset1
–
1
1.8
µs
5.3.23
Output settle time to 98%1)
tset2
–
4.6
–
µs
Gain=75;
RL=1kΩ;
CL=500pF;
0.3<VISO< 4.8V;
Rs=500Ω
1) Not subjected to production test; specified by design
2) Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external
resistors.
Data Sheet
22
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Application Information
6
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
This is the description how the IC is used in its environment…
L
2,2µH
VBAT
RVS
RG
CVS1
2,2µF
CVS2
10nF
CREG2
10nF
PGND
VS
VREG
GND
CREG1
2,2µF
RRPS
4.7kΩ
PGND
RVDH
RPP
VDH
ENA
BH1
CBS1
330nF THS1
GH1
CSNH1
RGH1
+ CB1
CC1
RSNH1
SH1
____
ERR
BH2
CBS2
330nF
PGND
THS2
C SNH2
GH2
IL1
___
IH1
IL2
___
IH2
R GH2
CC2
+ CB2
R SNH2
SH2
TLE
7182EM
PGND
M
TLS 1
µC
e.g.:
XC2xxx
GL1
C SNL1
RGL 1
RSNL1
TLS 2
VDD
C SNL2
GL2
RGL2
RSC1
SCDL
SL
R SNL2
Vref
R SC2
RREF1
ISP
CIS
50pF
ISN
GND
GND
Figure 6
Data Sheet
ISO
RISO
CISO
100pF
GND
RREF2
RS2
Shunt
GND
R S1
RFB
GND
RFB = (RREF1 ||RREF2)
PGND
Application Diagram 1: DC-Brush motor controlled by TLE7182EM
23
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Application Information
L
2,2µH
VBAT
RVS
RG
CVS1
2,2µF
CVS2
10nF
CREG2
10nF
PGND
VS
VREG
GND
CREG1
2,2µF
RRPS
4.7kΩ
PGND
RVDH
RPP
VDH
ENA
BH1
CBS1
330nF THS1
GH1
CSNH1
R GH1
C
+ B1
CC1
R SNH1
SH1
____
ERR
BH2
CBS2
330nF
PGND
THS2
CSNH2
GH2
IL1
___
IH1
IL2
___
IH2
RGH2
CC2
+ CB2
RSNH2
SH2
TLE
7182EM
PGND
V
V
TLS 1
µC
e.g.:
XC2xxx
GL1
CSNL1
RGL1
RSNL1
TLS 2
VDD
CSNL2
GL2
R GL2
RSC1
SCDL
RSNL2
SL
Vref
R SC2
RREF1
ISP
CIS
50pF
ISN
GND
GND
Figure 7
ISO
RISO
CISO
100pF
GND
R REF2
RS2
Shunt
GND
RS1
RFB
RFB = (RREF1||RREF2)
GND
PGND
Application Diagram 2: 2 inductive loads driven by TLE7182EM
Note: This are very simplified examples of an application circuit. The function must be verified in the real
application.
Data Sheet
24
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Application Information
6.1
Layout Guide Lines
Please refer also to the simplified application example.
•
•
•
•
•
•
•
•
•
Two separated bulk capacitors CB should be used - one per half bridge
Two separated ceramic capacitors CC should be used - one per half bridge
Each of the two bulk capacitors CB and each of the two ceramic capacitors CC should be assigned to one of
the half bridges and should be placed very close to it
The components within one half bridge should be placed close to each other: high side MOSFET, low side
MOSFET, bulk capacitor CB and ceramic capacitor CC (CB and CC are in parallel) and the shunt resistor form
a loop that should be as small and tight as possible. The traces should be short and wide
The connection between the source of the high side MOSFET and the drain of the low side MOSFET should
be as low inductive and as low resistive as possible.
VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point
of the drains of the high side MOSFETs to sense the voltage present on drain high side
SL is the sense pin used for short circuit detection; SL should be routed o the common point of the source of
the low side MOSFETs to sense the voltage present on source low side
Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during
switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C
(several nF) must be low inductive in terms of routing and packaging (ceramic capacitors)
if available the exposed pad on the backside of the package should be connected to GND
6.2
•
Further Application Information
For further information you may contact http://www.infineon.com/
Data Sheet
25
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Package Outlines
0.2
M
0.64 ±0.25
6 ±0.2
D
0.2
M
D
Bottom View
A
24
13
1
3.9 ±0.11)
0.08 C
Seating Plane
C A-B D 24x
0.19 +0.06
0.1 C D
12
B
8.65 ±0.1
Index Marking
1
12
24
13
2.65 ±0.25
0.25 ±0.05
2)
2x
8˚ MAX.
C
0.65
0.35 x 45˚
1.7 MAX.
Stand Off
(1.47)
Package Outlines
0.1+0
-0.1
7
6.4 ±0.25
0.1 C A-B 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion of 0.13 max.
PG-SSOP-24-4-PO V01
Figure 8
PG-SSOP-24-4
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
26
Dimensions in mm
Rev 1.1, 2010-09-30
H-Bridge and Dual Half Bridge Driver IC
TLE7182EM
Revision History
8
Revision History
Revision
Date
Changes
1.1
2010-09-30
Datasheet
Max rating of current at RPP pin increased
1.0
2010-09-29
Datasheet
Thermal resistance of package adjusted
Output rise time adjusted
Pull up and pull down resistor values adapted
Dead time values centered
Go to sleep time modified
Filter time of short circuit detection adjusted
SCDL pin open detection description improved
Overview of error condition table improved
Filter time and blanking time of short circuit detection adjusted
SCDL open pin detection level added
Filter time of SCDL open pin detection adjusted
Over voltage warning at Vs and/or VDH centered
Over voltage warning hysteresis for Vs and/or VDH centered
Over voltage warning filter time for Vs and/or VDH centered
ERR output voltage added
OpAmp bandwidth adjusted
0.8
2010-08-31
Preliminary Datasheet
0.7
2009-11-19
Target data sheet
0.6
2008-30-10
Target data sheet
Data Sheet
27
Rev 1.1, 2010-09-30
Edition 2010-09-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
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of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
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