DRV8302 SLES267 – AUGUST 2011 www.ti.com Three Phase Pre-Driver with Dual Current Shunt Amplifiers and Buck Regulator – Hardware Controlled Check for Samples: DRV8302 FEATURES DESCRIPTION • • The DRV8302 is a gate driver IC for three phase motor drive applications. It provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the high-side and one for the low side. It supports up to 2.3A sink and 1.7A source peak current capability and only needs a single power supply with a wide range from 8 to 60V. The DRV8302 uses bootstrap gate drivers with trickle charge circuitry to support 100% duty cycle. The gate driver uses automatic hand shaking when high side FET or low side FET is switching to prevent current shoot through. Vds of FETs is sensed to protect external power stage during overcurrent conditions. 1 • • • • • • • Operating Supply Voltage 8V–60V 2.3A Sink and 1.7A Source Gate Drive Current Capability Integrated Dual Shunt Current Amplifiers With Adjustable Gain and Offset Integrated Buck Converter to Support up to 1.5A External Load Independent Control of 3 or 6 PWM Inputs Bootstrap Gate Driver With 100% Duty Cycle Support Programmable Dead Time to Protect External FETs from Shoot Through Programmable Overcurrent Protection of External MOSFETs Thermally Enhanced 56-Pin TSSOP Pad Down DCA Package The DRV8302 includes two current shunt amplifiers for accurate current measurement. The current amplifiers support bi-directional current sensing and provide an adjustable output offset of up to 3V. The DRV8302 also has an integrated switching mode buck converter with adjustable output and switching frequency to support MCU or additional system power needs. The buck is capable to drive up to 1.5A load. APPLICATIONS • • • • 3-Phase Brushless DC Motor and Permanent Magnet Synchronous Motor CPAP and Pump E-bike, Hospital Bed, Wheel Chair Power Drill, Blender, Chopper PVDD DRV8302 GH_ A GL_A Buck Converter Vs Motor Controller Three-Phase NMOS Gate Driver PWM 3 or 6 Control Error Reporting Control and Protection Logic ADC1 GH_ B MOTOR GL_B GH_C GL_C offset + _ offset + _ Vref ADC2 Figure 1. DRV8302 Simplified Application Schematic 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated DRV8302 SLES267 – AUGUST 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION PIN ASSIGNMENT The DRV8302 is designed to fit the 56pin DCA package. Here is the pinout of the device. RT_CLK COMP 1 2 56 55 SS_TR EN_BUCK VSENSE PWRGD 3 4 54 53 PVDD2 PVDD2 OCTW FAULT DTC M_PWM M_OC GAIN 5 6 51 7 50 8 49 9 48 10 47 OC_ADJ DC_CAL 11 46 GVDD CP1 13 14 CP2 EN_GATE INH_A INL_A 15 INH_B INL_B INH_C INL_C DVDD REF 2 52 BST_BK PH PH BIAS BST_A GH_A SH_A GL_A 44 43 SL_A BST_B 42 39 GH_B SH_B GL_B SL_B 19 38 BST_C 20 37 21 36 GH_C SH_C GL_C SL_C SN1 16 17 18 Power Pad (57) - GND 45 12 41 40 22 35 23 34 24 33 SO1 SO2 25 32 26 31 SP1 SN2 AVDD AGND 27 28 30 29 SP2 PVDD1 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com PIN FUNCTIONS PIN NAME NO. I/O (1) DESCRIPTION RT_CLK 1 I Resistor timing and external clock for buck regulator. Resistor should connect to GND (power pad) with very short trace to reduce the potential clock jitter due to noise. COMP 2 O Buck error amplifier output and input to the output switch current comparator. VSENSE 3 I Buck output voltage sense pin. Inverting node of error amplifier. PWRGD 4 I An open drain output with external pull-up resistor required. Asserts low if buck output voltage is low due to thermal shutdown, dropout, over-voltage, or EN_BUCK shut down OCTW 5 O Over current and over temperature warning indicator. This output is open drain with external pull-up resistor required. FAULT 6 O Fault report indicator. This output is open drain with external pull-up resistor required. DTC 7 I Dead-time adjustment with external resistor to GND M_PWM 8 I Mode selection pin for PWM input configuration. If M_PWM = LOW, the device supports 6 independent PWM inputs. When M_PWM = HIGH, the device must be connected to ONLY 3 PWM input signals on INH_x. The complementary PWM signals for low side signaling will be internally generated from the high side inputs. M_OC 9 I Mode selection pin for over-current protection options. If M_OC = LOW, the gate driver will operate in a cycle-by-cycle current limiting mode. If M_OC = HIGH, the gate driver will shutdown the channel which detected an over-current event. GAIN 10 O Gain selection for integrated current shunt amplifiers. If GAIN = LOW, the internal current shunt amplifiers have a gain of 10V/V. If GAIN = HIGH, the current shunt amplifiers have a gain of 40V/V. OC_ADJ 11 I Over-current trip set pin. Apply a voltage on this pin to set the trip point for the internal over-current protection circuitry. A voltage divider from DVDD is recommended. DC_CAL 12 I When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset calibration can be done through external microcontroller. GVDD 13 P Internal gate driver voltage regulator. GVDD cap should connect to GND CP1 14 P Charge pump pin 1, ceramic cap should be used between CP1 and CP2 CP2 15 P Charge pump pin 2, ceramic cap should be used between CP1 and CP2 EN_GATE 16 I Enable gate driver and current shunt amplifiers. Control buck via EN_BUCK pin. INH_A 17 I PWM Input signal (high side), half-bridge A INL_A 18 I PWM Input signal (low side), half-bridge A INH_B 19 I PWM Input signal (high side), half-bridge B INL_B 20 I PWM Input signal (low side), half-bridge B INH_C 21 I PWM Input signal (high side), half-bridge C INL_C 22 I PWM Input signal (low side), half-bridge C DVDD 23 P Internal 3.3V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry. REF 24 I Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the voltage set on this pin. Connect to ADC reference in microcontroller. SO1 25 O Output of current amplifier 1 SO2 26 O Output of current amplifier 2 AVDD 27 P Internal 6V supply voltage, AVDD cap should connect to AGND. This is an output, but not specified to drive external circuitry. AGND 28 P Analog ground pin PVDD1 29 P Power supply pin for gate driver and current shunt amplifier. PVDD1 is independent of buck power supply, PVDD2. PVDD1 cap should connect to GND SP2 30 I Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best commom mode rejection. SN2 31 I Input of current amplifier 2 (connecting to negative input of amplifier). SP1 32 I Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground side of the sense resistor for the best commom mode rejection. SN1 33 I Input of current amplifier 1 (connecting to negative input of amplifier). (1) KEY: I =Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 3 DRV8302 SLES267 – AUGUST 2011 www.ti.com PIN FUNCTIONS (continued) PIN I/O (1) DESCRIPTION NAME NO. SL_C 34 I Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and SH_C. GL_C 35 O Gate drive output for Low-Side MOSFET, half-bridge C SH_C 36 I High-Side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and PVDD1. GH_C 37 O Gate drive output for High-Side MOSFET, half-bridge C BST_C 38 P Bootstrap cap pin for half-bridge C SL_B 39 I Low-Side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and SH_B. GL_B 40 O Gate drive output for Low-Side MOSFET, half-bridge B SH_B 41 I High-Side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and PVDD1. GH_B 42 O Gate drive output for High-Side MOSFET, half-bridge B BST_B 43 P Bootstrap cap pin for half-bridge B SL_A 44 I Low-Side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and SH_A. GL_A 45 O Gate drive output for Low-Side MOSFET, half-bridge A SH_A 46 I High-Side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and PVDD1. GH_A 47 O Gate drive output for High-Side MOSFET, half-bridge A BST_A 48 P Bootstrap cap pin for half-bridge A 49 I Bias pin. Connect 1MΩ resistor to GND, or 0.1 µF capacitor to GND. 50, 51 O The source of the internal high side MOSFET of buck converter BST_BK 52 P Bootstrap cap pin for buck converter PVDD2 BIAS PH 53,54 P Power supply pin for buck converter, PVDD2 cap should connect to GND. EN_BUCK 55 I Enable buck converter. Internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors SS_TR 56 I Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Cap should connect to GND GND (POWER PAD) 57 P GND pin. The exposed power pad must be electrically connected to ground plane through soldering to PCB for proper operation and connected to bottom side of PCB through vias for better thermal spreading. 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com FUNCTION BLOCK DIAGRAM PVDD1 OCTW FAULT EN _GATE DTC M_PWM M_OC GAIN OC_ADJ BIAS CP2 Gate Driver Control & Fault Handling OSC Charge Pump Regulator CP1 GVDD Trickle Charge PVDD1 BST _A Phase A ( repeated for B& C) Timing and Control Logic INH_A INL _A High Side Gate Drive GH _A Low Side Gate Drive GL _A Motor SH_A SL _A PVDD2 Current Sense Amplifier1 VSENSE BST _ BK SN1 SP1 Rshunt 1 REF PH PGND DC _ CAL Offset ½ Vref EN _ BUCK PWRGD SN2 Current Sense Amplifier2 Buck Converter SP2 Power Pad AVDD Offset ½ Vref SS _ TR RT _ CLK GND COMP DVDD SO1 SO2 AGND AGND GND PGND Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 5 DRV8302 SLES267 – AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) VALUE MIN MAX –0.3 70 UNITS PVDD Supply voltage range including transient Relative to PGND PVDDRAMP Maximum supply voltage ramp rate Voltage rising up to PVDDMAX VPGND Maximum voltage between PGND and GND ±0.3 V IIN_MAX Maximum current, all digital and analog input pins except FAULT and OCTW pins ±1 mA IIN_OD_MAX Maximum sinking current for open drain pins (FAULT and OCTW Pins) 7 mA VOPA_IN Voltage range for SPx and SNx pins ±0.6 VLOGIC Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C, INL_C, EN_GATE, M_PWM, M_OC, OC_ADJ, GAIN, DC_CAL) -0.3 VGVDD Maximum voltage for GVDD Pin 13.2 V VAVDD Maximum voltage for AVDD Pin 8 V VDVDD Maximum voltage for DVDD Pin 3.6 V VREF Maximum reference voltage for current amplifier 7 V IREF Maximum current for REF Pin 100 TJ Maximum operating junction temperature range –40 150 °C TSTORAGE Storage temperature range –55 150 °C (1) 50 V V/mS V 7 V µA Capacitive discharge model 500 V Human body model 2000 V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION DRV8302 THERMAL METRIC (1) DCA UNITS (56) PINS θJA Junction-to-ambient thermal resistance 30.3 θJCtop Junction-to-case (top) thermal resistance 33.5 θJB Junction-to-board thermal resistance 17.5 ψJT Junction-to-top characterization parameter 0.9 ψJB Junction-to-board characterization parameter 7.2 θJCbot Junction-to-case (bottom) thermal resistance 0.9 (1) 6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS PVDD1 DC supply voltage PVDD1 for normal operation Relative to PGND PVDD2 DC supply voltage PVDD2 for buck converter CAVDD External capacitance on AVDD pin (ceramic cap) 20% tolerance CDVDD CGVDD MIN TYP MAX 8 60 3.5 60 UNITS V V 1 µF External capacitance on DVDD pin (ceramic cap) 20% tolerance 1 µF External capacitance on GVDD pin (ceramic cap) 20% tolerance 2.2 µF CCP Flying cap on charge pump pins (between CP1 and CP2) (ceramic cap) 20% tolerance 22 nF CBST Bootstrap cap (ceramic cap) IDIN_EN Input current of digital pins when EN_GATE is high IDIN_DIS Input current of digital pins when EN_GATE is low CDIN CO_OPA RDTC Dead time control resistor range. Time range is 50ns (-GND) to 500ns (150kΩ) with a linear approximation. IFAULT FAULT pin sink current. Open-drain IOCTW OCTW pin sink current. Open-drain VREF External voltage reference voltage for current shunt amplifiers fgate Operating switching frequency of gate driver TA Ambient temperature 100 nF 100 µA 1 µA Maximum capacitance on digital input pin 10 pF Maximum output capacitance on outputs of shunt amplifier 20 pF 150 kΩ V = 0.4 V 2 mA V = 0.4 V 2 mA 6 V 0 2 Qg(TOT) = 25 nC or total 30 mA gate drive average current –40 200 kHz 125 °C ELECTRICAL CHARACTERISTICS PVDD = 8-60 V, TC = 25°C, unless specified under test condition PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT PINS: INH_X, INL_X, M_PWM, M_OC, GAIN, EN_GATE, DC_CAL VIH High input threshold 2 VIL Low input threshold REN_GATE Internal pull down resistor for EN_GATE RINH_X Internal pull down resistor for high side PWMs (INH_A, INH_B, and INH_C) RINH_X V 0.8 V 100 kΩ EN_GATE high 100 kΩ Internal pull down resistor for low side PWMs (INL_A, INL_B, and INL_C) EN_GATE high 100 kΩ RM_PWM Internal pull down resistor for M_PWM EN_GATE high 100 kΩ RM_OC Internal pull down resistor for M_OC EN_GATE high 100 kΩ RDC_CAL Internal pull down resistor for DC_CAL EN_GATE high 100 kΩ OUTPUT PINS: FAULT AND OCTW VOL Low output threshold IO = 2 mA VOH High output threshold External 47 kΩ pull up resistor connected to 3-5.5 V 0.4 IOH Leakage Current on Open Drain Pins When Logic High (FAULT and OCTW) 2.4 V 1 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 V µA 7 DRV8302 SLES267 – AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) PVDD = 8-60 V, TC = 25°C, unless specified under test condition PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C VGX_NORM Gate driver Vgs voltage PVDD = 8–60V Ioso1 Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 9.5 1.7 11.5 A Iosi1 Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.3 A Rgate_off Gate output impedence during standby mode when EN_GATE low (pins GH_x, GL_x) 1.6 V 2.4 kΩ 50 µA SUPPLY CURRENTS IPVDD1_STB PVDD1 supply current, standby EN_GATE is low. PVDD1 = 8V. 20 IPVDD1_OP PVDD1 supply current, operating EN_GATE is high, no load on gate drive output, switching at 10 kHz, 100 nC gate charge 15 IPVDD1_HIZ PVDD1 Supply current, HiZ EN_GATE is high, gate not switching 2 5 mA 11 mA INTERNAL REGULATOR VOLTAGE AVDD AVDD voltage 6 6.5 7 V DVDD DVDD voltage 3 3.3 3.6 V 6 V 8 V VOLTAGE PROTECTION VPVDD_UV Under voltage protection limit, PVDD VGVDD_UV Under voltage protection limit, GVDD VGVDD_OV Over voltage protection limit, GVDD 16 V CURRENT PROTECTION, (VDS SENSING) VDS_OC Drain-source voltage protection limit Toc OC sensing response time 1.5 µs TOC_PULSE OCTW pin reporting pulse stretch length for OC event 64 µs 8 0.125 Submit Documentation Feedback 2.4 V Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com GATE TIMING AND PROTECTION CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING, OUTPUT PINS tpd,If-O Positive input falling to GH_x falling CL=1nF, 50% to 50% 45 ns tpd,Ir-O Positive input rising to GL_x falling CL=1nF, 50% to 50% 45 ns (1) Td_min Minimum dead time after hand shaking Tdtp Dead Time With RDTC set to different values tGDr Rise time, gate drive output CL=1nF, 10% to 90% 25 ns tGDF Fall time, gate drive output CL=1nF, 90% to 10% 25 ns TON_MIN Minimum on pulse Not including handshake communication. Hiz to on state, output of gate driver Tpd_match Tdt_match 50 50 ns 500 ns 50 ns Propagation delay matching between high side and low side 5 ns Deadtime matching 5 ns 10 ms 10 us TIMING, PROTECTION AND CONTROL tpd,R_GATE-OP Start up time, from EN_GATE active high to device ready for normal operation PVDD is up before start up, all charge pump caps and regulator caps as in recommended condition tpd,R_GATE-Quick If EN_GATE goes from high to low and back to high state within quick reset time, it will only reset all faults and gate driver without powering down charge pump, current amp, and related internal voltage regulators. Maximum low pulse time tpd,E-L Delay, error event to all gates low 200 ns tpd,E-FAULT Delay, error event to FAULT low 200 ns OTW_CLR Junction temperature for resetting over temperature warning 115 °C Junction temperature for over OTW_SET/OTSD temperature warning and resetting over _CLR temperature shut down 130 °C 150 °C OTSD_SET (1) Junction temperature for over temperature shut down 5 Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 9 DRV8302 SLES267 – AUGUST 2011 www.ti.com CURRENT SHUNT AMPLIFIER CHARACTERISTICS TC = 25°C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G1 Gain option 1 (GAIN = 0V) 9.5 10 10.5 V/V G2 Gain Option 2 (GAIN = 2V) 38 40 42 V/V Tsettling Settling time to 1% Tc = 0-60°C, G = 10, Vstep = 2 V 300 ns Tsettling Settling time to 1% Tc = 0-60°C, G = 40, Vstep = 2 V 1.2 µs Vswing Output swing linear range 0.3 Slew Rate 5.7 G = 10 10 DC_offset Offset error RTI G = 10 with input shorted Drift_offset Offset drift RTI Ibias Input bias current Vin_com Common input mode range Vin_dif Differential input range Vo_bias Output bias With zero input current, Vref up to 6 V CMRR_OV Overall CMRR with gain resistor mismatch CMRR at DC, gain = 10 4 –0.3 –0.5% 0.5×Vref 70 85 mV µV/C 10 –0.15 V V/µs 100 µA 0.15 V 0.3 V 0.5% V dB BUCK CONVERTER CHARACTERISTICS TC = 25°C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX Internal undervoltage lockout threshold No voltage hysteresis, rising and falling ISD(PVDD2) Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 µA INON_SW(PVDD2) Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V 116 136 µA VEN_BUCK Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.25 1.55 V RDS_ON On-resistance VIN = 12 V, BOOT-PH = 6 V 200 410 mΩ ILIM Current limit threshold VIN = 12 V, TJ = 25°C OTSD_BK Thermal shutdown Fsw Switching frequency PWRGD 10 2.5 UNIT VUVLO 0.9 1.8 RT = 200 kΩ 450 V 2.7 A 150 °C 581 720 kHz VSENSE falling 92% VSENSE rising 94% VSENSE rising 109% VSENSE falling 107% Hysteresis VSENSE falling 2% Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω VSENSE threshold Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com FUNCTIONAL DESCRIPTION THREE-PHASE GATE DRIVER The DRV8302 provides three half bridge drivers, each capable of driving two N-type MOSFETs, one for the high-side and one for the low side. Gate driver has following features: • Internal hand shake between high side and low side FETs during switching transition to prevent current shoot through. • Support up to 200kHz switching frequency with Qg(TOT)=25nC or total 30mA gate drive average current • Provide cycle-by-cycle current limiting and latch over-current (OC) shut down of external FETs. Current is sensed through FET drain-to-source voltage and the over-current level is programmable through OC_ADJ pin • High side gate drive will survive negative output from half bridge up to –10V for 10ns • During EN_GATE pin low and fault conditions, gate driver will keep external FETs in high impedance mode. • Programmable dead time through DTC pin. Dead time control range: 50ns to 500ns. Short DTC pin to ground will provide minimum dead time (50ns). External dead time will override internal dead time as long as the time is longer than the dead time setting (minimum hand shake time cannot be reduced in order to prevent shoot through current). • Bootstraps are used in high side FETs of three-phase pre-gate driver. Trickle charge circuitry is used to replenish current leakage from bootstrap cap and support 100% duty cycle operation. CURRENT SHUNT AMPLIFIERS The DRV8302 includes two high performance current shunt amplifiers for accurate current measurement. The current amplifiers provide output offset up to 3V to support bi-directional current sensing. Current shunt amplifier has following features: • Programmable gain: 2 gain settings through GAIN pin • Programmable output offset through reference pin (half of the Vref) • Minimize DC offset and drift over temperature with dc calibrating through DC_CAL pin. When DC calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating can be done at anytime even when FET is switching since the load is disconnected. For best result, perform the DC calibrating during switching off period when no load is present to reduce the potential noise impact to the amplifier. The output of current shunt amplifier can be calculated as: V VO = REF - G ´ (SNX - SPX ) 2 (1) Where Vref is the reference voltage, G is the gain of the amplifier; SNx and SPx are the inputs of channel x. SPx should connect to resistor ground for the best common mode rejection. Figure 2 shows current amplifier simplified block diagram. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 11 DRV8302 SLES267 – AUGUST 2011 www.ti.com DC_CAL SN 200 kW S2 50 kW S1 5 kW AVDD _ 100 W DC_CAL SO 5 kW + SP 50 kW S1 200 kW S2 DC_CAL Vref /2 REF _ AVDD 50 kW + 50 kW Figure 2. Current Shunt Amplifier Simplified Block Diagram BUCK CONVERTER Although integrated in the same device, buck converter is designed completely independent of rest of the gate driver circuitry. Since buck will support external MCU or other external power need, the independency of buck operation is very critical for a reliable system; this will give buck minimum impact from gate driver operations. Some examples are: when gate driver shuts down due to any failure, buck will still operate unless the fault is coming from buck itself. The buck keeps operating at much lower PVDD of 3.5V, this will assure the system to have a smooth power up and power down sequence when gate driver is not able to operate due to a low PVDD. The buck has an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 450kHz to 720kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT_CLK pin. The buck converter has a default start up voltage of approximately 2.5V. The EN_BUCK pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN_BUCK pin is floating the device will operate. The operating current is 116µA when not switching and under no load. When the device is disabled, the supply current is 1.3µA. The integrated 200mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering 1.5 amperes of continuous current to a load. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset threshold. The buck can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V reference. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com The buck has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pin to transition high when a pull-up resistor is used. The buck minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%. The SS_TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault, The buck, also, discharges the slow start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current. PROTECTION FEATURES Power Stage Protection The DRV8302 provides over-current and under-voltage protection for the MOSFET power stage. During fault shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state. Over-Current Protection (OCP) and Reporting To protect the power stage from damage due to high currents, a VDS sensing circuitry is implemented in the DRV8302. Based on RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be calculated which, when exceeded, triggers the OC protection feature. This voltage threshold level is programmable through the OC_ADJ terminal (see next section) by applying an external reference voltage with a DAC or resistor divider from DVDD. There are a total of 2 OC_MODE settings selectable with the M_OC pin. 1. Current Limit Mode (M_OC = LOW) When current limit mode is enabled, device operates current limiting instead of OC shut down during OC event. During OC event, the FET that detected OC will turn off until next PWM cycle. The over-current event is reported through OCTW pin. OCTW reporting should hold low during same PWM cycle or for a max 64µs period (internal timer) so external controller has enough time to sample the warning signal. If in the middle of reporting, other FET(s) gets OC, then OCTW reporting will hold low and recount another 64µS unless PWM cycles on both FETs are ended. 2. OC latch shut down mode (M_OC = HIGH) When OC occurs, device will turn off both high side and low side FETs in the same phase if any of the FETs in that phase has OC. OC_ADJ When external MOSFET is turned on, the output current flows through the on resistance, RDS(on) of the MOSFET, which creates a voltage drop VDS. The over current protection event will be enabled when the VDS exceeds a pre-set value. The voltage on OC_ADJ pin will be used to pre-set the OC tripped value. The OC tripped value IOC has to meet following equations: R2 ´ DVDD = V DS (R1 + R2) (2) IOC = VDS RDS(on ) (3) Where Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 13 DRV8302 SLES267 – AUGUST 2011 www.ti.com R1 + R2 ≥ 100 KΩ DVDD = 3.3 V Connect OC_ADJ pin to DVDD to disable the over-current protection feature. DVDD R1 VOC OC_ADJ R2 Figure 3. OC_ADJ Current Programming Pin Connection Under-Voltage Protection (UVP) To protect the power output stage during startup, shutdown and other possible under-voltage conditions, the DRV8302 provides power stage under-voltage protection by driving its outputs low whenever PVDD is below 6V (PVDD_UV) or GVDD is below 8V (GVDD_UV). When UVP is triggered, the DRV8302 outputs are driven low and the external MOSFETs will go to a high impedance state. Over-Voltage Protection (GVDD_OV) Device will shut down both gate driver and charge pump if GVDD voltage exceeds 16V to prevent potential issue related to GVDD or charge pump (e.g. short of external GVDD cap or charge pump). The fault is a latched fault and can only be reset through a transition on EN_GATE pin. Over-Temperature Protection A two-level over-temperature detection circuit is implemented: • Level 1: over temperature warning (OTW) OTW is reported through OCTW pin. • Level 2: over temperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE) Fault will be reported to FAULT pin. This is a latched shut down, so gate driver will not be recovered automatically even if OT condition is not present anymore. An EN_GATE reset through pin is required to recover gate driver to normal operation after temperature goes below a preset value, tOTSD_CLR. Fault and Protection Handling The FAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature, over-voltage, or under-voltage. Note that FAULT is an open-drain signal. FAULT will go high when gate driver is ready for PWM signal (internal EN_GATE goes high) during start up. The OCTW pin indicates an over temperature or over current event that is not necessarily related to shut down. Following is the summary of all protection features and their reporting structure: 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com Table 1. Fault and Warning Reporting and Handling EVENT ACTION LATCH REPORTING ON FAULT PIN REPORTING ON OCTW PIN PVDD undervoltage External FETs HiZ; Weak pull down of all gate driver output N Y N DVDD undervoltage External FETs HiZ; Weak pull down of all gate driver output; When recovering, reset all status registers N Y N GVDD undervoltage External FETs HiZ; Weak pull down of all gate driver output N Y N GVDD overvoltage External FETs HiZ; Weak pull down of all gate driver output Shut down the charge pump Won’t recover and reset through SPI reset command or quick EN_GATE toggling Y Y N OTW None N N Y OTSD_GATE Gate driver latched shut down. Weak pull down of all gate driver output to force external FETs HiZ Shut down the charge pump Y Y Y OTSD_BUCK OTSD of Buck Y N N Buck output undervoltage UVLO_BUCK: auto-restart N Y, in PWRGD pin N Buck overload Buck current limiting (HiZ high side until current reaches zero and then auto-recovering) N N N External FET overload – current limit mode External FETs current Limiting (only OC detected FET) N N Y External FET overload – Latch mode Weak pull down of gate driver output and PWM logic “0” of LS and HS in the same phase. External FETs HiZ Y Y Y External FET overload – reporting only mode Reporting only N N Y Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 15 DRV8302 SLES267 – AUGUST 2011 www.ti.com PIN CONTROL FUNCTIONS EN_GATE EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low power consumption mode to save energy. Device will put the MOSFET output stage to high impedance mode as long as PVDD is still present. When EN_GATE pin goes to high, it will go through a power up sequence, and enable gate driver, current amplifiers, charge pump, internal regulator, etc and reset all latched faults related to gate driver block. All latched faults can be reset when EN_GATE is toggled after an error event unless the fault is still present. When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put external FETs in high impedance mode. It will then wait for 10us before completely shutting down the rest of the blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10µS). This will prevent device to shut down other function blocks such as charge pump and internal regulators and bring a quicker and simple fault recovery. One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset won’t work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 10 µs is required to reset GVDD_OV fault. It is highly recommended to inspect the system and board when GVDD_OV occurs. EN_BUCK Buck enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. DTC Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control the dead time. Dead time control range is from 50ns to 500ns. Short DTC pin to ground will provide minimum dead time (50ns). Resistor range is 0 to 150kΩ. Dead time is linearly set over this resistor range. Current shoot through prevention protection will be enabled in the device all time independent of dead time setting and input mode setting. DC_CAL When DC_CAL is enabled, device will short inputs of shunt amplifier and disconnect from the load, so external microcontroller can do a DC offset calibration. STARTUP AND SHUTDOWN SEQUENCE CONTROL During power-up all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present after a 10-ms wait time, the DRV8302 is ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as long as PVDD is within functional region. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 DRV8302 SLES267 – AUGUST 2011 www.ti.com APPLICATION SCHEMATIC EXAMPLE Example: Buck: PVDD= 3.5V – 40V, Iout_max = 1.5A, Vo = 3.3V, Fs = 570 kHz VCC 120 pF PVDD 0 .015 mF 6.8 nF 205 kW 3 .3 16 .2 KW SS_TR RT _CLK 31.6 kW EN_BUCK COMP 10 kW 10kW 10kW VCC 10 nF VSENSE PVDD 2 PWRGD PVDD 2 PVDD 0.1 mF 0.1 mF 10 kW OCTW BST _BK FAULT PH DTC PH 2.2 mF M_OC BST _A GAIN GH_A OC_ADJ SH_A DC_CAL GL_A GVDD 22 nF CP1 Motor Controller CP2 PWM EN_GATE ADC 1 mF 4.7 mF 22 mH VCC ( 3.3V ) 47 mF PVDD BIAS POWER PAD - GND GPIO M_PWM 470 mF 0.1 mF 1 MW SL _A MOTOR 0.1 mF BST _B GH_B SH_B INH_A GL _B INL_A SL_B INH_B BST _ C INL_B GH_ C INH_C SH _ C INL_C GL_ C DVDD SL_ C REF SN1 SO1 SP1 SO2 SN2 AVDD SP2 AGND PVDD 1 0.1 mF 1 nF 10 mW 1 nF Power Pad RS1 RS2 10mW GND 1 mF PVDD 0 .1 mF 4.7 mF AGND GND GND PGND Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): DRV8302 17 PACKAGE OPTION ADDENDUM www.ti.com 19-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8302DCA ACTIVE HTSSOP DCA 56 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8302DCAR ACTIVE HTSSOP DCA 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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