HYB/E 25L128160AC 128-MBit Mobile-RAM 128-MBit Synchronous Low-Power DRAM in Chipsize Packages Datasheet (Rev. 2003-02) • Automatic and Controlled Precharge Command High Performance: -7.5 -8 Units fCK,MAX 133 125 MHz tCK3,MIN 7.5 8 ns tAC3,MAX 5.4 6 ns tCK2,MIN 9.5 9.5 ns tAC2,MAX 6 6 ns • Programmable Burst Length: 1, 2, 4, 8 and full page • Programmable Power Reduction Feature by partial array activation during Self-Refresh • Data Mask for byte control • Auto Refresh (CBR) • 4096 Refresh Cycles / 64ms • Self Refresh with programmble refresh period • 8Mbit x 16 organisation • VDD = 2.5V, VDDQ = 1.8V / 2.5V • Power Down and Clock Suspend Mode • Fully Synchronous to Positive Clock Edge • Random Column Address every CLK (1-N Rule) • Four Banks controlled by BA0 & BA1 • 54-FBGA , with 9 x 6 ball array with 3 depopulated rows, 9 x 8 mm • Programmable CAS Latency: 1, 2, 3 • Programmable Wrap Sequence: Sequential or Interleave • Operating Temperature Range Commerical ( 00 to 700C) Extended ( -25oC to +85oC) • Deep Power Down Mode The HYB/E 25L128160AC Mobile-RAMs are a new generation of low power, four bank Synchronous DRAM’s organized as 4 banks × 2Mbit x16 with additional features for mobile applications. These synchronous Mobile-RAMs achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using the Infineon advanced process technology. The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory array can be selected for Self-Refresh and the refresh period during SelfRefresh is programmable in 4 steps which drastically reduces the self refresh current, depending on the case temperature of the components in the system application. In addition a “Deep Power Down Mode” is available. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. The device operates from a 2.5V power supply for the core and 1.8V for the bus interface. The Mobile-RAM is housed in a FBGA “chip-size” package. The Mobile-RAM is available in the commercial (00 to 700C) and Extended ( -25oC to +85oC) temperature range. INFINEON Technologies 1 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Ordering Information Type Function Code Package Description Commercial temperature range: HYB 25L128160AC-7.5 PC133-333-522 BGA-BOC 133 MHz 4B × 2M x16 LP-SDRAM HYB 25L128160AC-8 PC100-222-620 BGA-BOC 100 MHz 4B × 2M x16 LP-SDRAM Extended temperature range: HYE 25L128160AC-7.5 PC133-333-522 BGA-BOC 133 MHz 4B × 2M x16 LP-SDRAM HYE 25L128160AC-8 PC100-222-620 BGA-BOC 100 MHz 4B × 2M x16 LP-SDRAM Pin Definitions and Functions CLK Clock Input DQ Data Input/Output CKE Clock Enable LDQM, UDQM Data Mask CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable A0 - A11, A0 - A8 Row Addresses Column Addresses BA0, BA1 Bank Select INFINEON Technologies 9DD 9SS 9DDQ 9SSQ N.C. 2 Power (+ 2.5V) Ground Power for DQ’s (+1.8 V) Ground for DQ’s Not connected 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Pin Configuration for x16 devices: 1 2 3 7 8 9 VSS DQ15 VSSQ A VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 NC VSS E VDD LDQM DQ7 UDQM CLK CKE F CAS RAS WE NC A11 A9 G BA0 BA1 CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD < Top-view > INFINEON Technologies 3 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Functional Block Diagrams A0 - A11, BA0, BA1 Column Address Counter Column Address Buffer Row Address Buffer Row Decoder Row Decoder Bank 0 4096 x 512 x 16 Bit Input Buffer Memory Array Bank 1 4096 x 512 x 16 Bit Output Buffer Memory Array Bank 2 4096 x 512 x 16 Bit Row Decoder Column Decoder Sense amplifier & I(O) Bus Memory Array Refresh Counter Row Decoder Column Decoder Sense amplifier & I(O) Bus Column Decoder Sense amplifier & I(O) Bus Row Addresses A0 - A8, AP, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Column Addresses Memory Array Bank 3 4096 x 512 x 16 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQMU DQML DQ0 - DQ15 SPB04124 Block Diagram: 8Mb x16 SDRAM (12 / 9 / 2 addressing) INFINEON Technologies 4 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A11 Input Level – During a Bank Activate command cycle, A0 - A11 define the row address (RA0 - RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A8 define the column address (CA0 - CA8) when sampled at the rising clock edge. In addition to the column address, A10 (= AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input DQx Level – Bank Select Inputs. Selects which bank is to be active. Input Level Output – Data Input/Output pins operate in the same manner as on conventional DRAMs. INFINEON Technologies 5 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Pin Type Signal Polarity Function LDQM UDQM, Input Pulse VDD VSS VDDQ VSSQ Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQMx has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. LDQM and UDQM controls the lower and upper bytes in x16 SDRAM. Supply – – Power and ground for the input buffers and the core logic. Supply – – Isolated power supply and ground for the output buffers to provide improved noise immunity. INFINEON Technologies 6 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQMx at the positive edge of the clock. The following list shows the truth table for the operation commands. 2SHUDWLRQ Bank Active Device State Idle3 CKE n-1 CKE n DQM BA0 BA1 AP= A10 Addr CS RAS CAS WE H X X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active3 H X X V L V L H L L Write with Autoprecharge Active3 H X X V H V L H L L Read Active3 H X X V L V L H L H Read with Autoprecharge Active3 H X X V H V L H L H Mode Register Set Idle H X X V V V L L L L No Operation Any H X X X X X L H H H Burst Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L X X X X L L L H Self Refresh Exit Idle (Self Refr.) H X X X L H H X H X X X L H H H Power Down Entry (Precharge or active standby) L H X X X X H L X X X X Idle Active4 Power Down Exit Data Write/Output Enable Any (Power Down) L H X X X X H X X X L H H L Active H X L X X X X X X X Data Write/Output Disable Active H X H X X X X X X X Deep Power Down Entry Idle H L X X X X L H H L Deep Power Down Exit Deep5 Power Down L H X X X X X X X X Notes: 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level. 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can not entry in the burst cycle. Address Input for Mode Set (Mode Register Operation) 5. After Deep Power Down mode exit a full new initialisation of the memory device is mandatory. INFINEON Technologies 7 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM BA1 BA0 A11 A10 A9 0*) 0*) A8 A7 Operation Mode A6 A5 A4 A3 A2 CAS Latency BT Burst Length Operation Mode A1 A0 Address Bus (Ax) Mode Register (Mx) Burst Type BA1 BA0 M11 M10 M9 Mode M3 Type 0 0 0 0 0 M8 M7 0 0 Burst Read/ Burst Write 0 Sequential 1 Interleave 0 0 0 0 1 0 0 Burst Read/ Single Write CAS Latency Burst Length M6 M5 M4 Latency 0 0 0 Reserved 0 0 1 1 0 0 0 1 0 2 0 0 1 1 3 1 0 0 Reserved 1 0 1 1 1 0 1 1 1 M2 Reserved M1 Length M0 Sequential Interleave 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 1 0 1 1 1 0 1 1 1 Reserved Reserved full page *) BA0 and BA1 must be 0, 0 to select the Mode Register (Vs. the Extended Mode Register) 0RGH5HJLVWHU7DEOH INFINEON Technologies 8 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 3RZHU2QDQG,QLWLDOL]DWLRQ The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. 9DD must be applied before or at the same time as 9DDQ to the specified voltage when the input signals are held in the “NOP” or “DESELECT” state. The power on voltage must not exceed 9DD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. 3URJUDPPLQJWKH0RGH5HJLVWHU The Mode Register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. BA0 and BA1 have to be set to “0” to enter the Mode Register. ([WHQGHG0RGH5HJLVWHU The Extended Mode Register controls functions beyond those controlled by the Mode Register. These additional functions are unique to Mobile RAMs and includes a Refresh Period field (TCR) for temperature compensated self-refresh and a Partial-Array Self Refresh field (PASR). The PASR field is used to specify whether only one quarter (bank 0), one half (banks 0 + 1) or all banks of the SDRAM array are enabled. Disabled banks will not be refreshed in Self-Refresh mode and written data will get lost. When only bank 0 is selected, it is possible to partially select only half or one quarter of bank 0. The TCR field has four entries to set Refresh Period during self-refresh depending on the case temperature of the Mobile RAM devices. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 1) and retains the stored information until it is programmed again or the device loses power. The Extended mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either these requirements result in unspecified operation. Unused bit A5 to A11 have to be programmed to “0”. INFINEON Technologies 9 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM ([WHQGHG0RGH5HJLVWHU7DEOH BA1 BA0 A11 A10 1*) A9 A8 A7 A6 A5 A4 all have to be set to "0" 0*) A3 TCR A2 A1 A0 Address Bus (Ax) Mode Register (Mx) PASR Temperature-Compensated Self-Refresh: max. case temp. 70 0C M4 M3 0 0 0 1 1 0 15 C 1 1 85 C Partial-Array Self Refresh: M2 M1 M0 45 0C 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 banks to be self-refreshed all banks 1/2 array (BA1=0) 1/4 array (BA1=0, BA0=0) Reserved Reserved 1/8 array (BA1=BA0=0, RA11=0) 1/16 array (BA1=BA0=0, RA11=RA10=0) Reserved *)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register) 5HDGDQG:ULWH2SHUDWLRQ When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, WRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation does not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using another command. INFINEON Technologies 10 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum WRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. When the partial array activation is set, data will get lost when self-refresh is used in all non activated banks. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Burst Addressing (decimal) Interleave Burst Addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4 x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 Full Page nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 Cn, Cn+1, Cn+2 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 not supported 5HIUHVK0RGH Mobile-RAM has two refresh modes, Auto Refresh and Self Refresh. $XWR5HIUHVK Auto Refresh is similar to the CAS -before-RAS refresh of earlier DRAMs. All banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses. No bank information is required for both refresh modes. INFINEON Technologies 11 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock edge. The mode restores word line after the refresh and no external precharge command is necessary. A minimum WRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. In Auto-Refresh mode all banks are refreshed, independendly of the fact that the partial array selfrefresh has been set or not. 6HOI5HIUHVK The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one WRC delay is required prior to any access command. Low Power SDRAMs have the possibility to program the refresh period of the on-chip timer with the use of an appropriate extended MRS command, depending on the maximum operation case temperature in the application. In partial array self-refresh mode only the selected banks will be refreshed. Data written to the non activated banks will get lost after a period defined by tref. '40)XQFWLRQ DQMx has two functions for data I/O read and write operations. During reads, when it turns to “high” at a clock edge, data outputs are disabled and become high impedance after two clock periods (DQM Data Disable Latency WDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency WDQW = zero clocks). 6XVSHQG0RGH During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). 3RZHU'RZQ In order to reduce standby power consumption, a power down mode is available. All banks must be precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (WREF) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for power down mode entry and exit. 'HHS3RZHU'RZQ0RGH The Deep Power Down Mode is an unique function on Mobile RAMs with very low standby currents. All internal voltage generators inside the Mobile RAMs are stopped and all memory data is lost in this mode. To enter the Deep Power Down mode all banks must be precharged. INFINEON Technologies 12 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM $XWR3UHFKDUJH Two methods are available to precharge Mobile-RAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The Mobile-RAM automatically enters the precharge operation after WWR (Write recovery time) following the last data in. 3UHFKDUJH&RPPDQG There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock edge, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay WWR from the last data out to apply the precharge command. %DQN6HOHFWLRQE\$GGUHVV%LWV A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 x x all Banks %XUVW7HUPLQDWLRQ Once a burst read or write operation has been initiated, there are several methods used to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, using a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. INFINEON Technologies 13 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM (OHFWULFDO&KDUDFWHULVWLFV $EVROXWH0D[LPXP5DWLQJV Operating Case Temperature Range (commercial).........................................................0 to + 70°C Operating Case Temperature Range (extended) ........................................................ -25 to + 85°C Storage Temperature Range ................................................................................... – 55 to + 150°C Input/Output Voltage ......................................................................................... – 0.3 to 9DD + 0.3 V Power Supply Voltage 9DD ...................................................................................... – 0.3 to + 3.6 V Power Dissipation .................................................................................................................... 0.7 W Data out Current (short circuit) ............................................................................................... 50 mA 1RWH 6WUHVVHV DERYH WKRVH OLVWHG XQGHU ³$EVROXWH 0D[LPXP 5DWLQJV´ PD\ FDXVH SHUPDQHQW GDPDJH RI WKH GHYLFH ([SRVXUH WR DEVROXWH PD[LPXP UDWLQJ FRQGLWLRQV IRU H[WHQGHG SHULRGVPD\DIIHFWGHYLFHUHOLDELOLW\ Recommended Operation and DC Characteristics TCASE = 0 to 70°C (commercial) / -25 to 85oC (Extended); VSS = 0 V; VDD = 2.5 V nominal, VDDQ = 1.8V / 2.5V nominal Parameter Symbol Limit Values Unit Notes min. max. DRAM Core Supply Voltage VDD 2.3 2.9 V I/O Supply Voltage VDDQ 1.65 2.9 V Input High Voltage (CMD, Addr.) VIH 0.8 x VDDQ VDDQ + 0.3 V 1, 2 Input Low Voltage (CMD, Addr.) VIL – 0.3 + 0.3 V 1, 2 Data Input High (Logic 1) Voltage VIH 0.8 x VDDQ VDDQ + 0.3 V Data Input Low (Logic 0) Voltage VIL – 0.3 + 0.3 V Data Output High (Logic 1) Voltage (IOH=-0.1mA) VOH VDDQ - 0.2 – V Date Output Low (Logic 0) Voltage (IOL=+0.1mA) VOL – 0.2 V Input Leakage Current, any input (0 V < VIN < VDDQ, all other inputs = 0 V) II(L) –5 5 µA Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) IO(L) –5 5 µA 1RWHV 1. All voltages are referenced to 9SS. 2. 9IH may overshoot to 9DD + 0.8V for pulse width of < 4 ns with 2.5V.9IL may undershoot to – 0.8 V for pulse width < 4.0 ns with 2.5V. Pulse width measured at 50% points with amplitude measured peak to DC reference. INFINEON Technologies 14 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Capacitance : TCASE = 0 to 70 °C (commercial) / -25 to 85oC (Extended); VDD = 2.5 V nominal,VDDQ = 1.8 V nominal, f = 1 MHz Parameter Symbol Values min. max. Unit Input Capacitance (CLK) CI1 - 3.5 pF Input Capacitance (A0 - A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) CI2 - 3.8 pF Input/Output Capacitance (DQ) CIO - 6.0 pF Operating Currents TCASE = 0 to 70 °C (commercial) / -25 to 85oC (Extended); VDD = 2.5 V nominal, VDDQ = 1.8 V nominal (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Operating current Symb. -7.5 -8 Unit 70 65 mA 3,4 ICC1 – tCK = tCK(MIN.) Note one bank access Precharge standby current in Power Down Mode CS = VIH (MIN.), CKE ≤ VIL(MAX.) tCK = min ICC2P 0.4 0.4 mA 3 Precharge standby current in Non Power Down Mode CS = VIH (MIN.), CKE ≥ VIH(MIN.) tCK = min ICC2N 20 15 mA 3 No operating current tCK = min., CS = VIH (MIN.), active state (max. 4 banks) CKE ≥ VIH(MIN.) ICC3N 35 31 mA 3 3 3 mA 3 70 60 mA 3,4 160 150 CKE ≤ VIL(MAX.) ICC3P Burst Operating Current tCK = min Read command cycling – Auto Refresh Current tCK = min, trc = trcmin. Auto Refresh command cycling – ICC4 ICC5 ICC7 Deep Power Down Mode Current INFINEON Technologies 15 3 mA µA 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 3URJUDPPDEOH6HOI5HIUHVK&XUUHQWV Parameter & Test Condition Extended Mode Register M[4:3] Tcase [oC] Symb. max. Unit Self Refresh Current Self Refresh Mode CKE = 0.2 V, tck=infinity, full array activations, all banks 85oC max. ICC6 520 µA 70oC max. 350 µA 45oC max. 250 µA 210 µA 380 µA 250 µA 45 C max. 180 µA 15oC max. 160 µA o 15 C max. Self Refresh Current Self Refresh Mode CKE = 0.2 V, tck=infinity, half array activations, Bank 0 +1 Self Refresh Current Self Refresh Mode CKE = 0.2 V, tck=infinity, quarter array activation, Bank 0 85oC max. ICC6 70oC max. o 270 µA 70oC max. 180 µA 45oC max. 130 µA 120 µA o ICC6 85 C max. o 15 C max. Note 1RWHV 3. These parameters depend on the frequency. These values are measured at 133 MHz for -7 & -7.5 and at 100 MHz for -8 parts. Input signals are changed once during WCK. If the devices are operating at a frequency less than the maximum operation frequency, these current values are multiplied by 1/ freq, meaning operation at half the maximum frequency reduces these current value by a factor of 2. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 is assumed and the 9DDQ current is excluded. INFINEON Technologies 16 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM AC Characteristics 1, 2 TCASE = 0 to 70 °C (commercial) / -25 to 85oC (Extended); VSS = 0 V; VDD = 2.5 V nominal, VDDQ = 1.8 V nominal, tT = 1 ns Parameter Symb. Unit -7.5 Note -8 min. max. min. max. Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 CAS Latency = 1 7.5 9.5 20 – – – 8 9.5 20 – – – ns ns ns Clock frequency CAS Latency = 3 tCK CAS Latency = 2 CAS Latency = 1 – – – 133 105 50 – – – 125 105 50 MHz MHz Mhz Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 CAS Latency = 1 – – – 5.4 6 19 – – – 6 6 19 ns ns ns – 3 – ns Clock and Clock Enable 2, 3, 6 Clock High Pulse Width tCH 2.5 Clock Low Pulse Width tCL 2.5 – 3 – ns Transition Time tT 0.3 1.2 0.5 1.5 ns Input Setup Time tIS 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 1 – ns 4 CKE Setup Time tCKS 1.5 – 2 – ns 4 CKE Hold Time tCKH 0.8 – 1 – ns 4 Mode Register Set-up Time tRSC 2 – 2 – CLK Power Down Mode Entry Time tSB 0 7.5 0 8 ns Row to Column Delay Time tRCD 19 – 19 – ns 5 Row Precharge Time tRP 19 – 19 – ns 5 Row Active Time tRAS 45 100k 48 100k ns 5 Row Cycle Time tRC 67 – 70 – ns 5 Setup and Hold Times Common Parameters INFINEON Technologies 17 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM AC Characteristics (cont’d)1, 2 TCASE = 0 to 70 °C (commercial) / -25 to 85oC (Extended); VSS = 0 V; VDD = 2.5 V nominal, VDDQ = 1.8 V nominal, tT = 1 ns Parameter Symb. -7.5 Activate(a) to Activate(b) Command Period tRRD CAS(a) to CAS(b) Command tCCD Period Unit Note -8 min. max. min. max. 15 – 16 – ns 5 1 – 1 – CLK – – Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 ms Self Refresh Exit Time tSREX 1 – 1 – CLK Data Out Hold Time tOH 3 – 3 – ns 2, 5, 6 Data Out to Low Impedance Time tLZ 1 – 0 – ns – Data Out to High Impedance Time tHZ 3 7 3 8 ns – DQM Data Out Disable Latency tDQZ – 2 – 2 CLK – Write Recovery Time tWR 14 – 14 – ns DQM Write Mask Latency tDQW 0 – 0 – CLK Read Cycle Write Cycle INFINEON Technologies 18 7 – 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 1RWHV 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests are referenced to the 0.9 V crossover point for VDDQ = 1.8 V components. The transition time is measured between 9IH and 9IL. All AC measurements assume WT = 1 ns with the AC output load circuit (details will be defined later). Specified WAC and WOH parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1V / ns edge rate. I/O 30 pF Measurement conditions for tAC and tOH 3. If clock rising time is longer than 1 ns, a time (WT/2 - 0.5) ns has to be added to this parameter. 4. If WT is longer than 1 ns, a time (WT - 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: WKH QXPEHU RI FORFN F\FOH VSHFLILHG YDOXH RI WLPLQJ SHULRG FRXQWHG LQ IUDFWLRQV DV D ZKROH QXPEHU 6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 7. The write recovery time of twr = 14 ns cycles allows the use of one clock cycle for the write recovery time when the memory operation frequency is equal or less than 72MHz. For all memory operation frequencies higher than 72MHz two clock cycles for twr are mandatory. INFINEON recommends to use two clock cylces for the write recovery time in all applications. INFINEON Technologies 19 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM Package Outlines FBGA-BOC package 54 BGA package with 3 depop. rows INFINEON Technologies 20 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 7LPLQJ'LDJUDPV 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. AC- Parameters 8.1 AC Parameters for a Write Timing 8.2 AC Parameters for a Read Timing 9. Mode Register Set 10. Power on Sequence and Auto Refresh (CBR) 11. Clock Suspension (using CKE) 11. 1 Clock Suspension During Burst Read CAS Latency = 2 11. 2 Clock Suspension During Burst Read CAS Latency = 3 11. 3 Clock Suspension During Burst Write CAS Latency = 2 11. 4 Clock Suspension During Burst Write CAS Latency = 3 12. Power Down Mode and Clock Suspend 13. Self Refresh ( Entry and Exit ) 14. Auto Refresh ( CBR ) 15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst 20. Deep Power Down Mode 20.1 Deep Power Down Mode Entry 20.2 Deep Power Down Mode Exit INFINEON Technologies 21 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM %DQN$FWLYDWH&RPPDQG&\FOH (CAS latency = 3) T0 T1 T T T T T CLK Address Bank B Row Addr. Bank B Col. Addr. t RCD Command Bank B Activate NOP Bank B Row Addr. Bank A Row Addr. t RRD NOP Write B with Auto Precharge Bank A Activate NOP Bank B Activate t RC "H" or "L" SPT03784 %XUVW5HDG2SHUDWLRQ (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A NOP NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s CAS latency = 3 t CK3 , DQ’s INFINEON Technologies DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 SPT03712 22 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 5HDG,QWHUUXSWHGE\D5HDG (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A Read B NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 SPT03713 5HDGWR:ULWH,QWHUYDO 5HDGWR:ULWH,QWHUYDO (Burst Length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles Write latency t DQW of DQMx DQMx t DQZ Command NOP Read A DQ’s NOP NOP NOP DOUT A0 NOP Write B NOP NOP DIN B0 DIN B1 DIN B2 Must be Hi-Z before the Write Command "H" or "L" INFINEON Technologies SPT03787 23 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 0LQLPXP5HDGWR:ULWH,QWHUYDO (Burst Length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 Write A NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 CLK t DQW DQM t DQZ 1 Clk Interval Command NOP NOP Bank A Activate NOP Read A Must be Hi-Z before the Write Command CAS latency = 2 t CK2 , DQ’s "H" or "L" SPT03939 1RQ0LQLPXP5HDGWR:ULWH,QWHUYDO (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP CLK t DQW DQM t DQZ Command NOP Read A NOP NOP Read A NOP Write B Must be Hi-Z before the Write Command CAS latency = 2 t CK2 , DQ’s DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2 CAS latency = 3 t CK3 , DQ’s DOUT A0 DIN B0 DIN B1 DIN B2 "H" or "L" INFINEON Technologies SPT03940 24 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM %XUVW:ULWH2SHUDWLRQ (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care CLK Command DQ’s The first data element and the Write are registered on the same clock edge. INFINEON Technologies Extra data is ignored after termination of a Burst. 25 SPT03790 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM :ULWHDQG5HDG,QWHUUXSW :ULWH,QWHUUXSWHGE\D:ULWH (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A Write B NOP NOP NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 CLK Command 1 Clk Interval DQ’s DIN A0 DIN B0 SPT03791 :ULWH,QWHUUXSWHGE\D5HDG (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A Read B NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s DIN A0 don’t care CAS latency = 3 t CK3 , DQ’s DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ’s at least one clock cycle before the Read data appears on the outputs to avoid data contention. Input data for the Write is ignored. SPT03719 INFINEON Technologies 26 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM %XUVW:ULWHDQG5HDGZLWK$XWR3UHFKDUJH %XUVW:ULWHZLWK$ XWR3UHFKDUJH %XUVW/HQJWK &$6ODWHQF\ T0 T1 Bank A Active NOP T2 T3 T4 T5 T6 T7 Write A NOP NOP NOP NOP T8 CLK CAS Latency = 2: Command Auto Precharge t WR DIN A0 DQ’s NOP NOP NOP t RP * DIN A1 Activate CAS Latency = 3: Command Bank A Active NOP NOP Write A NOP Auto Precharge NOP NOP t WR DIN A0 DQ’s * DIN A1 * Activate t RP Begin Auto Precharge Bank can be reactivated after trp %XUVW5HDGZLWK$XWR3UHFKDUJH (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A with AP NOP NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 DQ’s CAS latency = 3 DQ’s * DOUT A0 DOUT A1 DOUT A2 t RP DOUT A3 t RP * DOUT A0 DOUT A1 DOUT A2 DOUT A3 * Begin Auto Precharge Bank can be reactivated after trp INFINEON Technologies 27 SPT03721_2 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM $&3DUDPHWHUV $&3DUDPHWHUVIRUD:ULWH7LPLQJ Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CH t CK2 t CL CKE t CKS t CH t CKH Begin Auto Precharge Bank B Begin Auto Precharge Bank A t CS CS RAS CAS WE BS t AH AP RBx RAx RAy RAz RBy RAz RBy t AS Addr. RAx CAx RAy CBx RBx RAy DQM t WR t RCD t DS t RP t DH t RC Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 DQ Activate Command Bank A Activate Command Bank B Write with Auto Precharge Command Bank A INFINEON Technologies t RP t RRD Ay0 Ay1 Ay2 Ay3 Activate Write Command Command Bank A Bank A Write with Auto Precharge Command Bank B t WR Precharge Activate Activate Command Command Command Bank A Bank A Bank B SPT03910_2 28 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM $&3DUDPHWHUVIRUD5HDG7LPLQJ Burst Length = 2, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK t CH t CK2 t CL CKE t CKH t CS Begin Auto Precharge Bank B t CKS t CH CS RAS CAS WE BS t AH RAx AP RBx RAy t AS Addr. RAx CAx RBx RBx RAy t RRD t RAS t RC DQM tAC2 t LZ t OH t RCD DQ t HZ Hi-Z t HZ Ax0 Activate Command Bank A INFINEON Technologies Read Command Bank A t RP t AC2 Activate Command Bank B 29 Ax1 Read with Auto Precharge Command Bank B Bx0 Precharge Command Bank A Bx1 Activate Command Bank A SPT03911_2 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 0RGH5HJLVWHU6HW CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t RSC CS RAS CAS WE BS AP Address Key Addr. Precharge Command All Banks Any Command Mode Register Set Command INFINEON Technologies SPT03912_2 30 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 3RZHURQ6HTXHQFHDQG$XWR5HIUHVK&%5 T2 T3 T4 CKE T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ ~ ~ ~ ~ T1 ~ ~ T0 CLK 2 Clock min. Minimum of 8 Refresh Cycles are required ~ ~ ~ ~ High Level is required ~ ~ ~ ~ ~ ~ AP ~ ~ ~ ~ BS ~ ~ ~ ~ ~ ~ WE ~ ~ ~ ~ ~ ~ ~ ~ CAS ~ ~ ~ ~ ~ ~ ~ ~ RAS ~ ~ ~ ~ ~ ~ ~ ~ CS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Address Key Addr. DQM t RC ~ ~ Hi-Z ~ ~ t RP DQ Precharge Command All Banks Inputs must be stable for 200 µs 8th Auto Refresh Command 1st Auto Refresh Command INFINEON Technologies Mode Register Set Command Any Command SPT03913 31 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &ORFN6XVSHQVLRQ8VLQJ&.( &ORFN6XVSHQVLRQ'XULQJ%XUVW5HDG&$6/DWHQF\ Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM t CSL t CSL DQ Hi-Z Ax0 Activate Read Command Command Bank A Bank A INFINEON Technologies t HZ t CSL Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles 32 SPT03914 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &ORFN6XVSHQVLRQ'XULQJ%XUVW5HDG&$6/DWHQF\ Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx t CSL t CSL DQM t CSL t HZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A INFINEON Technologies Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles 33 SPT03915 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &ORFN6XVSHQVLRQ'XULQJ%XUVW:ULWH&$6/DWHQF\ Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 Clock Suspend 1 Cycle DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A INFINEON Technologies SPT03916 34 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &ORFN6XVSHQVLRQ'XULQJ%XUVW:ULWH&$6/DWHQF\ Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BA A8/AP RAx Addr. RAx CAx DQMx DQ Hi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend 1 Cycle DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A INFINEON Technologies SPT03917 35 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 3RZHU'RZQ0RGHDQG&ORFN6XVSHQG Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CKS t CK2 t CKS CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM t HZ DQ Hi-Z Ax0 Ax1 Activate Command Bank A Active Standby Clock Suspend Mode Entry Read Command Bank A Ax2 Clock Mask End Clock Mask Start Clock Suspend Mode Exit Ax3 Precharge Command Bank A Precharge Standby Power Down Mode Entry Any Command Power Down Mode Exit SPT03918 INFINEON Technologies 36 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 6HOI5HIUHVK(QWU\DQG([LW T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ CLK ~ ~ CKE ~ ~ t CKS t CKS ~ ~ ~ ~ CS ~ ~ ~ ~ RAS ~ ~ CAS ~ ~ ~ ~ ~ ~ WE ~ ~ BS ~ ~ ~ ~ AP ~ ~ ~ ~ ~ ~ Addr. t SREX t RC*) DQM ~ ~ Hi-Z ~ ~ DQ All Banks must be idle Self Refresh Entry Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit Any Command *) minimum RAS cycle time depends on CAS Latency and trc INFINEON Technologies 37 SPT03919-2 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM $XWR5HIUHVK&%5 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS RAx AP RAx Addr. t RC t RP CAx t RC (Minimum Interval) DQM Hi-Z Ax0 Ax1 Ax2 Ax3 DQ Precharge Auto Refresh Command Command All Banks Auto Refresh Command Activate Read Command Command Bank A Bank A SPT03920_2 INFINEON Technologies 38 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 5DQGRP&ROXPQ5HDG3DJHZLWKLQVDPH%DQN &$ 6/DWHQF\ Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A INFINEON Technologies Read Command Bank A Read Command Bank A Precharge Command Bank A 39 Activate Command Bank A Az0 Az1 Az2 Az3 Read Command Bank A SPT03921 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &$ 6/DWHQF\ Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A INFINEON Technologies Read Command Bank A Read Command Bank A 40 Precharge Command Bank A Activate Command Bank A Read Command Bank A SPT03922 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 5DQGRP&ROXPQZULWH3DJHZLWKLQVDPH%DQN &$ 6/DWHQF\ Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RBw Addr. RBw RBz CBx CBy DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 CBw RBz CBz DQM Hi Z DQ Activate Write Command Command Bank B Bank B DBy1 DBy2 Write Write Command Command Bank B Bank B DBy3 DBz0 DBz1 DBz2 DBz3 Precharge Activate Read Command Command Command Bank B Bank B Bank B SPT03923_2 INFINEON Technologies 41 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &$6/DWHQF\ Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RBz Addr. RBz RBz CBz CBx CBy RBz CBz DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank B Write Command Bank B INFINEON Technologies Write Command Bank B Write Command Bank B 42 DBz0 DBz1 Precharge Command Bank B Activate Command Bank B Write Command Bank B SPT03924 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 5DQGRP5RZ5HDG,QWHUOHDYLQJ%DQNVZLWK3UHFKDUJH &$ 6/DWHQF\ Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RBx Addr. RBx RAx CBx RAx RBy CAx RBy CBy t RP t RCD DQM t AC2 Hi-Z DQ Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Activate Read Command Command Bank B Bank B Activate Command Bank A Precharge Activate Command Command Bank B Bank B Read Command Bank A INFINEON Technologies 43 By0 By1 Read Command Bank B SPT03925_2 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &$ 6/DWHQF\ Burst Length = 8, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS AP RBx Addr. RBx RAx CBx RBy RAx CAx RBy t AC3 t RCD CBy t RP DQM DQ Hi-Z Activate Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Command Bank B Precharge Command Bank A SPT03926 INFINEON Technologies 44 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 5DQGRP5RZ:ULWH,QWHUOHDYLQJ%DQNVZLWK3UHFKDUJH &$ 6/DWHQF\ Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RBx CAx RAy RBx CBx t RCD RAy t WR CAy t WR t RP DQM Hi-Z DQ DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 Write Activate Command Command Bank B Bank B Precharge Command Bank A INFINEON Technologies 45 DBx3 DBx4 Activate Command Bank A DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Precharge Command Bank B Write Command Bank A SPT03927_2 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &$ 6/DWHQF\ Burst Length = 8, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RAy RBx CAx RBx CBx t RCD RAy t WR t RP CAy t WR DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B SPT03928 INFINEON Technologies 46 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 3UHFKDUJHWHUPLQDWLRQRID%XUVW &$ 6/DWHQF\ Burst Length = 8 or Full Page, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RAz RAy CAx RAy CAy t RP RAz CAz t RP t RP Ay0 Ay1 Ay2 Az0 Az1 Az2 DQM DQ Hi Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked. Precharge Command Bank A Read Command Bank A Precharge Command Bank A Read Command Bank A Activate Command Bank A Activate Command Bank A Precharge Command Bank A Precharge Termination of a Read Burst. SPT03933 INFINEON Technologies 47 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 'HHS3RZHU'RZQ0RGH 'HHS3RZHU'RZQ0RGH(QWU\ CLK CKE CS WE CAS RAS Addr. DQM DQ input DQ output High-Z t RP Precharge Command Deep Power Down Entry Deep Power Down Mode Normal Mode DP1.vsd The deep power down mode has to be maintained for a minimum of 100µs. INFINEON Technologies 48 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM 'HHS3RZHU'RZQ([LW The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command: 1. Maintain NOP input conditions for a minimum of 200 µs 2. Issue precharge commands for all banks of the device 3. Issue eight or more autorefresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extende mode register CLK CK E CS RAS CAS WE 200 ms Deep Power Do wn exi t INFINEON Technologies tRP All banks prec harge tRC Au to refresh Auto refresh 49 Mode Register Set Exte nded Mode Regis ter Set New Com mand Accepted Here 2003-02 HYB/E 25L128160AC 128-MBit Mobile-RAM &KDQJH/LVW First Revision (Target Datasheet) 12/18/00 01/15/01 Various changes after JEDEC Low Power Task Force meeting in San Jose, Jan 9-10. 01: Introduction of a Extended Mode Register for temperature-compensated and partial array Self-Refresh New Deep Power Down Mode New 54 BGA package with 9 x 6 ball locations and 3 depop rows. 01/22/01 Truth table for Deep Power Down Mode changed according to latest JEDEC proposal some typos corrected 02/12/01 Pin J8 is “A2” Extended Mode Register “half array BA1=0” 02/19/01 Extended Mode Register, some clarifications Datasheet changed to “preliminary” Outline dimensions for BGA packages added Electrical pinout for x8 added 03/07/01 Full Page Mode added, thruth table clarified 04/02/01 Pin Configuration for x8 devices corrected : LDQM wird NC und UDQM wird DQM Deep Power Down Exit waveform changed according to JEDEC ballot 07/02/01 Page 10: Change of power-on description to : ”9DD must be applied before or at the same time as 9DDQ to the specified voltage when the input signals are held in the “NOP” or “DESELECT” state” 08/23/01 Adjusted currents Introduced CAS Latency 1 Solder Ball Diameter changed 09/18/01 Adjusted currents Introduced max. package height 11/14/01 Jedec conforming package drawings included tRCD and tRP for -7.5 changed Minimum time of deep power down mode added tAC for CAS Latency=1 specified 25/03/02 ICC3N (CKE high) changed from 32ma to 35mA for -7.5 and from 28mA to 31mA for -8.0 28/02/03 p.15: values for ICC1 and ICC5 changed INFINEON Technologies 50 2003-02