D a ta S h e e t , M a y 2 0 0 0 C504 8-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . Edition 2000-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S h e e t , M a y 2 0 0 0 C504 8-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . C504 Revision History: 2000-05 Previous Version: 1996-05 Page Subjects (major changes since last revision) 35 - 40 OTP Memory Operation is added. 41 Table on Version Byte Content is added. 57 - 60 AC Characteristics of Programming Mode is added. several VCC is replaced by VDD. several Specification for SAH-C504 is removed Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] 8-Bit Single-Chip Microcontroller C500 Family C504 C504 • Fully compatible to standard 8051 microcontroller • Up to 40 MHz external operating frequency • 16 Kbyte on-chip program memory – C504-2R: ROM version (with optional ROM protection) – C504-2E: programmable OTP version – C504-L: without on-chip program memory • 256 byte on-chip RAM • 256 byte on-chip XRAM • Four 8-bit ports – 2 ports with mixed analog/digital I/O capability • Three 16-bit timers/counters – Timer 2 with up/down counter feature Further features are listed next page. On-Chip Emulation Support Module Oscillator Watchdog XRAM 256 x 8 10-Bit ADC RAM 256 x 8 Port 0 I/O Port 1 8-Bit Digital I/O 4-Bit Analog Inputs Port 2 I/O Port 3 8-Bit Digital I/O 4-Bit Analog Inputs Timer 2 16-Bit Capture/Compare Unit T0 C500 Core T1 8-Bit USART 10-Bit Compare Unit Watchdog Timer ROM/OTP 16 k x 8 MCB02589 Figure 1 Data Sheet C504 Functional Units 1 2000-05 C504 • Capture/compare unit for PWM signal generation and signal capturing – 3-channel, 16-bit capture/compare unit – 1-channel, 10-bit compare unit • Full duplex serial interface (USART) • 10-bit A/D Converter with 8 multiplexed inputs • Twelve interrupt sources with two priority levels • On-chip emulation support logic (Enhanced Hooks Technology TM) • Programmable 15-bit Watchdog Timer • Oscillator Watchdog • Fast Power On Reset • Power Saving Modes – Idle mode – Power-down mode with wake-up capability through INT0 • M-QFP-44 package • Temperature ranges: SAB-C504 TA: 0 to 70 °C SAF-C504 TA: – 40 to 85 °C SAK-C504 TA: – 40 to 125 °C (max. operating frequency: 24 MHz) Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code indentifies: • The derivative itself, i.e. its function set • the specified temperature range • the package and the type of delivery For the available ordering codes for the C504, please refer to the “Product Information Microcontrollers” which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet 2 2000-05 C504 VDD VSS VAREF VAGND Port 0 8-Bit Digital I/O XTAL1 XTAL2 RESET EA ALE PSEN Port 1 8-Bit Digital I/O/ 4-Bit Analog Inputs C504 Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O/ 4-Bit Analog Inputs CTRAP COUT3 MCL02590 Figure 2 Data Sheet Logic Symbol 3 2000-05 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA COUT3 ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 C504 33 32 31 30 29 28 27 26 25 24 23 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V GND P1.0 / AN0 / T2 P1.1 / AN1 / T2EX P1.2 / AN2 / CC0 P1.3 / AN3 / COUT0 P1.4 / CC1 34 35 36 37 38 39 40 41 42 43 44 C504-LM C504-2RM C504-2EM 22 21 20 19 18 17 16 15 14 13 12 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 V DD V SS XTAL1 XTAL2 P3.7 / RD P3.6 / WR / INT2 P1.5 / COUT1 P1.6 / CC2 P1.7 / COUT2 RESET P3.0 / RxD CTRAP P3.1 / TxD P3.2 / AN4 / INT0 P3.3 / AN5 / INT1 P3.4 / AN6 / T0 P3.5 / AN7 / T1 1 2 3 4 5 6 7 8 9 10 11 Figure 3 Data Sheet MCP02532 Pin Configuration (top view) 4 2000-05 C504 Table 1 Symbol Pin Definitions and Functions Pin Number I/O1) Function (P-MQFP-44) P1.0 - P1.7 40 - 44, 1-3 I/O The functions are assigned to the pins of Port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 / input to Timer 2 P1.1 / AN1 / T2EX Analog input channel 1 / capture/reload trigger of Timer 2 up-down count P1.2 / AN2 / CC0 Analog input channel 2 / input/output of capture/ compare channel 0 P1.3 / AN3 / COUT0 Analog input channel 3 / output of capture/compare channel 0 P1.4 / CC1 Input/output of capture/ compare channel 1 P1.5 / COUT1 Output of capture/compare channel 1 P1.6 / CC2 Input/output of capture/ compare channel 2 P1.7 / COUT2 Output of capture/compare channel 2 40 41 42 43 44 1 2 3 RESET Data Sheet 4 Port 1 is an 8-bit bidirectional port. Port 1 pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D converter. As secondary digital functions, Port 1 contains the Timer 2 pins and the Capture/Compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD. 5 2000-05 C504 Table 1 Symbol Pin Definitions and Functions (cont’d) Pin Number I/O1) Function (P-MQFP-44) P3.0 - P3.7 5, 7 - 13 5 7 8 9 10 11 12 13 Data Sheet I/O Port 3 is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, and four of the analog inputs of the A/D converter. Port 3 pins are assigned to be used as analog inputs via the bits of SFR P3ANA. P3.6/WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / AN4 / INT0 Analog input channel 4 / external interrupt 0 input / Timer 0 gate control input P3.3 / AN5 / INT1 Analog input channel 5 / external interrupt 1 input / Timer 1 gate control input P3.4 / AN6 / T0 Analog input channel 6 / Timer 0 counter input P3.5 / AN7 / T1 Analog input channel 7 / Timer 1 counter input P3.6 / WR / INT2 WR control output; latches the data byte from port 0 into the external data memory / external interrupt 2 input RD control output; enables the P3.7 / RD external data memory 6 2000-05 C504 Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O1) Function (P-MQFP-44) CTRAP 6 I CCU Trap Input With CTRAP = low, the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode. XTAL2 14 – XTAL2 Output of the inverting oscillator amplifier. XTAL1 15 – XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. I/O Port 2 is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have “1”s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing “1”s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 special function register. P2.0 - P2.7 18-25 Data Sheet 7 2000-05 C504 Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O1) Function (P-MQFP-44) PSEN 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. ALE 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. When instructions are executed from internal ROM (EA = 1) the ALE generation can be disabled by clearing bit EALE in SFR SYSCON. COUT3 28 O 10-Bit compare channel output This pin is used for the output signal of the 10-bit Compare Timer 2 unit. COUT3 can be disabled and set to a high or low state. EA 29 I External Access Enable When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000H. When held at low level, the C504 fetches all instructions from external program memory. For the C504-L, this pin must be tied low. P0.0 - P0.7 37 - 30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have “1”s written to them float; and in that state, can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pullup resistors when issuing “1” s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification. VAREF – Reference voltage for the A/D converter. Data Sheet 38 8 2000-05 C504 Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O1) Function (P-MQFP-44) VAGND VSS VDD 39 – Reference ground for the A/D converter. 16 – Ground (0 V) 17 – Power Supply (+ 5 V) 1) I = Input, O = Output Data Sheet 9 2000-05 C504 VDD VSS Oscillator Watchdog XRAM 256 x 8 XTAL1 XTAL2 RAM 256 x 8 ROM/OTP 16 k x 8 OSC & Timing CPU RESET ALE PSEN EA Timer 0 Port 0 Port 0 8-Bit Digital I/O Timer 1 Port 1 Port 1 8-Bit Digital I/O 4-Bit Analog Inputs Timer 2 Port 2 Port 2 8-Bit Digital I/O Interrupt Unit Port 3 Port 3 8-Bit Digital I/O 4-Bit Analog Inputs USART COUT3 CTRAP Capture/Compare Unit VAREF VAGND A/D Converter 10-Bit S&H Emulation Support Logic MUX MCB02591 Figure 4 Data Sheet Block Diagram of the C504 10 2000-05 C504 CPU The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 µs (24 MHz: 500 ns, 40 MHz: 300 ns). Special Function Register PSW (Address D0H) Reset Value: 00H Bit No. MSB D0H LSB D7H D6H D5H D4H D3H D2H D1H D0H CY AC F0 RS1 RS0 OV F1 P PSW Bit Function CY Carry Flag Used by arithmetic instructions. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag 0 RS1 RS0 Register Bank Select Control bits These bits are used to select one of the four register banks. RS1 RS0 Function 0 0 Bank 0 selected, data address 00H-07H 0 1 Bank 1 selected, data address 08H-0FH 1 0 Bank 2 selected, data address 10H-17H 1 1 Bank 3 selected, data address 18H-1FH OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag 1 P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/ even number of “one” bits in the accumulator. Data Sheet 11 2000-05 C504 Memory Organization The C504 CPU manipulates operands in the following four address spaces: – up to 64 Kbyte of program memory: 16K ROM for C504-2R 16K OTP for C504-2E – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – 256 bytes of internal XRAM data memory – a 128 byte special function register area Figure 5 illustrates the memory address spaces of the C504. FFFF H FFFF H Internal XRAM FEFF H FF00 H External Indirect Address Direct Address FF H FF H Special Function Register Internal RAM External 4000 H 3FFFH Internal (EA = 1) 80 H 80 H 7F H External (EA = 0) Internal RAM 0000 H 0000 H "Code Space" "Data Space" 00 H "Internal Data Space" MCD02592 Figure 5 Data Sheet C504 Memory Map 12 2000-05 C504 Reset and System Clock Operation The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This, in turn, may cause unpredictable output operations at several port pins). At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the reset pin to VDD via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation is the oscillator start-up time and the time for 2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (Figure 6b). In each case, it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. Figure 6 shows the possible reset circuitries. a) b) & RESET RESET C504 C504 + c) + RESET C504 Figure 6 Data Sheet MCS03352 Reset Circuitries 13 2000-05 C504 Figure 7 shows the recommended oscillator circuit for the C504, while Figure 8 shows the circuit for using an external clock source. C XTAL2 3.5 - 40 MHz C504 C XTAL1 C = 20 pF 10 pF for crystal operation MCS03353 Figure 7 Recommended Oscillator Circuit C504 V DD N.C. External Clock Signal XTAL2 XTAL1 MCS03355 Figure 8 Data Sheet External Clock Source 14 2000-05 C504 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware RESET EA ALE PSEN SYSCON PCON TCON C500 MCU RSYSCON RPCON RTCON EH-IC Enhanced Hooks Interface Circuit Port 0 Port 2 Optional I/O Ports Port 3 Port 1 RPort 2 RPort 0 Target System Interface Figure 9 TEA TALE TPSEN MCS02647 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, Port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. Data Sheet 15 2000-05 C504 Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 63 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F0H, F8H) are bit-addressable. The SFRs of the C504 are listed in Table 2 and Table 3. In Table 2, they are organized in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Data Sheet 16 2000-05 C504 Table 2 Special Function Registers - Functional Blocks Block Symbol Name Addr. Contents after Reset CPU ACC B DPH DPL PSW SP Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer SYSCON System Control Register E0H1) F0H1) 83H 82H D0H1) 81H B1H 00H 00H 00H 00H 00H 07H XX10XXX0B3) Interrupt System IEN0 IEN1 CCIE2) IP0 IP1 ITCON Interrupt Enable Register 0 Interrupt Enable Register 1 Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register A8H1) A9H D6H B8H1) B9H 9AH 0X000000B3) XX000000B3) 00H XX000000B3) XX000000B3) 00101010B Ports P0 P1 P1ANA2) P2 P3 P3ANA2) Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 3 Analog Input Selection Register 80H1) 90H1) 90H1) 4) A0H1) B0H1) B0H1) 4) FFH FFH XXXX1111B3) FFH FFH XX1111XXB3) A/DConverter ADCON0 ADCON1 A/D Converter Control Register 0 A/D Converter Control Register 1 ADDATH A/D Converter Data Register High Byte ADDATL A/D Converter Data Register Low Byte P1ANA2) Port 1 Analog Input Selection Register P3ANA2) Port 3 Analog Input Selection Register D8H1) DCH D9H DAH 90H1) 4) B0H1) 4) XX000000B3) 01XXX000B3) 00H 00XXXXXXB3) XXXX1111B3) XX1111XXB3) Serial Channels PCON2) SBUF SCON Power Control Register Serial Channel Buffer Register Serial Channel Control Register 87H 99H 98H1) 000X0000B XXH3) 00H Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H1) 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet 17 2000-05 C504 Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Addr. Contents after Reset Timer 2 T2CON T2MOD RC2H RC2L TH2 TL2 Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte C8H1) C9H CBH CAH CDH CCH 00H XXXXXXX0B3) 00H 00H 00H 00H Capture / Compare Unit CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI TRCON CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE2) CT2CON CP2L CP2H CMP2L CMP2H BCON Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Trap enable control register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag reg. Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register E1H DEH DFH E6H E7H E3H E4H E2H CFH C2H C3H C4H C5H C6H C7H E5H D6H C1H D2H D3H D4H D5H D7H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00B3) 00H XXXXXX00B3) 00H Watchdog Timer WDCON Watchdog Timer Control Register WDTREL Watchdog Timer Reload Register C0H1) 86H XXXX0000B3) 00H Power Saving Mode PCON2) PCON1 87H 88H1) 4) 000X0000B3) 0XXXXXXXB3) Power Control Register Power Control Register 1 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet 18 2000-05 C504 Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H2) P0 FFH .7 .6 .5 .4 .3 .2 .1 .0 81H SP 07H .7 .6 .5 .4 .3 .2 .1 .0 82H DPL 00H .7 .6 .5 .4 .3 .2 .1 .0 83H DPH 00H .7 .6 .5 .4 .3 .2 .1 .0 86H WDTREL 00H WDT PSEL .6 .5 .4 .3 .2 .1 .0 87H PCON 000X0000B SMOD PDS IDLS – GF1 GF0 PDE IDLE TCON 00H TF1 TF0 TR0 IE1 IT1 IE0 IT0 PCON1 0XXXXXXXB EWPD – – – – – – – 89H TMOD 00H GATE C/T M1 M0 GATE C/T M1 M0 8AH TL0 00H .7 .6 .5 .4 .3 .2 .1 .0 8BH TL1 00H .7 .6 .5 .4 .3 .2 .1 .0 8CH TH0 00H .7 .6 .5 .4 .3 .2 .1 .0 8DH TH1 00H .7 .6 .5 .4 .3 .2 .1 .0 90H2) P1 FFH .7 .6 .5 .4 .3 .2 T2EX T2 P1ANA XXXX1111B – – – – EAN3 EAN2 EAN1 EAN0 98H2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 99H SBUF XXH .7 .6 .5 .4 .3 .2 .1 .0 9AH ITCON 00101010B IT2 IE2 I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR A0H2) P2 FFH .7 .6 .5 .4 .3 .2 .1 .0 A8H2) IEN0 0X000000B EA – ET2 ES ET1 EX1 ET0 EX0 A9H IEN1 XX000000B – – ECT1 ECCM ECT2 ECEM EX2 EADC 88H2) 88H 90H 1)3) 2)3) TR1 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet 19 2000-05 C504 Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0H2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B0H P3ANA XX1111XXB – – EAN7 EAN6 EAN5 EAN4 – – B1H SYSCON XX10XXX0B – – EALE RMAP – – – XMAP B8H2) IP0 XX000000B – – PT2 PS PT1 PX1 PT0 PX0 B9H IP1 XX000000B – – PCT1 PCCM PCT2 PCEM PX2 PADC C0H2) WDCON XXXX0000B – – – – OWDS WDTS WDT SWDT C1H CT2CON 00010000B CT2P ECT2O STE2 CT2 RES CT2R CLK2 CLK1 CLK0 C2H CCL0 00H .7 .6 .5 .4 .3 .2 .1 .0 C3H CCH0 00H .7 .6 .5 .4 .3 .2 .1 .0 C4H CCL1 00H .7 .6 .5 .4 .3 .2 .1 .0 C5H CCH1 00H .7 .6 .5 .4 .3 .2 .1 .0 C6H CCL2 00H .7 .6 .5 .4 .3 .2 .1 .0 C7H CCH2 00H .7 .6 .5 .4 .3 .2 .1 .0 C8H T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/ RL2 C9H T2MOD XXXXXXX0B – – – – – – – DCEN CAH RC2L 00H .7 .6 .5 .4 .3 .2 .1 .0 CBH RC2H 00H .7 .6 .5 .4 .3 .2 .1 .0 CCH TL2 00H .7 .6 .5 .4 .3 .2 .1 .0 CDH TH2 00H .7 .6 .5 .4 .3 .2 .1 .0 CFH TRCON 00H TRPEN TRF 2)3) 2) TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet 20 2000-05 C504 Table 3 Addr Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Register Content Bit 7 after Reset1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D0H2) PSW 00H CY AC F0 RS1 RS0 OV F1 P D2H CP2L 00H .7 .6 .5 .4 .3 .2 .1 .0 D3H CP2H XXXX. XX00B – – – – – – .1 .0 D4H CMP2L 00H .7 .6 .5 .4 .3 .2 .1 .0 D5H CMP2H XXXX. XX00B – – – – – – .1 .0 D6H CCIE 00H ECTP ECTC CC2 FEN CC2 REN CC1 FEN CC1 REN CC0 FEN CC0 REN D7H BCON 00H BCMP PWM1 PWM0 EBCE BCEM BCERR BCEN BCM1 BCM0 – – IADC BSY ADM MX2 MX1 MX0 D8H2) ADCON0 XX000000B D9H ADDATH 00H .9 .8 .7 .6 .5 .4 .3 .2 DAH ADDATL 00XXXXXXB .1 .0 – – – – – – DCH ADCON1 01XXX000B ADCL1 ADCL0 – – – MX2 MX1 MX0 DEH CCPL 00H .7 .6 .5 .4 .3 .2 .1 .0 DFH CCPH 00H .7 .6 .5 .4 .3 .2 .1 .0 E0H2) ACC 00H .7 .6 .5 .4 .3 .2 .1 .0 E1H CT1CON 00010000B CTM ETRP STE1 CT1 RES CT1R CLK2 CLK1 CLK0 E2H COINI COUT 3I COUTX COUT I 2I CC2I COUT 1I CC1I COUT 0I CC0I E3H CMSEL0 00H CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL 13 12 11 10 03 02 01 00 E4H CMSEL1 00H 0 E5H CCIR E6H FFH 0 CMSEL CMSEL CMSEL CMSEL 23 22 21 20 CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R CT1OFL 00H .7 .6 .5 .4 .3 .2 .1 .0 E7H CT1OFH 00H .7 .6 .5 .4 .3 .2 .1 .0 F0H2) B .7 .6 .5 .4 .3 .2 .1 .0 00H 00H 0 0 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Data Sheet 21 2000-05 C504 Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4. Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock Gate C/T M1 M0 internal external (max.) 0 8-bit timer/counter with a divide-by-32 prescaler X X 0 0 fOSC/12 × 32 fOSC/24 × 32 1 16-bit timer/counter X X 1 1 2 8-bit timer/counter with 8-bit auto-reload X X 0 0 fOSC/12 fOSC/12 fOSC/24 fOSC/24 3 Timer/counter 0 used as one X 8-bit timer/counter and one 8-bit timer Timer 1 stops X 1 1 fOSC/12 fOSC/24 In the “timer” function (C/T = ‘0’), the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic. f OSC f OSC/12 ÷ 12 C/T TMOD 0 P3.4/T0 P3.5/T1 max f OSC/24 Timer 0/1 Input Clock 1 TR 0/1 Control TCON Gate TMOD & =1 <_ 1 P3.2/INT0 P3.3/INT1 Figure 10 Data Sheet MCS01768 Timer/Counter 0 and 1 Input Clock Logic 22 2000-05 C504 Timer/Counter 2 Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as a timer or as an event counter. This is selected by bit C/T2 of SFR T2CON. It has three operating modes as shown in Table 5. Table 5 Timer/Counter 2 Operating Modes Mode T2CON R×CLK or T×CLK 16-bit Autoreload T2MOD T2CON CP/ TR2 RL2 DCEN P1.1/ T2EX 0 1 0 0 X 0 0 1 0 1 ↓ 0 0 0 0 1 1 1 1 X X 0 1 0 1 1 X 0 X 0 1 1 X 1 ↓ Baud Rate Generator 1 X 1 X 0 X 1 X 1 X 1 ↓ off X X 0 X X X Note: ↓ = Data Sheet Input Clock internal external (P1.0/T2) EXEN 0 16-bit Capture Remarks reload upon fOSC/12 overflow reload trigger (falling edge) Down counting Up counting max fOSC/24 16 bit Timer/ Counter (only up-counting) capture TH2, TL2 → RC2H, RC2L fOSC/12 max fOSC/24 no overflow interrupt request (TF2) extra external interrupt (“Timer 2”) fOSC/2 max fOSC/24 Timer 2 stops – – falling edge 23 2000-05 C504 Capture/Compare Unit The Capture/Compare Unit (CCU) of the C504 consists of a 16-bit 3-channel capture/ compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. In capture mode, the value of the Compare Timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx. Figure 11 shows the block diagram of the CCU. Figure 11 Data Sheet Block Diagram of the CCU 24 2000-05 C504 The Compare Timers 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers; each of which has a count rate with a maximum of fOSC/2 up to fOSC/256. The compare timer operations with its possible compare output signal waveforms are shown in Figure 12. Compare Timer 1 in Operating Mode 0 a) Standard PWM (Edge Aligned) b) Standard PWM (Single Edge Aligned) with programmable dead time ( t OFF ) Period Value Period Value Compare Value Compare Value Offset 0000 H t OFF CC CC COUT COUT Compare Timer 1 in Operating Mode 1 c) Symetrical PWM (Center Aligned) d) Symetrical PWM (Center Aligned) with programmable dead time ( t OFF ) Period Value Period Value Compare Value Compare Value Offset 0000 H t OFF t OFF CC COINI=0 CC COINI=0 COUT COINI=1 COUT COINI=1 : Interrupts can be generated Figure 12 MCT03356 Basic Operating Modes of the CAPCOM Unit Compare Timer 1 can be programmed for both operating modes while Compare Timer 2 works only in operating mode 0 with one output signal of selectable polarity at the pin COUT3. Data Sheet 25 2000-05 C504 Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 6. Table 6 USART Operating Modes Mode SCON Baud Rate Description Serial data enters and exits through R×D. T×D outputs the shift clock. 8-bit are transmitted/received (LSB first) SM0 SM1 0 0 0 fOSC/12 1 0 1 Timer 1/2 overflow rate 8-bit UART 10 bits are transmitted (through T×D) or received (R×D) 2 1 0 fOSC/32 or fOSC/64 3 1 1 Timer 1/2 overflow rate 9-bit UART Like mode 2 except the variable baud rate 9-bit UART 11 bits are transmitted (T×D) or received (R×D) Timer 2 Overflow Timer 1 Overflow Phase 2 CLK (= f OSC /2) PCON.7 (SMOD) SM0 / SM1 Mode 1, 3 2 Mode 2 T2CON (RCLK, TCLK) 0 0 1 1 Baud Rate Clock MCB02414 Figure 13 Data Sheet Baud Rate Generation for the Serial Interface 26 2000-05 C504 The possible baud rates can be calculated using the formulas given in Table 7. Table 7 Formulas for Calculating Baud Rates Source of Baud Rate Operating Mode Baud Rate Oscillator 0 2 fOSC/12 (2SMOD × fOSC)/64 Timer 1 (16-bit timer) (8-bit timer with 8-bit auto-reload) 1, 3 1, 3 (2SMOD × timer 1 overflow rate)/32 (2SMOD × fOSC)/(32 × 12 × (256-TH1)) Timer 2 1, 3 fOSC/(32 × (65536-(RC2H, RC2L)) Data Sheet 27 2000-05 C504 10-Bit A/D Converter The C504 has a high performance 8-channel 10-bit A/D converter using successive approximation technique for the conversion of analog input voltages. Figure 14 shows the block diagram of the A/D Converter. Internal Bus IEN1 (A9H ) - ECT1 ECCM ECT2 ECEM - EX2 EADC P1ANA (90 H) - - - - EAN3 EAN2 EAN1 EAN0 P3ANA (B0 H) - EAN7 EAN6 EAN5 EAN4 - - - ADCON1 (DCH ) ADCL1 ADCL0 - - - MX2 MX1 MX0 IADC BSY ADM MX2 MX1 MX0 ADCON0 (D8 H) - - Single/ Continuous Mode Port 1/3 MUX S&H A/D Converter f OSC /2 Clock Prescaler ÷ 32, 16, 8, 4 Conversion Clock f ADC ADDATH ADDATL (D9H ) (DA H) .2 .3 .4 .5 .6 .7 .8 MSB LSB .1 Input Clock f IN VAREF VAGND Start of Conversion Write to ADDATL Shaded bit locations are not used in ADC-functions. Internal Bus MCB02616 Figure 14 Data Sheet A/D Converter Block Diagram 28 2000-05 C504 The A/D Converter uses two clock signals for operation: the conversion clock fADC (= 1/ tADC) and the input clock fIN (= 1/tIN). Both clock signals are derived from the C504 system clock fOSC which is applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the fIN clock signal. The table in Figure 15 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates. MCU System Clock Rate (fOSC) fIN Prescaler fADC [MHz] Ratio ADCL1 ADCL0 [MHz] A/D Conversion Time [µs] 3.5 MHz 1.75 ÷4 0 0 .438 48 × tIN = 27.4 12 MHz 6 ÷4 0 0 1.5 48 × tIN = 8 16 MHz 8 ÷4 0 0 2 48 × tIN = 6 24 MHz 12 ÷8 0 1 1.5 96 × tIN = 8 32 MHz 16 ÷8 0 1 2 96 × tIN = 6 40 MHz 20 ÷ 16 1 0 1.25 192 × tIN = 9.6 Figure 15 A/D Converter Clock Selection The analog inputs are located at Port 1 and Port 3 (4 lines on each port). The corresponding Port 1 and Port 3 pins have a port structure, which allows the pins to be used either as digital I/Os or analog inputs. The analog input function of these mixed digital/analog port lines is selected via the registers P1ANA and P3ANA. Data Sheet 29 2000-05 C504 Interrupt System The C504 provides 12 interrupt sources with two priority levels. Figures 16 and 17 give a general overview of the interrupt sources and illustrate the interrupt request and control flags. Figure 16 Data Sheet Interrupt Request Sources (Part 1) 30 2000-05 C504 Low Priority <_1 P3.6/WR/INT2 IE2 IT2 ITCON.7 ITCON.6 ITCON.4 EX2 IEN1.1 004B H High Priority PX2 IP1.1 ITCON.5 <_1 CC0R CCIR.0 P1.2/AN2/CC0 CC0REN CCIE0.0 Capture/Compare Match Interrupt CC0F CCIR.1 CC0FEN CCIE0.1 CC1R CCIR.2 P1.4/CC1 CC1REN CCIE0.2 ECCM IEN1.4 CC1F CCIR.3 CC1FEN CCIE0.3 0063 H PCCM IP1.4 CC2R CCIR.4 P1.6/CC2 CC2REN CCIE0.4 CC2F CCIR.5 CC2FEN CCIE0.5 CT1FP Compare Timer 1 Interrupt CCIR.7 ECTP CCIE.7 <_ 1 ECT1 IEN1.5 CT1FC CCIR.6 Compare Timer 2 Interrupt ECTC CCIE.6 CT2P CT2CON.7 TRF CCU Emergency Interrupt Bit addressable Request Flag is cleared by hardware Figure 17 Data Sheet TRCON.6 ETRP CT1CON.6 005B H PCT1 IP1.5 PCT2 IP1.3 <_ 1 ECEM IEN1.2 BCERR BCON.3 ECT2 IEN1.3 006B H 0053 H PCEM IP1.2 EA EBCE BCON.4 IEN0.7 MCB02596 Interrupt Request Sources (Part 2) 31 2000-05 C504 Table 8 Interrupt Vector Addresses Request Flags Interrupt Source Vector Address IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 IADC IE2 TRF, BCERR CT2P CC0F-CC2F, CC0R-CC2R CT1FP, CT1FC – External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt A/D converter interrupt External interrupt 2 CAPCOM emergency interrupt Compare timer 2 interrupt Capture/compare match interrupt Compare timer 1 interrupt Power-down interrupt 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 007BH A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt sources. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9. Table 9 Interrupt Source Structure Interrupt Source High Priority External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt Data Sheet Priority Low Priority A/D Converter External Interrupt 2 CCU Emergency Interrupt Compare Timer 2 Interrupt Capture/Compare Match Interrupt Compare Timer 1 Interrupt 32 High Low 2000-05 C504 Fail Save Mechanisms The C504 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure. – a programmable 15-bit Watchdog Timer – Oscillator Watchdog Programmable Watchdog Timer The Watchdog Timer in the C504 is a 15-bit timer, which is incremented by a count rate of either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). Only the upper 7 bits of the 15-bit watchdog timer count value can be programmed. Figure 18 shows the block diagram of the programmable Watchdog Timer. Figure 18 Block Diagram of the Programmable Watchdog Timer The Watchdog Timer can be started by software (bit SWDT in SFR WDCON), but it cannot be stopped during active mode of the device. If the software fails to refresh the running Watchdog Timer, an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in SFR WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT and SWDT (both in SFR WDCON) consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the Watchdog Timer is halted during the idle mode and power down mode of the processor. Data Sheet 33 2000-05 C504 Oscillator Watchdog The Oscillator Watchdog of the C504 serves for three functions: – Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504 is brought into reset. If the failure condition disappears, the C504 executes a final reset phase of typically 1 ms in order to allow the oscillator to stabilize; then, the Oscillator Watchdog reset is released and the part starts program execution again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The Oscillator Watchdog unit also works identically to the monitoring function. – Control of external wake-up from software power-down mode When the software power-down mode is terminated by a low level at pin P3.2/INT0, the Oscillator Watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typically 1 ms in order to allow the on-chip oscillator to stabilize. Data Sheet 34 2000-05 C504 Figure 19 Block Diagram of the Oscillator Watchdog Power Saving Modes The C504 provides two power saving modes, the idle mode and the power down mode. – In the idle mode, the oscillator of the C504 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D Converter, and all timers with the exception of the Watchdog Timer, are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. – In the power down mode, the RC oscillator and the on-chip oscillator which operates with the XTAL pins are both stopped. Therefore all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFRs are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFRs. Table 10 gives a general overview of the entry and exit procedures of the power saving modes. Data Sheet 35 2000-05 C504 Table 10 Power Saving Modes Overview Mode Entering (2-Instruction Example) Leaving by Remarks Idle mode ORL PCON, #01H ORL PCON, #20H Occurrence of any enabled interrupt CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock. Hardware Reset Power With external wake-up Hardware Reset Oscillator is stopped; Down mode capability from power P3.2/INT0 goes low Contents of on-chip RAM down enabled and SFRs are maintained. for at least 10 µs. ORL SYSCON,#10H It is desired that the ORL PCON1,#80H pin be held at high ANL SYSCON,#0EFH level during the power down mode ORL PCON,#02H entry and up to the ORL PCON,#40H wake-up. With external wake-up Hardware Reset capability from power down disabled ORL PCON,#02H ORL PCON,#40H If a power saving mode is terminated through an interrupt, including the external wakeup via P3.2/INT0, the microcontroller state (CPU, ports, peripherals) remains preserved. If it is terminated by a hardware reset, the microcontroller is reset to its default state. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. Data Sheet 36 2000-05 C504 OTP Memory Operation (C504-2E only) The C504-2E is the OTP version of the C504 microcontroller with a 16Kbyte one-time programmable (OTP) program memory. Fast programming cycles are achieved (1 byte in 100 µs) with the C504-2E. Several levels of OTP memory protection can be selected as well. To program the device, the C504-2E must be put into the programming mode. Typically, this is not done in-system, but in a special programming hardware. In the programming mode, the C504-2E operates as a slave device similar to an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. Figure 20 shows the pins of the C504-2E which are required for controlling of the OTP programming mode. V DD P2.0 - 7 V SS Port 2 Port 0 P0.0 - 7 PALE PMSEL0 EA / V PP PMSEL1 PROG C504-2E PRD RESET PSEN XTAL1 PSEL XTAL2 MCS03360 Figure 20 Data Sheet C504-2E Programming Mode Configuration 37 2000-05 C504 D4 D5 D6 D7 EA / V PP N.C. PROG PSEN A7 A6 A5 / A13 Pin Configuration in Programming Mode 33 32 31 30 29 28 27 26 25 24 23 D3 D2 D1 D0 N.C. N.C. N.C. N.C. N.C. N.C. N.C. 34 35 36 37 38 39 40 41 42 43 44 C504-2E 22 21 20 19 18 17 16 15 14 13 12 A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 V DD V SS XTAL1 XTAL2 N.C. N.C. N.C. N.C. N.C. RESET PMSEL0 N.C. PMSEL1 PSEL PRD PALE N.C. 1 2 3 4 5 6 7 8 9 10 11 Figure 21 Data Sheet MCP03361 Pin Configuration of the C504-2E in Programming Mode (top view) 38 2000-05 C504 Pin Definitions Table 11 contains the functional description of all C504-2E pins which are required for OTP memory programming. Table 11 Symbol Pin Definitions and Functions of the C504-2E in Programming Mode Pin No. I/O Function 4 I Reset This input must be at static “1” (active) level throughout the entire programming mode. PMSEL0 5 PMSEL1 7 I I Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. P-MQFP-44 RESET PMSEL1 PMSEL0 Access Mode 0 0 Reserved 0 1 Read version bytes 1 0 Program/read lock bits 1 1 Program/read OTP memory byte PSEL 8 I Basic programming mode select This input is used for the basic programming mode selection and must be switched according to Figure 22. PRD 9 I Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. PALE 10 I Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. XTAL2 14 O XTAL2 Output of the inverting oscillator amplifier. Data Sheet 39 2000-05 C504 Table 11 Symbol Pin Definitions and Functions of the C504-2E in Programming Mode (cont’d) Pin No. I/O Function P-MQFP-44 XTAL1 15 I XTAL1 Input to the oscillator amplifier. VSS 16 – Ground (0 V) must be applied in programming mode. VDD 17 – Power Supply (+ 5 V) must be applied in programming mode. P2.0 P2.7 18 - 25 I Address lines P2.0 - P2.7 are used as multiplexed address input lines A0 - A7 and A8 - A13. A8 - A13 must be latched with PALE. PSEN 26 I Program store enable This input must be at static “0” level during the whole programming mode. PROG 27 I Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection, a low level must be applied to PROG. EA/VPP 29 – Programming Voltage This pin must be held at 11.5 V (VPP) during programming of an OTP memory byte or lock bit. During an OTP memory read operation, this pin must be at VIH. This pin is also used for basic programming mode selection. For basic programming mode selection, a low level must be applied. P0.7 P0.0 30-37 I/O Data lines In programming mode, data bytes are transferred via the bidirectional D7 - D0 data lines which are located at Port 0. N.C. 1-3, 6, 11-13, 28, 38-44 – Not Connected These pins should not be connected in programming mode. Data Sheet 40 2000-05 C504 Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts: – Basic programming mode selection – Access mode selection With basic programming mode selection, the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/ read, version byte read, and program/read lock byte operations. The basic programming mode selection scheme is shown in Figure 22. 5V VDD Clock (XTAL1/ XTAL2) Stable RESET "1" PSEN "0" PMSEL1,0 0,1 PROG "0" "1" PRD PSEL PALE "0" VPP EA/VPP VIH 0V Ready for access mode selection During this period signals are not actively driven Figure 22 Data Sheet MCT03362 Basic Programming Mode Selection 41 2000-05 C504 Table 12 Access Modes Selection Access Mode EA/ PROG PRD VPP Program OTP memory byte VPP Read OTP memory byte VIH Address (Port 2) Data (Port 0) 1 0 H H H A0 - A7 A8 - A15 D0 - D7 H H L – D1,D0 see Table 13 L H Byte addr. D0 - D7 of version byte H Read OTP lock bits VPP VIH H Read OTP version byte VIH Program OTP lock bits PMSEL H Lock Bits Programming / Read The C504-2E has two programmable lock bits which, when programmed according to Table 13, provide four levels of protection for the on-chip OTP code memory. Table 13 Lock Bit Protection Types Lock Bits D1 D0 Protection Protection Type Level 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C504-2E, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C504-2E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to ROM/OTP verification mode 2. Further programming of the OTP memory is disabled (reprogramming security). 0 1 Level 2 Same as level 1, but also OTP memory read operation using ROM verification mode 2 is disabled. 0 0 Level 3 Same as level 2; but additionally external code execution by setting EA = low during normal operation of the C504-2E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible. Note: A ‘1’ means that the lock bit is unprogrammed; a ‘0’ means that lock bit is programmed. Data Sheet 42 2000-05 C504 Version Bytes The C504-2E and C504-2R provide three version bytes at mapped address locations FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask of each microcontroller step. Therefore, the version bytes can be read but not written. The three version bytes hold information as manufacturer code, device type, and stepping code. The steppings of the C504 contain the following version byte information: Table 14 Content of Version Bytes Stepping Version Byte 1, Version Byte 2, Version Byte 0, VR0 (mapped addr. VR1 (mapped addr. VR2 (mapped addr. FDH) FEH) FCH) C504-2R AC-Step C5H 04H 01H C504-2E ES-AA-Step C5H 84H 01H C504-2E ES-BB-Step C5H 84H 04H C504-2E CA-Step C5H 84H 09H Future steppings of the C504 will typically have a different value for version byte 2. Data Sheet 43 2000-05 C504 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes min. max. TST VDD – 65 150 °C – – 0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN – 0.5 VDD + 0.5 V – Input current on any pin during overload condition – – 10 10 mA – Absolute sum of all input currents during overload condition – – |100 mA| mA – Power dissipation PDISS – 1 W – Storage temperature Voltage on VDD pins with respect to ground (VSS) Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Operating Conditions Parameter Supply voltage Ground voltage Ambient temperature SAB-C504 SAF-C504 SAK-C504 Analog reference voltage Analog ground voltage Analog input voltage CPU clock Data Sheet Symbol VDD VSS TA TA TA VAREF VAGND VAIN fCPU Limit Values min. max. 4.25 5.5 0 Unit Notes V – V – °C – 0 – 40 – 40 70 85 125 4 V – VSS – 0.1 VAGND VDD + 0.1 VSS + 0.2 VAREF V – V – 1.75 20 MHz – 44 2000-05 C504 Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C504 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C504 will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the C504. DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values min. Unit Test Condition max. Input low voltage (except EA, RESET, CTRAP) VIL SR – 0.5 0.2 VDD – 0.1 V – Input low voltage (EA) VIL1 SR – 0.5 0.2 VDD – 0.3 V – Input low voltage (RESET, CTRAP) VIL2 SR – 0.5 0.2 VDD + V 0.1 – Input high voltage (except XTAL1, RESET and VIH CTRAP) SR 0.2 VDD + 0.9 VDD + 0.5 V 11) Input high voltage to XTAL1 VIH1 SR 0.7 VDD VDD + 0.5 V – Input high voltage to RESET and CTRAP VIH2 SR 0.6 VDD VDD + 0.5 V – Output low voltage (Ports 1, 2, 3, COUT3) VOL 0.45 V IOL = 1.6 mA1) 0.45 V – – V IOL = 3.2 mA1) IOH = – 80 µA IOH = – 10 µA – V IOH = – 800 µA Output low voltage (Port 0, ALE, PSEN) Output high voltage (Ports 1, 2, 3) CC – VOL1 CC – VOH CC 2.4 0.9 VDD Output high voltage (Ports 1, 3 pins in push-pull VOH1 CC 0.9 VDD mode and COUT3) Data Sheet 45 2000-05 C504 DC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol Limit Values min. Output high voltage (Port 0 in external bus mode, ALE, PSEN) Unit Test Condition max. VOH2 CC 2.4 0.9 VDD – – V IOH = – 800 µA2) IOH = – 80 µA2) Logic 0 input current (Ports 1, 2, 3) IIL SR – 10 – 50 µA VIN = 0.45 V Logical 1-to-0 transition current (Ports 1, 2, 3) ITL SR – 65 – 650 µA VIN = 2 V ILI CIO CC – ±1 µA 0.45 < VIN < VDD CC – 10 pF fc = 1 MHz, TA = 25 °C IOV VPP SR – ±5 mA 7) 8) SR 10.9 12.1 V 11.5 V ± 5%10) Input leakage current (Port 0, EA) Pin capacitance Overload current Programming voltage (C504-2E) Power Supply Current Parameter Active mode Symbol C504-2R 24 MHz 40 MHz C504-2E 24 MHz 40 MHz Idle mode C504-2R 24 MHz 40 MHz C504-2E 24 MHz 40 MHz Power-down C504-2R mode C504-2E At EA/VPP C504-2E IDD IDD IDD IDD IDD IDD IDD IDD IPD IPD IDDP Limit Values Unit Test Condition typ.8) max.9) 27.4 43.1 35.9 57.2 mA mA 20.9 31.0 27.9 41.5 mA mA 14.6 22.4 19.3 31.3 mA mA 12.3 16.1 16.1 20.9 mA mA 1 30 µA 35 60 µA – 30 mA 4) 5) VDD = 2 … 5.5 V 3) – in prog. mode Data Sheet 46 2000-05 C504 Notes: 1) Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 2) Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port 0 = VDD; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS; VAGND = VSS; all other pins are disconnected. 4) IDD (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.; EA = Port 0 = Port 1 = RESET = VDD; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port 0 = VDD; all other pins are disconnected; 6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VDD and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 7) Not 100 % tested, guaranteed by design characterization. 8) The typical IDD values are periodically measured at TA = + 25 °C and VDD = 5 V but not 100% tested. 9) The maximum IDD values are measured under worst case conditions (TA = 0 °C or – 40 °C and VDD = 5.5 V) 10)This VPP specification is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2 = 01H must be programmed with VPP = 12 V ± 5%. 11)For the C504-2E ES-AA-step the VIH min. for EA is 0.8 VDD. Data Sheet 47 2000-05 C504 MCD03367 60 mA Ι DD max Ι DD typ Ι DD 50 Active Mode C504-2R Active Mode 40 Idle Mode 30 Idle Mode 20 10 0 0 5 10 15 20 25 30 35 MHz 40 f OSC MCD03368 60 C504-2E mA Ι DD max Ι DD typ Ι DD 50 Active Mode 40 Active Mode 30 Idle Mode 20 Idle Mode 10 0 0 Figure 23 Data Sheet 5 10 15 20 25 30 35 MHz 40 f OSC IDD Diagram 48 2000-05 C504 Power Supply Current Calculation Formulas Parameter Symbol Formula IDD typ 0.98 × fOSC + 3.9 IDD max 1.33 × fOSC + 4.0 IDD typ 0.63 × fOSC + 5.75 C504-2E IDD max 0.85 × fOSC + 7.5 IDD typ 0.51 × fOSC + 2.35 Idle mode C504-2R IDD max 0.75 × fOSC + 1.3 IDD typ 0.24 × fOSC + 6.5 C504-2E IDD max 0.30 × fOSC + 8.86 Note: fosc is the oscillator frequency in MHz. IDD values are given in mA. Active mode C504-2R A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol Limit Values min. Sample time VAIN SR tS CC Conversion cycle time tADCC CC Total unadjusted error TUE Analog input voltage CC Internal resistance of reference voltage source RAREF SR Internal resistance of analog source RASRC SR Unit Test Condition max. VAGND VAREF V – 64 × tIN ns 32 × tIN 16 × tIN 8 × tIN – 384 × tIN ns 192 × tIN 96 × tIN 48 × tIN 1) Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 42) Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 43) – ±2 LSB VSS + 0.5 V ≤ VIN ≤ VDD – 0.5 V4) – ±4 LSB VSS < VIN < VSS + 0.5 V VDD – 0.5 V < VIN < VDD4) – tADC/250 kΩ tADC in [ns] 5) 6) – 0.25 ADC input capacitance CAIN CC tS/500 – kΩ tS in [ns] 2) 6) pF 6) – 0.25 – 50 Notes see next page. Data Sheet 49 2000-05 C504 Clock Calculation Table Clock Prescaler Ratio ADCL1, 0 tADC tS tADCC ÷ 32 1 1 32 × tIN 64 × tIN 384 × tIN ÷ 16 1 0 16 × tIN 32 × tIN 192 × tIN ÷8 0 1 8 × tIN 16 × tIN 96 × tIN ÷4 0 0 4 × tIN 8 × tIN 48 × tIN Further timing conditions: tADC min = 500 ns tIN = 2/fOSC = 2 tCLCL Notes: 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time, the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion, the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Data Sheet 50 2000-05 C504 AC Characteristics for C504-L / C504-2R / C504-2E (Operating Conditions apply) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol Limit Values 12-MHz clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. max. min. max. Program Memory Characteristics CC 127 – 2tCLCL – 40 – ns CC 43 – – ns CC 30 – tCLCL – 40 tCLCL – 23 – ns SR – 233 – 4tCLCL – 100 ns CC 58 – CC 215 – SR – 150 tCLCL – 25 – ns 3tCLCL – 35 – ns – 3tCLCL – 100 ns SR 0 – 0 – ns Input instruction float after PSEN tPXIZ1) SR – 63 – tCLCL – 20 ns Address valid after PSEN tPXAV1) CC tAVIV SR tAZPL CC 75 – tCLCL – 8 – ns – 302 – 5tCLCL – 115 ns 0 – 0 – ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Address to valid instr in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX ns Notes: 1) Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers. Data Sheet 51 2000-05 C504 AC Characteristics for C504-L / C504-2R / C504-2E (cont’d) Parameter Symbol Limit Values 12-MHz clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. max. min. max. External Data Memory Characteristics tRLRH tWLWH WR pulse width tLLAX2 Address hold after ALE tRLDV RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD tLLDV ALE to valid data in tAVDV Address to valid data in tLLWL ALE to WR or RD Address valid to WR or RD tAVWL WR or RD high to ALE high tWHLH Data valid to WR transition tQVWX tQVWH Data setup before WR tWHQX Data hold after WR tRLAZ Address float after RD RD pulse width CC 400 – 6tCLCL – 100 – ns CC 400 – 6tCLCL – 100 – ns CC 114 – 2tCLCL – 53 – ns SR – 252 – 5tCLCL – 165 ns SR 0 – 0 – ns SR – 97 – 2tCLCL – 70 ns SR – 517 – 8tCLCL – 150 ns SR – 585 – 9tCLCL – 165 ns CC 200 300 3tCLCL – 50 3tCLCL + 50 ns CC 203 – 4tCLCL – 130 – ns CC 43 123 tCLCL + 40 ns CC 33 – – ns – ns – ns 0 ns CC 33 – tCLCL – 40 tCLCL – 50 7tCLCL – 150 tCLCL – 50 CC – 0 – CC 433 – External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 12 MHz Oscillator period High time Low time Rise time Fall time Data Sheet tCLCL tCHCX tCLCX tCLCH tCHCL min. max. SR 83.3 294 ns SR 20 ns SR 20 tCLCL – tCLCX tCLCL – tCHCX SR – 20 ns SR – 20 ns 52 ns 2000-05 C504 AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (Operating Conditions apply) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol Limit Values 24-MHz clock min. Unit Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz max. min. max. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX CC 43 – 2tCLCL – 40 – ns CC 17 – – ns CC 17 – tCLCL – 25 tCLCL – 25 – ns SR – 80 – 4tCLCL – 87 ns CC 22 – – ns CC 95 – tCLCL – 20 3tCLCL – 30 – ns SR – 60 – 3tCLCL – 65 ns SR 0 – 0 – ns Input instruction float after PSEN tPXIZ1) SR – 32 – tCLCL – 10 ns Address valid after PSEN tPXAV1) CC 37 tAVIV SR – tAZPL CC 0 – tCLCL – 5 – ns 148 – 5tCLCL – 60 ns – 0 – Address to valid instr in Address float to PSEN ns Notes: 1) Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers. Data Sheet 53 2000-05 C504 AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (cont’d) Parameter Symbol Limit Values 24-MHz clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max. External Data Memory Characteristics tRLRH tWLWH WR pulse width tLLAX2 Address hold after ALE tRLDV RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD tLLDV ALE to valid data in tAVDV Address to valid data in tLLWL ALE to WR or RD tAVWL Address valid to WR WR or RD high to ALE high tWHLH Data valid to WR transition tQVWX tQVWH Data setup before WR tWHQX Data hold after WR tRLAZ Address float after RD RD pulse width CC 180 – 6tCLCL – 70 – ns CC 180 – 6tCLCL – 70 – ns CC 56 – 2tCLCL – 27 – ns SR – 118 – 5tCLCL – 90 ns SR 0 – 0 – ns SR – 63 – 2tCLCL – 20 ns SR – 200 – 8tCLCL – 133 ns SR – 220 – 9tCLCL – 155 ns CC 75 175 3tCLCL – 50 3tCLCL + 50 ns CC 67 – 4tCLCL – 97 – ns CC 17 67 tCLCL + 25 ns CC 5 – – ns CC 170 – – ns CC 15 – tCLCL – 25 tCLCL – 37 7tCLCL – 122 tCLCL – 27 – ns CC – 0 – 0 ns External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 24 MHz min. Oscillator period High time Low time Rise time Fall time Data Sheet tCLCL tCHCX tCLCX tCLCH tCHCL max. SR 41.7 294 ns SR 12 ns SR 12 tCLCL – tCLCX tCLCL – tCHCX SR – 12 ns SR – 12 ns 54 ns 2000-05 C504 AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (Operating Conditions apply)1) (CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Parameter Symbol Limit Values 40-MHz clock min. Unit Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz max. min. max. Program Memory Characteristics ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX CC 35 – 2tCLCL – 15 – ns CC 10 – ns CC 10 – tCLCL – 15 – tCLCL – 15 – SR – 55 – CC 10 – CC 60 – tCLCL – 15 – 3tCLCL – 15 – SR – 25 – 3tCLCL – 50 ns SR 0 – 0 – ns ns 4tCLCL – 45 ns ns ns Input instruction float after PSEN tPXIZ2) SR – 20 – tCLCL – 5 ns Address valid after PSEN tPXAV2) CC 20 tAVIV SR – tAZPL CC – 5 – tCLCL – 5 – ns 65 – 5tCLCL – 60 ns – –5 – Address to valid instr in Address float to PSEN ns Notes: 1) SAK-C504 is not specified for 40 MHz operation. 2) Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not cause any damage to Port 0 drivers. Data Sheet 55 2000-05 C504 AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (cont’d) Parameter Symbol Limit Values 40-MHz clock Unit Variable Clock 1/tCLCL = 3.5 MHz to 40 MHz min. max. min. max. External Data Memory Characteristics tRLRH tWLWH WR pulse width tLLAX2 Address hold after ALE tRLDV RD to valid data in tRHDX Data hold after RD tRHDZ Data float after RD tLLDV ALE to valid data in tAVDV Address to valid data in tLLWL ALE to WR or RD tAVWL Address valid to WR WR or RD high to ALE high tWHLH Data valid to WR transition tQVWX tQVWH Data setup before WR tWHQX Data hold after WR tRLAZ Address float after RD RD pulse width CC 120 – 6tCLCL – 30 – ns CC 120 – 6tCLCL – 30 – ns CC 35 – 2tCLCL – 15 – ns SR – 75 – 5tCLCL – 50 ns 0 – ns SR 0 SR – 38 – 2tCLCL – 12 ns SR – 150 – 8tCLCL – 50 ns SR – 150 – 9tCLCL – 75 ns CC 60 90 3tCLCL – 15 3tCLCL + 15 ns CC 70 – 4tCLCL – 30 – ns CC 10 40 tCLCL + 15 ns CC 5 – – ns – ns – ns 0 ns CC 5 – tCLCL – 15 tCLCL – 20 7tCLCL – 50 tCLCL – 20 CC – 0 – CC 125 – External Clock Drive Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 40 MHz min. Oscillator period High time Low time Rise time Fall time Data Sheet tCLCL tCHCX tCLCX tCLCH tCHCL max. SR 25 294 ns SR 10 ns SR 10 tCLCL – tCLCX tCLCL – tCHCX SR – 10 ns SR – 10 ns 56 ns 2000-05 C504 t LHLL ALE t AVLL t PLPH t LLPL t LLIV t PLIV PSEN t AZPL t PXAV t LLAX t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Figure 24 Program Memory Read Cycle t WHLH ALE PSEN t LLDV t LLWL t RLRH RD t RLDV t AVLL t RHDZ t LLAX2 t RLAZ Port 0 t RHDX A0 - A7 from Ri or DPL Data IN A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Figure 25 Data Sheet Data Memory Read Cycle 57 2000-05 C504 t WHLH ALE PSEN t LLWL t WLWH WR t QVWX t AVLL t WHQX t LLAX2 Port 0 t QVWH A0 - A7 from Ri or DPL A0 - A7 from PCL Data OUT Instr.IN t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Figure 26 Data Memory Write Cycle t CLCL VDD- 0.5V 0.45V 0.7 VDD 0.2 VDD - 0.1 t CHCL Figure 27 Data Sheet t CLCX t CHCX MCT00033 t CLCH External Clock Cycle 58 2000-05 C504 AC Characteristics of Programming Mode (VDD = 5 V ± 10%; VPP = 11.5 V ± 5 %; TA = 25 °C ± 10 °C) Parameter Symbol Limit Values Unit min. max. 35 – ns 10 – ns 10 – ns Address hold after PALE, PROG, or PRD tPAH falling edge 10 – ns tPCS Address, data hold after PROG or PRD tPCH tPMS PMSEL setup to PROG or PRD tPMH PMSEL hold after PROG or PRD tPWW PROG pulse width tPRW PRD pulse width tPAD Address to valid data out tPRD PRD to valid data out tPDH Data hold after PRD tPDF Data float after PRD tPWH1 PROG high between two consecutive 100 – ns 0 – ns 10 – ns 10 – ns 100 – µs 100 – ns – 75 ns – 20 ns 0 – ns – 20 ns 1 – µs PRD high between two consecutive PRD tPWH2 low pulses 100 – ns tCLKP 83.3 285.7 ns tPAW tPMS PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD tPAS PALE pulse width falling edge Address, data setup to PROG or PRD PROG low pulses XTAL clock period Note: VPP = 11.5 V ± 5% is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2 = 01H must be programmed with VPP = 12 V ± 5%. Data Sheet 59 2000-05 C504 t PAW PALE t PMS H, H PMSEL1,0 t PAS Port 2 t PAH A8-A13 A0-A7 D0-D7 Port 0 PROG t PWH t PCS t PWW t PCH MCT03369 Note: PRD must be high during a programming read cycle Figure 28 Data Sheet Programming Code Byte - Write Cycle Timing 60 2000-05 C504 t PAW PALE t PMS H, H PMSEL1,0 t PAS Port 2 t PAH A8-A13 A0-A7 t PAD t PDH D0-D7 Port 0 t PRD t PDF PRD t PWH t PCS t PRW t PCH MCT03370 Note: PROG must be high during a programming read cycle Figure 29 Data Sheet Verify Code Byte - Read Cycle Timing 61 2000-05 C504 PMSEL1,0 H, L H, L Port 0 D0, D1 D0, D1 t PCH t PCS t PMS t PMH PROG t PDH t PMS t PRD t PWW t PDF t PRW t PMH PRD Note : PALE should be low during a lock bit read / write cycle Figure 30 MCT03371 Lock Bit Access Timing L, H PMSEL1,0 e. g. FD H Port 2 t PCH D0-7 Port 0 t PCS t PDH t PDF t PRD t PMS t PRW PRD t PMH MCT03372 Note : PROG must be high during a programming read cycle Figure 31 Data Sheet Version Byte Read Timing 62 2000-05 C504 ROM/OTP Verification Characteristics for C504-2R / C504-2E ROM Verification Mode 1 (C504-2R only) Parameter Symbol Address to valid data tAVQV Limit Values min. max. – 10 tCLCL P1.0 - P1.7 P2.0 - P2.5 Unit ns Address t AVQV Port 0 Data OUT Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.5 = A8 - A13 Data: P0.0 - P0.7 = D0 - D7 Inputs: P2.6, P2.7, PSEN = V SS ALE, EA = V IH RESET = V IH2 MCT03428 Figure 32 Data Sheet ROM Verification Mode 1 63 2000-05 C504 ROM/OTP Verification Mode 2 Parameter Symbol Limit Values tAWD tACY tDVA tDSA tAS 1/tCLCL ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Unit min. typ max. – 2 tCLCL – ns – 12 tCLCL – ns – – 4 tCLCL ns 8 tCLCL – – ns – tCLCL – ns 4 – 6 MHz t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.5 MCT02613 Figure 33 Data Sheet ROM Verification Mode 2 64 2000-05 C504 V DD -0.5 V 0.2 VDD +0.9 Test Points 0.2 VDD -0.1 0.45 V MCT00039 AC Inputs during testing are driven at VDD – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’. Figure 34 AC Testing: Input, Output Waveforms VOH -0.1 V VLoad +0.1 V Timing Reference Points VLoad VLoad -0.1 V VOL +0.1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20 mA Figure 35 AC Testing: Float Waveforms Figure 36 Recommended Oscillator Circuits for Crystal Oscillator Data Sheet 65 2000-05 C504 Package Information GPM05622 P-MQFP-44 (SMD) (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 66 Dimensions in mm 2000-05 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG