INFINEON SAB-C502

Microcomputer Components
8-Bit CMOS Microcontroller
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Data Sheet 08.94
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C502
8-Bit CMOS Microcontroller
C502
Preliminary
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Fully compatible to standard 8051 microcontroller
Versions for 12 / 20 MHz operating frequency
16 K × 8 ROM (SAB-C502-2R only)
256 × 8 RAM
256 × 8 XRAM (additional on-chip RAM)
Eight datapointers for indirect addressing of program and external data memory
(including XRAM)
Four 8-bit ports
Three 16 -bit Timers / Counters (Timer 2 with Up/Down Counter feature)
USART with programmable 10-bit Baudrate-Generator
Six interrupt sources, two priority levels
Programmable 15-bit Watchdog Timer
Oscillator Watchdog
Fast Power On Reset
Power Saving Modes
P-DIP-40 package and P-LCC-44 package
TA: 0 ˚C to 70 ˚C
Temperature ranges:
SAB-C502
TA: – 40 ˚C to 85 ˚C
SAF-C502
SAB-C502
Semiconductor Group
1
08.94
C502
The SAB-C502-L/C502-2R described in this document is compatible with the SAB 80C52 and can
be used for all present SAB 80C52 applications.
The SAB-C502-2R contains a non-volatile 16 K × 8 read-only program memory, a volatile 256 × 8
read/write data memory, four ports, three 16-bit timers/counters, a six source, two priority level
interrupt structure, a serial port and versatile fail save mechanisms. The SAB-C502-L/C502-2R
incorporates 256 × 8 additional on-chip RAM called XRAM. For higher performance eight
datapointers are implemented. The SAB-C502-L is identical, except that it lacks the program
memory on chip. Therefore the term SAB-C502 refers to both versions within this specification
unless otherwise noted.
Semiconductor Group
2
C502
Ordering Information
Type
Ordering
Code
Package
Description
(8-Bit CMOS microcontroller)
SAB-C502-LN
SAB-C502-LP
Q67120-C838
Q67120-C889
P-LCC-44
P-DIP-40
for external memory 12 MHz
SAB-C502-2RN
SAB-C502-2RP
Q67120-C839
Q67120-C890
P-LCC-44
P-DIP-40
with mask-programmable ROM,
12 MHz
SAB-C502-L20N
SAB-C502-L20P
Q67120-C885
Q67120-C891
P-LCC-44
P-DIP-40
for external memory 20 MHz
SAB-C502-2R20N
SAB-C502-2R20P
Q67120-C884
Q67120-C892
P-LCC-44
P-DIP-40
with mask-programmable ROM,
20 MHz
SAF-C502-LN
SAF-C502-LP
Q67120-C883
Q67120-C893
P-LCC-44
P-DIP-40
for external ROM, 12 MHz,
ext. temp. – 40 ˚C to 85 ˚C
SAF-C502-2RN
SAF-C502-2RP
Q67120-C886
Q67120-C894
P-LCC-44
P-DIP-40
with mask-programmable ROM,
12 MHz, ext. temp. – 40 ˚C to 85 ˚C
SAF-C502-L20N
SAF-C502-L20P
Q67120-C887
Q67120-C895
P-LCC-44
P-DIP-40
for external memory, 20 MHz,
ext. temp. – 40 ˚C to 85 ˚C
SAF-C502-2R20N
SAF-C502-2R20P
Q67120-C888
Q67120-C896
P-LCC-44
P-DIP-40
with mask-programmable ROM,
20 MHz, ext. temp. – 40 ˚C to 85 ˚C
Note: Extended temperature range – 40 ˚C to 110 ˚C (SAH-C502) on request.
Semiconductor Group
3
C502
Pin Configuration
(top view)
(P-LCC-44)
Semiconductor Group
4
C502
Pin Configuration
(top view)
(P-DIP-40)
Semiconductor Group
5
C502
Logic Symbol
Semiconductor Group
6
C502
Pin Definitions and Functions
Symbol
P1.7 – P1.0
Pin Number
P-LCC-44
P-DIP-40
9–2
8–1
I/O*)
Function
I
Port 1
is a bidirectional I/O port with internal pull-up
resistors. Port 1 pins that have 1s written to
them are pulled high by the internal pull-up
resistors, and in that state can be used as
inputs. As inputs, port 1 pins being externally
pulled low will source current (IIL, in the DC
characteristics) because of the internal pull-up
resistors. Port 1 also contains the timer 2 pins
as secondary function. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to
operate.
The secondary functions are assigned to the
pins of port 1, as follows:
2
3
1
2
P1.0 T2
Input to counter 2
P1.1 T2EX Capture - Reload trigger of
timer 2 / Up-Down count
*) I = Input
O = Output
Semiconductor Group
7
C502
Pin Definitions and Functions (cont’d)
Symbol
P3.0 – P3.7
Pin Number
P-LCC-44
P-DIP-40
11, 13–19
10–17
I/O*)
Function
I/O
Port 3
is a bidirectional I/O port with internal pull-up
resistors. Port 3 pins that have 1s written to
them are pulled high by the internal pull-up
resistors, and in that state can be used as
inputs. As inputs, port 3 pins being externally
pulled low will source current (IIL, in the DC
characteristics) because of the internal pull-up
resistors. Port 3 also contains the interrupt,
timer, serial port 0 and external memory strobe
pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that
function to operate.
The secondary functions are assigned to the
pins of port 3, as follows:
XTAL2
11
10
P3.0 R×D
13
11
P3.1 T×D
14
12
P3.2 INT0
15
13
P3.3 INT1
16
17
18
14
15
16
P3.4 T0
P3.5 T1
P3.6 WR
19
17
P3.7 RD
20
18
–
XTAL2
Output of the inverting oscillator amplifier
*)I = Input
O = Output
Semiconductor Group
receiver data input
(asynchronous) or data input/
output (synchronous) of serial
interface 0
transmitter data output
(asynchronous) or clock output
(synchronous) of the serial
interface 0
interrupt 0 input/timer 0 gate
control
interrupt 1 input/timer 1 gate
control
counter 0 input
counter 1 input
the write control signal latches
the data byte from port 0 into the
external data memory
the read control signal enables
the external data memory to
port 0
8
C502
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*)
Function
P-LCC-44
P-DIP-40
XTAL1
21
19
–
XTAL1
Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
To drive the device from an external clock
source, XTAL1 should be driven, while XTAL2
is left unconnected. There are no requirements
on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry
is divided down by a divide-by-two flip-flop.
Minimum and maximum high and low times as
well as rise fall times specified in the AC
characteristics must be observed.
P2.0 – P2.7
24–31
21–28
I/O
Port 2
ia a bidirectional I/O port with internal pull-up
resistors. Port 2 pins that have 1s written to
them are pulled high by the internal pull-up
resistors, and in that state can be used as
inputs. As inputs, port 2 pins being externally
pulled low will source current (IIL, in the DC
characteristics) because of the internal pull-up
resistors. Port 2 emits the high-order address
byte during fetches from external program
memory and during accesses to external data
memory that use 16-bit addresses (MOVX
@DPTR). In this application it uses strong
internal pull-up resistors when issuing 1s.
During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2
issues the contents of the P2 special function
register.
PSEN
32
29
O
The Program Store Enable
output is a control signal that enables the
external program memory to the bus during
external fetch operations. It is activated every
six oscillator periodes except during external
data memory accesses. Remains high during
internal program execution.
*) I = Input
O = Output
Semiconductor Group
9
C502
Pin Definitions and Functions (cont’d)
Symbol
Pin Number
I/O*)
Function
P-LCC-44
P-DIP-40
RESET
10
9
I
RESET
A high level on this pin for two machine cycles
while the oscillator is running resets the
device. An internal diffused resistor to VSS
permits power-on reset using only an external
capacitor to VCC.
ALE
33
30
O
The Address Latch Enable
output is used for latching the low-byte of the
address into external memory during normal
operation. It is activated every six oscillator
periodes except during an external data
memory access.
EA
35
31
I
External Access Enable
When held at high level, instructions are
fetched from the internal ROM (SAB-C502-2R
only) when the PC is less than 4000H. When
held at low level, the SAB-C502 fetches all
instructions from external program memory.
For the SAB-C502-L this pin must be tied low.
P0.0 – P0.7
43–36
39–32
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1s written to them float,
and in that state can be used as highimpedance inputs. Port 0 is also the
multiplexed low-order address and data bus
during accesses to external program or data
memory. In this application it uses strong
internal pull-up resistors when issuing 1s.
Port 0 also outputs the code bytes during
program verification in the SAB-C502-2R.
External pull-up resistors are required during
program verification.
VSS
22
20
–
Circuit ground potential
VCC
44
40
–
Supply terminal for all operating modes
N.C.
1, 12,
23, 34
–
–
No connection
*) I = Input
O = Output
Semiconductor Group
10
C502
Functional Description
The SAB-C502 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the SAB 80C52. While maintaining all architectural and operational
characteristics of the SAB 80C52 the SAB-C502 incorporates some enhancements in the Timer2
and Fail Save Mechanism Unit.
Figure 1 shows a block diagram of the SAB-C502.
Figure 1
Block Diagram of the SAB-C502
Semiconductor Group
11
C502
CPU
The SAB-C502 is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and
15 % three-byte instructions. With a 12 MHz crystal, 58 % of the instructions execute in 1.0 µs
(18 MHz : 667 ns).
Special Function Register PSW
Bit No.
Addr. D0H
MSB
7
6
5
4
3
2
1
LSB
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Function
CY
Carry Flag
AC
Auxiliary Carry Flag (for BCD operations)
F0
General Purpose Flag
RS1
0
0
1
1
RS0
0
1
0
1
PSW
Register Bank select control bits
Bank 0 selected, data address 00H - 07H
Bank 1 selected, data address 08H - 0FH
Bank 2 selected, data address 10H - 17H
Bank 3 selected, data address 18H - 1FH
OV
Overflow Flag
F1
General Purpose Flag
P
Parity Flag.
Set/cleared by hardware each instruction cycle to indicate an odd/
even number of “one” bits in the accumulator, i.e. even parity.
Reset value of PSW is 00H.
Semiconductor Group
12
C502
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the
special function register area.
The 36 special function register (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits
within the SFR area.
All SFRs are listed in table 1, table 2 and table 3. In table 1 they are organized in numeric order
of their addresses. In table 2 they are organized in groups which refer to the functional blocks of the
SAB-C502. Table 3 illustrates the contents of the SFRs.
Table 1
Special Function Register in Numeric Order of their Addresses
1):
2):
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
80H
81H
82H
83H
84H
85H
86H
87H
P0 1)
SP
DPL
DPH
reserved
reserved
WDTREL
PCON
FFH
07H
00H
00H
SCON 1)
SBUF
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
TCON 1)
TMOD
TL0
TL1
TH0
TH1
reserved
reserved
00H
000X0000B2)
00H
00H
00H
00H
00H
00H
XXH 2)
XXH 2)
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
P2 1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FFH
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
90H
91H
92H
93H
94H
95H
96H
97H
P1 1)
XPAGE
DPSEL
reserved
XCON
reserved
reserved
reserved
FFH
00H
XXXXX000B 2)
XXH 2)
F8H
XXH 2)
XXH 2)
XXH 2)
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
IE 1)
reserved
SRELL
reserved
reserved
reserved
reserved
reserved
0X000000B2)
XXH 2)
D9H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
Bit-addressable Special Function Register
X means that the value is indeterminate and the location is reserved
Semiconductor Group
13
C502
Table 1
Special Function Register in Numeric Order of their Addresses (cont’d)
1):
2):
Address
Register
Contents
after Reset
Address
Register
Contents
after Reset
B0H
B1H
B2H
B3H
B4H
B5H
N6H
B7H
P3 1)
SYSCON
reserved
reserved
reserved
reserved
reserved
reserved
FFH
XXXXXX01B 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
BAUD
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0XXXXXXXB 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
IP 1)
reserved
SRELH
reserved
reserved
reserved
reserved
reserved
X0000000B 2)
XXH 2)
XXXXXX11B 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
ACC 1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
WDCON 1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXXX0000B 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
T2CON 1)
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
00H
XXXXXXX0B 2)
00H
00H
00H
00H
XXH 2)
XXH 2)
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
B 1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
PSW 1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
Bit-addressable Special Function Register
X means that the value is indeterminate and the location is reserved
Semiconductor Group
14
C502
Table 2
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data pointer select register
Program Status Word Register
Stack Pointer
E0H1)
F0H1)
83H
82H
92H
D0H1)
81H
00H
00H
00H
00H
XXXX X000 B3)
00H
07H
Interrupt
System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8H1)
B8H1)
0X00 0000 B3)
X000 0000 B3)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80H1)
90H1)
A0H1)
B0H1)
FFH
FFH
FFH
FFH
XRAM
XPAGE
XCON
SYSCON
Page addr. reg. for XRAM
XRAM startaddress (highbyte)
XRAM control register
91H
94H
B1H
00H
F8H
XXXX XX01B3)
Serial
Channels
PCON2)
SBUF
SCON
SRELL
SRELH
BAUD
Power Control Register
Serial Channel Buffer Reg.
Serial Channel Control Reg.
Baudrate Generator Reloadvalue, Lowbyte
Baudrate Generator Reloadvalue, Highbyte
Baudrate Generator Enable Bit
87H
99H
98H1)
AAH
BAH
D8H1)
00H
XXH3)
00H
D9H
XXXX XX11B3)
0XXX XXXXB3)
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Timer 2
T2CON
T2MOD
RC2L
RC2H
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2, Reload Capture Register, Low Byte
Timer 2, Reload Capture Register, High Byte
Timer 2, High Byte
Timer 2, Low Byte
C8H1)
C9H
CAH
CBH
CDH
CCH
00H
XXXX XXX0 B3)
00H
00H
00H
00H
Watchdog
WDCON
WDTREL
Watchdog Timer Control Register
Watchdog Timer Reload Reg.
C0H1)
86H
XXXX 0000B3)
00H
Pow. Sav.
Modes
PCON2)
Power Control Register
87H
000X 0000B3)
1):
Contents
after Reset
Bit-addressable special function registers
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3): X means that the value is indeterminate and the location is reserved
2):
Semiconductor Group
15
C502
Table 3
Contents of SFR’s, SFR’s in Numeric Order
Address
Register
80H
P0
81H
SP
82H
DPL
83H
DPH
86H
WDTREL
87H
Bit 7
6
5
4
3
2
1
0
PCON
SMOD
PDS
IDLS
–
GF1
GF0
PDE
IDLE
88H
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89H
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
TL0
8BH
TL1
8CH
TH0
8DH
TH1
90H
P1
91H
XPAGE
92H
DPSEL
–
–
–
–
–
.2
.1
.0
94H
XCON
98H
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99H
SBUF
A0H
P2
A8H
IE
EA
–
ET2
ES
ET1
EX1
ET0
EX0
AAH
SRELL
bit and byte addressable
not bit addressable
– = reserved
Semiconductor Group
16
C502
Table 3
Contents of SFRs, SFRs in Numeric Order (cont’d)
Address
Register
B0H
P3
B1H
Bit 7
6
5
4
3
2
1
0
SYSCON
–
–
–
–
–
–
XMAP1
XMAP0
B8H
IP
–
PADC
PT2
PS
PT1
PX1
PT0
PX0
BAH
SRELH
C0H
WDCON
–
–
–
–
OWDS
WDTS
WDT
SWDT
C8H
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
C9H
T2MOD
–
–
–
–
–
–
–
DCEN
CAH
RC2L
CBH
RC2H
CCH
TL2
CDH
TH2
D0H
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
D8H
BAUD
BD
–
–
–
–
–
–
–
E0H
ACC
F0H
B
bit and byte addressable
not bit addressable
– = reserved
Semiconductor Group
17
C502
Timer/Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4:
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
Input Clock
Gate
C/T
M1
M0
internal
external
(max)
0
8-bit timer/counter with a
divide-by-32 prescaler
X
X
0
0
fOSC/12 × 32
fOSC/24 × 32
1
16-bit timer/counter
X
X
0
1
fOSC/12
fOSC/24
2
8-bit timer/counter with
8-bit auto-reload
X
X
1
0
fOSC/12
fOSC/24
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
X
X
1
1
fOSC/12
fOSC/24
In “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count
rate is fOSC/12.
In “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the
input clock logic.
Figure 2
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
18
C502
Timer 2
Timer 2 is a 16-bit Timer/Counter with up/down count feature. It can operate either as timer or as an
event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in
table 5.
Table 5
Timer/Counter 2 Operating Modes
T2CON
Mode
T2MOD T2CON
R×CLK
or
T×CLK
CP/
RL2
TR2
0
0
0
0
16-bit
Autoreload
16-bit
Capture
Input Clock
P1.1/
Remarks
T2EX
DCEN
EXEN
1
0
0
X
1
0
1
↓
0
0
0
0
1
1
1
1
X
X
0
1
0
1
1
X
0
X
0
1
1
X
1
↓
Baud
Rate
Generator
1
X
1
X
0
X
1
X
1
X
1
↓
off
X
X
0
X
X
X
Note: ↓ =
falling edge
Semiconductor Group
19
internal
external
(P1.0/T2)
reload upon
overflow
reload trigger
(falling edge)
Down counting
Up counting
fOSC/12
16-bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
fOSC/12
max
fOSC/24
no overflow
interrupt
request (TF2)
extra external
interrupt
(“Timer 2”)
fOSC/2
max
fOSC/24
Timer 2 stops
–
–
max
fOSC/24
C502
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. Figure 3 illustrates the block diagram of Baudrate
generation for the serial interface.
Table 6
USART Operating Modes
Mode
SCON
Baudrate
Description
SM0
SM1
0
0
0
fOSC/12
1
0
1
Timer 1/2 overflow rate
or
Baudrate Generator
2
1
0
fOSC/32 or fOSC/64
9-bit UART
11 bits are transmitted (T×D) or
received (R×D)
3
1
1
Timer 1/2 overflow rate
or
Baudrate Generator
9-bit UART
Like mode 2 except the variable
baud rate
Serial data enters and exits through R×D.
T×D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
8-bit UART
10 bits are transmitted (through T×D) or
received (R×D)
Figure 3
Block Diagram of Baud Rate Generation for Serial Interface
Semiconductor Group
20
C502
The possible baudrate can be calculated using the formulas given in table 7.
Table 7
Baudrates
Baud Rate
derived from
Interface Mode
Baudrate
Oscillator
0
2
fOSC/12
(2SMOD × fOSC)/64
Timer 1 (16-bit timer)
(8-bit timer with
8-bit autoreload)
1,3
1,3
(2SMOD × timer 1 overflow rate)/32
(2SMOD × fOSC)/(32 × 12 × (256-TH1))
Timer 2
1,3
fOSC/(32 × (65536-(RC2H, RC2L))
Baudrate
Generator
1,3
(2SMOD × fOSC)/(64 × (210-SREL))
The internal baudrate generator consists of a free running 10-bit timer with fOSC/2 input frequency.
The internal baudrate generator is selected by setting bit BD in SFR BAUD.
Semiconductor Group
21
C502
Additional On-Chip RAM - XRAM
The SAB-C502 contains another 256byte of On-Chip RAM additional to the 256bytes internal RAM.
This RAM is called XRAM (‘eXtended RAM’) in this document.
The additional ON-Chip RAM is logically located in the external data memory range. The highbyte
of the XRAM address range startaddress is programmable by SFR XCON (94H). The reset value of
XCON is 0F8H (that is, XRAM address range F800HH … F8FFH).
The contents of the XRAM is not affected by a reset. After power up the contents is undefined, while
it remains unchanged during and after reset as long as the power supply is not turned off. The
XRAM is controlled by SFR SYSCON as shown in table 8.
Table 8
Control of the XRAM
SFR SYSCON
Description
XMAP1
XMAP0
0
1
Resetvalue. Access to XRAM is disabled. When cleared it can
be set again only by a reset
0
0
XRAM enabled
1
0
XRAM enabled. The signals RD and WR are activated during
accesses to XRAM
Because of the XRAM is used in the same way as external data memory the same instruction types
must be used for accessing the XRAM. A general overview gives table 9.
Table 9
Accessing the XRAM
Instruction
using
Instruction
Remarks
DPTR
MOVX A @DPTR
MOVX @ DPTR,A
Normally the use of these instructions would use a
physically external memory. However, in the SAB-C502
the XRAM is accessed if it is enabled.
R0/R1
(page mode)
MOVX A, @Ri
MOVX@Ri,A
Normally Port 2 serves as page register. However, the
distinction, whether Port 2 is as general purpose I/O or
as “page address” is made by the external design.
Hence a special SFR XPAGE is implemented the serve
the same function for the XRAM as Port 2 for external
data memory.
Note: When writing the page address (in page mode) at Port2 the value is also written in XPAGE.
However when writing XPAGE the value at PORT2 is not changed!
The behaviour of Port0/Port2 and RD/WR during MOVX accesses is shown in table 10.
Semiconductor Group
22
MOVX
@DPTR
(DPH ≠ XCON)
DPTR within
XRAM address
range
(DPH = XCON)
XPAGE outside
XRAM addr. page
range
23
(XPAGE ≠ XCON)
MOVX
@Ri
XPAGE within
XRAM addr. page
range
(XPAGE = XCON)
EA = 1
XMAP1, XMAP0
XMAP1, XMAP0
00
10
X1
00
10
X1
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
(WR-Data only)
b) RD/WR
inactive
c) XRAM is used
a) P0/P2 ➔ Bus
(WR-Data only)
b) RD/WR
active
c) XRAM is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ Bus
(WR-Data only)
b) RD/WR
b) RD/WR
inactive
active
c) XRAM is used c) XRAM is used
a) P0/P2 ➔ Bus
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
(WR-Data only)
P2 ➔ I/O
b) RD/WR
inactive
c) XRAM is used
a) P0 ➔ Bus
(WR-Data only)
P2 ➔ I/O
b) RD/WR
active
c) XRAM is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0/P2 ➔ I/O
a) P0/P2 ➔ I/O
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
a) P0 ➔ Bus
(WR-Data only)
b) RD/WR
P2 ➔ I/O
inactive
b) RD/WR
c) XRAM is used active
c) XRAM is used
a) P0 ➔ Bus
P2 ➔ I/O
b) RD/WR
active
c) ext. memory
is used
Table 10
Behaviour of P0/P2 and RD/WR during MOVX Accesses
Semiconductor Group
DPTR outside
XRAM address
range
EA = 0
modes compatible to the standard 8051-family
C502
C502
Eight Datapointers for Faster External Bus Access
The SAB-C502 contains a set of eight 16-bit-Datapointer (DPTR) from which the actual DPTR can
be selected.
This means that the user’s program may keep up to eight 16-bit addresses resident in these
registers, but only one register at the time is selected to be the datapointer. Thus the DPTR in turn
is accessed (or selected) via indirect addressing. This indirect addressing is done through a special
function register (SFR) called DPSEL (data pointer select register, Bits 0 to 2). All instructions of the
SAB-C502 which handle the DPTR therefore affect only one of the eight pointers which is
addressed by DPSEL at that very moment.
A 3-bit field in SFR DPSEL points to the currently used DPTRx:
DPSEL
selected
DPTR
.2
.1
.0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Semiconductor Group
DPTR 0
DPTR 1
DPTR 2
DPTR 3
DPTR 4
DPTR 5
DPTR 6
DPTR 7
24
C502
Interrupt System
The SAB-C502 provides 6 interrupt sources with two priority levels. Figure 4 gives a general
overview of the interrupt sources and illustrates the request and control flags.
Figure 4
Interrupt Request Sources
Semiconductor Group
25
C502
Table 11
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
Vector
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
0003H
000BH
0013H
001BH
0023H
002BH
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 12.
Table 12
Interrupt Priority-within-Level
Interrupt Source
External Interrupt 0,
Timer 0 Interrupt,
External Interrupt 1,
Timer 1 Interrupt,
Serial Channel,
Timer 2 Interrupt,
Semiconductor Group
Priority
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
High
↓
Low
26
C502
Fail Safe Mechanisms
The SAB-C502 offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure.
1) Watchdog Timer (15 bit, WDT)
2) Oscillator Watchdog (OWD)
1) Watchdog Timer (WDT)
The Watchdog Timer in the SAB-C502 is a 15-bit timer, which is incremented by a count rate of
either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). That is, the machine clock is divided by a series of
arrangement of two prescalers, a divide-by-two and a divide-by-16 prescaler. The latter is enabled
by setting bit WDTREL.7.
Figure 5 shows the block diagram of the programmable Watchdog Timer.
Figure 5
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group
27
C502
– Starting and refreshing the WDT
Table 13 gives an overview how to start and refresh the WDT. The mentioned bits are located in
SFR WDCON.
Table 13
Starting and Refreshing the WDT
Function
Example
Remarks
Starting WD
SETB
SWDT
Cannot be stopped during active mode of the
device. WDT is halted during idle mode, power
down mode or the oscillator watchdog reset is
active.
Refreshing WD
SETB
SETB
WDT
SWDT
Double instruction sequence
(setting bit WDT and SWDT consecutively) to
increase system security.
– Watchdog reset and watchdog status flag (WDTS)
If the software fails to clear the watchdog in time, an internally generated watchdog reset is
entered at the counter state 7FFCH. The duration of the reset signal then depends on the
prescaler selection (either 8 or 128 cycles). This internal reset differs from an external one in so
far as the Watchdog Timer is not disabled and bit WDTS (SFR WDCON) is set. The WDTS is a
flip-flop, which is set by a Watchdog Timer reset and can be cleared by an external hardware
reset. Bit WDTS allows the software to examine from which source the reset was activated. The
bit WDTS can also be cleared by software.
Semiconductor Group
28
C502
2) Oscillator Watchdog (OWD)
The OWD consists of an internal RC oscillator which provides the reference frequency for the
comparison with the frequency of the on-chip oscillator.
Figure 6 shows the block diagram of the oscillator watchdog unit while table 14 shows the effect
when the OWD becomes activ/inactiv.
Note: The OWD is always enabled!
Figure 6
Functional Block Diagram of the Oscillator Watchdog
Table 14
Effects of the OWD
Conditions
Effect
fOSC < fRC/5
Switch input of internal clock system to RC oscillator output
Activating internal reset at the same time (reset sequence is clocked by
RC-oscillator).
Exception from effects of a Hardware Reset:
Watchdog Timer Status Flag, WDTS is not reset
Oscillator Watchdog Status Flag, OWDS is set
fOSC > fRC/5
Input of internal clock system is fOSC/2.
When failure condition (fOSC < fRC/5) disappears the part executes a
final reset phase of typ. 1 ms in order to allow the external oscillator to
stabilize.
Semiconductor Group
29
C502
Fast Internal Resest after Power-On
The SAB-C502 can use the oscillator watchdog unit for a fast internal resert procedure after poweron.
Normally members of the 8051 family enter their default reset state not before the on-chip oscillator
starts. The reason is that the external reset signal must be internally synchronized and processed
in order to bring the device into the correct reset state. Especially if a crystal is used the start up
timed of the oscillator is relatively long (typ. 1 ms). During this time period the pins have an
undefined state which could have severe effects e.g. to actuators connected to port pins.
In the SAB-C502 the oscillator watchdog unit avoids this situation. After power-on the oscillator
watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 µs). In the
following the watchdog circuitry detects a failure condition for the on-chip oscillator this has not yet
started (a failure is always recognized if the watchdog’s RC oscillator runs faster than the on-chip
oscillator). As long as this condition is valid the watchdog uses the RC oscillator output as a clock
source for the chip rather than the on-chip oscillator’s 16 output. This allows correct resetting of the
part and brings also all ports to the defined state.
Delay between power-on and correct reset state:
Typ:
18 µs
Max:
34 µs
Semiconductor Group
30
C502
Power Saving Modes
Two power down modes are available, the Idle Mode and the Power Down Mode.
The bits PDE, PDS and IDLE, IDLS select the Power Down mode or the idle mode, respectively. If
the Power Down mode and the idle mode are set at the same time, Power Down takes precedence.
Table 15 gives a general overview of the power saving modes.
Table 15
Entering and Leaving the Power Saving Modes
Mode
Entering
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
– enabled interrupt
– Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Double instruction sequence
Power Down
Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Oscillators are stopped. Contents
of on-chip RAM and SFR’s are
maintained (leaving Power
Down Mode means redefinition
of SFR’s contents.)
Double instruction sequence
In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC
is restored to its normal operating level, before the Power Down mode is terminated. The reset
signal that terminates the Power Down mode also restarts the oscillator. The reset should not be
activated before VCC is restored to its normal operating level and must be held active long enough
to allow the oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group
31
C502
Absolute Maximum Ratings
Ambient temperature under bias (TA) ..............................................................– 40 ˚C to + 85 ˚C
Storage temperature (TST) ...............................................................................– 65 ˚C to + 150 ˚C
Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS) ..............................................– 0.5 V to VCC + 0.5 V
Input current on any pin during overload condition..........................................– 10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..........................| 100 mA |
Power dissipation.............................................................................................TBD
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
32
C502
DC Characteristics
VCC = 5 V + 10 %, – 15 %; VSS = 0 V;
Parameter
TA = 0 to + 70 ˚C for the SAB-C502
TA = – 40 to + 85 ˚C for the SAF-C502
Symbol
Limit Values
min.
max.
Unit Test Condition
Input low voltage
(except EA, RESET)
VIL
– 0.5
0.2 VCC
– 0.1
V
–
Input low voltage (EA)
VIL1
– 0.5
0.2 VCC
– 0.3
V
–
Input low voltage (RESET)
VIL2
– 0.5
0.2 VCC
+ 0.1
V
–
Input high voltage
(except EA, RESET, XTAL1)
VIH
0.2 VCC
+ 0.9
VCC + 0.5
V
–
Input high voltage to XTAL1
VIH1
0.7 VCC
VCC + 0.5
V
Input high voltage to RESET, EA VIH2
0.6 VCC
VCC + 0.5
V
–
Output low voltage (ports 2, 3)
VOL
–
0.45
V
IOL = 1.6 mA1)
Output low voltage
(port 0, ALE, PSEN)
VOL1
–
0.45
V
IOL = 3.2 mA1)
Output high voltage (ports 2, 3)
VOH
2.4
0.9 VCC
–
–
V
IOH = – 80 µA
IOH = – 10 µA
2.4
0.9 VCC
–
–
V
IOH = – 800 µA2),
IOH = – 80 µA2)
Output high voltage (port 0 in
VOH1
external bus mode, ALE, PSEN)
Logic 0 input current
(ports 1, 2, 3)
IIL
– 10
– 50
µA
VIN = 0.45 V
Logical 1-to-0 transition current
(ports 1, 2, 3)
ITL
– 65
– 650
µA
VIN = 2 V
Input leakage current
(port 0, EA, P1)
ILI
–
±1
µA
0.45 < VIN < VCC
Pin capacitance
CIO
–
10
pF
fC = 1 MHz,
TA = 25 ˚C
Power supply current:
Active mode, 12 MHz7)
Idle mode, 12 MHz7)
Active mode, 20 MHz7)
Idle mode, 20 MHz7)
Power Down Mode
ICC
ICC
ICC
ICC
IPD
–
–
–
–
–
23.3
7.4
33.9
10.6
50
mA
mA
mA
mA
µA
VCC = 5 V,4)
VCC = 5 V,5)
VCC = 5 V,4)
VCC = 5 V,5)
VCC = 2 … 5.5 V,3)
Semiconductor Group
33
C502
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the
0.9 VCC specification when the address lines are stabilizing.
3)
IPD (Power Down Mode) is measured under following conditions:
EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected.
4)
ICC (active mode) is measured with:
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator
is used (appr. 1 mA).
5)
ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS; Port0 = VCC; all other pins are disconnected;
7)
ICC max at other frequencies is given by:
active mode: ICC max = 1.32 x fOSC + 7.48
ICC max = 0.40 x fOSC + 2.62
idle mode:
where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
Semiconductor Group
34
C502
AC Characteristics for SAB-C502-L / C502-2R
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
TA = 0 ˚C to + 70 ˚C
TA = – 40 ˚C to + 85 ˚C
for the SAB-C502
for the SAF-C502
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
12 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
127
–
2tCLCL – 40
–
ns
Address setup to ALE
tAVLL
43
–
tCLCL – 40
–
ns
Address hold after ALE
tLLAX
30
–
tCLCL – 53
–
ns
ALE low to valid instr in
tLLIV
–
233
–
4tCLCL – 100
ns
ALE to PSEN
tLLPL
58
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
215
–
3tCLCL – 35
–
ns
PSEN to valid instr in
tPLIV
–
150
–
3tCLCL – 100
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ*)
–
63
–
tCLCL – 20
ns
Address valid after PSEN
tPXAV*)
75
–
tCLCL – 8
–
ns
Address to valid instr in
tAVIV
–
302
–
5tCLCL – 115
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*) Interfacing the SAB-C502-L/C502-2R to devices with float times up to 75 ns is permissible. This limited bus
contention will not cause any damage to port 0 Drivers.
Semiconductor Group
35
C502
AC Characteristics for SAB-C502-L / C502-2R
External Data Memory Characteristics
Parameter
Symbol
Limit Values
12 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 12 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
400
–
6tCLCL – 100
–
ns
WR pulse width
tWLWH
400
–
6tCLCL – 100
–
ns
Address hold after ALE
tLLAX2
30
–
tCLCL – 53
–
ns
RD to valid data in
tRLDV
–
252
–
5tCLCL – 165
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
97
–
2tCLCL – 70
ns
ALE to valid data in
tLLDV
–
517
–
8tCLCL – 150
ns
Address to valid data in
tAVDV
–
585
–
9tCLCL – 165
ns
ALE to WR or RD
tLLWL
200
300
3tCLCL – 50
3tCLCL + 50
ns
Address valid to WR or RD
tAVWL
203
–
4tCLCL – 130
–
ns
WR or RD high to ALE high
tWHLH
43
123
tCLCL – 40
tCLCL + 40
ns
Data valid to WR transition
tQVWX
33
–
tCLCL – 50
–
ns
Data setup before WR
tQVWH
433
–
7tCLCL – 150
–
ns
Data hold after WR
tWHQX
33
–
tCLCL – 50
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
Semiconductor Group
36
C502
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min.
max.
Oscillator period
tCLCL
83.3
285.7
ns
High time
tCHCX
20
tCLCL – tCLCX
ns
Low time
tCLCX
20
tCLCL – tCHCX
ns
Rise time
tCLCH
–
20
ns
Fall time
tCHCL
–
20
ns
Semiconductor Group
37
C502
AC Characteristics for SAB-C502-L20 / C502-2R20
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
TA = 0 ˚C to + 70 ˚C
TA = – 40 ˚C to + 85 ˚C
for the SAB-C502
for the SAF-C502
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
20 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 20 MHz
min.
max.
min.
max.
ALE pulse width
tLHLL
60
–
2tCLCL – 40
–
ns
Address setup to ALE
tAVLL
20
–
tCLCL – 30
–
ns
Address hold after ALE
tLLAX
20
–
tCLCL – 30
–
ns
ALE low to valid instr in
tLLIV
–
100
–
4tCLCL – 100
ns
ALE to PSEN
tLLPL
25
–
tCLCL – 25
–
ns
PSEN pulse width
tPLPH
115
–
3tCLCL – 35
–
ns
PSEN to valid instr in
tPLIV
–
75
–
3tCLCL – 75
ns
Input instruction hold after PSEN
tPXIX
0
–
0
–
ns
Input instruction float after PSEN
tPXIZ*)
–
40
–
tCLCL – 10
ns
Address valid after PSEN
tPXAV*)
47
–
tCLCL – 3
–
ns
Address to valid instr in
tAVIV
–
190
–
5tCLCL – 60
ns
Address float to PSEN
tAZPL
0
–
0
–
ns
*) Interfacing the SAB-C502-L20/C502-2R20 to devices with float times up to 45 ns is permissible. This limited
bus contention will not cause any damage to port 0 Drivers.
Semiconductor Group
38
C502
AC Characteristics for SAB-C502-L20 / C502-2R20
External Data Memory Characteristics
Parameter
Symbol
Limit Values
18 MHz
Clock
Unit
Variable Clock
1/tCLCL = 3.5 MHz to 20 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
200
–
6tCLCL – 100
–
ns
WR pulse width
tWLWH
200
–
6tCLCL – 100
–
ns
Address hold after ALE
tLLAX2
20
–
tCLCL – 30
–
ns
RD to valid data in
tRLDV
–
155
–
5tCLCL – 95
ns
Data hold after RD
tRHDX
0
–
0
–
ns
Data float after RD
tRHDZ
–
76
–
2tCLCL – 24
ns
ALE to valid data in
tLLDV
–
250
–
8tCLCL – 150
ns
Address to valid data in
tAVDV
–
285
–
9tCLCL – 165
ns
ALE to WR or RD
tLLWL
100
200
3tCLCL – 50
3tCLCL + 50
ns
Address valid to WR or RD
tAVWL
70
–
4tCLCL – 130
–
ns
WR or RD high to ALE high
tWHLH
20
80
tCLCL – 30
tCLCL + 30
ns
Data valid to WR transition
tQVWX
5
–
tCLCL – 45
–
ns
Data setup before WR
tQVWH
200
–
7tCLCL – 150
–
ns
Data hold after WR
tWHQX
10
–
tCLCL – 40
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
Semiconductor Group
39
C502
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 20 MHz
min.
max.
Oscillator period
tCLCL
50
285.7
ns
High time
tCHCX
12
tCLCL – tCLCX
ns
Low time
tCLCX
12
tCLCL – tCHCX
ns
Rise time
tCLCH
–
12
ns
Fall time
tCHCL
–
12
ns
Figure 7
Program Memory Read Cycle
Semiconductor Group
40
C502
Figure 8
Data Memory Read Cycle
Semiconductor Group
41
C502
Figure 9
Data Memory Write Cycle
Semiconductor Group
42
C502
ROM Verification Characteristics for SAB-C502-2R
ROM Verification Mode 1
Parameter
Symbol
Limit Values
min.
max.
Unit
Address to valid data
tAVQV
–
48tCLCL
ns
ENABLE to valid data
tELQV
–
48tCLCL
ns
Data float after ENABLE
tEHQZ
0
48tCLCL
ns
Oscillator frequency
1/tCLCL
4
6
MHz
Figure 10
ROM Verification Mode 1
Semiconductor Group
43
C502
AC Inputs during testing are driven at VCC – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’. Timing
measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.
Figure 11
AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH / VOL level occurs.
IOL / IOH ≥ ± 20 mA.
Figure 12
AC Testing: Float Waveforms
Figure 13
External Clock Cycle
Semiconductor Group
44
C502
Figure 14
Recommended Oscillator Circuits
Semiconductor Group
45