INFINEON HYS72D128320GU-6-B

Data Sheet, Rev. 1.0, May. 2004
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
DDR SDRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
Edition 2004-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.0, May. 2004
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
DDR SDRAM
Memory Products
N e v e r
s t o p
t h i n k i n g .
HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B
Revision History:
Rev. 1.0
Previous Version:
Rev. 0.5
2004-05
Page
Subjects (major changes since last revision)
7
Added Non-Green Modules DDR400 & DDR333 and removed DDR266
8,12ff
editorial changes
22,23
Updated IDD currents to final
24,27,30,33
Update SPD Codes
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
5
Rev. 1.0, 2004-05
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Workstation main
memory applications
One rank 64M x 64, 64M ×72 and two ranks 128M × 64, 128M ×72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 speed grade supported
Lead-free
Table 1
Performance
Part Number Speed Code
Speed Grade
max. Clock Frequency
–5
–6
Unit
Component
DDR400B
DDR333B
—
Module
PC3200–3033
PC2700–2533
—
200
166
MHz
166
166
MHz
133
133
MHz
@CL3
@CL2.5
@CL2
1.2
fCK3
fCK2.5
fCK2
Description
The HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B, and
HYS72D128320[G/H]U–[5/6]–B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules
(UDIMM) organized as 64M ×64, 128M ×64 for non-parity and 64M ×72,128M ×72 for ECC main memory
applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of
decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD)
based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer
Data Sheet
6
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
HYS64D64300GU–5–B
PC3200U–30330–A0
one rank 512 MB DIMM
512 Mbit (×8)
HYS72D64300GU–5–B
PC3200U–30330–A0
one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320GU–5–B
PC3200U–30330–B0
two ranks 1 GB DIMM
512 Mbit (×8)
HYS72D128320GU–5–B
PC3200U–30330–B0
two ranks 1 GB ECC-DIMM
512 Mbit (×8)
HYS64D64300GU–6–B
PC2700U–25330–A0
one rank 512 MB DIMM
512 Mbit (×8)
HYS72D64300GU–6–B
PC2700U–25330–A0
one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320GU–6–B
PC2700U–25330–B0
two ranks 1 GB DIMM
512 Mbit (×8)
HYS72D128320GU–6–B
PC2700U–25330–B0
two ranks 1 GB ECC-DIMM
512 Mbit (×8)
HYS64D64300HU–5–B
PC3200U–30330–A0
one rank 512 MB DIMM
512 Mbit (×8)
HYS72D64300HU–5–B
PC3200U–30330–A0
one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320HU–5–B
PC3200U–30330–B0
two ranks 1 GB DIMM
512 Mbit (×8)
HYS72D128320HU–5–B
PC3200U–30330–B0
two ranks 1 GB ECC-DIMM
512 Mbit (×8)
HYS64D64300HU–6–B
PC2700U–25330–A0
one rank 512 MB DIMM
512 Mbit (×8)
HYS72D64300HU–6–B
PC2700U–25330–A0
one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320HU–6–B
PC2700U–25330–B0
two ranks 1 GB DIMM
512 Mbit (×8)
HYS72D128320HU–6–B
PC2700U–25330–B0
two ranks 1 GB ECC-DIMM
512 Mbit (×8)
PC3200 (CL=3.0)
PC2700 (CL=2.5)
PC3200 (CL=3.0)
PC2700 (CL=2.5)
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The
Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3
The pin configuration of the Unbuffered DDR SDRAM
DIMM is listed by function in Table 3 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
numbering is depicted in Figure 1.
Table 3
Pin Configuration of UDIMM
Pin# Name
Pin Buffer Function
Type Type
Clock Signals
137
CK0
I
SSTL
Clock Signals 2:0
NC
NC
–
16
CK1
I
SSTL
76
CK2
I
SSTL
Note: For clock net
loading see block
diagram, CK0 is
NC on 1R ×16
138
CK0
I
SSTL
NC
NC
–
17
CK1
I
SSTL
75
CK2
I
SSTL
21
CKE0
I
SSTL
Clock Enable Rank 0
111
CKE1
I
SSTL
Clock Enable Rank 1
NC
–
I
SSTL
Chip Select Rank 0
158
S1
I
SSTL
Chip Select Rank 1
NC
–
Note: 1-rank module
154
RAS
I
SSTL
Row Address Strobe
65
CAS
I
SSTL
Column Address
Strobe
63
WE
I
SSTL
Write Enable
Address Signals
59
BA0
I
SSTL
52
BA1
I
SSTL
Bank Address Bus
2:0
48
A0
I
SSTL
Address Bus 11:0
43
A1
I
SSTL
41
A2
I
SSTL
130
A3
I
SSTL
37
A4
I
SSTL
32
A5
I
SSTL
125
A6
I
SSTL
29
A7
I
SSTL
Data Sheet
I
SSTL
A9
I
SSTL
141
A10
I
SSTL
AP
I
SSTL
118
A11
I
SSTL
115
A12
I
SSTL
Address Bus 11:0
Address Signal 12
NC
NC
–
Note: 128 Mbit
module
based
A13
I
SSTL
Address Signal 13
based
NC
–
Note: Module based on
512 Mbit
or
smaller dies
Data Bus 63:0
Data Signals
Note: 2-rank module
NC
A8
27
NC
Control Signals
S0
122
Note: 1 Gbit
module
Note: 1-rank module
157
Pin Buffer Function
Type Type
167
Note: 2-rank module
NC
Pin# Name
Note: Module based on
256 Mbit or larger
dies
Complement Clock
Signals 2:0
Note: For clock net
loading see block
diagram, CK0 is
NC on 1R ×16
Pin Configuration of UDIMM (cont’d)
8
2
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
6
DQ2
I/O
SSTL
8
DQ3
I/O
SSTL
94
DQ4
I/O
SSTL
95
DQ5
I/O
SSTL
98
DQ6
I/O
SSTL
99
DQ7
I/O
SSTL
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
19
DQ10
I/O
SSTL
20
DQ11
I/O
SSTL
105
DQ12
I/O
SSTL
106
DQ13
I/O
SSTL
109
DQ14
I/O
SSTL
110
DQ15
I/O
SSTL
23
DQ16
I/O
SSTL
24
DQ17
I/O
SSTL
28
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
114
DQ20
I/O
SSTL
117
DQ21
I/O
SSTL
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 3
Table 3
Pin Configuration of UDIMM (cont’d)
Pin Configuration of UDIMM (cont’d)
Pin# Name
Pin Buffer Function
Type Type
Pin# Name
Pin Buffer Function
Type Type
121
DQ22
I/O
SSTL
178
DQ62
I/O
SSTL
123
DQ23
I/O
SSTL
179
DQ63
I/O
SSTL
33
DQ24
I/O
SSTL
44
CB0
I/O
SSTL
35
DQ25
I/O
SSTL
NC
NC
–
Note: Non-ECC module
CB1
I/O
SSTL
Check Bit 1
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
126
DQ28
I/O
SSTL
127
DQ29
I/O
SSTL
131
DQ30
I/O
SSTL
133
DQ31
I/O
SSTL
53
DQ32
I/O
SSTL
55
DQ33
I/O
SSTL
57
DQ34
I/O
SSTL
60
DQ35
I/O
SSTL
146
DQ36
I/O
SSTL
147
DQ37
I/O
SSTL
150
DQ38
I/O
SSTL
151
DQ39
I/O
SSTL
61
DQ40
I/O
SSTL
64
DQ41
I/O
SSTL
68
DQ42
I/O
SSTL
69
DQ43
I/O
SSTL
153
DQ44
I/O
SSTL
155
DQ45
I/O
SSTL
161
DQ46
I/O
SSTL
162
DQ47
I/O
SSTL
72
DQ48
I/O
SSTL
73
DQ49
I/O
79
DQ50
I/O
Data Bus 63:0
Check Bit 0
Note: ECC type module
45
Note: ECC type module
49
NC
NC
–
Note: Non-ECC module
CB2
I/O
SSTL
Check Bit 2
NC
NC
–
Note: Non-ECC module
CB3
I/O
SSTL
Check Bit 3
Note: ECC type module
51
Note: ECC type module
134
NC
NC
–
Note: Non-ECC module
CB4
I/O
SSTL
Check Bit 4
NC
NC
–
Note: Non-ECC module
CB5
I/O
SSTL
Check Bit 5
Note: ECC type module
135
Note: ECC type module
142
NC
NC
–
Note: Non-ECC module
CB6
I/O
SSTL
Check Bit 6
NC
NC
–
Note: Non-ECC module
CB7
I/O
SSTL
Check Bit 7
Note: ECC type module
144
Note: ECC type module
NC
NC
–
Note: Non-ECC module
5
DQS0
I/O
SSTL
Data Strobe Bus 7:0
SSTL
14
DQS1
I/O
SSTL
SSTL
25
DQS2
I/O
SSTL
DQS3
I/O
SSTL
Note: See
block
diagram
for
corresponding
DQ signals
80
DQ51
I/O
SSTL
36
165
DQ52
I/O
SSTL
56
DQS4
I/O
SSTL
166
DQ53
I/O
SSTL
67
DQS5
I/O
SSTL
170
DQ54
I/O
SSTL
78
DQS6
I/O
SSTL
171
DQ55
I/O
SSTL
86
DQS7
I/O
SSTL
83
DQ56
I/O
SSTL
47
DQS8
I/O
SSTL
84
DQ57
I/O
SSTL
NC
NC
–
87
DQ58
I/O
SSTL
88
DQ59
I/O
SSTL
174
DQ60
I/O
SSTL
175
DQ61
I/O
SSTL
Data Sheet
Data Bus 63:0
Data Strobe 8
Note: ECC type module
9
Note: Non-ECC module
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 3
Table 3
Pin Configuration of UDIMM (cont’d)
Pin Configuration of UDIMM (cont’d)
Pin# Name
Pin Buffer Function
Type Type
Pin# Name
Pin Buffer Function
Type Type
97
DM0
I
SSTL
GND –
Ground Plane
107
DM1
I
SSTL
119
DM2
I
SSTL
129
DM3
I
SSTL
149
DM4
I
SSTL
159
DM5
I
SSTL
169
DM6
I
SSTL
177
DM7
I
SSTL
140
DM8
I
SSTL
3,
VSS
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
O
VDD Identification
Data Mask Bus 7:0
Data Mask 8
Note: ECC type module
NC
NC
–
Note: Non-ECC module
EEPROM
92
SCL
I
CMOS Serial Bus Clock
91
SDA
I/O
OD
181
SA0
I
182
SA1
I
CMOS Slave Address Select
CMOS Bus 2:0
183
SA2
I
CMOS
Serial Bus Data
Power Supplies
1
184
VREF
AI
–
VDDSPD PWR –
15, VDDQ
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
PWR –
7,
VDD
38,
46,
70,
85,
108,
120,
148,
168
PWR –
Data Sheet
Other Pins
I/O Reference Voltage
82
EEPROM Power
Supply
VDDID
OD
Note: Pin in tristate,
indicating
VDD
and VDDQ nets
connected
on
PCB
I/O Driver Power
Supply
NC
9,
10,
71,
90,
101,
102,
103,
113,
163,
173
NC
–
Not connected
Pins not connected on
Infineon UDIMMs
Power Supply
10
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4
Abbreviations for Pin Type
Table 5
Abbreviations for Buffer Type
Abbreviation Description
Abbreviation Description
I
Standard input-only pin. Digital levels.
SSTL
Serial Stub Terminated Logic (SSTL2)
O
Output. Digital levels.
LV-CMOS
Low Voltage CMOS
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
A2 CB01/NC CB02/NC DQ32 DQ34 DQ40 CAS DQ43 DQ49 VDDQ VSS VDD VSS VSS DM0 NC DQ12 DQ14 NC DQ21 DQ22 A6 DM3 DQ31 CK0/NC A10/AP VSS DM4 DQ44 S0 DQ46 DQ52 DM6 NC DM7 SA0 -
Pin 041
Pin 045
Pin 049
Pin 053
Pin 057
Pin 061
Pin 065
Pin 069
Pin 073
Pin 077
Pin 081
Pin 085
Pin 089
Pin 093
Pin 097
Pin 101
Pin 105
Pin 109
Pin 113
Pin 117
Pin 121
Pin 125
Pin 129
Pin 133
Pin 137
Pin 141
Pin 145
Pin 149
Pin 153
Pin 157
Pin 161
Pin 165
Pin 169
Pin 173
Pin 177
Pin 181
VSS VDD VSS VDDQ -
CMOS Levels
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
- DQ01
- DQ03
- DQ08
- CK1
- DQ11
- DQ17
- DQ18
- A5
- DQS3
- DQ27
DQ10 DQ16 A9 DQ19 DQ25 DQ26 -
Pin 003
Pin 007
Pin 011
Pin 015
Pin 019
Pin 023
Pin 027
Pin 031
Pin 035
Pin 039
Pin 004
Pin 008
Pin 012
Pin 016
Pin 020
Pin 024
Pin 028
Pin 032
Pin 036
Pin 040
A1 DQS8/NC CB03/NC DQ33 BA0 WE DQS5 NC CK2 DQ50 DQ56 DQ58 SDA DQ05 DQ07 NC DM1 CKE1/NC A12/NC DM2 DQ23 DQ29 DQ30 CB5/NC VSS VDDQ DQ37 DQ39 DQ45 DM5 NC A13/NC DQ55 DQ61 DQ63 SA2 -
Pin 043
Pin 047
Pin 051
Pin 055
Pin 059
Pin 063
Pin 067
Pin 071
Pin 075
Pin 079
Pin 083
Pin 087
Pin 091
Pin 095
Pin 099
Pin 103
Pin 107
Pin 111
Pin 115
Pin 119
Pin 123
Pin 127
Pin 131
Pin 135
Pin 139
Pin 143
Pin 147
Pin 151
Pin 155
Pin 159
Pin 163
Pin 167
Pin 171
Pin 175
Pin 179
Pin 183
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 -
BACKSIDE
Pin 001
Pin 005
Pin 009
Pin 013
Pin 017
Pin 021
Pin 025
Pin 029
Pin 033
Pin 037
OD
FRONTSIDE
VREF DQS0 NC DQ09 CK1 CKE0 DQS2 A7 DQ24 A04 -
CMOS
CB00/NC
A0
BA1
DQS4
DQ35
DQ41
DQ42
DQ48
CK2
DQ51
DQ57
DQ59
SCL
VDDQ
VSS
VDDQ
VDD
VDDQ
VSS
VDD
VSS
VDDQ
VSS
VDDQ
DM8/NC
CB7/NC
VDD
VSS
VDDQ
VSS
VDDQ
VDD
VDDQ
VSS
VDDQ
VDDSPD
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038 -
DQ00
DQ02
NC
DQS1
VSS
VDDQ
VSS
VDDQ
VSS
VDD
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 -
VSS
VDD
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
DQS6
VDDID
DQS7
NC
DQ04
DQ06
NC
DQ13
DQ15
DQ20
A11
A8
DQ28
A3
CB4/NC
CK0/NC
CB06/NC
DQ36
DQ38
RAS
S1 /NC
DQ47
DQ53
DQ54
DQ60
DQ62
SA1
MPPD0030
Figure 1
Data Sheet
Pin Configuration 184-Pin, UDIMM
11
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 6
Address Format
Density
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
512 MB
64M ×64
1
64M ×8
8
13/2/11
8K
64 ms
7.8 µs
512 MB
64M ×72
1
64M ×8
8
13/2/11
8K
64 ms
7.8 µs
1 GB
128M ×64
2
64M ×8
16
13/2/12
8K
64 ms
7.8 µs
1 GB
128M ×72
2
64M ×8
18
13/2/12
8K
64 ms
7.8 µs
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
BA0 - BA1: SDRAMs D0 - D7
A0 - An: SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D7
VREF: SDRAMs D0 - D7
VSS: SDRAMs D0 - D7
Strap: see Note 1
S0
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D1
D2
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D4
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
D7
D5
SCL
SAD
SA0
SA1
SA2
VSS
E0
SCL
SAD
A0
A1
A2
WP
MPBD1011
Figure 2
Block Diagram UDIMM Raw Card A ×64, 1 Rank, ×8
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 5.1 Ω ±5 %
Data Sheet
Table 7
12
Clock Signal Loads
Clock Input
Number of SDRAMs
Note
CK0, CK0
2 SDRAMs
—
CK1, CK1
3 SDRAMs
—
CK2, CK2
3 SDRAMs
—
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
CKE1
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
BA0 - BA1: SDRAMs D0 - D15
A0 - An: SDRAMs D0 - D15
RAS: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
WE: SDRAMs D0 - D15
CKE: SDRAMs D0 - D7
CKE:SDRAMs D8 - D15
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D15
VREF: SDRAMs D0 - D15
VSS: SDRAMs D0 - D15
Strap: see Note 1
S0
S1
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D1
D2
D3
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D9
D10
D11
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SCL
SAD
SA0
SA1
SA2
VSS
Figure 3
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
D13
D14
D15
E0
MPBD1031
Block Diagram UDIMM Raw Card B (x64, 2 Ranks, x8)
Note:
Table 8
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 3 Ω ±5 %
Data Sheet
SCL
SAD
A0
A1
A2
WP
D4
13
Clock Signal Loads
Clock Input
Number of SDRAMs
Note
CK0, CK0
4 SDRAMs
—
CK1, CK1
6 SDRAMs
—
CK2, CK2
6 SDRAMs
—
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
BA0 - BA1: SDRAMs D0 - D8
A0 - An: SDRAMs D0 - D8
RAS: SDRAMs D0 - D8
CAS: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
CKE: SDRAMs D0 - D8
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D8
VREF: SDRAMs D0 - D8
VSS: SDRAMs D0 - D8
Strap: see Note 1
S0
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM1
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D1
D2
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SCL
SAD
SA0
SA1
SA2
VSS
Figure 4
SCL
SAD
A0
A1
A2
WP
D3
D4
D5
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM8
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
D7
D8
E0
MPBD1001
Block Diagram UDIMM Raw Card A ×72, 1Rank, ×8, ECC
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 5.1 Ω ±5 %
Data Sheet
Table 9
14
Clock Signal Loads
Clock Input
Number of SDRAMs
Note
CK0, CK0
3 SDRAMs
—
CK1, CK1
3 SDRAMs
—
CK2, CK2
3 SDRAMs
—
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1
A0 - An
RAS
CAS
WE
CKE0
CKE1
BA0 - BA1: SDRAMs D0 - D17
A0 - An: SDRAMs D0 - D17
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
CKE: SDRAMs D0 - D8
CKE:SDRAMs D9 - D17
SCL
SAD
SA0
SA1
SA2
VSS
E0
SCL
SAD
A0
A1
A2
WP
S0
S1
DM0/DQS9
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM1/DQS10
DQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM2/DQS11
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM3/DQS12
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
CS
CS
CS
CS
D0
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
CS
CS
CS
D9
DM4/DQS13
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM5/DQS14
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM6/DQS15
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM7/DQS16
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM8/DQS17
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D10
D11
D12
VDD: SPD EEPROM E0
VDD/VDDQ: SDRAMs D0 - D17
VREF: SDRAMs D0 - D17
VSS: SDRAMs D0 - D17
DM: SDRAMs D0 - D17
Strap: see Note 1
CS
CS
CS
CS
CS
D4
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
CS
CS
CS
CS
D13
D14
D15
D16
D17
MPBD1021
Figure 5
Block Diagram UDIMM Raw Card B ×72, 2Ranks, ×8, ECC
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 3 Ω ±5 %
Data Sheet
Table 10
15
Clock Signal Loads
Clock Input
Number of SDRAMs
Note
CK0, CK0
6 SDRAMs
—
CK1, CK1
6 SDRAMs
—
CK2, CK2
6 SDRAMs
—
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2
CK R = 120 Ω ± 5%
DIMM
Connector
DRAM3
4 DRAM Loads
DRAM4
CK
DRAM1
DRAM5
DRAM2
R = 120 Ω ± 5%
DRAM6
DIMM
Connector
Cap.
Cap.
3 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
DRAM1
DRAM5
Cap.
DRAM6
DRAM3
Cap.
2 DRAM Loads
DRAM5
Cap.
Cap.
1 DRAM Loads
R = 120 Ω ± 5%
DIMM
Connector
Cap.
R = 120 Ω ± 5%
Cap.
Cap.
DRAM5
Cap.
DIMM
Connector
DRAM1
DRAM3
Cap.
Cap.
Cap.
Cap.
Figure 6
Data Sheet
Clock Net Wiring
16
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 11
Absolute Maximum Ratings
Parameter
Symbol
Values
min.
Voltage on I/O pins relative to VSS
VIN, VOUT –0.5
typ.
max.
Unit Note/ Test
Condition
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–1
–
+3.6
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 12
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
VDD
Device Supply Voltage
VDD
Output Supply Voltage
VDDQ
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
VREF
Input Reference Voltage
Device Supply Voltage
I/O Termination Voltage
(System)
VTT
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
V
—
0.51 ×
V
4)
VDDQ
VDDQ
VREF – 0.04
VDDQ
VREF + 0.04 V
5)
VREF + 0.15
8)
0
0.49 ×
0.5 ×
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6 V
8)6)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
7)
Data Sheet
–0.3
17
—
8)
8)
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 12
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)9)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 8)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 8)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 8)
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
–5
–6
Unit
Note/ Test
Condition 1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
–0.6
+0.6
–0.6
+0.6
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.55
0.45
0.55
tCK
tCK
0.45
ns
2)3)4)5)
min. (tCL, tCH)
5
8
min. (tCL, tCH)
—
—
ns
2)3)4)5)
CL = 3.0
2)3)4)5)
6
12
7.5
12
ns
CL = 2.5
2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
Data Sheet
tDH
tDS
tIPW
0.4
—
0.45
—
ns
2)3)4)5)
0.4
—
0.45
—
ns
2)3)4)5)
2.2
—
2.2
—
ns
2)3)4)5)6)
18
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
DDR400B
DDR333
Min.
Max.
Min.
Max.
Unit
Note/ Test
Condition 1)
DQ and DM input pulse width (each
input)
tDIPW
1.75
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
Data-out low-impedance time from CK/ tLZ
CK
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.40
—
+0.45
ns
Data hold skew factor
tQHS
—
tQH
DQS input low (high) pulse width (write tDQSL,H
DQ/DQS output hold time
TSOPII
2)3)4)5)
+0.50
—
+0.55
ns
TSOPII
2)3)4)5)
tHP –tQHS
tHP –tQHS
ns
2)3)4)5)
0.35
—
0.35
—
tCK
2)3)4)5)
cycle)
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
0.6
—
0.75
—
ns
fast slew rate
Mode register set command cycle time tMRD
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
tWPRES
tWPST
tWPRE
tIS
2)3)4)5)
3)4)5)6)10)
0.7
—
0.8
—
ns
slow slew
rate
3)4)5)6)10)
Address and control input hold time
tIH
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
ns
slow slew
rate
3)4)5)6)10)
tRPRE
Read postamble
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command tRC
Read preamble
2)3)4)5)
0.60
tCK
tCK
42
70E+3
ns
2)3)4)5)
—
60
—
ns
2)3)4)5)
0.9
1.1
0.9
1.1
0.40
0.60
0.40
40
70E+3
55
2)3)4)5)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
70
—
72
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
15
—
18
—
ns
2)3)4)5)
15
—
18
—
ns
2)3)4)5)
ns
2)3)4)5)
Precharge command period
Active to Autoprecharge delay
Data Sheet
tRCD – tRASmin
19
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
DDR400B
DDR333
Min.
Max.
Min.
Max.
Unit
Note/ Test
Condition 1)
Active bank A to Active bank B
command
tRRD
10
—
12
—
ns
2)3)4)5)
Write recovery time
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)11)
Auto precharge write recovery +
precharge time
tWTR
Exit self-refresh to non-read command tXSNR
Exit self-refresh to read command
tXSRD
Average Periodic Refresh Interval
tREFI
Internal write to read command delay
2
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VIH(ac) and VIL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
21
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
HYS72D128320HU–5–B
HYS72D128320GU–5–B
Organization
HYS64D128320HU–5–B
HYS64D128320GU–5–B
Product Type
HYS72D64300HU–5–B
HYS72D64300GU–5–B
IDD Specification for HYS[64/72]D[64/128][300/320]HU–5–B
HYS64D64300HU–5–B
HYS64D64300GU–5–B
Table 14
512MB
512MB
1GB
1GB
×64
×64
×64
×72
1 Rank
1 Rank
2 Ranks
2 Ranks
–5
–5
–5
Unit
Note 1)2)
–5
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
800
920
900
1040
1110
1300
1250
1460
mA
3)
880
1040
990
1170
1190
1420
1340
1590
mA
3)4)
20
40
30
40
50
70
50
80
mA
5)
240
290
270
320
480
580
540
650
mA
3)
150
210
170
230
300
420
340
470
mA
5)
100
130
110
140
190
260
220
290
mA
5)
310
380
350
420
620
750
700
850
mA
5)
800
960
900
1080
1110
1340
1250
1500
mA
3)4)
840
1000
950
1130
1150
1380
1300
1550
mA
3)
1920
2320
2160
2610
2230
2700
2510
3030
mA
3)
23
46
26
51
46
91
52
103
mA
5)
2480
2920
2790
3290
2790
3300
3140
3710
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on
load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
22
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
HYS72D128320HU–6–B
HYS72D128320GU–6–B
Organization
HYS64D128320HU–6–B
HYS64D128320GU–6–B
Product Type
HYS72D64300HU––6–B
HYS72D64300GU–6–B
IDD Specification for HYS[64/72]D[64/128][300/320]HU–6–B
HYS64D64300HU–6–B
HYS64D64300GU–6–B
Table 15
512MB
512MB
1 GB
1 GB
×64
×72
×64
×72
1 Rank
1 Rank
2 Ranks
2 Ranks
–6
–6
–6
–6
Unit
Note 1)2)
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
720
840
810
950
1000
1170
1130
1310
mA
3)
760
920
860
1040
1040
1250
1170
1400
mA
3)4)
20
30
30
40
50
60
50
70
mA
5)
200
240
230
270
400
480
450
540
mA
5)
140
190
150
220
270
380
310
430
mA
5)
90
120
100
140
180
240
200
270
mA
5)
280
330
320
370
560
660
630
740
mA
5)
680
840
770
950
960
1170
1080
1310
mA
3)4)
720
880
810
990
1000
1210
1130
1360
mA
3)
1720
2040
1940
2300
2000
2370
2250
2660
mA
3)
23
46
26
51
46
91
52
103
mA
5)
2200
2600
2480
2930
2480
2930
2790
3290
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on
load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
[
Data Sheet
23
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Product Type
Organization
Label Code
JEDEC SPD Revision
HYS72D128320GU–5–B
SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B
HYS64D128320GU–5–B
Table 16
HYS72D64300GU–5–B
SPD Contents
HYS64D64300GU–5–B
4
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
Rev 0.0
Rev 0.0
PC3200U–30330
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
4
Number of Column Addresses
0B
0B
0B
0B
5
Number of DIMM Ranks
01
01
02
02
6
Data Width (LSB)
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
50
50
50
50
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
50
11
Error Correction Support
00
02
00
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
14
Error Checking SDRAM Width
00
08
00
08
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
18
CAS Latency
1C
1C
1C
1C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
20
20
20
20
22
Component Attributes
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
60
60
60
60
50
50
50
50
75
75
75
75
24
25
Data Sheet
24
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320GU–5–B
Organization
HYS64D128320GU–5–B
Product Type
HYS72D64300GU–5–B
SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B (cont’d)
HYS64D64300GU–5–B
Table 16
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
26
50
50
50
50
3C
3C
3C
3C
28
28
28
28
3C
3C
3C
3C
30
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
28
28
28
28
31
Module Density per Rank
80
80
80
80
32
60
60
60
60
60
60
60
60
40
40
40
40
35
tAS, tCS [ns]
tAH, tCH [ns]
tDS [ns]
tDH [ns]
40
40
40
40
36 - 40
not used
00
00
00
00
41
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
46
27
28
29
33
34
37
37
37
37
41
41
41
41
28
28
28
28
28
28
28
28
50
50
50
50
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
3E
50
3F
51
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 -8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
36
37
36
37
74
Part Number, Char 2
34
32
34
32
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
36
36
31
31
42
43
44
Data Sheet
25
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320GU–5–B
Organization
HYS64D128320GU–5–B
Product Type
HYS72D64300GU–5–B
SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B (cont’d)
HYS64D64300GU–5–B
Table 16
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
77
Part Number, Char 5
34
34
32
32
78
Part Number, Char 6
33
33
38
38
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
47
47
30
30
82
Part Number, Char 10
55
55
47
47
83
Part Number, Char 11
35
35
55
55
84
Part Number, Char 12
42
42
35
35
85
Part Number, Char 13
20
20
42
42
86
Part Number, Char 14
20
20
20
20
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
0x
0x
0x
0x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number (1 - 4)
xx
xx
xx
xx
00
00
00
00
99 - 127 not used
Data Sheet
26
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320HU–5–B
Organization
HYS64D128320HU–5–B
Product Type
HYS72D64300HU–5–B
SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B
HYS64D64300HU–5–B
Table 17
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
4
Number of Column Addresses
0B
0B
0B
0B
5
Number of DIMM Ranks
01
01
02
02
6
Data Width (LSB)
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
50
10
50
50
50
50
11
Error Correction Support
00
02
00
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
14
Error Checking SDRAM Width
00
08
00
08
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
18
CAS Latency
1C
1C
1C
1C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
20
20
20
20
22
Component Attributes
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
60
60
60
60
50
50
50
50
24
25
26
Data Sheet
75
75
75
75
50
50
50
50
27
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320HU–5–B
Organization
HYS64D128320HU–5–B
Product Type
HYS72D64300HU–5–B
SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d)
HYS64D64300HU–5–B
Table 17
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
27
3C
3C
3C
3C
28
28
28
28
3C
3C
3C
3C
30
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
28
28
28
28
31
Module Density per Rank
80
80
80
80
32
60
60
60
60
60
60
60
60
40
40
40
40
35
tAS, tCS [ns]
tAH, tCH [ns]
tDS [ns]
tDH [ns]
40
40
40
40
36 - 40
not used
00
00
00
00
41
37
37
37
37
41
41
41
41
28
28
28
28
28
28
28
28
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
50
50
50
50
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
3E
50
3F
51
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
36
37
36
37
74
Part Number, Char 2
34
32
34
32
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
36
36
31
31
77
Part Number, Char 5
34
34
32
32
28
29
33
34
42
43
44
Data Sheet
28
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320HU–5–B
Organization
HYS64D128320HU–5–B
Product Type
HYS72D64300HU–5–B
SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d)
HYS64D64300HU–5–B
Table 17
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
78
Part Number, Char 6
33
33
38
38
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
48
48
30
30
82
Part Number, Char 10
55
55
48
48
83
Part Number, Char 11
35
35
55
55
84
Part Number, Char 12
42
42
35
35
85
Part Number, Char 13
20
20
42
42
86
Part Number, Char 14
20
20
20
20
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
0x
0x
0x
0x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number (1 - 4)
xx
xx
xx
xx
00
00
00
00
99 - 127 not used
Data Sheet
29
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320GU–6–B
Organization
HYS64D128320GU–6–B
Product Type
HYS72D64300GU–6–B
SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B
HYS64D64300GU–6–B
Table 18
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
4
Number of Column Addresses
0B
0B
0B
0B
5
Number of DIMM Ranks
01
01
02
02
6
Data Width (LSB)
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
60
60
60
60
70
70
70
70
11
Error Correction Support
00
02
00
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
14
Error Checking SDRAM Width
00
08
00
08
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
18
CAS Latency
0C
0C
0C
0C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
20
20
20
20
22
Component Attributes
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
75
75
75
75
70
70
70
70
00
00
00
00
00
00
00
00
10
24
25
26
Data Sheet
30
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320GU–6–B
Organization
HYS64D128320GU–6–B
Product Type
HYS72D64300GU–6–B
SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d)
HYS64D64300GU–6–B
Table 18
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
27
48
48
48
48
30
30
30
30
48
48
48
48
30
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
2A
2A
2A
2A
31
Module Density per Rank
80
80
80
80
32
75
75
75
75
75
75
75
75
45
45
45
45
35
tAS, tCS [ns]
tAH, tCH [ns]
tDS [ns]
tDH [ns]
45
45
45
45
36 - 40
not used
00
00
00
00
41
3C
3C
3C
3C
48
48
48
48
30
30
30
30
2D
2D
2D
2D
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
55
55
55
55
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
42
54
43
55
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
36
37
36
37
74
Part Number, Char 2
34
32
34
32
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
36
36
31
31
77
Part Number, Char 5
34
34
32
32
28
29
33
34
42
43
44
Data Sheet
31
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320GU–6–B
Organization
HYS64D128320GU–6–B
Product Type
HYS72D64300GU–6–B
SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d)
HYS64D64300GU–6–B
Table 18
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
78
Part Number, Char 6
33
33
38
38
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
47
47
30
30
82
Part Number, Char 10
55
55
47
47
83
Part Number, Char 11
36
36
55
55
84
Part Number, Char 12
42
42
36
36
85
Part Number, Char 13
20
20
42
42
86
Part Number, Char 14
20
20
20
20
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
0x
0x
0x
0x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number (1 - 4)
xx
xx
xx
xx
00
00
00
00
99 - 127 not used
Data Sheet
32
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320HU–6–B
Organization
HYS64D128320HU–6–B
Product Type
HYS72D64300HU–6–B
SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B
HYS64D64300HU–6–B
Table 19
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
4
Number of Column Addresses
0B
0B
0B
0B
5
Number of DIMM Ranks
01
01
02
02
6
Data Width (LSB)
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
60
60
60
60
10
70
70
70
70
11
Error Correction Support
00
02
00
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM Width
08
08
08
08
14
Error Checking SDRAM Width
00
08
00
08
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
18
CAS Latency
0C
0C
0C
0C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
20
20
20
20
22
Component Attributes
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
75
75
75
75
70
70
70
70
24
25
26
Data Sheet
00
00
00
00
00
00
00
00
33
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320HU–6–B
Organization
HYS64D128320HU–6–B
Product Type
HYS72D64300HU–6–B
SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B
HYS64D64300HU–6–B
Table 19
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
27
48
48
48
48
30
30
30
30
48
48
48
48
30
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
2A
2A
2A
2A
31
Module Density per Rank
80
80
80
80
32
75
75
75
75
75
75
75
75
45
45
45
45
35
tAS, tCS [ns]
tAH, tCH [ns]
tDS [ns]
tDH [ns]
45
45
45
45
36 - 40
not used
00
00
00
00
41
3C
3C
3C
3C
48
48
48
48
30
30
30
30
2D
2D
2D
2D
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
55
55
55
55
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
42
54
43
55
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
36
37
36
37
74
Part Number, Char 2
34
32
34
32
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
36
36
31
31
77
Part Number, Char 5
34
34
32
32
28
29
33
34
42
43
44
Data Sheet
34
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Label Code
HYS72D128320HU–6–B
Organization
HYS64D128320HU–6–B
Product Type
HYS72D64300HU–6–B
SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B
HYS64D64300HU–6–B
Table 19
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8)
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
78
Part Number, Char 6
33
33
38
38
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
48
48
30
30
82
Part Number, Char 10
55
55
48
48
83
Part Number, Char 11
36
36
55
55
84
Part Number, Char 12
42
42
36
36
85
Part Number, Char 13
20
20
42
42
86
Part Number, Char 14
20
20
20
20
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
0x
0x
0x
0x
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number (1 - 4)
xx
xx
xx
xx
00
00
00
00
99 - 127 not used
Data Sheet
35
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
5
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
31.75 ±0.13
4 ±0.1
A
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-32
Figure 7
Data Sheet
Raw Card A DDR UDIMM HYS64D64300HU-[5/6/7]-B (1 Rank Module)
36
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
2.7 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 8
Data Sheet
L-DIM-184-30
Raw Card A DDR UDIMM HYS72D64300HU-[5/6/7F]-B (1 Rank Module)
37
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
31.75 ±0.13
4 ±0.1
A
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
L-DIM-184-33
Figure 9
Data Sheet
Raw Card B DDR UDIMM HYS64D128320HU-[5/6/7]-B (2 Ranks Module)
38
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
31.75 ±0.13
4 ±0.1
1)
1
2.36 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-31
Figure 10
Data Sheet
Raw Card B DDR UDIMM HYS72D128320HU-[5/6/7/-B (2 Rank Module)
39
Rev. 1.0, 2004-05
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