INFINEON HYS64D32020GDL-7-B

D a t a S h e e t , V 1 . 2 , A u g . 2 00 3
H Y S 64 D 3 2 0 2 0 G D L – [ 5 / 6 / 7 / 8 ] – B
H Y S 64 D 1 6 0 0 x G D L – [ 6 / 7 / 8 ] – B
200- Pi n Small Outli ne Dual -In- Line Memor y Modules
S O -D I M M
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2003-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
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characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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Due to technical requirements components may contain dangerous substances. For information on the types in
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Infineon Technologies Components may only be used in life-support devices or systems with the express written
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be endangered.
D a t a S h e e t , V 1 . 2 , A u g . 2 00 3
H Y S 64 D 3 2 0 2 0 G D L – [ 5 / 6 / 7 / 8 ] – B
H Y S 64 D 1 6 0 0 x G D L – [ 6 / 7 / 8 ] – B
200- Pi n Small Outli ne Dual -In- Line Memor y Modules
S O -D I M M
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS64D32020GDL–[5/6/7/8]–B, HYS64D1600xGDL–[6/7/8]–B,
Revision History:
V1.2
2003-08
Previous Version:
V1.1
2003-03
Page
Subjects (major changes since last revision)
all
New data sheet template
6,7,26,16
Added Part number HYS64D32020GDL-5-B including SPD and IDD
7
Updated Complinance Code
18
Added DDR400B AC characteristics added
16,17
Corrected IDD 256MB for speed sort –6 & –7
29
Updated Package Outlines
18
Removed tbd from Table 11 for DDR400B tIPW & tDIPW
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Template: mp_a4_v2.0_2003-06-06.fm
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Sheet
5
V1.2, 2003-08
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
HYS64D32020GDL–[5/6/7/8]–B
HYS64D1600xGDL–[6/7/8]–B
Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
One rank 16M × 64 and two bank 32M × 64 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
Single +2.5 V (± 0.2 V) power supply
Built with 256 Mbit DDR SDRAMs organised as × 16 in P–TSOPII–66–1 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
Jedec standard form factor: 67.60 mm × 31.75 mm × 3.00 / 3.80 mm
Jedec standard reference layout Raw Cards A and C
DDR400 speed grade supported
Gold plated contacts
Table 1
Performance
Part Number Speed Code
–5
–6
–7
–8
Unit
Speed Grade
Component
DDR400B
DDR333B
DDR266A
DDR200
—
Module
PC3200–3033 PC2700–2533 PC2100–2033 PC1600–2022 —
fCK3 200
@CL2.5 fCK2.5 166
@CL2 fCK2 133
max. Clock Frequency @CL3
1.2
166
—
—
MHz
166
143
125
MHz
133
133
100
MHz
Description
The HYS64D32020GDL–[5/6/7/8]–B and HYS64D1600xGDL–[6/7/8]–B are industry standard 200-Pin Small
Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 32M × 64 and 16M × 64. The memory array is
designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are
mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the
2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
6
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
PC3200S–3033–0–A1
two ranks 256 MB SO-DIMM
256 Mbit (× 16)
HYS64D16000GDL–6–B
PC2700S–2533–0–C1
one rank 128 MB SO-DIMM
256 MBit (× 16)
HYS64D16001GDL–6–B
PC2700S–2533–0–C1
one rank 128 MB SO-DIMM
256 MBit (× 16)
HYS64D32020GDL–6–B
PC2700S–2533–0–A1
two ranks 256 MB SO-DIMM
256 MBit (× 16)
HYS64D16000GDL–7–B
PC2100S–2033–0–C1
one rank 128 MB SO-DIMM
256 MBit (× 16)
HYS64D16001GDL–7–B
PC2100S–2033–0–C1
one rank 128 MB SO-DIMM
256 MBit (× 16)
HYS64D32020GDL–7–B
PC2100S–2033–0–A1
two ranks 256 MB SO-DIMM
256 MBit (× 16)
HYS64D16000GDL–8–B
PC1600S–2022–0–C1
one rank 128 MB SO-DIMM
256 MBit (× 16)
HYS64D32020GDL–8–B
PC1600S–2022–0–A1
two ranks 256 MB SO-DIMM
256 MBit (× 16)
PC3200 (CL=3)
HYS64D32020GDL-5-B
PC2700 (CL=2.5)
PC2100 (CL=2)
PC1600 (CL=2)
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3
Pin Definitions and Functions
Symbol
Type1)
Function
A0 - A12
I
Address Inputs
BA0, BA1
I
Bank Address
DQ0 - DQ63
I/O
Data Input/Output
RAS, CAS, WE
I
Command Input
CKE0 - CKE1
I
Clock Enable
DQS0 - DQS7
I/O
SDRAM Data Strobe
CK0 - CK1,
I
SDRAM Clock (true signal)
CK0 - CK1
I
SDRAM Clock (complementary signal)
DM0 - DM8
I
Data Mask
I
Chip Select
VDD
PWR
Power (+ 2.5 V)
VSS
GND
Ground
VDDQ
PWR
I/O Driver power supply
VDDID
PWR
VDD Indentification flag
VREF
AI
I/O reference supply
VDDSPD
PWR
Serial EEPROM power supply
SCL
I
Serial bus clock
SDA
I/O
Serial bus data line
SA0 - SA2
I
slave address select
NC
NC
Not Connected
NU
NU
Not Usable, reserved for future use
S0, S1
2)
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected; NU: Not Usable
2) CKE1 and S1 are used on two bank modules only
Table 4
Density
Address Format
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
128MB
16M × 64
1
16M × 16
4
13/2/9
8K
64 ms
7.8 µs
256MB
32M × 64
2
16M × 16
8
13/2/9
8K
64 ms
7.8 µs
Data Sheet
8
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Pin Configuration
Table 5
Pin Configuration
Front side
Back side
Front side
Back side
Front side
Back side
Pin #
Symbol
Pin #
Symbol
Pin #
Symbol
Pin #
Symbol
Pin #
Symbol
Pin #
Symbol
1
2
DQ26
66
DQ30
133
DQS4
134
DM4
4
VREF
VSS
65
3
VREF
VSS
67
DQ27
68
DQ31
135
DQ34
136
DQ38
5
DQ0
6
DQ4
69
VDD
70
VDD
137
VSS
138
VSS
7
DQ1
8
DQ5
71
(CB0)
72
(CB4)
139
DQ35
140
DQ39
9
VDD
10
VDD
73
(CB1)
74
(CB5)
141
DQ40
142
DQ44
11
DQS0
12
DM0
75
VSS
76
VSS
143
VDD
144
VDD
13
DQ2
14
DQ6
77
(DQS8)
78
(DM8)
145
DQ41
146
DQ45
15
VSS
16
VSS
79
(CB2)
80
(CB6)
147
DQS5
148
DM5
17
DQ3
18
DQ7
81
VDD
82
VDD
149
VSS
150
VSS
19
DQ8
20
DQ12
83
(CB3)
84
(CB7)
151
DQ42
152
DQ46
21
VDD
22
VDD
85
DU
86
DU
153
DQ43
154
DQ47
23
DQ9
24
DQ13
87
VSS
88
155
VDD
DQS1
26
DM1
89
(CK2)
90
158
CK1
27
VSS
28
VSS
91
(CK2)
92
160
CK1
29
DQ10
30
DQ14
93
VDD
94
161
VDD
VDD
VSS
VSS
156
25
VSS
VSS
VDD
VDD
162
VSS
31
DQ11
32
DQ15
95
CKE1
96
CKE0
163
DQ48
164
DQ52
33
VDD
34
97
DU
98
DU
165
DQ49
166
DQ53
35
CK0
36
99
A12
100
A11
167
VDD
168
VDD
37
CK0
38
101
A9
102
A8
169
DQS6
170
DM6
39
VSS
VDD
VDD
VSS
VSS
103
VSS
104
VSS
171
DQ50
172
DQ54
105
A7
106
A6
173
VSS
174
VSS
107
A5
108
A4
175
DQ51
176
DQ55
40
Key
157
159
41
DQ16
42
DQ20
109
A3
110
A2
177
DQ56
178
DQ60
43
DQ17
44
DQ21
111
A1
112
A0
179
VDD
180
VDD
45
VDD
46
VDD
113
VDD
114
VDD
181
DQ57
182
DQ61
47
DQS2
48
DM2
115
A10/AP
116
BA1
183
DQS7
184
DM7
49
DQ18
50
DQ22
117
BA0
118
RAS
185
VSS
186
VSS
51
VSS
52
VSS
119
WE
120
CAS
187
DQ58
188
DQ62
53
DQ19
54
DQ23
121
S0
122
S1
189
DQ59
190
DQ63
55
DQ24
56
DQ28
123
DU
124
DU
191
VDD
192
VDD
57
VDD
58
VDD
125
VSS
126
VSS
193
SDA
194
SA0
59
DQ25
60
DQ29
127
DQ32
128
DQ36
195
SCL
196
SA1
61
DQS3
62
DM3
129
DQ33
130
DQ37
197
198
SA2
63
VSS
64
VSS
131
VDD
132
VDD
199
VDDSPD
VDDID
200
DU
Data Sheet
9
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
pin 199
pin 39
pin 41
pin 40
pin 42
front side
pin 200
pin 1
pin 2
Pin Configuration
back side
Figure 1
Data Sheet
Pin Configuration
10
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Pin Configuration
CS 0
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DM1
DQS2
DM2
DQS3
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDQS
UDM
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D0
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS6
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
CS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D1
D2
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM6
UDQS
UDM
DM3
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
LDQS
LDM
DQS0
DM0
D3
Unless otherwise noted, resistor values are 22 Ohm with +/- 5% tolerance
Serial Presence Detect (SPD)
BA0-BA1
SDRAMS D0-D3
A0-AN
SDRAMS D0-D3
RAS
SDRAMS D0-D3
CAS
SDRAMS D0-D3
WE
SDRAMS D0-D3
CKE0
SDRAMS D0-D3
CKE1
N.C.
SCL
SA0
A0
SA1
A1
SA2
A2
SDA
WP
CK0
CK 0
V DD SPD
SPD
CK1
V REF
SDRAMS D0-D3
CK 1
V DD
SDRAMS D0-D3
V DD and V DD Q
V SS
SDRAMS D0-D3, SPD
V DD ID
Figure 2
Data Sheet
2 loads
2 loads
Note: DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
V DD ID strap connections:
Strap out (open): VDD = VDD Q
Block Diagram - One Rank 16M × 64 DDR SDRAM SO-DIMM HYS64D1600xGDL–[6/7/8]–B
11
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Pin Configuration
CS1
CS0
CS
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDM
LDQS
LDM
I/O 0
I/O 0
I/O 1
I/O 1
I/O 2
I/O 2
I/O 3
I/O 3
I/O 4
I/O 4
D0
I/O 5
I/O 5
I/O 6
I/O 6
I/O 7
I/O 7
UDQS
UDM
UDQS
UDM
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 10
I/O 11
I/O 11
I/O 12
I/O 12
I/O 13
I/O 13
I/O 14
I/O 14
I/O 15
I/O 15
CS
DQS2
DM2
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D4
CS
LDQS
LDQS
LDM
LDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5 D1
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
D5
I/O 5
I/O 6
I/O 7
UDQS
UDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS3
DM3
CS
CS
LDQS
CS
LDQS
LDM
LDQS
LDM
I/O 0
I/O 0
I/O 1
I/O 1
I/O 2
I/O 2
I/O 3
I/O 3
I/O 4
I/O 4
D2
I/O 5
I/O 6
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 7
UDQS
UDM
UDQS
UDM
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 10
I/O 11
I/O 11
I/O 12
I/O 12
I/O 13
I/O 13
I/O 14
I/O 14
I/O 15
I/O 15
CS
LDQS
LDQS
LDM
LDM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5 D3
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS7
DM7
D6
I/O 6
CS
DQS6
DM6
I/O 5
D7
Serial Presence Detect (SPD)
SCL
SA0
A0
SA1
A1
SA2
A2
SDA
WP
Unless otherwise noted, resistor values are 22 Ohm with +/- 5% tolerance
BA0-BA1
SDRAMS D0-D7
A0-AN
SDRAMS D0-D7
RAS
SDRAMS D0-D7
CK0
CK 0
CAS
SDRAMS D0-D7
CK1
WE
SDRAMS D0-D7
CK 1
CKE0
SDRAMS D0-D3
CKE1
SDRAMS D4-D7
V DD SPD
SPD
V REF
SDRAMS D0-D7
V DD
SDRAMS D0-D7
V SS
SDRAMS D0-D7, SPD
4 loads
4 loads
Note: DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
V DD ID strap connections:
V DD and V DD Q
Strap out (open): VDD = VDD Q
V DD ID
Figure 3
Data Sheet
Block Diagram - Two Rank 32M × 64 DDR SDRAM SO-DIMM HYS64D32020GDL–[5/6/7/8]–B
12
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6
Absolute Maximum Ratings
Parameter
Symbol
Values
min.
Voltage on I/O pins relative to VSS
VIN, VOUT –0.5
typ.
max.
Unit Note/ Test
Condition
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–1
–
+3.6
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 7
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤166 MHz
fCK > 166 MHz 2)
fCK ≤166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
V
—
0.51 ×
V
4)
VDDQ
VDDQ
VREF – 0.04
VDDQ
VREF + 0.04 V
5)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
8)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6 V
8)6)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
7)
VDD
Device Supply Voltage
VDD
Output Supply Voltage
VDDQ
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
VREF
Input Reference Voltage
Device Supply Voltage
I/O Termination Voltage
(System)
Data Sheet
VTT
0
0.49 ×
0.5 ×
13
—
8)
8)
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 7
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤VIN ≤VDD;
All other pins not under test
= 0 V 8)9)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤VOUT ≤VDDQ 8)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 8)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 8)
1) 0 ° C ≤TA ≤70 ° C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Data Sheet
14
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
3.2
Current Specification and Conditions
Table 8
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIH,MIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
15
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
HYS64D32020GDL-6-B
HYS64D32020GDL-5-B
IDD Specification
HYS64D16000GDL-6-B
HYS64D16001GDL-6-B
Part Number & Organization
Table 9
128MB
256MB
256MB
× 64
× 64
× 64
1 Rank
2 Ranks
2 Ranks
–6
–6
–5
Unit
Note1)2)
Symbol
typ.
max.
typ.
max.
typ.
max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
352
460
604
740
640
776
mA
3)
416
500
668
780
700
836
mA
3)4)
24
36
48
72
48
72
mA
5)
180
220
360
440
368
448
mA
5)
99
112
198
224
192
272
mA
5)
72
84
144
168
136
192
mA
5)
252
280
504
560
480
592
mA
5)
496
640
748
920
800
996
mA
3)4)
564
660
816
940
840
1016
mA
3)
574
760
826
1040
860
1076
mA
3)
5
5
10
10
10
10
mA
5)
872
1140
1280
1536
1280
1536
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending
on load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
16
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
HYS64D32020GDL-8-B
HYS64D16000GDL-7-B
HYS64D16001GDL-7-B
HYS64D32020GDL-7-B
IDD Specification
HYS64D16000GDL-8-B
Part Number & Organization
Table 10
128MB
256MB
128MB
256MB
× 64
× 64
× 64
× 64
1 Rank
2 Ranks
1 Rank
2 Ranks
–8
–8
–7
–7
Unit
Note1)2)
3)
3)4)
Symbol
typ.
max.
typ.
max.
typ.
max.
typ.
max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
288
380
456
580
308
420
516
660
mA
5)
332
420
500
620
376
460
584
700
mA
5)
20
28
40
56
22
32
44
64
mA
5)
120
140
240
280
140
160
280
320
mA
5)
72
88
144
176
376
100
752
200
mA
5)
52
64
104
128
60
72
120
144
mA
3)4)
168
200
336
400
208
240
416
480
mA
3)
356
440
524
640
428
520
636
760
mA
3)
384
480
552
680
476
560
684
800
mA
5)
504.8
680
672.8
880
540
720
748
960
mA
3)4)
6
6
12
12
6
6
12
12
mA
5)
632
880
800
1080
720
940
928
1180
mA
3)4)
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on
load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
17
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
4
AC Characteristics
Table 11
AC Timing - Absolute Specifications –6/–5
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
–6
–5
DDR333
DDR400B
Unit
Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)
–0.6
+0.6
–0.5
+0.5
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
ns
2)3)4)5)
min. (tCL, tCH)
6
12
min. (tCL, tCH)
5
12
ns
2)3)4)5)
CL = 3.0
2)3)4)5)
6
12
6
12
ns
CL = 2.5
2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0
2)3)4)5)
tDH
tDS
tIPW
0.45
—
0.4
—
ns
2)3)4)5)
0.45
—
0.4
—
ns
2)3)4)5)
2.2
—
2.2
—
ns
2)3)4)5)6)
DQ and DM input pulse width (each
input)
tDIPW
1.75
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
Data-out low-impedance time from CK/ tLZ
CK
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.45
—
+0.40
ns
Data hold skew factor
tQHS
—
tQH
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
0.35
—
0.35
—
tCK
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ/DQS output hold time
DQS input low (high) pulse width (write tDQSL,H
cycle)
TSOPII
2)3)4)5)
+0.55
—
+0.50
ns
TSOPII
2)3)4)5)
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
Mode register set command cycle time tMRD
Write preamble setup time
Write postamble
Write preamble
Data Sheet
tWPRES
tWPST
tWPRE
18
2)3)4)5)
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
Table 11
AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Address and control input setup time
Symbol
tIS
–6
–5
DDR333
DDR400B
Min.
Max.
Min.
Max.
0.75
—
0.6
—
Unit
ns
Note/ Test
Condition 1)
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew
rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew
rate
3)4)5)6)10)
tRPRE
Read postamble
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command tRC
Read preamble
2)3)4)5)
0.60
tCK
tCK
40
70E+3
ns
2)3)4)5)
—
55
—
ns
2)3)4)5)
0.9
1.1
0.9
1.1
0.40
0.60
0.40
42
70E+3
60
2)3)4)5)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
72
—
65
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
tRRD
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
12
—
10
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)11)
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
tWTR
Exit self-refresh to non-read command tXSNR
Exit self-refresh to read command
tXSRD
Average Periodic Refresh Interval
tREFI
Internal write to read command delay
1
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)12)
1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Data Sheet
19
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 12
AC Timing - Absolute Specifications –8/–7
Parameter
Symbol
–8
–7
DDR200
DDR266A
Min Max.
.
Min.
Max.
Unit Note/
Test Condition 1)
DQ output access time from CK/CK
tAC
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
DQS output access time from CK/CK
tDQSCK
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)
CK high-level width
tCH
0.4
5
0.55
0.45
0.55
tCK
2)3)4)5)
CK low-level width
tCL
0.4
5
0.55
0.45
0.55
tCK
2)3)4)5)
Clock Half Period
tHP
tCK3
tCK2.5
tCK2
tCK1.5
tDH
tDS
tIPW
min. (tCL, tCH)
ns
2)3)4)5)
min. (tCL, tCH)
8
12
7
12
ns
CL = 3.0 2)3)4)5)
8
12
7
12
ns
CL = 2.5 2)3)4)5)
10
12
7.5
12
ns
CL = 2.0 2)3)4)5)
10
12
—
—
ns
CL = 1.5 2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
0.6
—
0.5
—
ns
2)3)4)5)
2.5
—
2.2
—
ns
2)3)4)5)6)
2.0
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from CK/ tHZ
CK
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Data-out low-impedance time from CK/
CK
tLZ
–
0.8
+0.8
–0.75
+0.75
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.7
5
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.6
—
+0.5
ns
2)3)4)5)
Data hold skew factor
tQHS
tQH
—
1.0
—
0.75
ns
2)3)4)5)
tHP –
tQHS
—
ns
2)3)4)5)
0.35
—
tCK
2)3)4)5)
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ and DM input pulse width (each
input)
DQ/DQS output hold time
tDIPW
tHP —
–
tQH
S
DQS input low (high) pulse width (write
cycle)
Data Sheet
tDQSL,H 0.3 —
5
20
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
Table 12
AC Timing - Absolute Specifications –8/–7 (cont’d)
Parameter
Symbol
–8
–7
DDR200
DDR266A
Unit Note/
Test Condition 1)
Min Max.
.
Min.
Max.
DQS falling edge to CK setup time (write tDSS
cycle)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command cycle time
tMRD
2
—
tWPRES 0
—
tWPST
0.4 0.60
2
—
tCK
2)3)4)5)
0
—
ns
2)3)4)5)8)
0.40
0.60
tCK
2)3)4)5)9)
Write preamble setup time
Write postamble
0
Write preamble
tWPRE
0.2
5
—
0.25
—
tCK
2)3)4)5)
Address and control input setup time
tIS
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
1.1
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read preamble setup time
Read postamble
tRPRE
tRPRE1.5
tRPRES
tRPST
tRAS
Active to Active/Auto-refresh command tRC
Active to Precharge command
CL > 1.5 2)3)4)5)
NA
tCK
tCK
—
NA
ns
2)3)4)5)12)
0.4
0
0.60
0.40
0.60
tCK
2)3)4)5)
50
120E+3
45
120E+3 ns
2)3)4)5)
70
—
65
—
ns
2)3)4)5)
0.9
1.1
0.9
0.9
1.1
1.5
1.1
CL = 1.5 2)3)4)5)11)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
80
—
75
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
tRRD
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
20
—
20
—
ns
2)3)4)5)
15
—
15
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
(twr/tCK) + (trp/tCK)
tCK
2)3)4)5)13)
tWTR
tWTR1.5
tXSNR
tXSRD
tREFI
1
—
1
—
CL > 1.5 2)3)4)5)
2
—
—
—
tCK
tCK
80
—
75
—
ns
2)3)4)5)
200 —
200
—
tCK
2)3)4)5)
—
—
7.8
µs
2)3)4)5)14)
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
Data Sheet
7.8
21
CL = 1.5 2)3)4)5)
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
1) 0 ° C ≤TA ≤70 ° C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VOH(ac) and VOL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) tRPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
22
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
SPD Contents
HYS64D16000GDL–7–B
HYS64D16001GDL–7–B
HYS64D16000GDL–8–B
SPD Codes for HYS64D1600xGDL–[6/7/8]–B
HYS64D16001GDL–6–B
Table 13
HYS64D16000GDL–6–B
SPD Contents
Part Number & Organization
5
128MB
128MB
128MB
128MB
128MB
× 64
× 64
× 64
× 64
× 64
1 Rank
1 Rank
1 Rank
1 Rank
1 Rank
–6
–6
–7
–7
–8
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
08
2
Memory Type DDR-I = 07h
07
07
07
07
07
3
# of Row Addresses
0D
0D
0D
0D
0D
4
# Number of Column Addresses
09
09
09
09
09
5
# of DIMM Banks
01
01
01
01
01
6
Data Width (LSB)
40
40
40
40
40
7
Data Width (MSB)
00
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
70
70
80
10
tAC SDRAM @ CLmax (Byte 18) [ns]
70
70
75
75
80
11
DIMM Configuration Type (non- / ECC)
00
00
00
00
00
12
Refresh Rate
82
82
82
82
82
13
Primary SDRAM width
10
10
10
10
10
14
Error Checking SDRAM width
00
00
00
00
00
15
tCCD [cycles]
01
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
0E
17
Number of Banks on SDRAM
04
04
04
04
04
18
CAS Latency
0C
0C
0C
0C
0C
19
CS Latency
01
01
01
01
01
20
WE (Write) Latency
02
02
02
02
02
21
DIMM Attributes
20
20
20
20
20
22
Component Attributes
C1
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
75
75
A0
24
tAC SDRAM @ CLmax -0.5 [ns]
70
70
75
75
80
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
00
00
Data Sheet
23
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
SPD Contents
HYS64D16000GDL–6–B
HYS64D16001GDL–6–B
HYS64D16000GDL–7–B
HYS64D16001GDL–7–B
HYS64D16000GDL–8–B
SPD Codes for HYS64D1600xGDL–[6/7/8]–B
Part Number & Organization
Table 13
128MB
128MB
128MB
128MB
128MB
× 64
× 64
× 64
× 64
× 64
1 Rank
1 Rank
1 Rank
1 Rank
1 Rank
–6
–6
–7
–7
–8
Byte#
Description
HEX
HEX
HEX
HEX
HEX
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
00
00
27
tRPmin (ns)
48
48
50
50
50
28
tRRDmin [ns]
30
30
3C
3C
3C
29
tRCDmin [ns]
48
48
50
50
50
30
tRASmin [ns]
2A
2A
2D
2D
32
31
Module Density per Bank
20
20
20
20
20
32
tAS, tCS [ns]
75
75
90
90
B0
33
tAH, TCH [ns]
75
75
90
90
B0
34
tDS [ns]
45
45
50
50
60
35
tDH [ns]
45
45
50
50
60
36 - 40 not used
00
00
00
00
00
41
tRCmin [ns]
3C
3C
41
41
46
42
tRFCmin [ns]
48
48
4B
4B
50
43
tCKmax [ns]
30
30
30
30
30
44
tDQSQmax [ns]
2D
2D
32
32
3C
45
tQHSmax [ns]
55
55
75
75
A0
46 - 61 not used
00
00
00
00
00
62
SPD Revision
00
00
00
00
00
63
Checksum of Byte 0-62 (LSB only)
E8
E8
9A
9A
8F
64
JEDEC ID Code for Infineon
C1
C1
C1
C1
C1
65
JEDEC ID Code for Infineon
49
49
49
49
49
66
JEDEC ID Code for Infineon
4E
4E
4E
4E
4E
67
JEDEC ID Code for Infineon
46
46
46
46
46
68
JEDEC ID Code for Infineon
49
49
49
49
49
69
JEDEC ID Code for Infineon
4E
4E
4E
4E
4E
70
JEDEC ID Code for Infineon
45
45
45
45
45
71
JEDEC ID Code for Infineon
4F
4F
4F
4F
4F
72
Module Manufacturer Location
xx
09
xx
09
xx
73
Part Number, Char 1
36
36
36
36
36
Data Sheet
24
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
SPD Contents
HYS64D16000GDL–6–B
HYS64D16001GDL–6–B
HYS64D16000GDL–7–B
HYS64D16001GDL–7–B
HYS64D16000GDL–8–B
SPD Codes for HYS64D1600xGDL–[6/7/8]–B
Part Number & Organization
Table 13
128MB
128MB
128MB
128MB
128MB
× 64
× 64
× 64
× 64
× 64
1 Rank
1 Rank
1 Rank
1 Rank
1 Rank
–6
–6
–7
–7
–8
Byte#
Description
HEX
HEX
HEX
HEX
HEX
74
Part Number, Char 2
34
34
34
34
34
75
Part Number, Char 3
44
44
44
44
44
76
Part Number, Char 4
31
31
31
31
31
77
Part Number, Char 5
36
36
36
36
36
78
Part Number, Char 6
30
30
30
30
30
79
Part Number, Char 7
30
30
30
30
30
80
Part Number, Char 8
30
31
30
31
30
81
Part Number, Char 9
47
47
47
47
47
82
Part Number, Char 10
44
44
44
44
44
83
Part Number, Char 11
4C
4C
4C
4C
4C
84
Part Number, Char 12
36
36
37
37
38
85
Part Number, Char 13
42
42
42
42
42
86
Part Number, Char 14
20
20
20
20
20
87
Part Number, Char 15
20
20
20
20
20
88
Part Number, Char 16
20
20
20
20
20
89
Part Number, Char 17
20
20
20
20
20
90
Part Number, Char 18
20
20
20
20
20
91
Module Revision Code
xx
xx
xx
xx
xx
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98 Module Serial Number
xx
xx
xx
xx
xx
99 -127 not used
00
00
00
00
00
Data Sheet
25
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
SPD Contents
HYS64D32020GDL–5–B
HYS64D32020GDL–6–B
HYS64D32020GDL–7–B
HYS64D32020GDL–8–B
SPD Codes for HYS64D32020GDL–[5/6/7/8]–B
Part Number & Organization
Table 14
256MB
256MB
256MB
256MB
× 64
× 64
× 64
× 64
2 Ranks
2 Ranks
2 Ranks
2 Ranks
–5
–6
–7
–8
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
08
2
Memory Type DDR-I = 07h
07
07
07
07
3
# of Row Addresses
0D
0D
0D
0D
4
# Number of Column Addresses
09
09
09
09
5
# of DIMM Banks
02
02
02
02
6
Data Width (LSB)
40
40
40
40
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
50
60
70
80
10
tAC SDRAM @ CLmax (Byte 18) [ns]
50
70
75
80
11
DIMM Configuration Type (non- / ECC)
00
00
00
00
12
Refresh Rate
82
82
82
82
13
Primary SDRAM width
10
10
10
10
14
Error Checking SDRAM width
00
00
00
00
15
tCCD [cycles]
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
17
Number of Banks on SDRAM
04
04
04
04
18
CAS Latency
1C
0C
0C
0C
19
CS Latency
01
01
01
01
20
WE (Write) Latency
02
02
02
02
21
DIMM Attributes
20
20
20
20
22
Component Attributes
C1
C1
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
60
75
75
A0
24
tAC SDRAM @ CLmax -0.5 [ns]
50
70
75
80
25
tCK @ CLmax -1 (Byte 18) [ns]
75
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
50
00
00
00
27
tRPmin (ns)
3C
48
50
50
Data Sheet
26
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
SPD Contents
HYS64D32020GDL–5–B
HYS64D32020GDL–6–B
HYS64D32020GDL–7–B
HYS64D32020GDL–8–B
SPD Codes for HYS64D32020GDL–[5/6/7/8]–B
Part Number & Organization
Table 14
256MB
256MB
256MB
256MB
× 64
× 64
× 64
× 64
2 Ranks
2 Ranks
2 Ranks
2 Ranks
–5
–6
–7
–8
Byte#
Description
HEX
HEX
HEX
HEX
28
tRRDmin [ns]
28
30
3C
3C
29
tRCDmin [ns]
3C
48
50
50
30
tRASmin [ns]
28
2A
2D
32
31
Module Density per Bank
20
20
20
20
32
tAS, tCS [ns]
60
75
90
B0
33
tAH, TCH [ns]
60
75
90
B0
34
tDS [ns]
40
45
50
60
35
tDH [ns]
40
45
50
60
36 - 40
not used
00
00
00
00
41
tRCmin [ns]
37
3C
41
46
42
tRFCmin [ns]
41
48
4B
50
43
tCKmax [ns]
28
30
30
30
44
tDQSQmax [ns]
28
2D
32
3C
45
tQHSmax [ns]
50
55
75
A0
46 - 61
not used
00
00
00
00
62
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62 (LSB only)
E5
E9
9B
90
64
JEDEC ID Code for Infineon
C1
C1
C1
C1
65
JEDEC ID Code for Infineon
49
49
49
49
66
JEDEC ID Code for Infineon
4E
4E
4E
4E
67
JEDEC ID Code for Infineon
46
46
46
46
68
JEDEC ID Code for Infineon
49
49
49
49
69
JEDEC ID Code for Infineon
4E
4E
4E
4E
70
JEDEC ID Code for Infineon
45
45
45
45
71
JEDEC ID Code for Infineon
4F
4F
4F
4F
72
Module Manufacturer Location
xx
xx
xx
xx
73
Part Number, Char 1
36
36
36
36
74
Part Number, Char 2
34
34
34
34
75
Part Number, Char 3
44
44
44
44
Data Sheet
27
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
SPD Contents
HYS64D32020GDL–5–B
HYS64D32020GDL–6–B
HYS64D32020GDL–7–B
HYS64D32020GDL–8–B
SPD Codes for HYS64D32020GDL–[5/6/7/8]–B
Part Number & Organization
Table 14
256MB
256MB
256MB
256MB
× 64
× 64
× 64
× 64
2 Ranks
2 Ranks
2 Ranks
2 Ranks
–5
–6
–7
–8
Byte#
Description
HEX
HEX
HEX
HEX
76
Part Number, Char 4
33
33
33
33
77
Part Number, Char 5
32
32
32
32
78
Part Number, Char 6
30
30
30
30
79
Part Number, Char 7
32
32
32
32
80
Part Number, Char 8
30
30
30
30
81
Part Number, Char 9
47
47
47
47
82
Part Number, Char 10
44
44
44
44
83
Part Number, Char 11
4C
4C
4C
4C
84
Part Number, Char 12
35
36
37
38
85
Part Number, Char 13
42
42
42
42
86
Part Number, Char 14
20
20
20
20
87
Part Number, Char 15
20
20
20
20
88
Part Number, Char 16
20
20
20
20
89
Part Number, Char 17
20
20
20
20
90
Part Number, Char 18
20
20
20
20
91
Module Revision Code
xx
xx
xx
xx
92
Test Program Revision Code
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
00
00
00
00
99 - 127 not used
Data Sheet
28
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Package Outlines
6
Package Outlines
67.6
3.8 MAX.
31.75
4 ±0.1
1.8 ±0.05
63.6 ±0.1
(2.15)
1
(2.45)
18.45 ±0.1
100
1±0.1
1.8 ±0.1
0.15
(2.4)
11.4 ±0.1
47.4 ±0.1
(2.7)
(2.15)
1.5 ±0.1
4 ±0.1
1±0.1
200
20 ±0.1
101
6 ±0.1
(2.45)
2 MIN.
2.55
0.25 -0.18
Detail of contacts
0.45 ±0.03
0.6 ±0.1
Burnished, no burr allowed
L-DIM-200-006
Figure 4
Data Sheet
Package Outlines – Raw Card A DDR-SDRAM SO-DIMM Module HYS64D32020GDL–[5/6/7/8]–
B
29
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Package Outlines
67.6
2.4 MAX.
31.75
4 ±0.1
1.8 ±0.05
63.6
(2.15)
1
(2.45)
18.45 ±0.1
100
1±0.1
1.8 ±0.1
0.15
(2.4)
11.4 ±0.1
47.4 ±0.1
(2.7)
(2.45)
(2.15)
1.5 ±0.1
200
20
101
6
4 ±0.1
1±0.1
2 MIN.
2.55
0.25 -0.18
Detail of contacts
0.45 ±0.03
0.6 ±0.1
Burnished, no burr allowed
L-DIM-200-011
Figure 5
Data Sheet
Package Outlines Raw Card C DDR SDRAM SO-DIMM Modules HYS64D1600xGDL–[6/7/8]–B
30
V1.2, 2003-08
www.infineon.com
Published by Infineon Technologies AG