19-5707; Rev 0; 12/10 TION KIT EVALUA BLE IL AVA A Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter The MAX14886 high-speed, low-skew, active redriver multiplexer is ideal for switching between outputs of dual-graphics systems and signal conditioning to meet HDMIK v.1.4 compliance up to 2.25Gbps at an external HDMI connector. It is used for switching between integrated (e.g., Intel or AMD) and discrete graphics (e.g., NVIDIA or ATI GPU). The device is VESA DisplayPortK Interoperability Guideline v.1.1a-compliant (requires external DDC logic) and integrates seamlessly with an external HDMI connector on the motherboard. The device accommodates differential inputs as low as 200mV and drives transition minimized differential signaling (TMDS®) outputs to 1000mV (typ). A precision resistor on the output level adjust pin (ADJ) allows differentiated output back-termination resistors of 400I (typ) to better meet HDMI mask jitter compliance, while maintaining full TMDS swing requirements. The device supports AC-(DisplayPort) or DC-(HDMI) coupling directly to the graphics IC and must be DC-coupled to the HDMI connector. In addition, the device features current backflow protection at the HDMI connector and a low-power, active-high or active-low shutdown mode. Features S Single +3.3V Supply S Meets HDMI v.1.4 Eye Mask Up to 2.25Gbps S Meets VESA DisplayPort Interoperability Guideline v.1.1a (Requires External DDC Logic) S Low-Power Shutdown Mode Active High or Active Low S Output Level Adjust (ADJ) for Output Back- Termination Without Amplitude Loss S Seamless Integration into Dual-Graphics Systems with External HDMI Connector DC-Coupled HDMI Outputs Mate Directly to HDMI Connector AC- or DC-Coupled TMDS-Formatted Inputs Ordering Information PART MAX14886CTL+ TEMP RANGE PIN-PACKAGE 0NC to +70NC 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Typical Operating Circuit The device operates with a single +3.3V supply, is specified over the 0NC to +70NC commercial temperature range, and is available in a 5mm x 5mm, 40-pin TQFN package. 3.3V VAVCC = 3.3V Applications 50Ω D0AP D0CP D0AN D0CN CKAP CKCP CKAN CKCN 100nF DisplayPort B D0BP MAX14886 SEL EN1 D0BN HDMI SINK VCC HDMI CONNECTOR DisplayPort A Dual Mode DisplayPort to HDMI External Switches or Adapters 100nF MCU Dual Graphics Notebook Computers EN2 ADJ CKBP 3.3kΩ CKBN GND HDMI is a trademark of HDMI Licensing, LLC. DisplayPort is a trademark of Video Electronics Standards Association (VESA). TMDS is a registered trademark of Silicon Image, Inc. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX14886 General Description MAX14886 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VCC. ......................................................................-0.3V to +4.0V EN1, EN2, SEL, ADJ................................. -0.3V to (VCC + 0.3V) D_CP, D_CN, CKCP, CKCN Short-Circuit Output Current.............................................................. Q30mA All Other Pins Short-Circuit Current................................... Q5mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 35.7mW/NC above +70NC)...................2857mW Operating Temperature Range.............................. 0NC to +70NC Storage Temperature Range............................. -65NC to +150NC Maximum Junction Temperature......................................+150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC PACKAGE THERMAL CHARACTERISTICS (Note 1) TQFN Junction-to-Ambient Thermal Resistance (qJA)...........45°C/W Junction-to-Case Thermal Resistance (qJC)..................2°C/W Note 1: P ackage thermal resistances were obtained using method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.3V, TA = 0NC to +70NC, RADJ = 3.3kI, CCL = 100nF, typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.6 V EN1 = high, EN2 = low 52.5 mA 105 mA 100 FA 40 60 I DC PERFORMANCE Supply Voltage VCC Supply Current ICC 3 Total Supply Current IGND 50I termination to AVCC, VAVCC = +3.3V (Note 3) Shutdown Supply Current ISHUT EN1 = low or EN2 = high Single-Ended Input Termination Resistance RIN DC Single-Ended Output Voltage High VOH DC, VAVCC = +3.3V (Notes 3, 4) VAVCC - 0.01 VAVCC + 0.01 V Single-Ended Output Voltage Low VOL DC, VAVCC = +3.3V (Notes 3, 4) VAVCC - 0.6 VAVCC - 0.45 V 2 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.3V, TA = 0NC to +70NC, RADJ = 3.3kI, CCL = 100nF, typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -8 dB AC PERFORMANCE Differential Input Return Loss Input Frequency Range SDD11 fIN 150MHz P f P 1.25GHz Clock 25 225 Data 225 1125 200 1600 mV 900 1250 mV 80 ps MHz Differential Input Range VIDIFF Differential Output Voltage VODIFF 50I single termination Output Rise/Fall Time tR/F 20% to 80%, 2.25Gbps Deterministic Jitter tDJ K28.5 pattern, up to 2.25Gbps (Note 4) 0.04 UI Random Jitter tRJ D10.2 pattern, 2.25Gbps (Note 4) 1.1 psRMS Lane-to-Lane Skew tSK 50 ps Propagation Delay tPD 250 ps CONTROL LOGIC (EN1, EN2, SEL) Input Logic-Low Voltage VIL Input Logic-High Voltage VIH 0.6 1.4 V V Input Logic Hysteresis VHYST 50 mV Input Pulldown/Pullup Resistor RIPULL 400 kI Shutdown Recovery Time tSHUT 20 Fs TMDS Mux Switching Time tMUX 50 ns ±8 kV ESD PROTECTION All Pins Human Body Model Note 2: All units are production tested at TA = +70NC. Specifications over temperature are guaranteed by design. Note 3: AVCC is an external supply. Note 4: Guaranteed by design; not production tested. 3 Typical Operating Characteristics (VCC = +3.3V, TA = +25NC, RADJ = 3.3kI, unless otherwise noted.) EYE DIAGRAM, VIN = 200mVP-P, 250Mbps, NO BACK TERMINATION, 25MHz CLOCK, 640 x 480, 8-BIT COLOR, 60Hz 600 800 600 600 400 0 -200 VOLTAGE (mV) 200 200 0 -200 200 0 -200 -400 -400 -400 -600 -600 -600 -800 -800 -800 -5 -4 -3 -2 -1 0 1 2 3 4 -5 -4 -3 -2 -1 0 1 2 3 -600 4 -400 -200 0 200 400 600 EYE DIAGRAM, VIN = 200mVP-P, 1.5Gbps, NO BACK TERMINATION, 1080p, 8-BIT COLOR, 60Hz EYE DIAGRAM, VIN = 1600mVP-P, 2.25Gbps, NO BACK TERMINATION EYE DIAGRAM, VIN = 200mVP-P, 2.25Gbps, NO BACK TERMINATION, 225MHz CLOCK, 1080p, 12-BIT COLOR, 60Hz 600 800 600 400 800 600 400 0 -200 VOLTAGE (mV) VOLTAGE (mV) 400 200 200 0 -200 200 0 -200 -400 -400 -400 -600 -600 -600 -800 -800 -800 -600 -400 -200 0 200 400 600 -400 -300 -200 -100 (ps) 0 -400 -300 -200 -100 100 200 300 400 DIFFERENTIAL INPUT RETURN LOSS vs. FREQUENCY 600 0 -5 MAGNITUDE (dB) 400 200 0 -200 MAX14886 toc08 5 MAX14886 toc07 800 -10 -15 -20 -25 -30 -400 -35 -600 -40 -800 -45 -400 -300 -200 -100 0 (ps) 100 200 300 400 0 (ps) (ps) EYE DIAGRAM, VIN = 200mVP-P, 2.25Gbps, 400Ω BACK TERMINATION, RSET = 3kΩ, FIGURE 1 VOLTAGE (mV) MAX14886 toc06 (ps) MAX14886 toc05 (ns) MAX14886 toc04 (ns) 800 4 800 400 VOLTAGE (mV) VOLTAGE (mV) 400 MAX14886 toc03 800 EYE DIAGRAM, VIN = 1600mVP-P, 1.5Gbps, NO BACK TERMINATION, 150MHz CLOCK MAX14886 toc02 MAX14886 toc01 EYE DIAGRAM, VIN = 1600mVP-P, 250Mbps, NO BACK TERMINATION, 25MHz CLOCK, 640 x 480, 8-BIT COLOR, 60Hz VOLTAGE (mV) MAX14886 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter 0 1 2 FREQUENCY (GHz) 3 100 200 300 400 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter D2BN D2AP D2AN GND 26 25 GND 28 27 D2BP 30 29 D1BP D1BN D1AP D1AN TOP VIEW 24 23 22 21 VCC 31 20 D2CP GND 32 19 D2CN ADJ 33 18 D1CP 17 D1CN SEL 34 MAX14886 GND 35 16 VCC VCC 36 15 D0CP EN2 37 14 D0CN EN1 38 GND 39 13 CKCP *EP + 12 CKCN 11 GND 1 2 3 4 5 6 7 8 9 10 D0AP D0AN D0BP D0BN GND CKAP CKAN CKBP CKBN GND VCC 40 TQFN (5mm × 5mm × 0.75mm) *CONNECT EP TO GND. Pin Description PIN NAME PIN NAME 1 D0AP Noninverting Input D0 for Channel A FUNCTION 18 D1CP Noninverting Output D1 2 D0AN Inverting Input D0 for Channel A 19 D2CN Inverting Output D2 3 D0BP Noninverting Input D0 for Channel B 20 D2CP Noninverting Output D2 4 D0BN Inverting Input D0 for Channel B 22 D2BP Noninverting Input D2 for Channel B 23 D2BN Inverting Input D2 for Channel B 24 D2AP Noninverting Input D2 for Channel A 25 D2AN Inverting Input D2 for Channel A 27 D1BP Noninverting Input D1 for Channel B 28 D1BN Inverting Input D1 for Channel B 29 D1AP Noninverting Input D1 for Channel A 30 D1AN Inverting Input D1 for Channel A 33 ADJ Output Level Adjust 34 SEL Mux Select Input. SEL is internally pulled down by a 400kI (typ) resistor. 37 EN2 Active-Low Enable Input. EN2 is internally pulled up by a 400kI (typ) resistor. 38 EN1 Active-High Enable Input. EN1 is internally pulled down by a 400kI (typ) resistor. — EP 5, 10, 11, 21, 26, 32, 35, 39 GND 6 CKAP Noninverting Input Clock for Channel A 7 CKAN Inverting Input Clock for Channel A 8 CKBP Noninverting Input Clock for Channel B 9 CKBN Inverting Input Clock for Channel B 12 CKCN Inverting Output Clock 13 CKCP Noninverting Output Clock 14 D0CN Inverting Output D0 15 D0CP Noninverting Output D0 16, 31, 36, 40 VCC 17 D1CN Ground Power-Supply Voltage. Bypass VCC to GND with low-ESR 10nF and 4.7FF ceramic capacitors in parallel as close as possible to the device. Recommended on each VCC pin. Inverting Output D1 FUNCTION Exposed Pad. Connect EP to GND. 5 MAX14886 Pin Configuration Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter MAX14886 Functional Diagram/Truth Tables EN1 VCC VCC MAX14886 50Ω 50Ω EN2 X FUNCTION 0/Unconnected X 1/Unconnected Shutdown 1 0 Active Shutdown X = Don’t care. D2AP D2AN VCC 50Ω 50Ω D_A_, CKA_ D_B_, CKB_ On Off 1 Off On X = Don’t care. D2BP D2BN VCC 50Ω 50Ω D1AP D2CP D1AN D2CN VCC 50Ω 50Ω D1BP D1CP D1BN D1CN VCC 50Ω MULTIPLEXER/ LIMITING AMPLIFIER 50Ω D0AP D0CP D0AN D0CN VCC 50Ω 50Ω D0BP CKCP D0BN CKCN VCC 50Ω 50Ω CKAP CKAN VCC 50Ω 50Ω CKBP CKBN CONTROL GND 6 SEL 0/Unconnected EN1 EN2 SEL ADJ Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter The MAX14886 is a high-speed, low-skew, active redriver multiplexer designed to switch and amplify TMDS-formatted signals. Input buffers have 50I HDMIcompliant terminations to VCC (see the Functional Diagram/Truth Tables), allowing either DC-coupling to an HDMI source or AC-coupling to a DisplayPort source. Signals from the input buffers are multiplexed and redriven by the limiting amplifier and an open-collector output buffer. The HDMI monitor sink is DC-coupled to the outputs and provides DC bias. Both TMDS clock and data are multiplexed and redriven to full HDMI v.1.4 levels with low skew and jitter to guarantee mask compliance at an external HDMI connector. The device is VESA DisplayPort Interoperability Guideline v.1.1a-compliant and integrates seamlessly with an external HDMI connector on the motherboard. The low-frequency signals (DDC, CEC, and HPD) can be handled by external low-cost logic. The device accommodates differential inputs as low as 200mV and drives differential TMDS outputs to 1000mV (typ). A precision resistor on the output level adjust pin (ADJ) allows differential output back-termination resistors of 400I (typ) to better meet HDMI mask jitter compliance, while maintaining full TMDS swing requirements. This device also features both active-high and activelow enable inputs. One of the enable inputs can be connected to either VCC or GND, while the other can be used to control the device (see the Functional Diagram/ Truth Tables and Enable Inputs (EN1, EN2) section). This eliminates any issues with logic sense and the need for an inverter. Level Translation The device accepts two sets of four differential DisplayPort-level TMDS-formatted inputs, each with magnitudes as low as 200mV. The selected channel is translated to full HDMI TMDS levels that are HDMI v.1.4 port mask-compliant up to 2.25Gbps. Enable Inputs (EN1, EN2) The device features both an active-high enable input (EN1) and an active-low enable input (EN2) that can be controlled by LVCMOS or LVTTL. EN1 has an internal 400kI (typ) pulldown resistor, and EN2 has an internal 400kI (typ) pullup resistor. When EN1 is driven low or left unconnected, or EN2 is driven high or left unconnected, the device enters low-power shutdown mode. For normal operation drive both EN1 high and EN2 low. See the Functional Diagram/Truth Tables. Only one input is necessary to control the device. If active-high enable is desired, connect EN2 to GND and use EN1 to control the device. Similarly, for active-low enable, connect EN1 to VCC and use EN2 to control the device. Note: The monitor sink termination must be present and powered before enabling the device (see the Control Sequence section and Figure 2). Digital Control Input (SEL) The device provides two sets of 4 channels for all the differential signals required by HDMI connections. The SEL input controls which channel is translated to the output channel (see the Functional Diagram/Truth Tables). An internal 400kI pulldown resistor guarantees that channel A is translated to the output if the SEL pin is not externally driven. Output Level Adjust (ADJ) The level-shifter’s output current and output signal swing are set with an external ±1% precision 3.3kI (typ) resistor. If a double output termination (400I typ) is desired for signal integrity reasons, the ADJ resistor value can be decreased to maintain a desired output swing (Figure 1). Applications Information HDMI Driver The device’s high-speed, low-skew, active redriver multiplexer is ideal for switching between outputs of dual-graphics systems and signal conditioning to meet HDMI v.1.4 compliance at an external HDMI connector (Figure 1). It is well suited for switching between integrated (e.g., Intel or AMD) and discrete graphics (e.g., NVIDIA or ATI GPU). The device is VESA DisplayPort Interoperability Guideline v.1.1a-compliant (requires external DDC logic) and integrates seamlessly with an external HDMI connector on the motherboard. Output Termination Outputs are terminated in normal use by the HDMI monitor. For 50I test equipment purposes, terminate each output with a high-frequency bias-T that has an inductor in series with a 50I resistor to VCC. Control Sequence The monitor sink termination must be present and powered before enabling the device. A simple circuit can be added to protect the device by forcing hot-plug detection (HPD) to be present before the part is enabled (Figure 2). 7 MAX14886 Detailed Description MAX14886 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter VAVCC = 3.3V 3.3V 50Ω VCC D0AP D0CP D0CN CKAP CKCP HDMI SINK D0AN HDMI CONNECTOR SOURCE A 400Ω 400Ω MAX14886 D0BP SOURCE B CKCN SEL MCU CKAN EN1 D0BN EN2 ADJ CKBP 3kΩ CKBN GND FOR DisplayPort SOURCE, ADD AC-COUPLING CAPACITORS. Figure 1. HDMI Driver Application with Output Back Termination Power-Supply Bypassing Adequate power-supply bypassing is necessary to maximize performance and noise immunity. Bypass each VCC pin to GND with high-frequency, low-ESR, X7R/X5R 10nF and 4.7FF surface-mount ceramic capacitors as close as possible to the device. MAX14886 EN1 CONTROL CPU EN Printed Circuit Board (PCB) Traces 10kΩ 10kΩ GPIO HPD N HPD +3.3V Figure 2. Control Sequence Protection Circuit 8 Input and output trace characteristics affect the performance of the device. Connect each of the inputs and outputs to a 50I characteristic impedance trace in to minimize reflections. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces and avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50I characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN-EP T4055+2 21-0140 90-0002 9 MAX14886 Chip Information Exposed-Pad Package The exposed-pad, 40-pin TQFN package incorporates features that provide a very low thermal resistance path for heat removal from the IC. The exposed pad on the device must be soldered to the circuit board ground plane for proper electrical and thermal performance. For more information on exposed-pad packages, refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages. MAX14886 Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter Revision History REVISION NUMBER REVISION DATE 0 12/10 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 © 2010 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.