MAXIM MAX8893BEWV+

19-4971; Rev 1; 2/10
TION KIT
EVALUA BLE
IL
AVA A
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Features
The MAX8893A/MAX8893B/MAX8893C power-management integrated circuits (PMICs) are designed for a
variety of portable devices including cellular handsets.
The PMICs include a high-efficiency step-down DC-DC
converter, five low-dropout linear regulators (LDOs) with
programmable output voltages, individual power-on/
off control inputs, a load switch, and a USB high-speed
switch. These devices maintain high efficiency with a low
no-load supply current, and the small 3.0mm x 2.5mm
WLP package makes them ideal for portable devices.
S High-Efficiency Step-Down Converter
Guaranteed 500mA Output Current
The step-down DC-DC converter utilizes a proprietary
4MHz hysteretic PWM control scheme that allows for
ultra-small external components. Internal synchronous
rectification improves efficiency and eliminates the external Schottky diode that is required in conventional stepdown converters. Its output voltage is programmable by
the I2C serial interface and output current is guaranteed
up to 500mA.
S Two Low Supply Current LDOs with
Programmable Output Voltages
LDO1, LDO4, and LDO5 offer low 45FVRMS output noise
and low dropout of only 100mV at 100mA. They deliver
up to 300mA, 150mA, and 200mA continuous output currents, respectively. LDO2 and LDO3 each deliver 300mA
continuous output current with very low ground current.
All LDO output voltages are programmable by the I2C
serial interface. Three standard versions of the PMIC are
available with different LDO default startup voltages (see
Table 1).
The MAX8893A/MAX8893B/MAX8893C are available in
a 3.0mm x 2.5mm, 30-bump WLP package.
Applications
Cellular Handsets
Smartphones and PDAs
Up to 4MHz Switching Frequency
Programmable Output Voltage from 0.8V to 2.4V
Dynamic Voltage Scaling with Programmable
Ramp Rate
S Three Low-Noise LDOs with Programmable
Output Voltages
S Low On-Resistance Load Switch
S USB High-Speed Switch with ±15kV ESD
S Individual Enable Control for All Regulators and
Switches
S I2C Serial Interface
S Overcurrent and Thermal Protection for All LDOs
S 3.0mm x 2.5mm x 0.64mm, 30-Bump WLP
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX8893AEWV+
-40NC to +85NC
30-Bump WLP
(3.0mm x 2.5mm)
MAX8893BEWV+
-40NC to +85NC
30-Bump WLP
(3.0mm x 2.5mm)
MAX8893CEWV+
-40NC to +85NC
30-Bump WLP
(3.0mm x 2.5mm)
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX8893A/MAX8893B/MAX8893C
General Description
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ABSOLUTE MAXIMUM RATINGS
IN1, IN2, BATT, COM1, COM2 to AGND..............-0.3V to +6.0V
BUCK, LS, ENLS, ENBUCK, ENLDO1, ENLDO2,
ENLDO3, ENLDO45, REFBP, LDO2, LDO3,
SCL, SDA, ENUSB, CB, NC1, NC2,
NO1, NO2 to AGND........................... -0.3V to (VBATT + 0.3V)
LDO1, LDO4, LDO5 to AGND................... -0.3V to (VIN2 + 0.3V)
PGND to AGND.....................................................-0.3V to +0.3V
LX Current...................................................................... 1.5ARMS
LX to AGND (Note 1)................................. -0.3V to (VIN1 + 0.3V)
Continuous Power Dissipation (TA = +70NC)
30-Bump, 3.0mm x 2.5mm WLP (derate 20.0mW/NC
above +70NC).............................................................1600mW
Junction-to-Ambient Thermal Resistance (θJA)
(Note 2).........................................................................50NC/W
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Bump Temperature (soldering)
Infrared (15s)................................................................+200NC
Vapor Phase (20s)........................................................+215NC
Note 1: LX has internal clap diodes to PGND and IN1. Applications that forward bias these diodes should take care not to exceed
the IC’s package-dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
Input Supply Range
MIN
TYP
2.7
MAX
UNIT
5.5
V
Shutdown Supply Current
VCB = 0V or VIN, VENUSB = VIN, VENLS = VENBUCK =
VENLDO1 = VENLDO2 = VENLDO3 = VENLDO45 = 0V
0.6
5
FA
No-Load Supply Current
No load on BUCK, LDO1, LDO2, LDO3, LDO4, and
LDO5, VENUSB = 0V, VENLS = VIN
160
200
FA
Light-Load Supply Current
BUCK on with 500FA load, all LDOs on with no load,
VENUSB = 0V, VENLS = VIN
315
FA
UNDERVOLTAGE LOCKOUT
Undervoltage Lockout (Note 5)
VIN_ rising
2.85
3.05
VIN_ falling
2.70
2.35
2.55
TA rising
160
NC
10
NC
V
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
REFERENCE
Reference Bypass Output
Voltage
REF Supply Rejection
0.786
2.7V P VIN P 5.5V
0.800
0.814
0.2
V
mV/V
LOGIC AND CONTROL INPUTS
Input Low Level
ENLS, ENBUCK, ENLDO1, ENLDO2, ENLDO3,
ENLDO45, ENUSB, SDA, SCL, 2.7V P VIN P 5.5V
Input High Level
ENLS, ENBUCK, ENLDO1, ENLDO2, ENLDO3,
ENLDO45, ENUSB, SDA, SCL, 2.7V P VIN P 5.5V
0.4
1.4
2 _______________________________________________________________________________________
V
V
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
Logic Input Current
CONDITIONS
SDA, SCL, 0V < VIN < 5.5V
MIN
TA = +25NC
TYP
-1
TA = +85NC
MAX
+1
0.1
UNIT
FA
ENUSB Pullup Resistor to BATT
400
800
1600
kI
ENLS, ENBUCK, ENLDO1,
ENLDO2, ENLDO3, ENLDO45,
Pulldown Resistor to AGND
400
800
1600
kI
0.776
0.800
STEP-DOWN DC-DC CONVERTER (BUCK)
Supply Current
ILOAD = 0A, no switching
25
FA
0.824
0.90
0.97
1.00
1.03
1.10
1.20
1.30
1.40
Programmable Output Voltage
1.50
ILOAD = 100mA, programmable output voltage 0.8V to
2.4V in 100mV steps
1.60
V
1.70
1.80
1.90
2.00
2.10
2.20
Output-Voltage Line Regulation
LX Leakage Current
Current Limit
2.231
2.300
2.369
2.328
2.400
2.472
VIN = 2.7V to 5.5V
VLX = 0V or 5.5V
0.3
TA = +25NC
-1
TA = +85NC
%/V
+1
0.1
p-MOSFET switch
600
990
1500
n-MOSFET rectifier
400
700
1300
FA
mA
p-MOSFET switch, ILX = -40mA
0.65
n-MOSFET rectifier, ILX = 40mA
0.4
Rectifier Off Current Threshold
ILXOFF
30
mA
Minimum On- and Off-Times
tON, tOFF
70
Shutdown Output Resistance
BUCK_ADEN = 1, VENBUCK = 0V
300
ns
I
On-Resistance
I
_______________________________________________________________________________________ 3
MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
LDO1
Input Voltage Range
2.7
1.552
1.600
1.648
1.70
1.80
1.90
2.00
2.10
2.20
2.30
Programmable Output Voltage
2.40
ILOAD = 25mA, programmable output voltage 1.6V to
3.3V in 100mV steps
V
2.50
2.60
2.70
2.80
2.90
2.910
3.000
3.090
3.1
3.2
Output Voltage Accuracy
3.201
3.300
3.399
VIN = 5.5V with ILOAD = 1mA, and
VIN = 3.2V with ILOAD = 300mA (MAX8893A)
2.716
2.800
2.884
VIN = 5.5V with ILOAD = 1mA, and
VIN = 3.0V with ILOAD = 300mA (MAX8893B)
2.522
2.600
2.678
VIN = 5.5V with ILOAD = 1mA, and
VIN = 2.7V with ILOAD = 300mA (MAX8893C)
1.746
1.800
1.854
Output Current
300
V
mA
Current Limit
VLDO1 = 0V
550
mA
Dropout Voltage
ILOAD = 200mA, TA = +25NC
200
mV
Load Regulation
1mA < ILOAD < 300mA
VENLDO1 = VBATT
25
mV
Power-Supply Rejection
DVLDO1/DVIN2
10Hz to 10kHz, CLDO1 = 1FF, ILOAD = 30mA
75
dB
Output Noise Voltage
100Hz to 100kHz, CLDO1 = 1FF, ILOAD = 30mA
45
FVRMS
Output Capacitor for Stable
Operation (Note 6)
0mA < ILOAD < 300mA
1.4
2.2
0mA < ILOAD < 150mA
0.7
1.0
Ground Current
ILOAD = 500FA
21
FA
Startup Time from Shutdown
CLDO1 = 2.2FF, ILOAD = 300mA
40
Shutdown Output Resistance
LDO1_ADEN = 1, VENLDO1 = 0V
300
Fs
I
4 _______________________________________________________________________________________
FF
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
1.200
1.236
LDO2
Input Voltage Range
2.7
1.164
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
Programmable Output Voltage
ILOAD = 25mA, programmable output voltage 1.2V to
3.3V in 100mV steps
2.134
2.200
2.266
2.30
V
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
Output Voltage Accuracy
VIN = 5.5V with ILOAD = 1mA, and
VIN = 3.0V with ILOAD = 300mA
3.201
3.300
3.399
2.522
2.600
2.678
V
300
mA
Output Current
Current Limit
VLDO2 = 0V
550
mA
Dropout Voltage
ILOAD = 200mA, TA = +25NC
200
mV
Load Regulation
1mA < ILOAD < 300mA
VENLDO2 = VBATT
25
mV
Power-Supply Rejection
DVLDO2/DVBATT
10Hz to 10kHz, CLDO2 = 1FF, ILOAD = 30mA
60
dB
Output Noise Voltage
100Hz to 100kHz, CLDO2 = 1FF, ILOAD = 30mA
80
FVRMS
Output Capacitor for Stable
Operation (Note 6)
0mA < ILOAD < 300mA
1.4
2.2
0mA < ILOAD < 150mA
0.7
1.0
Ground Current
ILOAD = 500FA
Startup Time from Shutdown
Shutdown Output Resistance
FF
21
FA
CLDO2 = 1FF, ILOAD = 300mA
40
LDO2_ADEN = 1, VENLDO2 = 0V
300
Fs
I
_______________________________________________________________________________________ 5
MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
LDO3
Input Voltage Range
2.7
1.552
1.600
1.648
1.70
1.80
1.90
2.00
2.10
2.20
2.30
Programmable Output Voltage
2.40
ILOAD = 25mA, programmable output voltage 1.6V to
3.3V in 100mV steps
V
2.50
2.60
2.70
2.80
2.90
2.910
3.000
3.090
3.10
3.20
Output Voltage Accuracy
VIN = 5.5V with ILOAD = 1mA, and
VIN = 3.7V with ILOAD = 300mA
3.201
3.300
3.399
3.201
3.300
3.399
V
300
mA
Output Current
Current Limit
VLDO3 = 0V
550
mA
Dropout Voltage
ILOAD = 200mA, TA = +25NC
200
mV
Load Regulation
1mA < ILOAD < 300mA
VENLDO3 = VBATT
25
mV
Power-Supply Rejection
DVLDO3/DVBATT
10Hz to 10kHz, CLDO3 = 1FF, ILOAD = 30mA
60
dB
Output Noise Voltage
100Hz to 100kHz, CLDO3 = 1FF, ILOAD = 30mA
80
FVRMS
Output Capacitor for Stable
Operation (Note 6)
0mA < ILOAD < 300mA
1.4
2.2
0mA < ILOAD < 150mA
0.7
1.0
Ground Current
ILOAD = 500FA
Startup Time from Shutdown
Shutdown Output Resistance
FF
21
FA
CLDO3 = 2.2FF, ILOAD = 300mA
40
LDO3_ADEN = 1, VENLDO3 = 0V
300
Fs
I
6 _______________________________________________________________________________________
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
LDO4
Input Voltage Range
2.7
0.776
5.5
0.800
V
0.824
0.90
1.00
1.10
1.20
1.30
1.358
1.400
1.442
1.50
1.60
1.70
1.80
1.90
Programmable Output Voltage
2.00
ILOAD = 25mA, programmable output voltage 0.8V to
3.3V in 100mV steps
V
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
Output Voltage Accuracy
3.201
3.300
3.399
VIN = 5.5V with ILOAD=1mA, and VIN = 3.4V with ILOAD =
150mA (MAX8893A)
2.910
3.000
3.090
VIN = 5.5V with ILOAD = 1mA, and VIN = 3.7V with ILOAD
= 150mA (MAX8893B/MAX8893C)
3.201
3.300
3.399
V
Output Current
150
mA
Current Limit
VLDO4 = 0V
360
mA
Dropout Voltage
ILOAD = 100mA
100
mV
Load Regulation
1mA < ILOAD < 150mA, VENLDO4 = VBATT
25
mV
Power-Supply Rejection
DVLDO4/DVIN2
10Hz to 10kHz, CLDO4 = 1FF, ILOAD = 30mA
75
dB
Output Noise Voltage
100Hz to 100kHz, CLDO4 = 1FF, ILOAD = 30mA
45
FVRMS
Output Capacitor for Stable
Operation
0mA < ILOAD < 150mA (Note 6)
1.0
FF
0.7
_______________________________________________________________________________________ 7
MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Ground Current
ILOAD = 500FA
21
FA
Startup Time from Shutdown
CLDO4 = 1.0FF, ILOAD = 150mA
40
Shutdown Output Resistance
LDO4_ADEN = 1, VENLDO4 = 0V
300
Fs
I
LDO5
Input Voltage Range
2.7
0.776
5.5
0.800
V
0.824
0.90
1.00
1.10
1.20
1.30
1.358
1.400
1.442
1.50
1.60
1.70
1.80
1.90
Programmable Output Voltage
2.00
ILOAD = 100mA, programmable output voltage 0.8V to
3.3V in 100mV steps
V
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
Output Voltage Accuracy
3.201
3.300
3.399
VIN = 5.5V with ILOAD = 1mA,
and VIN = 3.4V with ILOAD = 150mA (MAX8893A)
0.970
1.000
1.030
VIN = 5.5V with ILOAD = 1mA,
and VIN = 3.4V with ILOAD = 150mA (MAX8893B)
2.716
2.800
2.884
VIN = 5.5V with ILOAD = 1mA,
and VIN = 3.4V with ILOAD = 150mA (MAX8893C)
2.910
3.000
3.090
Output Current
200
V
mA
Current Limit
VLDO5 = 0V
460
mA
Dropout Voltage
ILOAD = 100mA
100
mV
8 _______________________________________________________________________________________
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Load Regulation
1mA < ILOAD < 150mA
VENLDO5 = VBATT
25
mV
Power-Supply Rejection
DVLDO5/DVIN2
10Hz to 10kHz, CLDO5 = 1FF, ILOAD = 30mA
75
dB
Output Noise Voltage
100Hz to 100kHz, CLDO5 = 1FF, ILOAD = 30mA
45
FVRMS
Output Capacitor for Stable
Operation (Note 6)
0mA < ILOAD < 200mA
1.4
2.2
0mA < ILOAD < 150mA
0.7
1.0
Ground Current
ILOAD = 500FA
21
FA
Startup Time from Shutdown
CLDO5 = 2.2FF, ILOAD = 200mA
40
Shutdown Output Resistance
LDO5_ADEN = 1, VENLDO5 = 0V
300
Fs
I
FF
USB HIGH-SPEED SWITCH
Operating Power-Supply Range
2.7
Supply Current
VENUSB = 0V, VCB = 0V or VBATT
Fault Protection Trip Threshold
(VFP)
COM_ only, TA = +25NC
On-Resistance (RON)
5.5
VBATT = 3.0V
0.6
VBATT = 5.5V
3
VIN +
0.6
VCOM_ = 0V to VBATT
VIN +
1.0
5
10
5.5
On-Resistance Match Between
Channels (DRON)
VBATT = 3.0V, VCOM_ = 2V (Note 7)
0.1
On-Resistance Flatness (RFLAT)
VBATT = 3.0V, VCOM_ = 0V to VIN (Note 8)
0.1
Off-Leakage Current
(ICOM_(OFF))
On-Leakage Current (ICOM_(ON))
VBATT = 4.5V, VCOM_ = 0V or 4.5V,
VNO_, VNC_ = 4.5V or 0V
-250
VBATT = 5.5V, VCOM_ = 0V or 5.5V,
VNO_, VNC_ with 50FA sink current to AGND
VBATT = 5.5V, VCOM_ = 0V or 5.5V,
VNO_, and VNC_ are unconnected
FA
VIN +
0.8
VCOM_ = 3.6V, VBATT = 3.0V
-250
V
1
V
I
I
I
+250
nA
180
FA
+250
nA
USB HIGH-SPEED SWITCH AC PERFORMANCE
On-Channel -3dB Bandwidth
(BW)
RL = RS = 50I, signal = 0dBm
VNO_, VNC_ = 0dBm,
RL = RS = 50I,
Figure 1
f = 10MHz
-48
Off-Isolation (VISO)
f = 250MHz
-20
f = 500MHz
-17
VNO_, VNC_ = 0dBm,
RL = RS = 50I,
Figure 1 (Note 9)
f = 10MHz
-73
f = 250MHz
-54
f = 500MHz
-33
Crosstalk (VCT)
950
MHz
dB
dB
USB HIGH-SPEED SWITCH LOGIC INPUT (CB)
Input Logic-High (VIH)
1.4
Input Logic-Low (VIL)
Input Leakage Current (IIN)
-250
V
0.4
V
+250
nA
_______________________________________________________________________________________ 9
MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
USB HIGH-SPEED SWITCH DYNAMIC
Turn-On Time (tON)
VNO_ or VNC_ = 1.5V, RL = 300I, CL = 35pF, V/ENUSB =
VBATT to 0V, Figure 2
1
5
Fs
Turn-Off Time (tOFF)
VNO_ or VNC_ = 1.5V, RL = 300I, CL = 35pF, V/ENUSB =
0V to VBATT, Figure 2
1
5
Fs
Propagation Delay (tPLH, tPHL)
RL = RS = 50I, Figure 3
Fault Protection Response Time
(tFP)
VCOM_ = 0V to 5V step, RL = RS = 50I, VBATT = 3.3V,
Figure 4
Fault Protection Recovery Time
(tFPR)
VCOM_ = 5V to 0V step, RL = RS = 50I, VBATT = 3.3V,
Figure 4
Output Skew Between Switches
(tSK)
Skew between switch 1 and 2, RL = RS = 50I, Figure 3
(Note 6)
40
ps
NO_ or NC_ Off-Capacitance
(CNO(OFF) or CNC(OFF))
f = 1MHz, Figure 5 (Note 6)
2
pF
100
0.5
ps
5.0
Fs
100
Fs
COM Off-Capacitance
(CCOM(OFF)) (Note 6)
f = 1MHz, Figure 5
5.5
f = 240 MHz, Figure 5
4.8
COM On-Capacitance
(CCOM(ON)) (Note 6)
f = 1MHz, Figure 5
6.5
f = 240 MHz, Figure 5
5.5
Total Harmonic Distortion Plus
Noise
VCOM_ = 1VP-P, VBIAS = 1V, RL = RS = 50I, f = 20Hz to
20kHz
0.03
%
Human Body Model
±2
kV
Human Body Model
±15
IEC 61000-4-2 Air-Gap Discharge
±15
IEC 61000-4-2 Contact Discharge
±8
pF
pF
USB HIGH-SPEED SWITCH—ESD PROTECTION
ENUSB, CB, NC1, NC2, NO1,
NO2
COM1, COM2
kV
I2C SERIAL INTERFACE (Figure 8)
Clock Frequency
400
kHz
Bus-Free Time Between START
and STOP (tBUF)
1.3
Fs
Hold Time Repeated START
Condition (tHD_STA)
0.6
Fs
SCL Low Period (tLOW)
1.3
Fs
SCL High Period (tHIGH)
0.6
Fs
Setup Time Repeated START
Condition (tSU_STA)
0.6
Fs
SDA Hold Time (tHD_DAT)
0
Fs
SDA Setup time (tSU_DAT)
100
ns
Setup Time for STOP Condition
(tSU_STO)
0.6
Fs
10 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted.
Typical values are at TA = +25NC.) (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
Maximum Pulse Width of
Spikes Suppressed
TYP
MAX
50
UNIT
ns
LOAD SWITCH (LS)
Input Supply Operating Range
(VBUCK)
After VBUCK starts up
On-Resistance (RDS(ON))
VBUCK = 1.0V, ILS = 300mA, TA = +25NC
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSTOD = 0 (Note 6)
Turn-On Delay Time (tON_DLY)
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSTOD = 1
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 0
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 1
LS Rise Time (tR)
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 2
VLS = 2.4V, RL = 400I, VENLS =
1.8V, Register LSRT = 3
Turn-Off Delay Time (tOFF_DLY)
VLS = 2.4V, RL = 400I, VENLS =
1.8V
VLS = 2.4V, RL = 400I, VENLS =
1.8V
LS Fall Time (tF)
Shutdown Output Resistance
0.8
50
CL = 0.1FF
0.85
CL = 1FF
0.85
CL = 3FF
0.85
CL = 0.1FF
30
CL = 1FF
34
CL = 3FF
37
CL = 0.1FF
10
CL = 1FF (Note 6)
10
CL = 3FF (Note 6)
10
CL = 0.1FF
25
CL = 1FF
27
CL = 3FF
30
CL = 0.1FF
100
CL = 1FF
100
CL = 3FF
100
CL = 0.1FF
300
CL = 1FF
300
CL = 3FF
300
CL = 0.1FF
11
CL = 1FF
11
CL = 3FF
11
CL = 0.1FF
15
CL = 1FF
150
CL = 3FF
447
VLS = 2.4V, VENLS = 0V, LS_ADEN = 1
100
2.4
V
100
mI
Fs
Fs
Fs
Fs
200
I
Note 3: VIN1, VIN2, and VBATT are connected together and single input is referred to as VIN.
Note 4: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by
design.
Note 5: When the input voltage is greater than 2.85V (typ), the UVLO comparator trips, and the threshold is reduced to 2.35V
(typ). This allows the system to start normally even if the input voltage decays to 2.35V.
Note 6: Not production tested; guaranteed by design.
Note 7: DRON(MAX) = |RON(CH1) - RON(CH2)|.
Note 8: Flatness is defined as the difference between the maximum and minimum value of on-resistance, as measured over
specified analog signal ranges.
Note 9: Between any two switches.
______________________________________________________________________________________ 11
MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
150
STEP-DOWN AND ALL LDOs
ENUSB = BATT, ENLS = GND
100
VBATT = 3.0V
180
170
160
150
VBATT = 4.2V
140
VBATT = 3.7V
130
120
50
110
STEP-DOWN ONLY
100
2.5
3.0
3.5
4.0
4.5
5.0
10
35
60
TEMPERATURE (°C)
USB SWITCH ON-RESISTANCE
vs. COM VOLTAGE
USB SWITCH ON-RESISTANCE
vs. COM VOLTAGE
5.5
MAX8893A toc03
TA = +25°C
4.5
VBATT = 3.0V
VBATT = 3.7V
VBATT = 4.2V
3.0
85
TA = +85°C
5.0
ON-RESISTANCE (I)
5.0
3.5
-15
SUPPLY VOLTAGE (V)
5.5
4.0
-40
5.5
TA = +60°C
4.5
MAX8893A toc04
0
ON-RESISTANCE (I)
MAX8893A toc02
190
TA = +35°C
4.0
TA = +10°C
TA = -15°C
3.5
TA = -40°C
3.0
FAULT PROTECTION
VBATT = 3.7V
2.5
2.5
1
2
3
4
5
0
6
1
2
3
4
COM VOLTAGE (V)
COM VOLTAGE (V)
COM LEAKAGE CURRENT
vs. TEMPERATURE
LOGIC THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX8893A toc05
45
43
41
39
37
1.4
1.2
THRESHOLD VOLTAGE (V)
0
5
MAX8893A toc06
SUPPLY CURRENT (µA)
200
200
SUPPLY CURRENT (µA)
STEP-DOWN AND ALL LDOs
ENUSB = GND, ENLS = BATT
MAX8893A toc01
250
COM LEAKAGE CURRENT (nA)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
RISING
1.0
0.8
0.6
FALLING
0.4
0.2
0
35
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
12 ��
5.0
5.5
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
LOAD SWITCH ON-RESISTANCE
vs. BATTERY VOLTAGE
LOAD SWITCH ON-RESISTANCE
vs. TEMPERATURE
MAX8893A toc08
80
ON-RESISTANCE (mI)
80
ON-RESISTANCE (mI)
90
MAX8893A toc07
90
70
60
50
70
60
50
VBUCK = 1.0V
VBUCK = 1.0V, ILS = 500mA
40
-40
-15
10
35
60
40
85
2.5
TEMPERATURE (°C)
3.0
3.5
4.0
4.5
5.0
LOAD SWITCH TURN-ON/OFF WAVEFORM
LOAD SWITCH TURN-ON/OFF WAVEFORM
MAX8893A toc09
MAX8893A toc10
VENLS
2V/div
VLS
ILS
2V/div
VENLS
500mV/div
VLS
200mA/div
ILS
500mV/div
2I LOAD
CLS = 1.0µF
10I LOAD, CLS = 1.0µF
20µs/div
20µs/div
LOAD SWITCH VOLTAGE DROP
vs. LOAD CURRENT
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
VBUCK = 1.0V
80
EFFICIENCY (%)
30
20
VBATT = 3.0V
90
70
500mA/div
MAX8893A toc12
100
MAX8893A toc11
40
VBUCK - VLS (mV)
5.5
BATTERY VOLTAGE (V)
VBATT = 3.7V
60
50
VBATT = 4.2V
40
30
10
20
10
0
VBUCK = 1.0V
0
0
100
200
300
LOAD CURRENT (mA)
400
500
0.1
1.0
10
100
1000
LOAD CURRENT (mA)
______________________________________________________________________________________ 13
MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
STEP-DOWN SWITCHING FREQUENCY
vs. LOAD CURRENT
STEP-DOWN OUTPUT VOLTAGE
vs. LOAD CURRENT
3600
1.01
OUTPUT VOLTAGE (V)
3200
2800
2400
2000
1600
1200
800
VBATT = 3.7V
VBATT = 4.2V
1.00
0.99
VBATT = 3.0V
0.98
VBATT = 3.7V
VBUCK = 1.0V
400
MAX8893A toc14
1.02
MAX8893A toc13
4000
SWITCHING FREQUENCY (kHz)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
VBUCK = 1.0V
0.97
0
0
100
200
300
400
0
500
100
200
300
400
LOAD CURRENT (mA)
LOAD CURRENT (mA)
STEP-DOWN LIGHT-LOAD
SWITCHING WAVEFORMS
STEP-DOWN MEDIUM-LOAD
SWITCHING WAVEFORMS
MAX8893A toc15
500
MAX8893A toc16
20mV/div
(AC-COUPLED)
VBUCK
50mV/div
(AC-COUPLED)
VBUCK
2V/div
VLX
IL
100mA/div
1mA LOAD, VBUCK = 1.0V
VLX
IL
2V/div
100mA/div
40mA LOAD, VBUCK = 1.0V
10µs/div
400ns/div
STEP-DOWN HEAVY-LOAD
SWITCHING WAVEFORMS
STEP-DOWN STARTUP AND
SHUTDOWN WAVEFORM
MAX8893A toc17
MAX8893A toc18
20mV/div
(AC-COUPLED)
VBUCK
VLX
2V/div
2V/div
VENBUCK
VBUCK
500mV/div
500mA LOAD, VBUCK = 1.0V
IL
300mA LOAD, VBUCK = 1.0V
400ns/div
200mA/div
IIN
100mA/div
100µs/div
14 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
STEP-DOWN LOAD TRANSIENT WAVEFORM
STEP-DOWN LINE TRANSIENT WAVEFORM
MAX8893A toc20
MAX8893A toc19
4V
500mV/div
VBATT
3.5V
VBUCK
50mV/div
20mA/div
(AC-COUPLED)
VBUCK
300mA
5mA
IOUT
5mA
200mA/div
10I LOAD
10µs/div
20µs/div
LDO1 DROPOUT VOLTAGE
vs. LOAD CURRENT
LDO1 OUTPUT-VOLTAGE ERROR
vs. LOAD CURRENT
100
50
-10
-20
-30
-40
-50
0
0
50
100
150
200
250
50
0
300
100
150
200
250
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO1 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
LDO1 LINE TRANSIENT WAVEFORM
300
MAX8893A toc24
MAX8893A toc23
2.80
2.75
OUTPUT VOLTAGE (V)
MAX8893A toc22
MAX8893A toc21
150
0
OUTPUT-VOLTAGE ERROR (mV)
DROPOUT VOLTAGE (mV)
200
4V
VBATT
500mV/div
3.5V
2.70
2.65
10mV/div
(AC-COUPLED)
VLDO1
2.60
2.55
300mA LOAD
10I LOAD
2.50
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
10µs/div
INPUT VOLTAGE (V)
______________________________________________________________________________________ 15
MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO1 STARTUP AND
SHUTDOWN WAVEFORM
LDO1 LOAD TRANSIENT WAVEFORM
MAX8893A toc25
MAX8893A toc26
300mA
5mA
IOUT
5mA
VENLOD1
2V/div
VLDO1
1V/div
200mA/div
200mV/div
(AC-COUPLED)
VLDO1
300mA LOAD, VLDO1 = 2.8V
500mA/div
IIN
20µs/div
100µs/div
LDO2 DROPOUT VOLTAGE
vs. LOAD CURRENT
LDO2 OUTPUT-VOLTAGE ERROR
vs. LOAD CURRENT
100
50
0
MAX8893A toc28
MAX8893A toc27
150
0
OUTPUT-VOLTAGE ERROR (mV)
DROPOUT VOLTAGE (mV)
200
-10
-20
-30
-40
-50
0
50
100
150
200
250
300
50
0
100
150
200
250
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO2 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
LDO2 LINE TRANSIENT WAVEFORM
300
MAX8893A toc30
MAX8893A toc29
2.65
OUTPUT VOLTAGE (V)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
2.60
4V
VBATT
500mV/div
3.5V
2.55
VLDO2
10mV/div
(AC-COUPLED)
2.50
10I LOAD
300mA LOAD
2.45
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
10µs/div
INPUT VOLTAGE (V)
16 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
LDO2 STARTUP AND
SHUTDOWN WAVEFORM
LDO2 LOAD TRANSIENT WAVEFORM
MAX8893A toc31
MAX8893A toc32
300mA
5mA
IOUT
5mA
VENLDO2
2V/div
VLDO2
1V/div
200mA/div
200mV/div
(AC-COUPLED)
VLDO1
300mA LOAD, VLDO2 = 2.6V
500mA/div
IIN
20µs/div
100µs/div
LDO3 DROPOUT VOLTAGE
vs. LOAD CURRENT
LDO3 OUTPUT-VOLTAGE ERROR
vs. LOAD CURRENT
100
50
0
-10
-20
-30
-40
-50
0
50
100
150
200
250
300
50
0
100
150
200
250
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO3 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
LDO3 LINE TRANSIENT WAVEFORM
300
MAX8893A toc36
MAX8893A toc35
3.3
3.2
OUTPUT VOLTAGE (V)
MAX8893A toc34
MAX8893A toc33
150
0
OUTPUT-VOLTAGE ERROR (mV)
DROPOUT VOLTAGE (mV)
200
3.1
4V
VBATT
500mV/div
3.5V
3.0
2.9
2.8
VLDO3
10mV/div
(AC-COUPLED)
2.7
2.6
300mA LOAD
2.5
2.7
3.1
3.5 3.9 4.3 4.7
INPUT VOLTAGE (V)
5.1
10I LOAD
5.5
10µs/div
______________________________________________________________________________________ 17
MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO3 STARTUP AND
SHUTDOWN WAVEFORM
LDO3 LOAD TRANSIENT WAVEFORM
MAX8893A toc38
MAX8893A toc37
300mA
5mA
5mA
IOUT
VENLDO3
2V/div
VLDO3
2V/div
200mA/div
VLDO3
200mV/div
(AC-COUPLED)
300mA LOAD, VLDO3 = 3.3V
500mA/div
IIN
20µs/div
100µs/div
LDO4 DROPOUT VOLTAGE
vs. LOAD CURRENT
LDO4 OUTPUT-VOLTAGE ERROR
vs. LOAD CURRENT
60
40
20
0
0
30
60
90
LOAD CURRENT (mA)
120
150
MAX8893A toc40
80
0
OUTPUT-VOLTAGE ERROR (mV)
MAX8893A toc39
100
DROPOUT VOLTAGE (mV)
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
-10
-20
-30
-40
-50
0
30
60
90
120
LOAD CURRENT (mA)
18 ��
150
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
LDO4 OUTPUT VOLTAGE
INPUT VOLTAGE
LDO4 LINE TRANSIENT WAVEFORM
MAX8893A toc42
MAX8893A toc41
3.0
OUTPUT VOLTAGE (V)
2.9
4V
500mV/div
VBATT
3.5V
2.8
2.7
VLDO4
10mV/div
(AC-COUPLED)
2.6
20I LOAD
150mA LOAD
2.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
10µs/div
INPUT VOLTAGE (V)
LDO5 DROPOUT VOLTAGE
vs. LOAD CURRENT
LDO4 LOAD TRANSIENT WAVEFORM
MAX8893A toc43
IOUT
5mA
5mA
200mA/div
200mV/div
(AC-COUPLED)
VLDO4
20µs/div
MAX8893A toc44
150mA
DROPOUT VOLTAGE (mV)
150
120
90
60
30
0
0
40
80
120
160
200
LOAD CURRENT (mA)
______________________________________________________________________________________ 19
MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO4 OUTPUT-VOLTAGE ERROR
vs. LOAD CURRENT
LDO5 OUTPUT VOLTAGE
vs. INPUT VOLTAGE
1.01
OUTPUT VOLTAGE (V)
-10
MAX8893A toc46
1.02
MAX8893A toc45
0
OUTPUT-VOLTAGE ERROR (mV)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
-20
-30
1.00
0.99
-40
0.98
-50
0.97
200mA LOAD
0
40
80
120
160
2.7
200
3.1
3.5
3.9
4.3
4.7
5.1
5.5
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
LDO5 LINE TRANSIENT WAVEFORM
LDO5 LOAD TRANSIENT WAVEFORM
MAX8893A toc47
4V
MAX8893A toc48
500mV/div
VBATT
3.5V
200mA
IOUT
VLDO5
10mV/div
(AC-COUPLED)
5mA
5mA
200mA/div
200mV/div
(AC-COUPLED)
VLDO5
5I LOAD
10µs/div
20µs/div
LDO4 AND LDO5 STARTUP
AND SHUTDOWN WAVEFORM
POWER-UP SEQUENCING (MAX8893A)
MAX8893A toc49
VENLDO45
2V/div
VLDO4
2V/div
VLDO5
IIN
MAX8893A toc50
1V/div
VLDO4 = 3.0V, 150mA LOAD
VLDO5 = 1.0V, 200mA LOAD
500mA/div
1.0V
VBUCK
2.8V
2V/div
VLDO1
2.6V
4V/div
4V/div
VLDO2
3.3V
VLDO3
3.0V
VLDO4
1.0V
VLDO5
5V/div
5V/div
2V/div
5I LOAD
100µs/div
2V/div
VEN_
100µs/div
20 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
POWER-UP SEQUENCING (MAX8893B)
POWER-UP SEQUENCING (MAX8893C)
MAX8893A toc51
MAX8893A toc52
2V/div
VEN_
1.0V
VBUCK
2.6V
2V/div
VLDO1
2.6V
4V/div
4V/div
VLDO2
3.3V
VLDO3
3.3V
2.8V
VLDO5
1.0V
VBUCK
1.8V
VLDO1
2.6V
VLDO2
5V/div
VLDO3
5V/div
VLDO4
2V/div
4V/div
4V/div
3.3V
3.3V
5V/div
5V/div
3.0V
VLDO5
5V/div
2V/div
100µs/div
5V/div
100µs/div
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
FREQUENCY RESPONSE
0
MAX8893A toc53
1
RL = 600I
ON-LOSS
-10
-20
THD+N (%)
MAGNITUDE (dB)
0.1
0.01
MAX8893A toc54
VLDO4
VEN_
OFF-ISOLATION
-30
-40
-50
-60
-70
CROSSTALK
-80
-90
0.001
-100
100
1000
10,000
100,000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (Hz)
EYE DIAGRAM
MAX8893A toc55
DIFFERENTIAL SIGNAL (V)
10
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (x 10-9)s
______________________________________________________________________________________ 21
MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Test Circuits/Timing Diagrams
0V OR VCC
CB
NC1
50I
COM1
MAX8893A
MAX8893B
MAX8893C
NO1*
50I
VIN
NETWORK
ANALYZER
50I
MEAS
VOUT
OFF-ISOLATION = 20log
VOUT
VIN
CROSSTALK = 20log
VOUT
VIN
REF
50I
50I
SWITCH IS ENABLED.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
Figure 1. USB High-Speed Switch Off-Isolation and Crosstalk
MAX8893A
MAX8893B
MAX8893C
VIN_
LOGIC
INPUT
COM
NO_
OR NC_
VOUT
RL
VIL
50%
t OFF
CL
EN (EN)
VOUT
LOGIC
INPUT
SWITCH
OUTPUT
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
RL
VOUT = VIN_
RL + RON
(
)
t R < 5ns
t F < 5ns
VIH
0.9 x V0UT
0V
0.1 x VOUT
t ON
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 2. USB High-Speed Switch Switching Time
22 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
RS
VIN+
MAX8893A
MAX8893B
MAX8893C
NC1 OR
NO1
COM1
VOUT+
tPLH = tPLHX OR tPLHY
tPHL = tPHLX OR tPHLY
tSK(O) = |tPLHX - tPLHY| OR |tPHLX - tPHLY|
tSK(P) = |tPLHX - tPHLX| OR |tPLHY - tPHLY|
RL
RS
VIN-
NC2 OR
NO2
COM2
VOUTRL
CB
VIL TO VIH
tINFALL
tINRISE
VCC
90%
VIN+
50%
90%
50%
10%
0V
10%
VCC
VIN-
50%
50%
0V
tOUTRISE
tPLHX
tOUTFALL
tPHLX
VCC
90%
VOUT+
90%
50%
50%
10%
0V
10%
VCC
50%
VOUT-
50%
0V
tPHLY
tPLHY
Figure 3. USB High-Speed Switch Output Signal Skew, Rise/Fall Time, Propagation Delay
______________________________________________________________________________________ 23
MAX8893A/MAX8893B/MAX8893C
Test Circuits/Timing Diagrams (continued)
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Test Circuits/Timing Diagrams (continued)
5V
VCC = 3.3V
3V
COM
VCOM
MAX8893A
MAX8893B
MAX8893C
0V
tFP
tFPR
CB
CAPACITANCE
METER
VFP
VIL OR VIH
NC_ OR
NO_
3V
VNO_
VNC_
0V
Figure 4. USB High-Speed Switch Fault-Protection Response/
Recovery Time
Figure 5. USB High-Speed Switch Channel Off-/On-Capacitance
Pin Configuration
TOP VIEW
(BUMPS ON BOTTIOM)
1
2
3
4
5
6
MAX8893A/MAX8893B/MAX8893C
A
LDO1
LDO2
LDO3
BATT
IN1
LX
B
REFBP
CB
ENUSB
ENLDO1
ENBUCK
PGND
C
IN2
NC1
NC2
ENLDO2
ENLS
BUCK
D
LDO5
NO1
NO2
ENLDO3
ENLDO45
SCL
E
LDO4
COM1
COM2
AGND
LS
SDA
WLP
(3.0mm x 2.5mm)
24 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
PIN
NAME
FUNCTION
A1
LDO1
300mA LDO1 Output. Bypass LDO1 to AGND with a 2.2FF ceramic capacitor. The output voltage
is programmable from 1.6V to 3.3V in 100mV steps. The output impedance of LDO1 is 300I when
disabled with the LDO1_ADEN bit set to 1.
A2
LDO2
300mA LDO2 Output. Bypass LDO2 to AGND with a 2.2FF ceramic capacitor. The output voltage
is programmable from 1.2V to 3.3V in 100mV steps. The output impedance of LDO2 is 300I when
disabled with the LDO2_ADEN bit set to 1.
A3
LDO3
300mA LDO3 Output. Bypass LDO3 to AGND with a 2.2FF ceramic capacitor. The output voltage
is programmable from 1.6V to 3.3V in 100mV steps. The output impedance of LDO3 is 300I when
disabled with the LDO3_ADEN bit set to 1.
A4
BATT
Supply Voltage to the Control Section, LDO2, LDO3, and USB Switch. Connect a 2.2FF ceramic
capacitor from BATT to AGND.
A5
IN1
Supply Voltage to the Step-Down Converter. Connect a 2.2FF input ceramic capacitor from IN1 to
PGND.
A6
LX
Inductor Connection for Step-Down Converter. LX is internally connected to the drain of the internal
p-channel MOSFET and the drain of the internal n-channel synchronous rectifier. The output impedance
of LX is 300I when the step-down converter is disabled with the BUCK_ADEN bit set to 1.
B1
REFBP
Reference Noise Bypass. Bypass REFBP to AGND with a 0.1FF ceramic capacitor to reduce noise on
the LDO outputs. REFBP is high impedance in shutdown.
B2
CB
Digital Control Input for USB High-Speed Switch. Drive CB low to connect COM1 to NC1 and COM2 to
NC2. Drive CB high to connect COM1 to NO1 and COM2 to NO2.
B3
ENUSB
B4
ENLDO1
Enable Input for LDO1. Drive ENLDO1 high to turn on the LDO1. Drive ENLDO1 low to turn off the LDO1.
LDO1 can also be enabled/disabled through the I2C interface. ENLDO1 and I2C control bit are logically
ORed. ENLDO1 has an internal 800kI pulldown resistor.
B5
ENBUCK
Enable Input for the Step-Down Converter. Drive ENBUCK high to turn on the step-down converter.
Drive ENBUCK low to turn off the step-down converter. The step-down converter can also be enabled/
disabled through the I2C interface. ENBUCK and I2C control bit are logically ORed. ENBUCK has an
internal 800kI pulldown resistor.
B6
PGND
C1
IN2
Active-Low Enable Input for USB High-Speed Switch. Drive ENUSB high to put the switch in high
impedance. Drive ENUSB low for normal operation.
Power Ground for Step-Down Converter
Supply Voltage to LDO1, LDO4, and LDO5. Connect a 2.2FF input ceramic capacitor from IN2 to AGND.
______________________________________________________________________________________ 25
MAX8893A/MAX8893B/MAX8893C
Pin Description
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Pin Description (continued)
PIN
NAME
C2
NC1
Normally Closed Terminal for USB Switch 1. NC1 is high impedance in shutdown.
FUNCTION
C3
NC2
Normally Closed Terminal for USB Switch 2. NC2 is high impedance in shutdown.
C4
ENLDO2
C5
ENLS
Enable Input for Load Switch. Drive ENLS high to turn on the load switch. Drive ENLS low to turn off the
load switch. The load switch can also be enabled/disabled through the I2C interface. ENLS and I2C
control bit are logically ORed. ENLS has an internal 800kI pulldown resistor.
C6
BUCK
Voltage Feedback for Step-Down Converter
D1
LDO5
200mA LDO5 Output. Bypass LDO5 to AGND with a 2.2FF ceramic capacitor. The output voltage of
LDO5 is programmable from 0.8V to 3.3V in 100mV steps. The output impedance of LDO5 is 300I when
disabled with the LDO5_ADEN bit set to 1.
D2
NO1
Normally Open Terminal for USB Switch 1. NO1 is high impedance in shutdown.
D3
NO2
Normally Open Terminal for USB Switch 2. NO2 is high impedance in shutdown.
D4
ENLDO3
Enable Input for LDO3. Drive ENLDO3 high to turn on the LDO3. Drive ENLDO3 low to turn off the LDO3.
LDO3 can also be enabled/disabled through the I2C interface. ENLDO3 and I2C control bit are logically
ORed. ENLDO3 has an internal 800kI pulldown resistor.
D5
ENLDO45
Enable Input for LDO4 and LDO5. Drive ENLDO45 high to turn on the LDO4 and LDO5. Drive ENLDO45
low to turn off the LDO4 and LDO5. LDO4 and LDO5 can also be enabled/disabled individually through
the I2C interface. ENLDO45 and I2C control bits (ELDO4 and ELDO5) are logically ORed. ENLDO45 has
an internal 800kI pulldown resistor.
D6
SCL
E1
LDO4
150mA LDO4 Output. Bypass LDO4 to GND with a 1FF ceramic capacitor. The output voltage of LDO4
is programmable from 0.8V to 3.3V in 100mV steps. The output impedance of LDO4 is 300I when
disabled with the LDO4_ADEN bit set to 1.
E2
COM1
Common Terminal for USB High Switch 1
E3
COM2
Common Terminal for USB High Switch 2
E4
AGND
Analog Ground. Ground for all the LDOs, control section, and USB switches.
E5
LS
E6
SDA
Enable Input for LDO2. Drive ENLDO2 high to turn on the LDO2. Drive ENLDO2 low to turn off the LDO2.
LDO2 can also be enabled/disabled through the I2C interface. ENLDO2 and I2C control bit are logically
ORed. ENLDO2 has an internal 800kI pulldown resistor.
I2C-Compatible Serial Interface Clock High-Impedance Input
Load Switch Output. LS is connected to the drain of an internal p-channel MOSFET. VLS = VBUCK RDS(ON) (p-channel MOSFET) x load current.
I2C-Compatible Serial Interface Data High-Impedance Input
26 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
IN2
AGND
BATT
Li+ BATTERY
CIN1
2.2µF
IN1
LS
MAX8893A
MAX8893B
MAX8893C
CLS
1µF
LOAD SWITCH
CONTROL
EN
VBUCK
IN
LX
ENLS
BUCK
VBUCK, 0.8V TO 2.4V
100mV STEP, 500mA
LX
2.2µH
CBUCK
2.2µF
STEP-DOWN
CONVERTER
PGND
EN
IN
SDA
SCL
OUT
PGND
ENBUCK
LDO1
EN
SCL
OUT
IN
I2C AND LOGIC
ENLDO1
OUT
IN
ENLDO2
VLDO3, 1.6V TO 3.3V
100mV STEP, 300mA
CLDO3
2.2µF
EN
OUT
ENLDO3
ENLDO3
VLDO4, 0.8V TO 3.3V
100mV STEP, 150mA
LDO4
CLDO4
1.0µF
LDO4
ANALOG LDO
EN
OUT
IN
ENLDO2
LDO3
LDO3
IN
VLDO2, 1.2V TO 3.3V
100mV STEP, 300mA
CLDO2
2.2µF
EN
REFBP
ENLDO1
LDO2
LDO2
CREFBP
0.1µF
VLDO1, 1.6V TO 3.3V
100mV STEP, 300mA
CLDO1
2.2µF
LDO1
ANALOG LDO
SDA
ENBUCK
ENLDO45
ENLDO45
LDO5
VLDO5, 0.8V TO 3.3V
100mV STEP, 200mA
CLDO5
2.2µF
LDO5
ANALOG LDO
EN
ENUSB
USBSEL
ENUSB
CB
EN
COM1
COM2
IN
USB HIGH S/W
NC1
NC2
NO1
NO2
Figure 6. Block Diagram and Application Circuit
______________________________________________________________________________________ 27
MAX8893A/MAX8893B/MAX8893C
CBATT
2.2µF
CIN2
2.2µF
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Detailed Description
The MAX8893A/MAX8893B/MAX8893C highly integrated power-management ICs integrate a high-efficiency
500mA step-down DC-DC converter, five low-dropout
linear regulators, a load switch with ultra-low on-resistance, a USB high-speed switch, and a 400kHz I2C
serial interface.
The step-down converter delivers over 500mA at I2C
programmable output levels from 0.8V to 2.4V. It uses a
proprietary hysteretic-PWM control scheme that switches up to 4MHz, allowing a trade-off between efficiency
and tiny external components. The step-down converter
also features dynamic voltage scaling (DVS) control. Its
output voltage ramps up with the I2C-controlled ramp
rate from 1mV/Fs to 12mV/Fs.
Five low-dropout linear regulators feature low 45FVRMS
output noise (LDO1, LDO4, and LDO5) and very low
ground currents (LDO2 and LDO3).
The USB high-speed switch is a high ESD-protected
DPDT analog switch. It is ideal for USB 2.0 Hi-Speed
(480Mbps) switching applications and also meets USB
low- and full-speed requirements. The load switch features ultra-low on-resistance and operates from 0.8V
to 2.4V input range. Its rise time is I2C programmable
to control the inrush current. The internal I2C interface
provides flexible control on regulator ON/OFF control,
output voltage setting, step-down dynamic voltage scaling and ramp rate, and load switch timing.
Step-Down DC-DC Converter
Control Scheme
The MAX8893A/MAX8893B/MAX8893C step-down converter is optimized for high-efficiency voltage conversion over a wide load range, while maintaining excellent
transient response, minimizing external component size,
and output voltage ripple. The step-down converter also
features an optimized on-resistance internal MOSFET
switch and synchronous rectifier to maximize efficiency.
The IC utilizes a proprietary hysteretic-PWM control
scheme that switches with nearly fixed frequency up to
4MHz allowing for ultra-small external components. Its
output current is guaranteed up to 500mA.
When the step-down output voltage falls below the regulation threshold, the error comparator begins a switching
cycle by turning on the high-side switch. This switch
remains on until the minimum on-time (tON) expires and
the output voltage is in regulation or the current-limit
threshold is exceeded. Once off, the high-side switch
remains off until the minimum off-time (tOFF) expires
and the output voltage again falls below the regulation
threshold. During the off period, the low-side synchronous rectifier turns on and remains on until either the
high-side switch turns on again or the inductor current
reduces to the rectifier-off current threshold (ILXOFF =
30mA (typ)). The internal synchronous rectifier eliminates the need for an external Schottky diode.
The step-down converter has the internal soft-start circuitry with a fixed ramp to eliminate input current spikes
when it is enabled.
Voltage Positioning Load Regulation
The step-down converter uses a unique feedback network. By taking feedback from the LX node, the usual
phase lag due to the output capacitor is removed, making the loop exceedingly stable and allowing the use of
very small ceramic output capacitors. This configuration
causes the output voltage to shift by the inductor series
resistance multiplied by the load current. This voltagepositioning load regulation greatly reduces overshoot
during load transients, which effectively halves the
peak-to-peak output-voltage excursions compared to
traditional step-down converters.
Dynamic Voltage Scaling (DVS)
Control with Ramp Rate
The step-down output voltage has a variable ramp rate
that is set by the BUCKRAMP bits in the DVS RAMP
CONTROL register. This register controls the outputvoltage ramp rate during a positive voltage change (for
example, from 1.0V to 1.1V), and a negative voltage
change (for example, from 1.1V to 1.0V). Ramp rate
adjustment range is from 1mV/Fs to 12mV/Fs in the step
of 1mV/Fs.
After the step-down converter is in regulation, its output
voltage can dynamically ramp up at the rate set by the
BUCKRAMP bits for a positive voltage change. For a
negative voltage change, the decay rate of the output
voltage depends on the size of the external load: a small
load results in an output-voltage decay that is slower
than the specified ramp rate and LX sinks current from
the output capacitor to actively ramp down the output
voltage; a large load (greater than COUT x Ramp Rate)
results in an output-voltage decay with the specified
ramp rate.
When the step-down converter is disabled, the output
voltage decays to ground at a rate determined by the
output capacitance, internal discharge resistance, and
the external load.
28 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Enable Inputs (ENBUCK, ENLDO_,
ENLS, ENUSB)
The MAX8893A/MAX8893B/MAX8893C have individual enable inputs for each regulator, load switch, and
USB switch. The individual enable inputs (ENBUCK,
ENLDO1, ENLDO2, ENLDO3, ENLDO45, ENLS) are
logically ORed with the corresponding I2C serial interface control bit. ENUSB input is logically NANDed with
the EUSB bit. See Tables 2, 3, and 4 for enable logic
truth tables. The enable inputs (ENBUCK, ENLDO_, and
ENLS) are internally pulled to AGND by an 800kI (typ)
pulldown resistor. ENUSB is internally pulled up to BATT
by an 800kω (typ) pullup resistor.
Any valid enable input signal turns on the MAX8893A/
MAX8893B/MAX8893C. After the IC is up, the I2C interface is active and the IC can be reprogrammed through
the I2C interface. To turn off the IC, both I2C bus and
enable inputs must be low.
Default Regulator Output Voltages
The default regulator output voltages are set as shown
in Table 1. All regulator output voltages (BUCK, LDO1,
LDO2, LDO3, LDO4, and LDO5) are programmable
through the I2C serial interface.
All I2C register values return to the default value when no
enable input signals are present.
Table 1. Default Regulator Output Voltages
PART
BUCK (V)
LDO1 (V)
LDO2 (V)
LDO3 (V)
LDO4 (V)
LDO5 (V)
MAX8893A
1.0
2.8
2.6
3.3
3.0
1.0
MAX8893B
1.0
2.6
2.6
3.3
3.3
2.8
MAX8893C
1.0
1.8
2.6
3.3
3.3
3.0
Table 2. Truth Table for BUCK, LDO1 to LDO3, and Load Switch
ENABLE INPUT (ENBUCK, ENLDO1,
ENLDO2, ENLDO3, OR ENLS)
CORRESPONDING I2C ON/OFF
CONTROL BIT
CORRESPONDING REGULATOR OR
SWITCH
0
0
0
1
Off
On
1
1
0
1
On
On
Table 3. Truth Table for LDO4 and LDO5
ENABLE INPUT
(ENLDO45)
ELDO4 BIT
ELDO5 BIT
LDO4
LDO5
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Off
Off
On
On
On
On
Off
On
Off
On
On
On
______________________________________________________________________________________ 29
MAX8893A/MAX8893B/MAX8893C
Low-Dropout Linear Regulators
The MAX8893A/MAX8893B/MAX8893C contain five lowdropout, low-quiescent-current, high-accuracy, linear
regulators (LDOs). The LDO output voltages are set
through the I2C serial interface. The LDOs include
an internal reference, error amplifier, p-channel pass
transistor, and internal programmable voltage-divider.
Each error amplifier compares the reference voltage to
a feedback voltage and amplifies the difference. If the
feedback voltage is lower than the reference voltage,
the pass-transistor gate is pulled lower, allowing more
current to pass to the output and increasing the output
voltage. If the feedback voltage is too high, the passtransistor gate is pulled up, allowing less current to pass
to the output.
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Table 4. Truth Table for USB Switch
ENUSB
EUSB BIT
USB SWITCH
0
0
On
0
1
1
0
On
On
1
1
Off
Power-Up Sequencing
Drive ENBUCK or ENLDO_ high to turn on the BUCK
converter or the corresponding LDOs. When ENBUCK
and ENLDO_ are connected together and driven from
low to high, all the regulators are turned on with the
preset power-up sequencing. There are time delays
between each regulator to limit input current rush.
The MAX8893A/MAX8893B/MAX8893C have different
power-up time delays between each regulator. See the
Typical Operating Characteristics for details.
Undervoltage Lockout
When VIN rises above the undervoltage lockout threshold (2.85V typ), the MAX8893A/MAX8893B/MAX8893C
can be enabled by driving any EN_ high or ENUSB
low. The UVLO threshold hysteresis is typically 0.5V.
Therefore, if VIN falls below 2.35V (typ), the undervoltage lockout circuitry disables all outputs and all internal
registers are reset to default values.
Reference Noise Bypass (REFBP)
Bypass REFBP to AGND with a 0.1FF ceramic capacitor to reduce noise on the LDO outputs. REFBP is high
impedance in shutdown.
USB High-Speed Switch
The USB high-speed switch is a Q15kV ESD-protected
DPDT analog switch. It is ideal for USB 2.0 Hi-Speed
(480Mbps) switching applications and also meets USB
low- and full-speed requirements.
The USB switch is fully specified to operate from a single
2.7V to 5.5V supply. The switch is based on charge-pumpassisted n-channel architecture. The switch also features a
shutdown mode to reduce the quiescent current.
Digital Control Input
The USB high-speed switch provides a single-bit control
logic input, CB. CB controls the position of the switches
as shown in Figure 7. Driving CB rail-to-rail minimizes
power consumption.
BATT
ENUSB
MAX8893A
MAX8893B
MAX8893C
CB
NC1
COM1
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8893A/MAX8893B/MAX8893C. The
step-down converter and LDOs have independent thermal protection circuits. When the junction temperature
exceeds +160NC, the LDO, or step-down thermaloverload protection circuitry disables the corresponding
regulators, allowing the IC to cool. The LDO thermaloverload protection circuit enables the LDOs after the
LDO junction temperature cools down, resulting in
pulsed LDO outputs during continuous thermal-overload
conditions. The step-down converter’s thermal-overload
protection circuitry enables the step-down converter
after the junction temperature cools down. Thermaloverload protection safeguards the IC in the event of
fault conditions.
NO1
NC2
COM2
NO2
ENUSB
CB
N0_
NC_
COM_
0
0
OFF
ON
—
0
1
ON
OFF
—
1
X
OFF
OFF
HI-Z
X = DON'T CARE.
Figure 7. USB Switch Functional Diagram/Truth Table
30 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Overvoltage Fault Protection
The USB switch features overvoltage fault protection
on COM_. Fault protection protects the switch and USB
transceiver from damaging voltage levels. When voltages on COM_ exceed the fault protection threshold
(VFP), COM_, NC_, and NO_ are high impedance.
Enable Input (ENUSB)
The USB switch features a shutdown mode that reduces
the quiescent current supply and places COM_ in high
impedance. Drive ENUSB high to place the USB switch
in shutdown mode. Drive ENUSB low to allow the USB
switch to enter normal operation.
Load Switch
The MAX8893A/MAX8893B/MAX8893C include an ultralow RON p-channel MOSFET load switch. The switch
has its own enable input, ENLS. When it is enabled, its
output soft-starts with I2C programmed rising time to
avoid inrush current. See Table 8. The switch input is
from the step-down converter output and can operate
over the 0.8V to 2.4V range. With LS_ADEN bit set to 1,
when the switch is disabled, an internal 100ω resistor is
connected between the load switch output and ground
for quick discharging.
I2C Serial Interface
An I2C-compatible, 2-wire serial interface controls all the
regulator output voltages, load switch timing, individual
enable/disable control, and other parameters. The serial
bus consists of a bidirectional serial-data line (SDA) and
a serial-clock input (SCL). The MAX8893A/MAX8893B/
MAX8893C are slave-only devices, relying upon a
master to generate a clock signal. The master initiates
data transfer to and from the MAX8893A/MAX8893B/
MAX8893C and generates SCL to synchronize the data
transfer (Figure 8).
I2C is an open-drain bus. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage
through a pullup resistor. They both have Schmitt triggers and filter circuits to suppress noise spikes on the
bus to assure proper device operation.
SDA
tSU,STA
tSU,DAT
tLOW
tBUF
tHD,STA
tHD,DAT
tSU,STO
tHIGH
SCL
tHD,STA
tR
tF
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 8. 2-Wire Serial Interface Timing Detail
______________________________________________________________________________________ 31
MAX8893A/MAX8893B/MAX8893C
Analog Signal Levels
The on-resistance of the USB switch is very low and
stable as the analog input signals are swept from ground
to VIN (see the Typical Operating Characteristics). These
switches are bidirectional, allowing NO_, NC_, and
COM_ to be configured as either inputs or outputs. The
charge-pump-assisted n-channel architecture allows the
switch to pass analog signals that exceed VIN up to the
overvoltage fault protection threshold. This allows USB
signals that exceed VIN to pass, allowing compliance
with USB requirements for voltage levels.
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Slave Address
A bus master initiates communication with a slave
device (MAX8893A/MAX8893B/MAX8893C) by issuing
a START condition followed by the slave address. The
slave address byte consists of 7 address bits (0111110)
and a read/write bit (RW). Its address is 0x7C for write
operations and 0x7D for read operations. After receiving the proper address, the MAX8893A/MAX8893B/
MAX8893C issue an acknowledge by pulling SDA low
during the ninth clock cycle.
Bit Transfer
Each data bit, from the most significant bit to the least
significant bit, is transferred one by one during each
clock cycle. During data transfer, the SDA signal is
allowed to change only during the low period of the SCL
clock and it must remain stable during the high period of
the SCL clock (Figure 9).
START and STOP Conditions
Both SCL and SDA remain high when the bus is not busy.
The master signals the beginning of a transmission with
a START (S) condition by transitioning SDA from high to
low while SCL is high. When the master has finished communicating with the MAX8893A/MAX8893B/MAX8893C,
it issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 10). Both START and STOP
conditions are generated by the bus master.
SCL
SDA
DATA LINE STABLE
DATA VALID
START
CONDITION
(S)
DATA ALLOWED TO
CHANGE
STOP
CONDITION
(P)
Figure 9. Bit Transfer
SDA
SCL
START
CONDITION
STOP
CONDITION
Figure 10. START and STOP Conditions
32 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Write Operation
The MAX8893A/MAX8893B/MAX8893C recognize the
write-byte protocol as defined in the SMBus™ specification and shown in section A of Figure 12. The write-byte
protocol allows the I2C master device to send 1 byte of
data to the slave device. The write-byte protocol requires
a register pointer address for the subsequent write.
The MAX8893A/MAX8893B/MAX8893C acknowledge
any register pointer even though only a subset of those
registers actually exists in the device. The write-byte
protocol is as follows:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed by
a write bit (0x7C).
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) The master sends a STOP condition.
In addition to the write-byte protocol, the MAX8893A/
MAX8893B/MAX8893C can write to multiple registers as
SDA BY MASTER
D7
D0
D6
NOT ACKNOWLEDGE
SDA BY SLAVE
ACKNOWLEDGE
SCL
1
2
START CONDITION
8
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 11. Acknowledge
shown in section B of Figure 12. This protocol allows the
I2C master device to address the slave only once and
then send data to a sequential block of registers starting
at the specified register pointer.
Use the following procedure to write to a sequential
block of registers:
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit (0x7C).
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends the 8-bit register pointer of the
first register to write.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
10) The master sends a STOP condition.
SMBus is a trademark of Intel Corp.
______________________________________________________________________________________ 33
MAX8893A/MAX8893B/MAX8893C
Acknowledge
The acknowledge bit is used by the recipient to handshake the receipt of each byte of data (Figure 11). After
data transfer, the master generates the acknowledge
clock pulse and the recipient pulls down the SDA line
during this acknowledge clock pulse, such that the SDA
line stays low during the high duration of the clock pulse.
When the master transmits the data to the MAX8893A/
MAX8893B/MAX8893C, it releases the SDA line and the
MAX8893A/MAX8893B/MAX8893C take the control of
the SDA line and generate the acknowledge bit. When
SDA remains high during this 9th clock pulse, this is
defined as the not acknowledge signal. The master
can then generate either a STOP condition to abort the
transfer, or a REPEATED START condition to start a new
transfer.
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
A. WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
S
7
SLAVE ADDRESS
1
1
8
1
8
1
1
NUMBER OF BITS
0
A
REGISTER POINTER
A
DATA
A
P
8
1
8
1
A
DATA X+1
A
R/W
B. WRITING TO MULTIPLE REGISTERS
1
7
1
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
8
1
8
DATA X+n-1
A
DATA X+n
DATA X
R/W
1
NUMBER OF BITS
NUMBER OF BITS
A P
Figure 12. Writing to the MAX8893A/MAX8893B/MAX8893C
Read Operation
The method for reading a single register (byte) is shown
in section A of Figure 13. To read a single register:
section B of Figure 13. Use the following procedure to
read a sequential block of registers:
1)
The master sends a start command.
1)
The master sends a start command.
2)
2)
The master sends the 7-bit slave address followed
by a read bit (0x7D).
The master sends the 7-bit slave address followed
by a read bit (0x7D).
3)
3)
The addressed slave asserts an acknowledge by
pulling SDA low.
The addressed slave asserts an acknowledge by
pulling SDA low.
4)
4)
The master sends an 8-bit register pointer.
The master sends an 8-bit register pointer of the
first register in the block.
5)
The slave acknowledges the register pointer.
5)
The slave acknowledges the register pointer.
6)
The master sends a REPEATED START condition.
6)
The master sends a REPEATED START condition.
7)
The master sends the 7-bit slave address followed
by a read bit.
7)
The master sends the 7-bit slave address followed
by a read bit.
8)
The slave asserts an acknowledge by pulling SDA low.
8)
The slave asserts an acknowledge by pulling SDA low.
9)
The slave sends the 8-bit data (contents of the register).
9)
The slave sends the 8-bit data (contents of the register).
10) The master asserts an acknowledge by pulling
SDA low.
11) The master sends a STOP condition.
In addition, the MAX8893A/MAX8893B/MAX8893C can
read a block of multiple sequential registers as shown in
10) The master asserts an acknowledge by pulling SDA low.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
12) The master sends a STOP condition.
34 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
MASTER TO
SLAVE
SLAVE TO
MASTER
A. READING A SINGLE REGISTER
1
S
7
SLAVE ADDRESS
1
1
8
1
0
A
REGISTER POINTER
1
A Sr
8
1
1
SLAVE ADDRESS
1
A
8
DATA
1
1
A
P
NUMBER OF BITS
R/W
B. READING MULTIPLE REGISTERS
1
7
1
1
8
1
1
8
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
Sr
SLAVE ADDRESS
R/W
1 1
1
A
8
1
DATA X
A
NUMBER OF BITS
R/W
8
DATA X+1
1
8
A ...
DATA X+n-1
1
8
A
DATA X+n
1
1
NUMBER OF BITS
A P
Figure 13. Reading from the MAX8893A/MAX8893B/MAX8893C
Table 5. Register Map
NAME
TABLE
REGISTER
ADDRESS
(hex)
RESET
VALUE
TYPE
DESCRIPTION
ON/OFF CONTROL
Table 6
0x00
0x01
R/W
BUCK, LDO1–LDO5, load switch, and USB
switch ON/OFF control
ACTIVE DISCHARGE
CONTROL
Table 7
0x01
0xFF
R/W
Active discharge enable/disable control for
step-down converter and LDO regulators
LS TIME CONTROL
Table 8
0x02
0x08
R/W
Load switch rising time, turn-on, and turnoff delay time control
DVS RAMP CONTROL
Table 9
0x03
0x09
R/W
BUCK enable and ramp rate control
BUCK
Table 10
0x04
0x02
R/W
BUCK output voltage setting
LDO1
Table 11
0x05
0x0C
0x0A
0x02
R/W
LDO1 output voltage setting
LDO2
Table 12
0x06
0x0E
R/W
LDO2 output voltage setting
LDO3
Table 13
0x07
0x11
R/W
LDO3 output voltage setting
R/W
LDO4 output voltage setting
LDO5 output voltage setting
LDO4
Table 14
0x08
0x16
0x19
LDO5
Table 15
0x09
0x02
0x14
0x16
R/W
SVER
Table 16
0x46
N/A
R only
Die type information
______________________________________________________________________________________ 35
MAX8893A/MAX8893B/MAX8893C
LEGEND
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Table 6. On/Off Control
This register contains BUCK, LDO1−LDO5, USB switch, and load switch ON/OFF controls.
REGISTER NAME
ON/OFF CONTROL
Register Pointer
0x00
Reset Value
0x01
Type
Read/write
Special Features
BIT
—
NAME
DESCRIPTION
DEFAULT VALUE
0 = BUCK is disabled
1 = BUCK is enabled
0
0 = Load switch is disabled
1 = Load switch is enabled
0
B7 (MSB)
EBUCK
B6
ELS
B5
ELDO1
0 = LDO1 is disabled
1 = LDO1 is enabled
0
B4
ELDO2
0 = LDO2 is disabled
1 = LDO2 is enabled
0
B3
ELDO3
0 = LDO3 is disabled
1 = LDO3 is enabled
0
B2
ELDO4
0 = LDO4 is disabled
1 = LDO4 is enabled
0
B1
ELDO5
0 = LDO5 is disabled
1 = LDO5 is enabled
0
B0 (LSB)
EUSB
0 = USB switch is enabled
1 = USB switch is disabled
1
36 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
This register contains the active discharge enable bits for the BUCK, load switch, and LDO1−LDO5.
REGISTER NAME
ACTIVE DISCHARGE CONTROL
Register Pointer
0x01
Reset Value
0xFF
Type
Read/write
Special Features
BIT
—
NAME
DESCRIPTION
DEFAULT VALUE
0 = BUCK active discharge is disabled
1 = BUCK active discharge is enabled
1
0 = Load switch active discharge is disabled
1 = Load switch active discharge is enabled
1
B7 (MSB)
BUCK_ADEN
B6
LS_ADEN
B5
LDO1_ADEN
0 = LDO1 active discharge is disabled
1 = LDO1 active discharge is enabled
1
B4
LDO2_ADEN
0 = LDO2 active discharge is disabled
1 = LDO2 active discharge is enabled
1
B3
LDO3_ADEN
0 = LDO3 active discharge is disabled
1 = LDO3 active discharge is enabled
1
B2
LDO4_ADEN
0 = LDO4 active discharge is disabled
1 = LDO4 active discharge is enabled
1
B1
LDO5_ADEN
0 = LDO5 active discharge is disabled
1 = LDO5 active discharge is enabled
1
B0 (LSB)
—
Reserved for future use
—
______________________________________________________________________________________ 37
MAX8893A/MAX8893B/MAX8893C
Table 7. Active Discharge Control
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
Table 8. LS Time Control
This register contains the load switch timing controls.
REGISTER NAME
LS TIME CONTROL
Register Pointer
0x02
Reset Value
0x08
Type
Read/write
Special Features
—
BIT
NAME
B7 (MSB)
—
Reserved for future use
—
B6
—
Reserved for future use
—
B5
—
Reserved for future use
—
Load switch rising time control
00 = 10Fs
01 = 27Fs
10 = 100Fs
11 = 300Fs
01
LSTOD
Load switch turn-on delay time control
0 = Load switch turn-on delay OFF
1 = Load switch turn-on delay is 34Fs
0
LSTOFFD
Load switch turn-off delay time control
00 = 11Fs
01 = 63Fs
10 = 177Fs
11 = 11Fs
00
B4
LSRT
B3
B2
B1
B0 (LSB)
DESCRIPTION
DEFAULT VALUE
38 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
This register contains DVS enable/disable and ramp rate control for the step-down converter.
REGISTER NAME
DVS RAMP CONTROL
Register Pointer
0x03
Reset Value
0x09
Type
Read/write
Special Features
—
BIT
NAME
B7 (MSB)
—
Reserved for future use
—
B6
—
Reserved for future use
—
B5
—
Reserved for future use
—
B4
ENDVS
0 = BUCK DVS is disabled
1 = BUCK DVS is enabled
0
B3
B2
BUCKRAMP
B1
B0 (LSB)
DESCRIPTION
Step-down output voltage ramp rate control
0000 (0x0) = 1mV/Fs
0001 (0x1) = 2mV/Fs
0010 (0x2) = 3mV/Fs
0011 (0x3) = 4mV/Fs
0100 (0x4) = 5mV/Fs
0101 (0x5) = 6mV/Fs
0110 (0x6) = 7mV/Fs
0111 (0x7) = 8mV/Fs
1000 (0x8) = 9mV/Fs
1001 (0x9) = 10mV/Fs
1010 (0xA) = 11mV/Fs
1011 (0xB) = 12mV/Fs
DEFAULT VALUE
1001
(0x9)
______________________________________________________________________________________ 39
MAX8893A/MAX8893B/MAX8893C
Table 9. DVS Ramp Control
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
Table 10. Buck
This register contains the step-down converter output voltage controls.
REGISTER NAME
BUCK
Register Pointer
0x04
Reset Value
0x02
Type
Read/write
Special Features
BIT
—
NAME
B7 (MSB)
B6
B5
B4
BUCK
B3
B2
B1
B0 (LSB)
DESCRIPTION
DEFAULT VALUE
00000000 (0x00) = 0.8V
00000001 (0x01) = 0.9V
00000010 (0x02) = 1.0V
00000011 (0x03) = 1.1V
00000100 (0x04) = 1.2V
00000101 (0x05) = 1.3V
00000110 (0x06) = 1.4V
00000111 (0x07) = 1.5V
00001000 (0x08) = 1.6V
00001001 (0x09) = 1.7V
00001010 (0x0A) = 1.8V
00001011 (0x0B) = 1.9V
00001100 (0x0C) = 2.0V
00001101 (0x0D) = 2.1V
00001110 (0x0E) = 2.2V
00001111 (0x0F) = 2.3V
00010000 (0x10) = 2.4V
40 ��
00000010
(0x02)
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
This register contains LDO1 output voltage controls.
REGISTER NAME
ON/OFF CONTROL
Register Pointer
0x05
0x0C (MAX8893A)
0x0A (MAX8893B)
0x02 (MAX8893C)
Reset Value
Type
Read/write
Special Features
BIT
—
NAME
B7 (MSB)
B6
B5
B4
LDO1
B3
B2
B1
B0 (LSB)
DESCRIPTION
00000000 (0x00) = 1.6V
00000001 (0x01) = 1.7V
00000010 (0x02) = 1.8V
00000011 (0x03) = 1.9V
00000100 (0x04) = 2.0V
00000101 (0x05) = 2.1V
00000110 (0x06) = 2.2V
00000111 (0x07) = 2.3V
00001000 (0x08) = 2.4V
00001001 (0x09) = 2.5V
00001010 (0x0A) = 2.6V
00001011 (0x0B) = 2.7V
00001100 (0x0C) = 2.8V
00001101 (0x0D) = 2.9V
00001110 (0x0E) = 3.0V
00001111 (0x0F) = 3.1V
00010000 (0x10) = 3.2V
00010001 (0x11) = 3.3V
DEFAULT VALUE
MAX8893A
00001100 (0x0C)
MAX8893B
00001010 (0x0A)
MAX8893C
00000010 (0x02)
______________________________________________________________________________________ 41
MAX8893A/MAX8893B/MAX8893C
Table 11. LDO1
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
Table 12. LDO2
This register contains LDO2 output voltage controls.
REGISTER NAME
LDO2
Register Pointer
0x06
Reset Value
0x0E
Type
Read/write
Special Features
BIT
—
NAME
B7 (MSB)
B6
B5
B4
B3
B2
B1
B0 (LSB)
LDO2
DESCRIPTION
00000000 (0x00) = 1.2V
00000001 (0x01) = 1.3V
00000010 (0x02) = 1.4V
00000011 (0x03) = 1.5V
00000100 (0x04) = 1.6V
00000101 (0x05) = 1.7V
00000110 (0x06) = 1.8V
00000111 (0x07) = 1.9V
00001000 (0x08) = 2.0V
00001001 (0x09) = 2.1V
00001010 (0x0A) = 2.2V
00001011 (0x0B) = 2.3V
00001100 (0x0C) = 2.4V
00001101 (0x0D) = 2.5V
00001110 (0x0E) = 2.6V
00001111 (0x0F) = 2.7V
00010000 (0x10) = 2.8V
00010001 (0x11) = 2.9V
00010010 (0x12) = 3.0V
00010011 (0x13) = 3.1V
00010100 (0x14) = 3.2V
00010101 (0x15) = 3.3V
DEFAULT VALUE
00001110 (0x0E)
42 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
This register contains LDO3 output voltage controls.
REGISTER NAME
LDO3
Register Pointer
0x07
Reset Value
0x11
Type
Read/write
Special Features
BIT
—
NAME
B7 (MSB)
B6
B5
B4
LDO3
B3
B2
B1
B0 (LSB)
DESCRIPTION
00000000 (0x00) = 1.6V
00000001 (0x01) = 1.7V
00000010 (0x02) = 1.8V
00000011 (0x03) = 1.9V
00000100 (0x04) = 2.0V
00000101 (0x05) = 2.1V
00000110 (0x06) = 2.2V
00000111 (0x07) = 2.3V
00001000 (0x08) = 2.4V
00001001 (0x09) = 2.5V
00001010 (0x0A) = 2.6V
00001011 (0x0B) = 2.7V
00001100 (0x0C) = 2.8V
00001101 (0x0D) = 2.9V
00001110 (0x0E) = 3.0V
00001111 (0x0F) = 3.1V
00010000 (0x10) = 3.2V
00010001 (0x11) = 3.3V
DEFAULT VALUE
00010001 (0x11)
______________________________________________________________________________________ 43
MAX8893A/MAX8893B/MAX8893C
Table 13. LDO3
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Table 14. LDO4
This register contains LDO4 output voltage controls.
REGISTER NAME
LDO4
Register Pointer
0x08
0x16(MAX8893A)
0x19(MAX8893B/MAX8893C)
Reset Value
Type
Read/write
Special Features
BIT
—
NAME
B7 (MSB)
B6
B5
B4
LDO4
B3
B2
B1
B0 (LSB)
DESCRIPTION
00000000 (0x00) = 0.8V
00000001 (0x01) = 0.9V
00000010 (0x02) = 1.0V
00000011 (0x03) = 1.1V
00000100 (0x04) = 1.2V
00000101 (0x05) = 1.3V
00000110 (0x06) = 1.4V
00000111 (0x07) = 1.5V
00001000 (0x08) = 1.6V
00001001 (0x09) = 1.7V
00001010 (0x0A) = 1.8V
00001011 (0x0B) = 1.9V
00001100 (0x0C) = 2.0V
00001101 (0x0D) = 2.1V
00001110 (0x0E) = 2.2V
00001111 (0x0F) = 2.3V
00010000 (0x10) = 2.4V
00010001 (0x11) = 2.5V
00010010 (0x12) = 2.6V
00010011 (0x13) = 2.7V
00010100 (0x14) = 2.8V
00010101 (0x15) = 2.9V
00010110 (0x16) = 3.0V
00010111 (0x17) = 3.1V
00011000 (0x18) = 3.2V
00011001 (0x19) = 3.3V
DEFAULT VALUE
MAX8893A
00010110 (0x16)
MAX8893B
/MAX8893C
00011001 (0x19)
44 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
This register contains LDO5 output voltage controls.
REGISTER NAME
LDO5
Register Pointer
0x09
0x02 (MAX8893A)
0x14 (MAX8893B)
0x16 (MAX8893C)
Reset Value
Type
Read/write
Special Features
BIT
—
NAME
B7 (MSB)
B6
B5
B4
LDO5
B3
B2
B1
B0 (LSB)
DESCRIPTION
00000000 (0x00) = 0.8V
00000001 (0x01) = 0.9V
00000010 (0x02) = 1.0V
00000011 (0x03) = 1.1V
00000100 (0x04) = 1.2V
00000101 (0x05) = 1.3V
00000110 (0x06) = 1.4V
00000111 (0x07) = 1.5V
00001000 (0x08) = 1.6V
00001001 (0x09) = 1.7V
00001010 (0x0A) = 1.8V
00001011 (0x0B) = 1.9V
00001100 (0x0C) = 2.0V
00001101 (0x0D) = 2.1V
00001110 (0x0E) = 2.2V
00001111 (0x0F) = 2.3V
00010000 (0x10) = 2.4V
00010001 (0x11) = 2.5V
00010010 (0x12) = 2.6V
00010011 (0x13) = 2.7V
00010100 (0x14) = 2.8V
00010101 (0x15) = 2.9V
00010110 (0x16) = 3.0V
00010111 (0x17) = 3.1V
00011000 (0x18) = 3.2V
00011001 (0x19) = 3.3V
DEFAULT VALUE
MAX8893A
00000010 (0x02)
MAX8893B
00010100 (0x14)
MAX8893C
00010110 (0x16)
______________________________________________________________________________________ 45
MAX8893A/MAX8893B/MAX8893C
Table 15. LDO5
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
Table 16. SVER
This register contains the MAX8893A/MAX8893B/MAX8893C version number.
REGISTER NAME
SVER
Register Pointer
0x46
Reset Value
N/A
Type
Read
Special Features
—
BIT
NAME
B7 (MSB)
—
Reserved for future use
—
B6
—
Reserved for future use
—
B5
—
Reserved for future use
—
B4
—
Reserved for future use
—
B3
—
Reserved for future use
—
B2
—
Reserved for future use
—
00 = MAX8893A
01 = MAX8893B
10 = MAX8893C
—
B1
SVER
B0 (LSB)
DESCRIPTION
Applications Information
Step-Down Converter
Input Capacitor
The input capacitor, CIN1, reduces the current peaks
drawn from the battery or input power source and reduces switching noise in the IC. The impedance of CIN1 at
the switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R temperature characteristics
are highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the step-down
converter’s fast soft-start, the input capacitance can be
very low. For most applications, a 2.2FF capacitor is sufficient. Connect CIN1 as close as possible to the IC to
minimize the impact of PCB trace inductance.
For other input capacitors, use a 2.2FF ceramic capacitor from IN2 to ground and a 2.2FF ceramic capacitor
from BATT to ground.
Output Capacitor
The output capacitor, CBUCK, is required to keep the
output voltage ripple small and to ensure regulation loop
stability. CBUCK must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R
temperature characteristics are highly recommended
due to their small size, low ESR, and small temperature
coefficients. Due to the unique feedback network, the
DEFAULT VALUE
output capacitance can be very low. For most applications a 2.2FF capacitor is sufficient. For optimum loadtransient performance and very low output ripple, the
output capacitor value in FF should be equal to or larger
than the inductor value in FH.
Inductor Selection
The recommended inductor for the step-down converter
is from 1.0FH and 4.7FH. Low inductance values are
physically smaller, but require faster switching, resulting
in some efficiency loss. The inductor’s DC current rating
needs to be only 100mA greater than the application’s
maximum load current because the step-down converter
features zero current overshoot during startup and load
transients.
For output voltages above 2.0V, when light load efficiency is important, the minimum recommended inductor is
2.2FH. For optimum voltage-positioning load transients,
choose an inductor with DC series resistance in the
50mω to 150mω range. To achieve higher efficiency at
heavy loads (above 200mA) or minimum load regulation
(but some transient overshoot), the inductor resistance
should be kept below 100mω. For light -oad applications
up to 200mA, much higher resistance is acceptable with
very little impact on performance. See Table 17 for some
suggested inductors.
46 ��
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
MANUFACTURER
Taiyo Yuden
SERIES
INDUCTANCE
(FH)
ESR
(mI)
ISAT
(mA)
DIMENSIONS
(LTYP O WTYP O HMAX)
(mm)
LB2012
1.0
2.2
150
230
300
240
2.0 x 1.25 x 1.45
LB2016
1.0
1.5
2.2
3.3
90
110
130
200
455
350
315
280
2.0 x 1.6 x 1.8
LB2518
1.0
1.5
2.2
3.3
60
70
90
110
500
400
340
270
2.5 x 1.8 x 2.0
LBC2518
1.0
1.5
2.2
3.3
4.7
80
110
130
160
200
775
660
600
500
430
2.5 x 1.8 x 2.0
LQH32C_53
1.0
2.2
4.7
60
100
150
1000
790
650
3.2 x 2.5 x 1.7
LQM43FN
2.2
4.7
100
170
400
300
4.5 x 3.2 x 0.9
D310F
1.5
2.2
3.3
130
170
190
1230
1080
1010
3.6 x 3.6 x 1.0
D312C
1.5
2.2
2.7
3.3
100
120
150
170
1290
1140
980
900
3.6 x 3.6 x 1.2
CDRH2D11
1.5
2.2
3.3
4.7
50
80
100
140
900
780
600
500
3.2 x 3.2 x 1.2
Murata
TOKO
Sumida
______________________________________________________________________________________ 47
MAX8893A/MAX8893B/MAX8893C
Table 17. Suggested Inductors
MAX8893A/MAX8893B/MAX8893C
FPMIC for Multimedia Application Processor
in 2.5mm x 3.0mm WLP
Capacitors for LDOs
For LDOs, the required output capacitance is dependent on the load currents. With rated maximum load
currents, 2.2FF (typ) capacitors are recommended for
LDO1, LDO2, LDO3, and LDO5 and a 1.0FF capacitor is
recommended for LDO4. For loads less than 150mA, it
is sufficient to use 1.0FF capacitors for stable operation
over the full temperature range for LDO1, LDO2, LDO3,
and LDO5. Reduce output noise and improve load transient response, stability, and power-supply rejection by
using larger output capacitors.
USB High-Speed Switch
USB Switching
The USB high-speed switch is fully compliant with the
USB 2.0 specification. The low on-resistance and low
on-capacitance of these switches make it ideal for highperformance switching applications. It is ideal for routing
USB data lines (see Figure 14) and for applications that
require switching between multiple USB hosts (see Figure
15). The USB switch also features overvoltage fault protection to guard systems against shorts to the USB VBUS
voltage that is required for all USB applications.
Extended ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
COM1 and COM2 are further protected against static
electricity. The state-of-the-art structures are developed
to protect these pins against ESD up to ±15kV without
damage. The ESD structures withstand high ESD in normal operation and when the device is powered down.
After an ESD event, the USB switch continues to function
without latchup.
The USB high-speed switch is characterized for protection to the following limits:
ASIC I
D+
HI-SPEED
USB
TRANSCEIVER
DNC1
MAX8893A
MAX8893B
MAX8893C
NO1
VBUS
COM1
D+
NC2
COM2
ASIC II
NO2
D-
D+
HI-SPEED
USB
TRANSCEIVER
DGND
USB
CONNECTOR
Figure 14. USB Data Routing/Typical Application Circuit
MAX8893A
MAX8893B
MAX8893C
D+
NC1
D+
COM1
HI-SPEED
USB
TRANSCEIVER
D-
USB
HOST I
NO1
NC2
D-
COM2
NO2
D+
U ±15kV using Human Body Model
U ±8kV using IEC 61000-4-2 Contact Discharge method
D-
U ±15kV using IEC 61000-4-2 Air-Gap Discharge method
Figure 15. Switching Between Multiple USB Hosts
48 ��
USB
HOST II
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
USB Hi-Speed requires careful PCB layout with 45ω
controlled-impedance matched traces of equal lengths.
Ensure that bypass capacitors are as close as possible
to the IC. Use large ground planes where possible.
Refer to the MAX8893 evaluation kit for an example PCB
layout design.
Typical Operating Circuit
INPUT
2.7V TO 5.5V
LS
IN1
1.0µF
2.2µF
BUCK
LX
IN2
2.2µF
2.2µF
0.1µF
AGND
SDA
ENLS
ENBUCK
LDO1 ON/OFF
ENLDO1
LDO2 ON/OFF
ENLDO2
LDO3 ON/OFF
ENLDO3
ENLDO45
VLDO1
1.6V TO 3.3V
LDO1
SCL
BUCK ON/OFF
LDO4/LDO5 ON/OFF
2.2µH
REFBP
2.2µF
LS ON/OFF
VBUCK
0.8V TO 2.4V
PGND
BATT
I 2C
VLS
2.2µF
MAX8893A
MAX8893B
MAX8893C
VLDO2
1.2V TO 3.3V
LDO2
2.2µF
VLDO3
1.6V TO 3.3V
LDO3
2.2µF
VLDO4
0.8V TO 3.3V
LDO4
1µF
VLDO5
0.8V TO 3.3V
LDO5
2.2µF
USB ON/OFF
USBSEL
ENUSB
NC1
CB
NC2
COM1
NO1
COM2
NO2
______________________________________________________________________________________ 49
MAX8893A/MAX8893B/MAX8893C
PCB Layout and Routing
High switching frequencies and relatively large peak
currents make the PCB layout a very important aspect
of design. Good design minimizes excessive EMI on the
voltage gradients in the ground plane that can result in
instability or regulation errors. Connect the input and output capacitors as close as possible to the IC. Connect
the inductor as close as possible to the IC and keep the
traces short, direct, and wide. Connect AGND to the
exposed pad directly under the IC. Connect AGND and
PGND to the ground plane. Keep noisy traces, such as
the LX node, as short as possible.
MAX8893A/MAX8893B/MAX8893C
µPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suffix character, but the drawing pertains to the package
regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
30 WLP
W302A3+2
21-0016
50 ��
µFPMICs for Multimedia Application Processors
in a 3.0mm x 2.5mm WLP
REVISION REVISION
NUMBER
DATE
DESCRIPTION
PAGES
CHANGED
0
10/09
Initial release
—
1
2/10
Added new TOCs 53, 54, and 55 to Typical Operating Characteristics section
21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010
Maxim Integrated Products 51
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX8893A/MAX8893B/MAX8893C
Revision History

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