GS8342R08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36, x18 and x9) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available SigmaDDR™ Family Overview The GS8342R08/09/18/36BD are built in compliance with the SigmaDDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342R08/09/18/36BD SigmaDDR-II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8342R08/09/18/36BD SigmaDDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each internal read and write operation in a SigmaDDR-II B4 RAM is four times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. When a new address is loaded into a x18 or x36 version of the part, A0 and A1 are used to initialize the pointers that control the data multiplexer / de-multiplexer so the RAM can perform "critical word first" operations. From an external address point of view, regardless of the starting point, the data transfers always follow the same linear sequence {00, 01, 10, 11} or {01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where the digits shown represent A1, A0). Unlike the x18 and x36 versions, the input and output data multiplexers of the x8 and x9 versions are not preset by address inputs and therefore do not allow "critical word first" operations. The address fields of the x8 and x9 SigmaDDR-II B4 RAMs are two address pins less than the advertised index depth (e.g., the 4M x 8 has a 1M addressable index, and A0 and A1 are not accessible address pins). Parameter Synopsis Rev: 1.02 6/2012 -400 -350 -333 -300 -250 tKHKH 2.5 ns 2.86 ns 3.0 ns 3.3 ns 4.0 ns tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 1/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 1M x 36 SigmaDDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/SA (144Mb) SA R/W BW2 K BW1 LD SA NC/SA (72Mb) CQ B NC DQ27 DQ18 SA BW3 K BW0 SA NC/SA (288Mb) NC DQ8 C NC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10 P NC NC DQ26 SA SA C SA SA NC DQ9 DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes to DQ27:DQ35. 2. A2, A10, and B9 are the expansion addresses. Rev: 1.02 6/2012 2/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 2M x 18 SigmaDDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/SA (72Mb) SA R/W BW1 K NC/SA (144Mb) LD SA SA CQ B NC DQ9 NC SA NC/SA (288Mb) K BW0 SA NC NC DQ8 C NC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS SA SA SA VSS NC NC NC P NC NC DQ17 SA SA C SA SA NC NC DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17. 2. A2, A7, and B5 are the expansion addresses. Rev: 1.02 6/2012 3/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 4M x 9 SigmaDDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/SA (72Mb) SA R/W NC K NC/SA (144Mb) LD SA SA CQ B NC NC NC SA NC/SA (288Mb) K BW0 SA NC NC DQ4 C NC NC NC VSS SA NC SA VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ5 VDDQ VSS VSS VSS VDDQ NC NC DQ3 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ6 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ2 NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC DQ7 NC VDDQ VSS VSS VSS VDDQ NC NC DQ1 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS SA SA SA VSS NC NC NC P NC NC DQ8 SA SA C SA SA NC NC DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to 0 at the beginning of each access. 2. BW0 controls writes to DQ0:DQ8. 3. A2, A7, and B5 are the expansion addresses. Rev: 1.02 6/2012 4/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 4M x 8 SigmaDDR-II SRAM—Top View 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/SA (72Mb) SA R/W NW1 K NC/SA (144Mb) LD SA SA CQ B NC NC NC SA NC/SA (288Mb) K NW0 SA NC NC DQ3 C NC NC NC VSS SA NC SA VSS NC NC NC D NC NC NC VSS VSS VSS VSS VSS NC NC NC E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2 F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC L NC DQ6 NC VDDQ VSS VSS VSS VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS SA SA SA VSS NC NC NC P NC NC DQ7 SA SA C SA SA NC NC NC R TDO TCK SA SA SA C SA SA SA TMS TDI 11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch Notes: 1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to 0 at the beginning of each access. 2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7. 3. A2, A7, and B5 are the expansion addresses. Rev: 1.02 6/2012 5/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Pin Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read/Write Input Read: Active High Write: Active Low BW0–BW3 Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1 Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — MCL Must Connect Low — — DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active Low CQ Output Echo Clock Output — CQ Output Echo Clock Output — VDD Power Supply Supply 1.8 V Nominal VDDQ Isolated Output Buffer Supply Supply 1.8 V or 1.5 V Nominal VSS Power Supply: Ground Supply — NC No Connect — — Notes: 1. NC = Not Connected to die or any other pin 2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. C, C, K, K cannot be set to VREF voltage. Rev: 1.02 6/2012 6/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Background Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operations Read and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted. Deselect Cycles Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations. SigmaDDR-II B4 SRAM Read Cycles The status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer in response to a read command, if the previous command captured was a read or write command, the Address, LD and R/ W pins are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat of data is transferred on the next rising edge of C, then on the next rising edge of C and finally on the next rising edge of C, for a total of four transfers per address load. SigmaDDR-II B4 SRAM Write Cycles The status of the Address, LD and R/W pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD and R/ W pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst of four write transfer the SRAM captures data in on the next rising edge of K, the following rising edge of K and finally on the next rising edge of K, for a total of four transfers per address load. Rev: 1.02 6/2012 7/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Special Functions Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Beat 3 0 0 Data In Data In Beat 4 1 0 Don’t Care Data In Resulting Write Operation Byte 1 Byte 2 Byte 1 Byte 2 Byte 1 Byte 2 Byte 1 Byte 2 D0–D8 D9–D17 D0–D8 D9–D17 D0–D8 D9–D17 D0–D8 D9–D17 Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1 Beat 2 Beat 3 Beat 4 Output Register Control SigmaDDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM. FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaDDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance at mid-rail. The allowable range of RQ to guarantee impedance matching continuously is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Rev: 1.02 6/2012 8/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Example Four Bank Depth Expansion Schematic LD3 LD2 LD1 LD0 R/W A0–An K Bank 0 Bank 1 Bank 2 Bank 3 A A A A LD LD LD LD R/W R/W R/W R/W K CQ DQ K C C K CQ K DQ C CQ DQ C CQ DQ C DQ1–DQn CQ Note: For simplicity BWn (or NWn), K, and C are not shown. Rev: 1.02 6/2012 9/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Common I/O SigmaDDR-II B4 SRAM Truth Table DQ Kn LD ↑ 1 ↑ ↑ R/W Operation A+0 A+1 A+2 A+3 X Hi-Z Hi-Z Hi-Z Hi-Z Deselect 0 0 D@Kn+1 D@Kn+1 D@Kn+2 D@Kn+2 Write 0 1 Q@Kn+1 or Cn+1 Q@Kn+2 or Cn+2 Q@Kn+2 or Cn+2 Q@Kn+3 or Cn+3 Read Note: Q is controlled by K clocks if C clocks are not used. Burst of 4 Byte Write Clock Truth Table BW BW BW BW Current Operation D D D D K↑ (tn+1) (tn+1½) K↑ K↑ (tn+2) K↑ (tn+2½) K↑ (tn) K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) T T T T Write Dx stored if BWn = 0 in all four data transfers D0 D1 D2 D3 T F F F Write Dx stored if BWn = 0 in 1st data transfer only D0 X X X F T F F Write Dx stored if BWn = 0 in 2nd data transfer only X D1 X X F F T F Write Dx stored if BWn = 0 in 3rd data transfer only X X D2 X F F F T Write Dx stored if BWn = 0 in 4th data transfer only X X X D3 F F F F Write Abort No Dx stored in any of the four data transfers X X X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. Rev: 1.02 6/2012 10/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Burst of 4 Nybble Write Clock Truth Table NW NW NW NW Current Operation D D D D K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) K↑ (tn) K↑ (tn+1) K↑ (tn+1½) K↑ (tn+2) K↑ (tn+2½) T T T T Write Dx stored if NWn = 0 in all four data transfers D0 D1 D2 D3 T F F F Write Dx stored if NWn = 0 in 1st data transfer only D0 X X X F T F F Write Dx stored if NWn = 0 in 2nd data transfer only X D1 X X F F T F Write Dx stored if NWn = 0 in 3rd data transfer only X X D2 X F F F T Write Dx stored if NWn = 0 in 4th data transfer only X X X D3 F F F F Write Abort No Dx stored in any of the four data transfers X X X X Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more NWn = 0, then NW = “T”, else NW = “F”. Rev: 1.02 6/2012 11/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 x36 Byte Write Enable (BWn) Truth Table BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35 1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care 0 1 1 1 Data In Don’t Care Don’t Care Don’t Care 1 0 1 1 Don’t Care Data In Don’t Care Don’t Care 0 0 1 1 Data In Data In Don’t Care Don’t Care 1 1 0 1 Don’t Care Don’t Care Data In Don’t Care 0 1 0 1 Data In Don’t Care Data In Don’t Care 1 0 0 1 Don’t Care Data In Data In Don’t Care 0 0 0 1 Data In Data In Data In Don’t Care 1 1 1 0 Don’t Care Don’t Care Don’t Care Data In 0 1 1 0 Data In Don’t Care Don’t Care Data In 1 0 1 0 Don’t Care Data In Don’t Care Data In 0 0 1 0 Data In Data In Don’t Care Data In 1 1 0 0 Don’t Care Don’t Care Data In Data In 0 1 0 0 Data In Don’t Care Data In Data In 1 0 0 0 Don’t Care Data In Data In Data In 0 0 0 0 Data In Data In Data In Data In x18 Byte Write Enable (BWn) Truth Table BW0 BW1 D0–D8 D9–D17 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In x8 Nybble Write Enable (NWn) Truth Table NW0 NW1 D0–D3 D4–D7 1 1 Don’t Care Don’t Care 0 1 Data In Don’t Care 1 0 Don’t Care Data In 0 0 Data In Data In Rev: 1.02 6/2012 12/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 2.9 V VDDQ Voltage in VDDQ Pins –0.5 to VDD V VREF Voltage in VREF Pins –0.5 to VDDQ V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 (≤ 2.9 V max.) V IIN Input Current on Any Pin +/–100 mA dc IOUT Output Current on Any I/O Pin +/–100 mA dc TJ Maximum Junction Temperature 125 TSTG Storage Temperature –55 to 125 o C oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 1.7 1.8 1.9 V I/O Supply Voltage VDDQ 1.4 — VDD V Reference Voltage VREF 0.68 — 0.95 V Note: The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up. Operating Temperature Parameter Symbol Min. Typ. Max. Unit Junction Temperature (Commercial Range Versions) TJ 0 25 85 °C Junction Temperature (Industrial Range Versions)* TJ –40 25 100 °C Note: * The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Rev: 1.02 6/2012 13/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Thermal Impedance Package Test PCB Substrate θ JA (C°/W) Airflow = 0 m/s θ JA (C°/W) Airflow = 1 m/s θ JA (C°/W) Airflow = 2 m/s θ JB (C°/W) θ JC (C°/W) 165 BGA 4-layer 19.0 16.3 15.3 7.7 2.5 Notes: 1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. Please refer to JEDEC standard JESD51-6. 3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to the PCB can result in cooling or heating of the RAM depending on PCB temperature. HSTL I/O DC Input Characteristics Parameter Symbol Min Max Units Notes DC Input Logic High VIH (dc) VREF + 0.10 VDDQ + 0.3 V V 1 DC Input Logic Low VIL (dc) –0.3 V VREF – 0.10 V 1 Notes: 1. Compatible with both 1.8 V and 1.5 V I/O drivers 2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 3. VIL (Min) DC = –0.3 V, VIL(Min) AC = –1.5 V (pulse width ≤ 3 ns). 4. VIH (Max) DC = VDDQ + 0.3 V, VIH(Max) AC = VDDQ + 0.85 V (pulse width ≤ 3 ns). HSTL I/O AC Input Characteristics Parameter Symbol Min Max Units Notes AC Input Logic High VIH (ac) VREF + 0.20 — V 2,3 AC Input Logic Low VIL (ac) — VREF – 0.20 V 2,3 VREF (ac) — 5% VREF (DC) V 1 VREF Peak-to-Peak AC Voltage Notes: 1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. Rev: 1.02 6/2012 14/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKHKH VDD + 1.0 V VSS 50% 50% VDD VSS – 1.0 V 20% tKHKH VIL Note: Input Undershoot/Overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Output Capacitance COUT VOUT = 0 V 6 7 pF Clock Capacitance CCLK — 5 6 pF Note: This parameter is sample tested. AC Test Conditions Parameter Conditions Input high level VDDQ Input low level 0V Max. input slew rate 2 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 Note: Test conditions as specified with output loading as shown unless otherwise noted. AC Test Load Diagram DQ 50Ω RQ = 250 Ω (HSTL I/O) VREF = 0.75 V VT = VDDQ/2 Rev: 1.02 6/2012 15/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Input and Output Leakage Characteristics Parameter Symbol Test Conditions Min. Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA Doff IILDOFF VIN = 0 to VDD –20 uA 2 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDDQ –2 uA 2 uA Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Symbol Min. Max. Units Notes Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3 Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3 Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5 Output Low Voltage VOL2 Vss 0.2 V 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. 0Ω ≤ RQ ≤ ∞Ω 5. IOH = –1.0 mA 6. IOL = 1.0 mA Rev: 1.02 6/2012 16/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Operating Currents -400 Parameter Symbol Test Conditions Operating Current (x36): DDR IDD Operating Current (x18): DDR -350 -333 -300 -250 Notes 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 770 mA 780 mA 725 mA 735 mA 660 mA 670 mA 570 mA 580 mA 575 mA 585 mA 2, 3 IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 600 mA 610 mA 565 mA 575 mA 515 mA 525 mA 450 mA 460 mA 395 mA 405 mA 2, 3 Operating Current (x9): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 600 mA 610 mA 565 mA 575 mA 515 mA 525 mA 450 mA 460 mA 395 mA 405 mA 2, 3 Operating Current (x8): DDR IDD VDD = Max, IOUT = 0 mA Cycle Time ≥ tKHKH Min 600 mA 610 mA 565 mA 575 mA 515 mA 525 mA 450 mA 460 mA 395 mA 405 mA 2, 3 Standby Current (NOP): DDR ISB1 215 mA 225 mA 210 mA 220 mA 195 mA 205 mA 185 mA 195 mA 175 mA 185 mA 2, 4 Device deselected, IOUT = 0 mA, f = Max, All Inputs ≤ 0.2 V or ≥ VDD – 0.2 V Notes: 1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed. Rev: 1.02 6/2012 17/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Parameter Symbol -400 -350 -333 -300 -250 Min Max Min Max Min Max Min Max Min Max Units Notes AC Electrical Characteristics Clock K, K Clock Cycle Time C, C Clock Cycle Time tKHKH tCHCH 2.5 8.4 2.86 8.4 3.0 8.4 3.3 8.4 4.0 8.4 ns tKC Variable tKCVar — 0.2 — 0.2 — 0.2 — 0.2 — 0.2 ns K, K Clock High Pulse Width C, C Clock High Pulse Width tKHKL tCHCL 1.0 — 1.14 — 1.2 — 1.32 — 1.6 — ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width tKLKH tCLCH 1.0 — 1.14 — 1.2 — 1.32 — 1.6 — ns K to K High C to C High tKHKH tCHCH 1.0 — 1.13 — 1.35 — 1.49 — 1.8 — ns K to K High C to C High tKHKH tCHCH 1.0 — 1.13 — 1.35 — 1.49 — 1.8 — ns K, K Clock High to C, C Clock High tKHCH 0 1.13 0 1.29 0 1.35 0 1.49 0 1.8 ns DLL Lock Time tKCLock 1024 — 1024 — 1024 — 1024 — 1024 — cycle K Static to DLL reset tKCReset 30 — 30 — 30 — 30 — 30 — ns K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid tKHQV tCHQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 ns 4 K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold tKHQX tCHQX –0.45 — –0.45 — –0.45 — –0.45 — –0.45 — ns 4 K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid tKHCQV tCHCQV — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold tKHCQX tCHCQX –0.45 — –0.45 — –0.45 — –0.45 — –0.45 — ns CQ, CQ High Output Valid tCQHQV — 0.20 — 0.23 — 0.25 — 0.27 — 0.30 ns 8 CQ, CQ High Output Hold tCQHQX –0.20 — –0.23 — –0.25 — –0.27 — –0.30 — ns 8 CQ Phase Distortion tCQHCQH tCQHCQH 0.9 — 1.0 — 1.10 — 1.24 — 1.55 — ns K Clock High to Data Output High-Z C Clock High to Data Output High-Z tKHQZ tCHQZ — 0.45 — 0.45 — 0.45 — 0.45 — 0.45 ns 4 K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z tKHQX1 tCHQX1 –0.45 — –0.45 — –0.45 — –0.45 — –0.45 — ns 4 Address Input Setup Time tAVKH 0.4 — 0.4 — 0.4 — 0.4 — 0.5 — ns 1 Control Input Setup Time(R/ W) (LD) tIVKH 0.4 — 0.4 — 0.4 — 0.4 — 0.5 — ns 2 Control Input Setup Time (BWX) (NWX) tIVKH 0.28 — 0.28 — 0.28 — 0.3 — 0.35 — ns 3 Data Input Setup Time tDVKH 0.28 — 0.28 — 0.28 — 0.3 — 0.35 — ns 6 7 Output Times Setup Times Rev: 1.02 6/2012 18/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Parameter Symbol -400 -350 -333 -300 -250 Min Max Min Max Min Max Min Max Min Max Units Notes AC Electrical Characteristics (Continued) Hold Times Address Input Hold Time tKHAX 0.4 — 0.4 — 0.4 — 0.4 — 0.5 — ns 1 Control Input Hold Time (R/ W) (LD) tKHIX 0.4 — 0.4 — 0.4 — 0.4 — 0.5 — ns 2 Control Input Hold Time (BWX) (NWX) tKHIX 0.28 — 0.28 — 0.28 — 0.3 — 0.35 — ns 3 Data Input Hold Time tKHDX 0.28 — 0.28 — 0.28 — 0.3 — 0.35 — ns Notes: 1. 2. 3. 4. 5. 6. 7. 8. All Address inputs must meet the specified setup and hold times for all latching clock edges. Control signals are R/ W, LD. Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). If C, C are tied high, K, K become the references for C, C timing parameters To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations. Rev: 1.02 6/2012 19/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology Rev: 1.02 6/2012 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 20/35 CQ CQ DQ C C BWx R/W LD Address K K A KHIX KHIX KHKH CHCQV CHCQX IVKH IVKH KHKH KHAX AVKH Read A KHKL KHKL Cont Read A CHCQV B Write B CQHQV A+2 A CHCQX CHQX A+1 KHnKH KHnKH CHQX1 KLKH KLKH NOP A+3 CHQV B CQHQX B B+1 B+1 KHIX DVKH IVKH Cont Write B CHQZ C and C Controlled Read First Timing Diagram B+2 B+2 C Read C B+3 KHDX B+3 GS8342R08/09/18/36BD-400/350/333/300/250 © 2011, GSI Technology Rev: 1.02 6/2012 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 21/35 CQ CQ DQ BWx R/W LD Address K K A KHKH KHAX CHCQV CHCQX IVKH KHIX IVKH KHIX AVKH Read A CHCQV CHCQX KHKL Cont Read A CQHQV A KHQX1 KLKH A+1 KH#KH NOP CQHQX A+2 KHQX B A+3 KHQV Write B KHQZ B B DVKH IVKH KHIX Cont Write B K and K Controlled Read First Timing Diagram B+1 B+1 B+2 KHDX B+2 C Read C B+3 B+3 GS8342R08/09/18/36BD-400/350/333/300/250 © 2011, GSI Technology Rev: 1.02 6/2012 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 22/35 CQ CQ DQ C C BWx R/W LD Address K K A KHAX IVKH KHIX AVKH Write A A A A+1 DVKH A+1 KHKH IVKH KHIX KHKH Cont Write A A+2 KHDX A+2 B KHKL A+3 A+3 KHIX IVKH KHKL Read B CHCQV CHCQX KLKH KLKH KHnKH KHnKH Cont Read B B CQHQV CHQX1 B+1 NOP C CQHQX B+2 CHQV C and C Controlled Write First Timing Diagram B+3 Write C C CHQZ CHQX C C+1 C+1 Cont Write C C+2 GS8342R08/09/18/36BD-400/350/333/300/250 © 2011, GSI Technology Rev: 1.02 6/2012 KHIX Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 23/35 CQ CQ CHCQX A DQ CHCQV IVKH A A KHAX AVKH BWx R/W LD Address K K Write A1 DVKH IVKH A+1 A+1 KHIX KHKH Cont Write A A+2 KHDX A+2 B A+3 CHCQX Cont Read B KHnKH CHCQV KLKH A+3 KHIX IVKH KHKL Read B B CQHQV KHQX1 B+1 NOP CQHQX B+2 KHQV C B+3 Write C K and K Controlled Write First Timing Diagram KHQX C KHQZ C C+1 C+1 Cont Write C C+2 C+2 GS8342R08/09/18/36BD-400/350/333/300/250 © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Rev: 1.02 6/2012 24/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram · · · · · · · · Boundary Scan Register · · 0 Bypass Register 0 108 1 · 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · ·· 2 1 0 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.02 6/2012 25/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 GSI Technology JEDEC Vendor ID Code See BSDL Model Bit # Presence Register ID Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 X X X X X X X X X X X X X X X X X X X 0 0 0 1 1 0 1 1 0 0 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.02 6/2012 26/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 1 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 1.02 6/2012 27/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 GSI 011 GSI private instruction. 1 SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 GSI 110 GSI private instruction. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.02 6/2012 28/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes Test Port Input Low Voltage VILJ –0.3 0.3 * VDD V 1 Test Port Input High Voltage VIHJ 0.7 * VDD VDD +0.3 V 1 TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3 TDO Output Leakage Current IOLJ –1 1 uA 4 Test Port Output High Voltage VOHJ VDD – 0.2 — V 5, 6 Test Port Output Low Voltage VOLJ — 0.2 V 5, 7 Test Port Output CMOS High VOHJC VDD – 0.1 — V 5, 8 Test Port Output CMOS Low VOLJC — 0.1 V 5, 9 Notes: 1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDD supply. 6. IOHJ = –2 mA 7. IOLJ = + 2 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA JTAG Port AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDD/2 JTAG Port AC Test Load TDO 50Ω 30pF* VDD/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.02 6/2012 29/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Rev: 1.02 6/2012 30/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Package Dimensions—165-Bump FPBGA (Package D) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 15±0.05 1.0 A B C D E F G H J K L M N P R A 1.0 1.0 10.0 0.15 C B Rev: 1.02 6/2012 SEATING PLANE 0.20(4x) 0.36~0.46 1.40 MAX. C 13±0.05 31/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Ordering Information—GSI SigmaDDR-II SRAM Org Part Number1 Type Package Speed (MHz) TJ2 4M x 8 GS8342R08BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C 4M x 8 GS8342R08BD-350 SigmaDDR-II B4 SRAM 165-bump BGA 350 C 4M x 8 GS8342R08BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C 4M x 8 GS8342R08BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C 4M x 8 GS8342R08BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C 4M x 8 GS8342R08BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I 4M x 8 GS8342R08BD-350I SigmaDDR-II B4 SRAM 165-bump BGA 350 I 4M x 8 GS8342R08BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I 4M x 8 GS8342R08BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I 4M x 8 GS8342R08BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I 4M x 9 GS8342R09BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C 4M x 9 GS8342R09BD-350 SigmaDDR-II B4 SRAM 165-bump BGA 350 C 4M x 9 GS8342R09BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C 4M x 9 GS8342R09BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C 4M x 9 GS8342R09BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C 4M x 9 GS8342R09BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I 4M x 9 GS8342R09BD-350I SigmaDDR-II B4 SRAM 165-bump BGA 350 I 4M x 9 GS8342R09BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I 4M x 9 GS8342R09BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I 4M x 9 GS8342R09BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I 2M x 18 GS8342R18BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C 2M x 18 GS8342R18BD-350 SigmaDDR-II B4 SRAM 165-bump BGA 350 C 2M x 18 GS8342R18BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C 2M x 18 GS8342R18BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C 2M x 18 GS8342R18BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C 2M x 18 GS8342R18BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I 2M x 18 GS8342R18BD-350I SigmaDDR-II B4 SRAM 165-bump BGA 350 I 2M x 18 GS8342R18BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I 2M x 18 GS8342R18BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I 2M x 18 GS8342R18BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I 1M x 36 GS8342R36BD-400 SigmaDDR-II B4 SRAM 165-bump BGA 400 C 1M x 36 GS8342R36BD-350 SigmaDDR-II B4 SRAM 165-bump BGA 350 C Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8342Rx36BD-300T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. Rev: 1.02 6/2012 32/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Ordering Information—GSI SigmaDDR-II SRAM Org Part Number1 Type Package Speed (MHz) TJ2 1M x 36 GS8342R36BD-333 SigmaDDR-II B4 SRAM 165-bump BGA 333 C 1M x 36 GS8342R36BD-300 SigmaDDR-II B4 SRAM 165-bump BGA 300 C 1M x 36 GS8342R36BD-250 SigmaDDR-II B4 SRAM 165-bump BGA 250 C 1M x 36 GS8342R36BD-400I SigmaDDR-II B4 SRAM 165-bump BGA 400 I 1M x 36 GS8342R36BD-350I SigmaDDR-II B4 SRAM 165-bump BGA 350 I 1M x 36 GS8342R36BD-333I SigmaDDR-II B4 SRAM 165-bump BGA 333 I 1M x 36 GS8342R36BD-300I SigmaDDR-II B4 SRAM 165-bump BGA 300 I 1M x 36 GS8342R36BD-250I SigmaDDR-II B4 SRAM 165-bump BGA 250 I 4M x 8 GS8342R08BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C 4M x 8 GS8342R08BGD-350 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 C 4M x 8 GS8342R08BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C 4M x 8 GS8342R08BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C 4M x 8 GS8342R08BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C 4M x 8 GS8342R08BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I 4M x 8 GS8342R08BGD-350I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 I 4M x 8 GS8342R08BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I 4M x 8 GS8342R08BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I 4M x 8 GS8342R08BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I 4M x 9 GS8342R09BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C 4M x 9 GS8342R09BGD-350 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 C 4M x 9 GS8342R09BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C 4M x 9 GS8342R09BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C 4M x 9 GS8342R09BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C 4M x 9 GS8342R09BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I 4M x 9 GS8342R09BGD-350I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 I 4M x 9 GS8342R09BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I 4M x 9 GS8342R09BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I 4M x 9 GS8342R09BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I 2M x 18 GS8342R18BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C 2M x 18 GS8342R18BGD-350 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 C 2M x 18 GS8342R18BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C 2M x 18 GS8342R18BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C 2M x 18 GS8342R18BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8342Rx36BD-300T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. Rev: 1.02 6/2012 33/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Ordering Information—GSI SigmaDDR-II SRAM Org Part Number1 Type Package Speed (MHz) TJ2 2M x 18 GS8342R18BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I 2M x 18 GS8342R18BGD-350I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 I 2M x 18 GS8342R18BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I 2M x 18 GS8342R18BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I 2M x 18 GS8342R18BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I 1M x 36 GS8342R36BGD-400 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 C 1M x 36 GS8342R36BGD-350 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 C 1M x 36 GS8342R36BGD-333 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 C 1M x 36 GS8342R36BGD-300 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 C 1M x 36 GS8342R36BGD-250 SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 C 1M x 36 GS8342R36BGD-400I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 400 I 1M x 36 GS8342R36BGD-350I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 350 I 1M x 36 GS8342R36BGD-333I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 333 I 1M x 36 GS8342R36BGD-300I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 300 I 1M x 36 GS8342R36BGD-250I SigmaDDR-II B4 SRAM RoHS-compliant 165-bump BGA 250 I Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8342Rx36BD-300T. 2. C = Commercial Temperature Range. I = Industrial Temperature Range. Rev: 1.02 6/2012 34/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology GS8342R08/09/18/36BD-400/350/333/300/250 Revision History File Name Types of Changes Format or Content Revisions • Creation of new datasheet GS8342RxxB_r1 GS8342RxxB_r1_01 Content • Updated Operating Currents table • (Rev1.01a: Editorial updates) • (Rev1.01b: Updated DLL lock time in AC Char table) GS8342RxxB_r1_02 Content • Updated to reflect MP status Rev: 1.02 6/2012 35/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology