V6209643 VID

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
10-04-06
CHECKED BY
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
A
REV
AMSC N/A
.
CODE IDENT. NO.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
TITLE
MICROCIRCUIT, DIGITAL, DIGITAL MEDIA
SYSTEM ON CHIP (DMSoC), MONOLITHIC
SILICON
DWG NO.
V62/09643
16236
PAGE
1
OF
49
5962-V039-10
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance Digital Media System on Chip (DMSoC)
microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/09643
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s). 1/
Device type
Generic
01
SM32DM355-EP
Clock Rate
Circuit function
216 MHz
Digital Media System on Chip (DMSoC)
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
Package style
X
337
Plastic ball grid array
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
1/
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
Users are cautioned to review the manufacturers data manual for additional user information relating to this device.
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1.3 Absolute maximum ratings.
2/ 3/
Supply voltage ranges:
All 1.3 V supplies ...................................................................................................
All digital 1.8 V supplies .........................................................................................
All analog 1.8 V supplies ........................................................................................
All 3.3 V supplies ...................................................................................................
Input voltage ranges, (VI):
All 1.8 V I/Os ..........................................................................................................
All 3.3 V I/Os ..........................................................................................................
VBUS .....................................................................................................................
Clamp current for input or output, (Iclamp) ..........................................................................
Operating case temperature ranges, (TC):
Device type: 01 ......................................................................................................
Storage temperature range, (TSTG) ....................................................................................
-0.5 V to 1.7 V
-0.5 V to 2.8 V
-0.5 V to 1.89 V
-0.5 V to 4.4 V
-0.5 V to 2.3 V
-0.5 V to 3.8 V
0.0 V to 5.5 V
-20 mA to +20 mA
4/
-55C to +125C
-65C to +150C
1.4 Recommended operating conditions. 5/
Supply voltage:
Supply voltage, Core (CVDD) ..................................................................................
Supply voltage, PLL1 (VDDA_PLL1) ...........................................................................
Supply voltage, PLL2 (VDDA_PLL2) ...........................................................................
Supply voltage, USB digital (VDDD13_USB) ................................................................
Supply voltage, USB analog (VDDA13_USB) ...............................................................
Supply voltage, USB analog (VDDA33_USB) ...............................................................
Supply voltage, USB common PLL (VDDA33_USB_PLL) ...............................................
Supply voltage, DDR2/MDDR (VDD_DDR) ................................................................
Supply voltage, DDR DLL Analog (VDDA33_DDRDLL) ..................................................
Supply voltage, Digital video in (VDD_VIN) ................................................................
Supply voltage, Digital video out (VDD_VOUT) ...........................................................
Supply voltage, DAC analog (VDDA18_DAC) ..............................................................
Supply voltage, I/Os (VDD) ......................................................................................
Supply ground:
Supply ground, Core, USB digital (VSS) .................................................................
Supply ground, PLL1 (VSSA_PLL1) ............................................................................
Supply ground, PLL2 (VSSA_PLL2) ............................................................................
Supply ground, USB (VSS_USB) ...............................................................................
Supply ground, DLL (VSSA_DLL) ...............................................................................
Supply ground, DAC analog (VSSA_DAC) ..................................................................
MXI1 osc ground, (VSS_MX1) ....................................................................................
MXI2 osc ground, (VSS_MX2) ....................................................................................
Supply ground, (VSS) .............................................................................................
2/
3/
4/
5/
6/
1.235 V to 1.365 V
1.235 V to 1.365 V
1.235 V to 1.365 V
1.235 V to 1.365 V
1.235 V to 1.365 V
3.135 V to 3.465 V
3.135 V to 3.465 V
1.71 V to 1.89 V
3.135 V to 3.465 V
3.135 V to 3.465 V
3.135 V to 3.465 V
1.71 V to 1.89 V
3.135 V to 3.465 V
0V
0V
0V
0V
0V
0V
0V
0V
0V
6/
6/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
All voltage values are with respect to VSS.
Clamp current flows from an input or putput pad to a supply rail through a clamp circuit or an intrinsic diode. Positive current
results from an applied input or output voltage that is more than 0.5 V higher (more positive) than the supply voltage,
VDD/VDDA_PLL1/2/VDD_USB/VDD_DDR for dual supply macros. Negative results from an applied voltage that is more than 0.5 V less
(more negative) than the VSS voltage.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (see
manufacturer data for more details).
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1.4 Recommended operating conditions - Continued.
Minimum high level input voltage, (VIH) ......................................................................
Maximum low level input voltage, (VIL) .......................................................................
DAC: 8/
DAC reference voltage, (VREF) ........................................................................
DAC full scale current adjust resistor, (RBIAS) ..................................................
Output resistor, (RLOAD) ...................................................................................
Bypass capacitor, (CBG) ..................................................................................
Video buffer 8/
Output resistor (ROUT), between TVOUT and VFB pins (ROUT) .....................
Feed back resistor, between VFB and IOUT pins, (RFB) .................................
DAC full scale current adjust resistor, (RBIAS) ..................................................
Bypass capacitor, (CBG) ..................................................................................
USB:
USB external charge pump input (USB_VBUS) ..............................................
USB reference resistor, (R1) ...........................................................................
Operating case temperature (TC): 10/
Device type 01 ..................................................................................
Thermal resistance characteristics for case outline X
Junction to case
Junction to board
Junction to free air
Junction to package top
Junction to board
RθJC
RθJB
RθJA
PsiJT
PsiJB
2.0 V
0.8 V
7/
7/
450 TYP mV
2550 TYP Ω
499 TYP Ω
0.1 TYP µF
1070 TYP Ω
1000 TYP Ω
2550 TYP Ω
0.1 µF
4.85 V to 5.25 V
9.9 kΩ to 10.1 kΩ
9/
-55C to +125C
C/W 11/
7.2
11.4
27.0
0.1
11.3
2. APPLICABLE DOCUMENTS
JEDEC PUB 95
EIA/JESD51-2
EIA/JESD51-3
EIA/JESD51-7
–
–
–
–
Registered and Standard Outlines for Semiconductor Devices
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still air).
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA
22201-3834 or online at http://www.jedec.org)
________
7/
8/
9/
10/
11/
These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os are 1.8 V I/Os and adhere to
USB2.0 spec.
See manufacturer data for more information. Also, resistors should be E-96 spec line (3 digits with 1% accuracy).
Connect USB_R1 to VSS_USB_REF via 10 KΩ, 1% resistor placed as close to the device as possible.
To avoid frequency performance device degradation, limit the total device power on hours to less than 16500 hrs at TC = 125C.
The junction to case measurement was conducted in a JDEC defined 2S2P system and will change based on environment as
well as application. For more information, see three EIA/JEDEC standards: EIA/JEDEC standards: 51-2, 51-3, 51-7.
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3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as specified in figure 3.
3.5.4 Test load circuit for AC timing measurement. The test load circuit for AC timing measurements shall be as specified in figure
4.
3.5.5 Timing waveforms. The timing waveforms shall be as shown in figures 4-48.
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TABLE I. Electrical performance characteristics.
Test
Voltage output
Symbol
High level output voltage 3/
Low level output voltage 3/
Input current for I/O without internal
pull-up/pull-down
Input current for I/O with internal
pull-up 4/ 5/
Input current for I/O with internal
pull-down 4/ 5/
High level output current
Low level output current
I/O off state output current
Input capacitance
Output capacitance
Resolution
IOH
IOL
IOZ
CI
CO
Resolution
DAC
Integral non-linearity, best fit
Differential non-linearity
Output compliance range
INL
DNL
Compliance
Video buffer
Output high voltage (top of 75%
NTSC or PAL colorbar) 6/
Output low voltage (bottom of sync
tip)
Current
Input/Output
Capacitance
VOH
VOL
II
1/
Test condition
2/
Device type: All
Limits
Min
Unit
Max
DVDD = MIN, IOH = MAX
DVDD = MIN, IOL = MAX
VI = VSS to VDD
2.4
-1
0.6
1
II(pullup)
VI = VSS to VDD
40
190
II(pulldown)
VI = VSS to VDD
-190
-40
VO = VDD or VSS, Internal pull disabled
RLOAD = 499 Ω,
Video buffer disabled
RLOAD = 499 Ω, IFS = 1.4 mA
V
µA
-100
4000
±10 TYP
4
4
10 TYP
pF
Bits
1 TYP
0.5 TYP
0
0.700
VOH(VIDBUF)
1.55 TYP
VOL(VIDBUF)
0.470 TYP
LSB
V
V
RESET
Timing requirements for Reset 7/ 8/ (See figure 5)
No
1
Test
Symbol
Active low width of the RESET pulse
Test condition
2/
Device type: All
Min
Unit
Max
12C
tw(RESET)
tsu(BOOT)
Setup time, boot configuration pins valid before
RESET rising edge
th(BOOT)
3
Hold time, boot configuration pins valid after
RESET rising edge
OSCILLATORS AND CLOCKS
Switching characteristics for 24 MHz system
2
ns
12C
12C
Start up time (from power up until oscillating at
stable frequency)
Oscillation frequency
ESR
Limits
4
ms
24 or 36 TYP
24 MHz
36 MHz
MHz
60
30
±50
Frequency stability
Ω
ppm
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
1/
Limits
Test condition
2/
Device type: All
Unit
Min
Max
OSCILLATORS AND CLOCKS - Continued
Switching characteristics for 27 MHz system
Start up time (from power up until oscillating at
stable frequency)
Oscillation frequency
4
ms
27 TYP
MHz
ESR
50
Ω
Frequency stability
±50
ppm
CLOCK PLL ELECTRICAL DATA/TIMING (Input and output clocks)
Timing requirements for MXI1/CLKIN1 9/ 10/
1
Cycle time, MXI1/CLKIN1
2
Pulse duration, MXI1/CLKIN1 high
3
Pulse duration, MXI1/CLKIN1 low
4
Transition time, MXI1/CLKIN1
5
Period jitter, MXI1/CLKIN1
Timing requirements for MXI2/CLKIN2 9/ 12/
1
Cycle time, MXI2/CLKIN2
2
Pulse duration, MXI2/CLKIN2 high
3
Pulse duration, MXI2/CLKIN2 low
4
Transition time, MXI2/CLKIN2
5
Period jitter, MXI2/CLKIN2
Switching characteristics for CLKOUT1
tc(MXI1)
tw(MXI1H)
tw(MXI1L)
tt(MXI1)
tJ(MXI1)
See figure 6
27.7 11/
0.45C
0.45C
41.6 11/
0.55C
0.55C
0.05C
0.02C
ns
tc(MXI2)
See figure 7
37.037 13/
0.45C
0.45C
37.037 13/
0.55C
0.55C
0.05C
0.02C
ns
See figure 8
tc(MXI1)
0.45P
0.45P
tw(MXI2H)
tw(MXI2L)
tt(MXI2)
tJ(MXI2)
9/ 14/
1
2
3
4
5
Cycle time CLKOUT1
Pulse duration, CLKOUT1 high
Pulse duration, C:LKOUT1 low
Transition time, CLKOUT1
Delay time, MXI1/CLKIN1 high to CLKOUT1
high
6
Delay time, MXI1/CLKIN1 low to CLKOUT1
low
Switching characteristics for CLKOUT2 9/ 15/
tc(CLKOUT1)
tw(CLKOUT1H)
tw(CLKOUT1L)
tt(CLKOUT1)
td(MXI1H-
1
2
3
4
5
tc(CLKOUT2)
tw(CLKOUT2H)
tw(CLKOUT2L)
tt(CLKOUT2)
td(MXI1H-
6
Cycle time CLKOUT2
Pulse duration, CLKOUT2 high
Pulse duration, C:LKOUT2 low
Transition time, CLKOUT2
Delay time, MXI1/CLKIN1 high to CLKOUT2
high
Delay time, MXI1/CLKIN1 low to CLKOUT2
low
ns
1
0.55P
0.55P
0.55P
8
1
8
CLKOUT1H)
td(MXI1LCLKOUT1L)
See figure 9
tc(MXI1)/3
0.45P
0.45P
ns
1
0.55P
0.55P
0.05P
8
1
8
CLKOUT2H)
td(MXI1LCLKOUT2L)
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
1/
Limits
Test condition
2/
Device type: All
Min
Unit
Max
CLOCK PLL ELECTRICAL DATA/TIMING (Input and output clocks) - Continued
Switching characteristics for CLKOUT3 9/ 16/
1
2
3
4
5
6
Cycle time CLKOUT3
tc(CLKOUT3)
See figure 10
Pulse duration, CLKOUT3 high
tw(CLKOUT3H)
Pulse duration, C:LKOUT3 low
tw(CLKOUT3L)
Transition time, CLKOUT3
tt(CLKOUT3)
Delay time, CLKIN/MXI high to CLKOUT3 high
td(MXI2H-CLKOUT3H)
Delay time, CLKIN/MXI low to CLKOUT3 low
td(MXI2L-CLKOUT3L)
GPIO PERIPHERAL INPUT/OUTPUT ELECTRICAL DATA/TIMING
Timing requirements for GPIO inputs
1
Pulse duration, GPIx high
2
Pulse duration, GPIx high
Switching characteristics for GPIO outputs
tw(GPIH)
tw(GPIL)
tc(MXI1)/8
0.45P
0.45P
1
1
See figure 10
3
4
Pulse duration, GPOx high
tw(GPOH)
See figure 11
Pulse duration, GPOx low
tw(GPOL)
GPIO PERIPHERAL EXTERNAL INTERRUPTS ELECTRICAL DATA/TIMING
Timing requirements for external interrupts/EDMA events 18/
ns
0.55P
0.55P
0.05P
8
8
52
52
ns
26 17/
26 17/
ns
1
2
Width of the external interrupt pulse low
Width of the external interrupt pulse high
tw(ILOW)
See figure 12
tw(IHIGH)
AEMIF ELECTRICAL DATA/TIMING
Timing requirements for Asynchronous Memory Cycles for AEMIF module 19/ See figure 13 and 14
READS and WRITES
52
52
ns
2
Pulse duration, EM_WAIT assertion and deassertion
tw(EM_WAIT)
2E
ns
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
5
0
ns
READS
12 Setup time, EM_D[15:0] valid before EM_OE high
13 Hold time, EM_D[15:0] valid after EM_OE high
14 Setup time EM_WAIT asserted before EM_OE high
READS (OneNAND Synchrnous Burst Read)
20/
30 Setup time, EM_D[15:0] valid before EM_CLK high
31 Hold time, EM_D[15:0] valid after EM_CLK high
WRITES
tsu(EMDV-EMCLKH)
th(EMCLKH-EMDIV)
28
tsu(EMWEL-EMWAIT)
Setup time, EM_WAIT asserted before valid before
EM_WE high
4E TYP
tsu(EMOEL-EMWAIT)
4
4
ns
4E TYP
ns
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
Test condition
2/
Device type:
All
1/
Limits
Min
Unit
TYPICAL
Max
AEMIF ELECTRICAL DATA/TIMING – Continued
Switching characteristics for Asynchrnous Memory Cycles for AEMIF module 19/ 21/ 22/ See figure 13 and 14
READS and WRITES
1
Turn around time
td(TURNAROUND)
(TA)*E
ns
tc(EMRCYCLE)
(RS+RST+RH)*E
(RS+RST+RH+(EW
C*16))*E
(RS)*E
ns
READS
3
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
4
Output setup time, EM_CE 1: 0 low to EM_OE low
(SS = 0)
Output setup time, EM_CE 1: 0 low to EM_OE low
(SS = 1)
tsu(EMCEL-EMOEL)
Output hold time, EM_OE high to EM_CE 1: 0 high
(SS = 0)
th(EMOEH-EMCEH)
5
0
(RH)*E
0
Output hold time, EM_OE high to EM_CE 1: 0 high
(SS = 1)
6
Output setup time, EM_BA 1: 0 valid to EM_OE low
tsu(EMBAV-EMOEL)
(RS)*E
7
Output hold time, EM_OE high to EM_BA 1: 0 invalid
th(EMOEH-EMBAIV)
(RH)*E
8
Output setup time, EM_A 13: 0 valid to EM_OE low
9
Output hold time, EM_OE high to EM_A 13: 0 invalid
10
EM_OE active low width (EW = 0)
EM_OE active low width (EW = 1)
11
Delay time from EM_WAIT deasserted to EM_OE
high
READS(OneNAND Synchronous Burst Read)
32
Frequency, EM_CLK
33
Cycle time, EM_CLK
34
Output setup time, EM_ADV valid before EM_CLK
high
Output hold time, EM_CLK high to EM_ADV invalid
35
th(EMOEH-EMBAIV)
(RS)*E
tsu(EMBAV-EMOEL)
(RH)*E
th(EMOEL)
(RST)*E
(RST+(EWC*16))*E
4E
td(EMWAITHEMOEH)
fc(EMWCYCLE)
1
66
MHz
tc(EM_CLK)
15
1000
ns
tsu(EM_ADVV-
5
EM_CLKH)
th(EM_CLKH-
6
EM_ADVIV)
36
38
Output setup time, EM_A[13:0]/EM_BA[1] valid
before EM_CLK high
Output hold time, EM_CLK high to
EM_A[13:0]/EM_BA[1] invalid
Pulse duration, EM_CLK high
tw(EM_CLKH)
23/
39
Pulse duration, EM_CLK low
tw(EM_CLKL)
23/
37
tsu(EM_AV-
5
EM_CLKH)
th(EM_CLKH-
6
EM_AIV)
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
Test condition
2/
Device type: All
1/
Limits
Min
Unit
TYPICAL
Max
AEMIF ELECTRICAL DATA/TIMING – Continued
Switching characteristics for Asynchrnous Memory Cycles for AEMIF module 19/ 21/ 22/ See figure 13 and 14
WRITES
15
EMIF write cycle time (EW = 0)
tc(EMWCYCLE)
(WS+WST+WH)*
E
(WS+WST+WH+
(EWC*16))*E
(WS)*E
EMIF write cycle time (EW = 1)
16
17
Output setup time, EM_CE 1: 0 low to EM_WE low
(SS = 0)
Output setup time, EM_CE 1: 0 low to EM_WE low
(SS = 1)
Output hold time, EM_WE high to EM_CE 1: 0 high
(SS = 0)
tsu(EMCEL-EMWEL)
0
(WH)*E
th(EMWEH-EMCEH)
0
Output hold time, EM_WE high to EM_CE 1: 0 high
(SS = 1)
20
Output setup time, EM_BA 1: 0 valid to EM_WE low
tsu(EMBAV-EMWEL)
(WS)*E
21
Output hold time, EM_WE high to EM_BA 1: 0 invalid
th(EMWEH-EMBAIV)
(WH)*E
22
Output setup time, EM_A 13: 0 valid to EM_WE low
th(EMWEH-EMBAIV)
(WS)*E
23
Output hold time, EM_WE high to EM_A 13: 0 invalid
EM_WE active low width (EW = 0)
EM_WE active low width (EW = 1)
tsu(EMBAV-EMWEL)
(WH)*E
th(EMWEL)
(WST)*E
(WST+(EWC*16)
)*E
4E
24
25
26
27
ns
td(EMWAITH-
Delay time from EM_WAIT deasserted to EM_WE
high
EMWEH)
Output setup time, EM_D 15: 0 valid to EM_WE low
tsu(EMDV-EMWEL)
(WS)*E
Output hold time, EM_WE high to EM_D 15: 0 invalid
th(EMWEH-EMDIV)
(WH)*E
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test condition
2/
Device type: All
1/
Limits
Fast mode
Min
Max
Unit
Standard
mode
Min
Max
MMC/SD ELECTRICAL DATA/TIMING
Timing requirements for MMC/SD module (See figure 19 and 21)
1
2
Setup time, SD_CMD valid before SD_CLK high
Hold time, SD_CMD valid after SD_CLK high
tsu(CMDV-CLKH)
th(CLKH-CMDV)
6
2.5
24/
6
2.5
3
Setup time, SD_DATx valid before SD_CLK high
tsu(DATV-CLKH)
4
Hold time, SD_DATx valid after SD_CLK high
th(CLKH-DATV)
Switching characteristics for MMC/SD module (See figure 18 - 21)
7
8
9
10
11
12
13
14
Operating frequency, SD_CLK
Identification mode frequency, SD_CLK
Pulse width, SD_CLK low
Pulse width, SD_CLK high
Rise time, SD_CLK
Fall time, SD_CLK
Delay time, SD_CLK low to SD_CMD transition
Delay time, SD_CLK low to SD_DATx transition
f(CLK)
0
0
7
7
f(CLK_ID)
tw(CLKL)
tw(CLKH)
tr(CLK)
tf(CLK)
td(CLKL-CMD)
td(CLKL-DAT)
-7.5
-7.5
5
5
ns
5
5
50
400
3
3
4
4
0
0
10
10
25
400
ns
10
10
14
14
-7.5
-7.5
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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11
TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
Test condition
2/
Device type: All
1/
Limits
Unit
Min
Max
100
100
VPFE LECTRICAL DATA/TIMING
Timing requiremenets for VPFE PCLK Master/Slave mode 25/ (See figure 22)
1
Cycle time, PCLK
tc(PCLK)
H3A not used
H3A used
2
Pulse duration, PCLK high
tw(PCLKH)
13.33 or P 26/
2P + 1
5.7
3
Pulse duration, PCLK low
tw(PCLKL)
5.7
4
Transition time, UXCLK
tt(PCLK)
ns
3
Timing requirements for VPFE(CCD) Slave mode (See figure 23)
5
6
7
8
9
10
11
Setup time, CCD valid before PCLK edge
tsu(CCDV-PCLK)
Hold time, CCD valid after PCLK edge
th(PCLK-CCDV)
Setup time, HD valid before PCLK edge
tsu(HDV-PCLK)
Hold time, HD valid after PCLK edge
th(PCLK-HDV)
Setup time, VD valid before PCLK edge
tsu(VDV-PCLK)
Hold time, VD valid after PCLK edge
th(PCLK-VDV)
Setup time, CAM_WEN_FIELD valid
tsu(CAM_WEN_FILELDV
before PCLK edge
-PCLK)
12
Hold time, CAM_WEN_FIELD valid after
th(PCLKPCLK edge
CAM_WEN_FIELDV)
Timing requirements for VPFE(CCD) Master mode
27/ (See figure 24)
3
2
3
2
3
2
3
2
15
16
23
Setup time, CCD valid before PCLK edge
tsu(CCDV-PCLK)
Hold time, CCD valid after PCLK edge
th(PCLK-CCDV)
Setup time, CAM_WEN_FIELD valid
tsu(CAM_WEN_FILELDV
before PCLK edge
-PCLK)
24
Hold time, CAM_WEN_FIELD valid after
th(PCLKPCLK edge
CAM_WEN_FIELDV)
Switching characteristics for VPFE(CCD) Master mode (See figure 25)
18
20
Delay time, PCLK edge to HD invalid
Delay time, PCLK edge to VD invalid
ns
3
2
3
ns
2
td(PCLKL-HDIV)
td(PCLKL-VDIV)
3
3
11
11
ns
See footnotes at end of table.
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PAGE
12
TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
Test condition
2/
Device type: All
1/
Limits
Unit
Min
Max
13.33
160
VPBE ELECTRICAL DATA/TIMING
Timing requirements for VPBE CLK inputs
1
Cycle time, PCLK 28/
tc(PCLK)
See figure 26
2
Pulse duration, PCLK high
tw(PCLKH)
5.7
3
Pulse duration, PCLK low
tw(PCLKL)
5.7
4
Transition time, PCLK
5
Cycle time, EXTCLK
6
tt(PCLK)
ns
3
tc(EXTCLK)
13.33
Pulse duration, EXTCLK high
tw(EXTCLKH)
5.7
7
Pulse duration, EXTCLK low
tw(EXTCLKL)
5.7
8
Transition time, EXTCLK
160
tt(EXTCLK)
3
Timing requirements for VPBE control input with respect to PCLK and EXTCLK 27/ 29/ 30/
9
Setup time, VCTL valid before VCLKIN edge
tsu(VCTLV-VCLKIN)
See figure 27
10
Hold time, VCTL valid after VCLKIN edge
th(VCLKIN-VCTLV)
Switching characteristics for VPBE control and data output with respect to PCLK and EXTCLK
2
1
11
Delay time, VCLKIN edge to VCTL valid
td(VCLKIN-VCTLV)
See figure 28
12
Delay time, VCLKIN edge to VCTL invalid
td(VCLKIN-VCTLIV)
13
Delay time, VCLKIN edge to VDATA valid
td(VCLKIN-VDATAV)
14
Delay time, VCLKIN edge to VDATA invalid
td(VCLKIN-VDATAIV)
Switching characteristics for VPBE control and data output with respect to VCLK 27/ 32/
13.3
Cycle time, VCLK
Pulse duration, VCLK high
tw(VCLKH)
5.7
19
Pulse duration, PCLK low
tw(VCLKL)
5.7
Transition time, VCLK
Delay time, VCLKIN high to VCLK high
Delay time, VCLKIN low to VCLK low
Delay time, VCLK edge to VCTL valid
Delay time, VCLK edge to VCTL invalid
Delay time, VCLK edge to VDATA valid
Delay time, VCLK edge to VDATA invalid
ns
2
18
21
22
23
24
25
26
See figure 29
13.3
2
17
20
tc(VCLK)
ns
13.33
160
tt(VCLK)
ns
3
td(VCLKINH-VCLKH)
td(VCLKINL-VCLKL)
td(VCLK-VCTLV)
td(VCLK-VCTLIV)
td(VCLK-VDATAV)
td(VCLK-VDATAIV)
2
2
12
12
4
0
4
0
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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PAGE
13
TABLE I. Electrical performance characteristics - Continued.
No
Test
Symbol
Test condition
2/
Device type: All
1/
Limits
Low speed
1.5 Mbps
Min
Max
Unit
Full speed
12 Mbps
High speed 33/
480 Mbps
Min
Max
Min
Max
USB2.0 ELECTRICAL DATA/TIMING
Switching chrasteristics for USB2.0
1
2
3
4
8
9
output signal cross over
voltage 34/
Source (Host) driver jitter, next
transaction
Function driver jitter, next
transaction
Source (Host) driver jitter,
paired transaction 36/
Function driver jitter, next
transaction
Pulse duration, EOP
transmitter
Pulse duration, EOP receiver
Data rate
10
driver output resistance
5
6
7
No
75
300
4
20
0.5
ns
tf(D)
75
300
4
20
0.5
ns
tfrfm
80
125
90
111.11
%
VCRS
1.3
2
1.3
2
V
ns
Rise time, USB_DP and
USB_DM signals 34/
Fall time, USB_DP and
USB_DM signals 34/
Rise/Fall time, matching 35/
See figure 30
tr(D)
tjr(source)NT
2
2
tjr(FUNC)NT
25
2
tjr(source)PT
1
1
tjr(FUNC)PT
10
1
tw(EOPT)
1250
tw(EOPR)
t(DRATE)
670
1500
175
82
1.5
ZDRV
Test
160
12
28
Test condition
2/
Device type: All
UART ELECTRICAL DATA/TIMING
40.5
49.5
Symbol
480
Mb/s
49.5
Ω
Limits
Unit
Min
Max
0.99U 37/
0.99U 37/
1.05U 37/
1.05U 37/
ns
MHz
U-2 37/
U-2 37/
1.5
5
U+2 37/
U+2 37/
Timing requirements for UARTx receiver
4
Pulse duration, receive data bit (RXDn)
5
Pulse duration, receive start bit
Switching characteristic for UARTx transmit
1
2
3
UART0/1 maximun programmable baud rate
UART2 maximum programmable baud rate
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
tw(URXDB)
tw(URXSB)
See figure 31
f(baud)
See figure 31
tw(UTXDB)
tw(UTXSB)
ns
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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PAGE
14
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test condition
2/
Device type: All
1/
Limits
Unit
Min
Max
37.037
0.45*T
0.45*T
0.55*T
0.55*T
SPI ELECTRICAL DATA/TIMING
Timing requirements for SPI (All modes)
1
Cycle time, SPI_CLK
2
Pulse duration, SPI_CLK high (All master Modes)
3
Pulse duration, SPI_CLK low (All master Modes)
Timing requirements for SPI master mode [Clock phase = 0]
tc(CLK)
See figure 32
tw(CLKH)
tw(CLKL)
39/ See figure 33
4
Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKL)
Clock polarity = 0
(output) falling edge
5
Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKH)
Clock polarity = 1
(output) rising edge
6
Hold time, SPI_DI (input) valid after SPI_CLK
th(CLKL-DIV)
Clock polarity = 0
(output) falling edge
7
Setup time, SPI_DI (input) valid after SPI_CLK
th(CLKH-DIV)
Clock polarity = 1
(output) rising edge
Switching characteristics for SPI master mode [Clock phase = 0] See figure 33
Delay time, SPI_CLK (output) rising edge to
td(CLKH_DOV)
Clock polarity = 0
SPI_DO (output) transition
9
Delay time, SPI_CLK (output) falling edge to
td(CLKL_DOV)
Clock polarity = 1
SPI_DO (output) transition
10
Delay time, SPI_EN[1:0] (output) falling edge to first
td(ENL_CLKH/L)
SPI_CLK (output) rising or falling edge
11
Delay time, SPI_CLK (output) rising or falling edge e
td(CLKH/L-ENH)
to SPI_EN[1:0] (output) rising edge
Timing requirements for SPI master mode [Clock phase = 1] 39/ See figure 34
.5P+3
Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKL)
Clock polarity = 0
(output) riing edge
14
Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKH)
Clock polarity = 1
(output) falling edge
15
Hold time, SPI_DI (input) valid after SPI_CLK
th(CLKL-DIV)
Clock polarity = 0
(output) rising edge
16
Setup time, SPI_DI (input) valid after SPI_CLK
th(CLKH-DIV)
Clock polarity = 1
(output) falling edge
Switching characteristics for SPI master mode [Clock phase = 1] See figure 34
17
18
19
20
Delay time, SPI_CLK (output) falling edge to
SPI_DO (output) transition
Delay time, SPI_CLK (output) rising edge to
SPI_DO (output) transition
Delay time, SPI_EN[1:0] (output) falling edge to first
SPI_CLK (output) rising or falling edge
Delay time, SPI_CLK (output) rising or falling edge
to SPI_DO (output) high impedance
ns
.5P+3
.5P+3
2.5P+3
8
13
ns
-4
5
-4
5
2P 40/
40/
P+.5C
41/
41/
ns
.5P+3
ns
.5P+3
.5P+3
.5P+3
td(CLKH_DOV)
Clock polarity = 0
-4
5
td(CLKL_DOV)
Clock polarity = 1
-4
5
td(ENL_CLKH/L)
2P 40/
40/
td(CLKH/L-DOHz)
P+.5C
41/
41/
ns
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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PAGE
15
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
1/
Limits
Test condition
2/
Device type: All
Standard mode
Min
Max
Unit
Fast mode
Min
Max
I2C ELECTRICAL DATA/TIMING
Timing requirements for I2C timings
1
2
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
3
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
4
Pulse duration, SCL low
5
Pulse duration, SCL high
6
Setup time, SDA valid before SCL high
7
Hold time, SDA valid after SCL low (For
I2C bus device)
8
Pulse duration, SDA high between STOP
and Start conditions
9
Rise time, SDA
10
Rise time, SCL
11
Fall time, SDA
12
Fall time, SCL
13
Setup time, SCL high before SDA high (for
STOP condition)
14
Pulse duration, spike (must be suppressed)
15
Capacitive load for each bus line
Switching characteristics for I2C timings 47/
16
Cycle time, SCL
17
Delay time, SCL high to SDA low ( for a
repeated START condition)
18
Delay time, SDA low to SCL low (for a
START and a repeated START condition)
19
Pulse duration, SCL low
20
Pulse duration, SCL high
21
Dealy time, SDA valid to SCL high
22
Valid time, SDA valid after SCL low (For
I2C devices)
23
Pulse duration, SDA high between STOP
and START conditions
28
Delay time, SCL high to SDA high (for
STOP condition)
29
Capacitance for each I2C pin
tc(SCL)
tsu(SCLH-SDAL)
See figure 35
10
4.7
2.5
0.6
th(SCLL-SDAL)
4
0.6
tw(SCLL)
tw(SCLH)
tsu(SDAV-SCLH)
th(SDA-SCLL)
4.7
4
250
0 44/
1.3
0.6
100 43/
0 44/
tw(SDAH)
4.7
1.3
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
1000
1000
300
300
tsu(SCLH-SDAH)
4
tw(SP)
Cb 47/
tc(SCL)
µs
0.9 45/
µs
46/ 47/
46/ 47/
46/ 47/
46/ 47/
0.6
300
300
300
300
0
50
400
td(SCLH-SDAL)
10
4.7
2.5
0.6
td(SDAL-SCLL)
4
0.6
tw(SCLL)
tw(SCLH)
td(SDAV-SCLH)
tv(SCLL-SDAV)
4.7
4
250
0
1.3
0.6
100
0
tw(SDAH)
4.7
1.3
td(SCLH-SDAH)
4
0.6
Cp
ns
µs
400
See figure 36
ns
µs
ns
pF
µs
0.9
10
10
pF
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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CODE IDENT NO.
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PAGE
16
TABLE I. Electrical performance characteristics - Continued.
No
Test
Timing requirements for ASP
15
Symbol
44/ See figure
Test condition
2/
Device types: All
Cycle time, CLKR/X
tc(CKRX)
Min
38.5 or 2P 49/ 50/
19.25 or P 49/ 50/
51/
21
Pulse duration, CLKR/X high or CLKR/X low
OTG(CLKS)
5
Setup time, external FSR high before CLKR low
tsu(FRH-CKRL)
CLKR int
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
CLKR ext
6
th(CKRL-FRH)
CLKR int
0
CLKR ext
6
tsu(DRV-CKRL)
CLKR int
21
CLKR ext
6
0
8
Hold time, DR valid after CLKR low
th(CKRL-DRV)
CLKR int
CLKR ext
6
10
Setup time, external FSX high before CLKX low
tsu(FXH-CKXL)
CLKR int
21
CLKR ext
6
11
Hold time, external FSX high after CLKX low
th(CKXL-FXH)
Switching characteristics for McBSP
44/
2
Cycle time, CLKR/X
17
Delay time, CLKS high to internal CLKR/X
CLKR/X int
6P or 1 49/ 50/
53/
td(CLKS-CLKRX)
CLKR/X int
1
24
CLKR/X int
C-1 54/
C+1 54/
3
25
Pulse duration, CLKR/X high or CLKR/X low
tw(CKRX)
Delay time, CLKR high to internal FSR valid
td(CKRH-FRV)
9
Delay tine, CLKR high to internal FSX valid
12
Disable time, DX high impedance following last
data bit from CLKX high
13
Delay time, CLKX high to DX valid
ONLY applies when in data delay 0
(XDATDLY = 00b) mode
0
10
tc(CKRX)
4
Delay time, FSX high to DX valid
CLKR int
CLKR ext
ns
47/ See figure 37
3
14
Max
CLK ext
16
7
Unit
ASP ELECTRICAL DATA/TIMING
37
CLKS ext
6
Limits
CLKR int
td(CKXH-FXV)
tdis(CKXH-DXHZ)
td(CKXH-DXV)
td(FXH-DXV)
ns
CLKX ext
3
25
CLKX int
-4
8
CLKX ext
3
25
CLKX int
12
CLKX ext
12
CLKX int
-5
12
CLKX ext
3
25
FSX int
14
FSX ext
25
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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SIZE
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CODE IDENT NO.
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DWG NO.
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PAGE
17
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test condition
2/
Device type: All
1/
Master
Min
Unit
Max
ASP TIMING
ASP as SPI timing requirements CLKSP = 10b, CLKXP = 0
M30
Setup time, DR valid before CLKX low
tsu(DRV-CKXL)
M31
Hold time, DR valid after CLKX low
th(CKXL-DRV)
ASP as SPI switching characteristics CLKSP = 10b, CLKXP = 0
See figure 38
11
0
ns
M33
See figure 38
38.4 or 2P
49/ 50/
T-2
L1-2
-2
L1-3
ns
Cycle time, CLKX
tc(CKX)
M24
M25
M26
M27
Delay time, CLKX low to FSX high 55/
td(CKXL-FXH)
Delay time, FSX low to CLKX high 56/
td(FXL-CKXH)
Delay time, CLKX high to DX valid
td(CKXH-DXV
Disable time, DX high impedance following last
tdis(CKXL-DXHZ)
data bit from CLKX low
ASP as SPI timing requirements CLKSP = 11b, CLKXP = 0
M39
Setup time, DR valid before CLKX high
tsu(DRV-CKXH)
M40
Hold time, DR valid after CLKX high
th(CKXH-DRV)
ASP as SPI switching characteristics CLKSP = 11b, CLKXP = 0
M42
Cycle time, CLKX
M34
M35
M36
M37
Delay time, CLKX low to FSX high 57/
Delay time, FSX low to CLKX high 56/
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last
data bit from CLKX low
Delay time, FSX low to DX valid
M38
T+3
L1+2
6
L1+3
11
1
ns
ns
tdis(CKXL-DXHZ)
38.5 or 2P
49/ 50/
L1-2
T-2
-2
-3
L1+3
T+2
6
3
td(FXL-DXV)
H1- 2
H1+ 10
tc(CKX)
See figure 39
td(CKXL-FXH)
td(FXL-CKXH)
td(CKXL-DXV
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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CODE IDENT NO.
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DWG NO.
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PAGE
18
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test condition
2/
Device type: All
1/
Master
Min
Unit
Max
ASP TIMING - Continued
ASP as SPI timing requirements CLKSP = 10b, CLKXP = 1
M49
Setup time, DR valid before CLKX high
tsu(DRV-CKXH)
M50
Hold time, DR valid after CLKX high
th(CKXH-DRV)
ASP as SPI switching characteristics CLKSP = 10b, CLKXP = 1
See figure 40
11
0
ns
M52
See figure 40
38.5 or 2P
49/ 50/
T-1
H1-2
-2
H1-3
ns
Cycle time, CLKX
tc(CKX)
M43
M44
M45
M46
Delay time, CLKX HIGH to FSX high 51/
td(CKXH-FXH)
Delay time, FSX low to CLKX low 56/
td(FXL-CKXL)
Delay time, CLKX low to DX valid
td(CKXL-DXV
Disable time, DX high impedance following last
tdis(CKXH-DXHZ)
data bit from CLKX high
ASP as SPI timing requirements CLKSP = 11b, CLKXP = 1
T+3
H1+2
6
H1+3
M58
Setup time, DR valid before CLKX low
tsu(DRV-CKXL)
M59
Hold time, DR valid after CLKX low
th(CKXL-DRV)
ASP as SPI switching characteristics CLKSP = 11b, CLKXP = 1
See figure 41
11
0
ns
M62
Cycle time, CLKX
See figure 41
ns
M53
M54
M55
M56
Delay time, CLKX high to FSX high 51/
Delay time, FSX low to CLKX low 58/
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last
data bit from CLKX high
Delay time, FSX low to DX valid
tdis(CKXH-DXHZ)
38.5 or 2P
49/ 50/
H1-1
T-2
-2
-3
H1+3
T+2
6
3
td(FXL-DXV)
L1- 1
L1+ 10
M57
tc(CKX)
td(CKXH-FXH)
td(FXL-CKXL)
td(CKXL-DXV
See footnotes at end of table.
DEFENSE SUPPLY CENTER, COLUMBUS
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PAGE
19
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
1/
Test condition
2/
Device type: All
Limits
Min
Unit
Max
TIMER ELECTRICAL DATA/TIMING
Timing requirements for Timer input 59/ 60/ 61/
1
2
3
4
Cycle time, TIM_IN
Pulse duration, TIM_IN high
Pulse duration, TIM_IN low
Transition time, YTIM_IN
tc(TIN)
See figure 42
tw(TINPH)
tw(TINPL)
tt(TIN)
PULSE WIDTH MODULA (PWM)0/1/2/3 LECETRICAL TIMING DATA
Switching characteristics forPWM0/1/2/3 outputs
4P
0.45C
0.45C
ns
0.55C
0.55C
0.05C
1
2
3
4
Pulse duration, PWMx high
tw(PWMH)
See figure 43 and 44
Pulse duration, PWMx low
tw(PWML)
Transition time, PWMx
tt(PWM)
Delay time, CCDC(VD) trigger event to PWMx
td(CCDC-PWMV)
valid
REAL TIME OUT (RTO) ELECTRICAL/TIMING DATA
Switching characteristics for RTO outputs
P
P
1
2
3
4
Pulse duration, RTOx high
tw(RTOH)
See figure 45 and 46
Pulse duration, RTOx low
tw(RTOL)
Transition time, RTOx
tt(RTO)
Delay time, Timer 3 (TINT 12 or TINT34) trigger
td(TIMER3-RTOV)
event to RTOx valid
JTAG TEST PORT ELECTRICAL DATA/TIMING
Timing requirements for JTAG test port
P
P
1
Cycle time, TCK
2
Pulse duration, TCK high
3
Pulse duration, TCK low
4
Setup time, TDI valid before RTCK high
5
Hold time, TDI valid after RTCK high
6
Setup time, TMS valid before RTCK high
7
Hold time, TMS valid after RTCK high
Switching characteristics for JTAG test port
See figure 47
20
8
8
10
9
2
5
ns
See figure 47
20
10
10
ns
8
9
10
11
Cycle time, TCK
Pulse duration, TCK high
Pulse duration, TCK low
Rise time, all JTAG outputs
tc(TCK)
tw(TCKH)
tw(TCKL)
tsu(TDIV-RTCKH)
th(RTCKH-TDIV)
tsu(TMSV-RTCKH)
th(RTCKH-TMSIV)
tc(TCK)
tw(TCKH)
tw(TCKL)
tr(all JTAG
ns
.05P
10
ns
.1P
10
1.3
outputs)
12
Fall time, all JTAG outputs
1.3
tf(all JTAG
outputs)
13
Delay time, TCK low to TDO valid
td(RTCKL-TDOV)
0.25*tc(RTCK)
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
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Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over
the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by
characterization and/or design.
Over recommended ranges of supply voltage and operating temperature in the recommended operating conditions table. For
test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions
table. (Unless otherwise noted.)
These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os are 1.8 V I/Os and adhere to
USB2.0 spec.
This specifications applies only to pins with an internal pullup (PU) or pulldown (PD). See manufacturer data for more
information.
To pull up a signal to the opposite supply rail, a 1 kΩ resistor is recommended.
100% color bar are not supported. 100% color bar require 1.2 V peal-to peak. The video buffer only provides 1.0 V peak-topeak.
BTSEL[1:0] and AECFG[4:0] are the boot configuration pins during device reset.
C = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 24 MHz use C = 41.6 ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
C= MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns
tc(MXI1) = 41.6 ns and tc(MXI1) = s7.7 ns are the only supported cycle times for MXI1/CLKIN1.
C = MXI2/CLKIN2 cycle time in ns. For example, when MXI2/CLKIN2 frequency is 24 MHz use C = 41.6 ns
tc(MXI2) = 37.037 ns is the only supported cycle times for MXI2/CLKIN2.
P = 1/CLKOUT1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is 24 MHz use P = 41.6 ns.
P = 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is 8 MHz use P = 125 ns.
P = 1/CLKOUT3 clock frequency in nanoseconds (ns). For example, when CLKOUT3 frequency is 3 MHz use P = 333.3 ns.
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back
accesses of the GPIO is dependent upon internal bus activity.
The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have DM355 to
recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow
DM355 enough time to access the GPIO register through the internal bus.
E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock.
For Example when PLLC output clock = 432 MHz, E = 9.259 ns. See manufacturer for more information.
Set up before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add
extended wait states. Figure 15 and 16 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the $E requirement is
to the start of where the HOLD phase would begin if there were no extended wait cycles.
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write stobe, WH =
Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and
Asynchronous Wait cycle Configuration registers. These support the following range of values: TA[4-1], RS[16-1], RH[8-1],
WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1].
Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration
register.
tc(EM_CLK)/3
For this parameter, you may include margin in your board design so that the toh = 2.5 ns of the MMC/SD device is not
degraded at the DM355 input pin.
P = 1/SYSCLK4 in ns. For example, if SYSCLK4 frequency is 135 MHz, use P = 7.41 ns.
Use whichever value is greater.
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking
mode the rising edge of PCLK is referenced. When in negative edge clocking mode the failing edge of PCLK is referenced.
For timing specifications relating to PCLK see manufacturer for more information.
VCTL = HSYNC, VSYNC, and FIELD
VCLKIN = PCLK or EXTCLK
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VCTL = HSYNC, VSYNC, FIELD and LCD_OE
VCLKIN = PCLK or EXTCLK. for timing specifications relating to PCLK see manufacturer data for more information.
For more detailed specification, see manufacturer data for more information.
Low speed: CL = 200 pF, Full speed: CL = 50 pF, High speed: CL = 50 pF
tfrfm = (tr/tf) x 100. [Excluding the first transaction from the idle state.]
tjr = tpx(1) – tpx(0)
U = UART baud time = 1/programmed baud rate.
T = tc(CLK) = SPI_CLK period is equal to the SPI module clock divided by a configurable divider.
P = 1/SYSCLK2 in ns. For example, if SYSCLK2 frequency is 135 MHz, use P = 7.41 ns.
The delay time can be adjusted using the SPI module register C2TDELAY.
The delay time can be adjusted using the SPI module register T2CDELAY.
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is
powered down.
A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) =
2
1000 + 250 = 1250 ns (according to the standard mode I C bus specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
20 + 0.1Cb
Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall time are allowed.
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal
are also inverted.
P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1
Use whichever value is greater.
The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLRK/X
cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC
timing requirements.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK2, where SYSCLK2 is an output of PLLC1)
S = sample rate generator input clock = CLKS if CLKSM = 0
H = CLKX high pulse width = (CLKGDV/2 + 1)*S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLGKDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit
T = CLKX period = (1 + CLKGDV) x 2P
L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) x 2P when CLKGVD is even
H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) x 2P when CLKGDV is even
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of
the master clock (CLKX).
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active low slave enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
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TABLE I. Electrical performance characteristics - Continued.
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FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of
the master clock (CLKX).
GPIO000, GPIO001, GPIO002, and GPIO003 can be used as an external clock input for Timer 3.
P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
C = TIM_IN ycle time in ns. For example, when TIM_IN frequency is 24 MHz use C = 41.6 ns.
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Case X
Symbol
A
A1
A2
b
Notes:
1.
2.
Millimeters
Min
Max
1.30
0.23
0.33
0.84
0.94
0.36
0.46
Symbol
D/E
D1/E1
e
Millimeters
Min
Max
12.90
13.10
11.70 TYP
0.65 BSC
This drawing is subject to change without notice.
Dimensioning and tolerancing per ASME Y14.5M-1994
FIGURE 1. Case outline.
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Case X
FIGURE 2. Terminal connections.
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Case X
FIGURE 2. Terminal connections - Continued.
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Case - Continued
FIGURE 2. Terminal connections - Continued.
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Case - Continued
FIGURE 2. Terminal connections - Continued.
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FIGURE 3. Block diagram - Continued.
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Notes:
1. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line
effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
FIGURE 4. Test load circuit for AC timing measurements.
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FIGURE 5. Timing waveforms.
FIGURE 6. Timing waveforms.
FIGURE 7. Timing waveforms.
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FIGURE 8. Timing waveforms.
FIGURE 9. Timing waveforms.
FIGURE10. Timing waveforms.
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FIGURE 11. Timing waveforms.
FIGURE12. Timing waveforms.
FIGURE 13. Timing waveforms.
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FIGURE14. Timing waveforms.
FIGURE15. Timing waveforms.
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FIGURE 16. Timing waveforms.
FIGURE 17. Timing waveforms.
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FIGURE 18. Timing waveforms.
FIGURE 19. Timing waveforms.
FIGURE 20. Timing waveforms.
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FIGURE 21. Timing waveforms.
FIGURE 22. Timing waveforms.
FIGURE 23. Timing waveforms.
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FIGURE 24. Timing waveforms.
FIGURE 25. Timing waveforms.
FIGURE 26. Timing waveforms.
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NOTES:
1.
2.
VCLKIN = PCLK or EXTCLK
VCTL = HSYNC, VSYNC, and FIELD
FIGURE 27. Timing waveforms.
NOTES:
1.
2.
3..
VCLKIN = PCLK or EXTCLK
VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
VDATA = COUT[7:0], YOUT[7:0], R{7:3], G[7:2], and B[7:3]
FIGURE 28. Timing waveforms.
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NOTES:
1.
2.
3..
VCLKIN = PCLK or EXTCLK
VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
VDATA = COUT[7:0], YOUT[7:0], R{7:3], G[7:2], and B[7:3]
FIGURE 29. Timing waveforms.
FIGURE 30. Timing waveforms.
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FIGURE 31. Timing waveforms.
FIGURE 32. Timing waveforms.
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FIGURE 33. Timing waveforms.
FIGURE 34. Timing waveforms.
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FIGURE 35. Timing waveforms.
FIGURE 36. Timing waveforms.
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FIGURE 37. Timing waveforms.
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FIGURE 38. Timing waveforms.
FIGURE 39. Timing waveforms.
FIGURE 40. Timing waveforms.
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FIGURE 41. Timing waveforms.
FIGURE 42. Timing waveforms.
FIGURE 43. Timing waveforms.
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FIGURE 44. Timing waveforms.
FIGURE 45. Timing waveforms.
FIGURE 46. Timing waveforms.
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FIGURE 47. Timing waveforms.
FIGURE 48. Timing waveforms.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.
1/
Vendor item drawing administrative
control number 1/
Device manufacturer
CAGE code
Vendor part number
V62/09643-01XE
01295
SM32DM355GCEM216EP
The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
CAGE code
01295
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Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
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