IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 IA6805E2 Microprocessor Unit Data Sheet Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 1 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 FEATURES • • • • • • • • • • • • Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and Motorola© MC146805E2 Internal 8-bit Timer with 7-Bit Programmable Prescaler On-chip Clock Memory Mapped I/O Versatile Interrupt Handling True Bit Manipulation Bit Test and Branch Instruction Vectored Interrupts Power-saving STOP and WAIT Modes Fully Static Operation 112 Bytes of RAM Packaging options available: 40 Pin Plastic DIP or, 44 Pin Plastic Leaded Chip Carrier, Standard or RoHS packages available The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable timing. OSC1 TIMER PB0 (41) (40) RESET_N OSC2 IRQ_N (1) (42) LI (2) (43) DS DS (3) (3) RW_N LI (4) (2) NC (1) IRQ_N (5) RESET_N (6) Package Pinout OSC1 (38) OSC2 (4) (37) TIMER RW_N (5) (36) PB0 AS (7) (39) PB1 AS (6) (35) PB1 PA7 (8) (38) PB2 PA7 (7) (34) PB2 PA6 (9) PA6 (8) (33) PB3 PA5 (10) VDD VDD (39) (44) (40) IA6805E2 40 Pin DIP IA6805E2 44 Pin LCC (37) PB3 (36) PB4 PA5 (9) (32) PB4 PA4 (11) (35) PB5 PA4 (10) (31) PB5 PA3 (12) (34) PB6 PA3 (11) (30) PB6 PA2 (13) (33) PB7 PA2 (12) (29) PB7 PA1 (14) (32) B0 B4 (23) B5 A8 (19) (22) B6 VSS (20) (21) B7 Copyright © 2007 (28) (24) (18) (27) (17) A9 B4 A10 NC B3 (26) (25) B5 (16) (25) B3 A11 B6 (29) (24) (17) B7 NC (23) B2 VSS (26) (22) (15) A8 B2 A12 (21) B1 (30) A9 (31) (16) (20) (15) NC A10 PA0 B1 (19) B0 (27) (18) (28) (14) A11 (13) A12 PA1 PA0 IA211081401-03 www.Innovasic.com Customer Support: Page 2 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Description The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The following paragraphs will further describe this system block diagram and design in more detail. TIMER PRESCALER OSC1 TIMER/ COUNTER OSC2 RESET_N TIMER CONTROL OSCILLATOR LI IRQ_N PA0 B0 PA0 ACCUMULATOR PA1 8 CPU CONTROL A PA2 PORT A I/O LINES PA3 PA4 PORT A REG DATA DIR REG X PA7 STACK POINTER 6 PB1 PB2 PB3 PB4 PORT B REG DATA DIR REG B4 MULTIPLEXED ADDRESS DATA BUS B6 B7 CPU SP PROGRAM COUNTER HIGH PCH 5 PB0 B3 B5 CONDITION CODE 5 REGISTER CC PA5 PA6 PORT B I/O LINES B2 MUX BUS DRIVE INDEX REGISTER 8 B1 A8 A9 PROGRAM COUNTER LOW PCL 8 ADDRESS DRIVE A10 ADDRESS BUS A11 A12 ALU PB5 PB6 PB7 AS 112x8 RAM BUS CONTROL DS RW_N ADDRESS STROBE DATA STROBE READ/WRITE Figure 1. System Block Diagram Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 3 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 I/O Signal Description The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. S IG N A L N A M E V DD an d V SS (P o w e r a n d G ro u n d ) R ESET _n (R e s e t) IR Q _ n (In te rru p t R e q u e s t) LI (L o a d In s tru c tio n ) I/O D E S C R IP T IO N N /A S o u rc e : T h e s e tw o p in s p ro v id e p o w e r to th e c h ip . p o w e r a n d V S S is g ro u n d . I T T L : In p u t p in th a t c a n b e u s e d to re s e t th e M P U 's in te rn a l s ta te b y p u llin g th e re s e t_ n p in lo w . I T T L : In p u t p in th a t is le v e l a n d e d g e s e n s itiv e . C a n b e u s e d to re q u e s t a n in te rru p t sequence. O DS (D a ta S tro b e ) O R W _n (R e a d /W rite ) O AS (A d d re s s S tro b e ) O P A 0 -P A 7 /P B 0 -P B 7 (In p u t/O u tp u t L in e s ) I/O A 8 -A 1 2 (H ig h O rd e r A d d re s s L in e s ) O B 0 -B 7 (A d d re s s /D a ta B u s ) I/O I T im e r O SC 1, O SC 2 (S y s te m C lo c k ) I/O C rys ta l E x te rn a l C lo c k V D D p ro v id e s + 5 v o lts (± 0 .5 ) T T L w ith s le w ra te c o n tro l: O u tp u t p in u s e d to in d ic a te th a t a n e x t o p c o d e fe tc h is in p ro g re s s . U s e d o n ly fo r c e rta in d e b u g g in g a n d te s t s ys te m s . N o t c o n n e c te d in n o rm a l o p e ra tio n . O v e rla p s D a ta S tro b e (D S ) s ig n a l. T h is o u tp u t is c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d a n d 5 0 p F . T T L w ith s le w ra te c o n tro l: O u tp u t p in u s e d to tra n s fe r d a ta to o r fro m a p e rip h e ra l o r m e m o ry. D S o c c u rs a n ytim e th e M P U d o e s a d a ta re a d o r w rite a n d d u rin g d a ta tra n s fe r to o r fro m in te rn a l m e m o ry. D S is a v a ila b le a t f O S C ¸5 w h e n th e M P U is n o t in th e W A IT o r S T O P m o d e . T h is o u tp u t is c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d a n d 130pF. T T L w ith s le w ra te c o n tro l: O u tp u t p in u s e d to in d ic a te th e d ire c tio n o f d a ta tra n s fe r fro m in te rn a l m e m o ry, I/O re g is te rs , a n d e x te rn a l p e rip h e ra l d e vic e s a n d m e m o rie s . In d ic a te s to a s e le c te d p e rip h e ra l w h e th e r th e M P U is to re a d (R W _ n h ig h ) o r w rite (R W _ n lo w ) d a ta o n th e n e x t d a ta s tro b e . T h is o u tp u t is c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d a n d 1 3 0 p F . T T L w ith s le w ra te c o n tro l: O u tp u t s tro b e u s e d to in d ic a te th e p re s e n c e o f a n a d d re s s o n th e 8 -b it m u ltip le x e d b u s . T h e A S lin e is u s e d to d e m u ltip le x th e e ig h t le a s t s ig n ific a n t a d d re s s b its fro m th e d a ta b u s . A S is a v a ila b le a t f O S C ¸ 5 w h e n th e M P U is n o t in th e W A IT o r S T O P m o d e s . T h is o u tp u t is c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d a n d 1 3 0 p F . T T L w ith s le w ra te c o n tro l: T h e s e 1 6 lin e s c o n s titu te In p u t/O u tp u t p o rts A a n d B . E a c h lin e is in d iv id u a lly p ro g ra m m e d to b e e ith e r a n in p u t o r o u tp u t u n d e r s o ftw a re c o n tro l o f th e D a ta D ire c tio n R e g is te r (D D R ) a s s h o w n b e lo w in T a b le 1 a n d F ig u re 2 . T h e p o rt I/O is p ro g ra m m e d b y w ritin g th e c o rre s p o n d in g b it in th e D D R to a "1 " fo r o u tp u t a n d a "0 " fo r in p u t. In th e o u tp u t m o d e th e b its a re la tc h e d a n d a p p e a r o n th e c o rre s p o n d in g o u tp u t p in s . A ll th e D D R 's a re in itia lize d to a "0 " o n re s e t. T h e o u tp u t p o rt re g is te rs a re n o t in itia lize d o n re s e t. E a c h o u tp u t is c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d a n d 5 0 p F . T T L w ith s le w ra te c o n tro l: T h e s e five o u tp u ts c o n s titu te th e h ig h e r o rd e r n o n m u ltip le x e d a d d re s s lin e s . E a c h o u tp u t is c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d and 130pF. T T L w ith s le w ra te c o n tro l: T h e s e b i-d ire c tio n a l lin e s c o n s titu te th e lo w e r o rd e r a d d re s s e s a n d d a ta . T h e s e lin e s a re m u ltip le x e d w ith a d d re s s p re s e n t a t a d d re s s s tro b e tim e a n d d a ta p re s e n t a t d a ta s tro b e tim e . W h e n in th e d a ta m o d e , th e s e lin e s a re b i-d ire c tio n a l, tra n s fe rrin g d a ta to a n d fro m m e m o ry a n d p e rip h e ra l d e v ic e s a s in d ic a te d b y th e R W _ n p in . A s o u tp u ts , th e s e lin e s a re c a p a b le o f d riv in g o n e s ta n d a rd T T L lo a d a n d 1 3 0 p F . T T L : In p u t u s e d to c o n tro l th e in te rn a l tim e r/c o u n te r c irc u itry. T T L O s c illa to r in p u t/o u tp u t: T h e s e p in s p ro v id e c o n tro l in p u t fo r th e o n -c h ip c lo c k o s c illa to r c irc u its . E ith e r a c rys ta l o r e x te rn a l c lo c k is c o n n e c te d to th e s e p in s to p ro v id e a s ys te m c lo c k . T h e c rys ta l c o n n e c tio n is s h o w n in F ig u re 3 . T h e O S C 1 to b u s tra n s itio n s fo r s ys te m d e s ig n s u s in g o s c illa to rs s lo w e r th a n 5 M H z is s h o w n in F ig u re 4 . T h e c irc u it s h o w n in F ig u re 3 is re c o m m e n d e d w h e n u s in g a c rys ta l. A n e x te rn a l C M O S o s c illa to r is re c o m m e n d e d w h e n u s in g c rys ta ls o u ts id e th e s p e c ifie d ra n g e s . T o m in im ize o u tp u t d is to rtio n a n d s ta rt-u p s ta b iliza tio n tim e , th e c rys ta l a n d c o m p o n e n ts s h o u ld b e m o u n te d a s c lo s e to th e in p u t p in s a s p o s s ib le . W h e n a n e x te rn a l c lo c k is u s e d , it s h o u ld b e a p p lie d to th e O S C 1 in p u t w ith th e O S C 2 in p u t n o t c o n n e c te d , a s s h o w n in F ig u re 3 . Table 1 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 4 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 I/O Pin Functions R/W-n DDR I/O Pin Functions 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 the I/O pin is in an output mode. The output data latch is read. I/O Port Circuitry and Register Configuration: DATA DIRECTION REGISTER BIT TO AND LATCHED OUTPUT DATA BIT FROM I/O PIN OUTPUT CPU INPUT REG BIT INPUT I/O PIN 7 6 5 4 3 2 1 0 DATA DIRECTION DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 A(B) (DDB7) (DDB6) (DDB5) (DDB4) (DDB3) (DDB2) (DDB1) (DDB0) REGISTER PORT A(B) REGISTER PIN $0004 ($0005) $0000 ($0001) PA7 (PB7) PA6 (PB6) PA5 (PB5) PA4 (PB4) PA3 (PB3) PA2 (PB2) PA1 (PB1) PA0 (PB0) Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines) Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 5 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Crystal Parameters Representative Frequencies: 5.0 MHz 50Ω 8 pF 0.02 pF 50 k 15-30 pF 15-25 pF RS max C0 C1 Q COSC1 COSC2 4.0 MHz 75Ω 7 pF 0.012 pF 40 k 15-30 pF 15-25 pF 1.0 MHz 400Ω 5 pF 0.008 pF 30 k 15-40 pF 15-30 pF Oscillator Connections: CRYSTAL CIRCUIT CRYSTAL OSCILLATOR CONNECTIONS L C1 38 OSC2 C0 38 NC 10 MΩ 39 OSC1 38 39 38 IA6805E2 OSC1 C OSC1 C OSC2 OSC1 OSC2 39 OSC2 39 OSC2 OSC1 ia6805E2 RS tOH tOL OSC1 PIN t tOLOL Figure 3. OSC1, OSC2 (System Clock) OSC1 to Bus Transitions Timing Waveforms: OSC1 AS DS RW_n A[12:8] B[7:0] MPU READ MUX ADDR B[7:0] MPU WRITE MUX ADDR MPU READ DATA* MPU WRITE DATA *READ DATA "LATCHED" ON DS FALL Figure 4. OSC1, OSC2 (System Clock) Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 6 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Functional Description Memory: The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations are divided into internal memory space and external memory space as shown in Figure 5. The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112 bytes of RAM. The MPU can read from or write to any of these locations. During program reads from on chip locations, the MPU accepts data only from the addressed on chip location. Any read data appearing on the input bus is ignored. The shared stack area is used during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used for data storage or temporary work locations, but care must be taken to prevent it from being overwritten due to stacking from an interrupt or subroutine call. $0000 0 I/O PORTS TIMER RAM ACCESS VIA PAGE 0 DIRECT ADDRESS $007F 127 $0080 128 0 PORT A DATA REGISTER 1 PORT B DATA REGISTER 2 EXTERNAL MEMORY SPACE 3 EXTERNAL MEMORY SPACE 4 PORT A DATA DIRECTION REGISTER 5 PORT B DATA DIRECTION REGISTER 6 EXTERNAL MEMORY SPACE 7 EXTERNAL MEMORY SPACE 255 $00FF 8 TIMER DATA REGISTER 256 $0100 9 TIMER CONTROL REGISTER 10 EXTERNAL MEMORY SPACE 15 EXTERNAL MEMORY SPACE (8064 BYTES) 16 63 64 TIMER INTERRUPT FROM WAIT STATE ONLY $1FF6 - $1FF7 TIMER INTERRUPT $1FF8 - $1FF9 EXTERNAL INTERRUPT $1FFA - $1FFB SWI $1FFC - $1FFD RESET $1FFE - $1FFF INTERRUPT VECTORS 8191 RAM (112 BYTES) STACK (64 BYTES MAX) 127 Figure 5. Memory Map Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 7 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Registers: The following paragraphs describe the registers contained in the MPU. Figure 6 shows the programming model and Figure 7 shows the interrupt stacking order. 7 0 A ACCUMULATOR 7 0 X 12 8 7 0 PCL PCH 12 0 0 0 INDEX REGISTER 0 0 6 1 0 PROGRAM COUNTER 0 SP 4 STACK POINTER 0 CC H I N Z C CONDITION CODE REGISTER CARRY/BORROW ZERO NEGATIVE INTERRUPT MASK HALF CARRY Figure 6. Programming Model NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. STACK 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER 0 0 0 PCH PCL I N T E R R U P T DECREASING MEMORY ADDRESSES UNSTACK Figure 7. Interrupt Stacking Order Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 8 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 A(Accumulator): The accumulator is an 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. X(Index Register): The index register is an 8-bit register used during the indexed addressing mode. It contains an 8-bit value used to create an effective address. The index register may also be used as a temporary storage area when not performing addressing operations. PC(Program Counter): The program counter is a 13-bit register that holds the address of the next instruction to be performed by the MPU. SP(Stack Pointer): The stack pointer is a 13-bit register that holds the address of the next free location on the stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $007f. The seven most significant bits of the stack pointer are permanently set to 0000001. They are appended to the six least significant register bits to produce an address range down to location $0040. The stack pointer gets decremented as data is pushed onto the stack and incremented as data is removed from the stack. The stack area of RAM is used to store the return address on subroutine calls and the machine state during interrupts. The maximum number of locations for the stack pointer is 64 bytes. If the stack goes beyond this limit the stack pointer wraps around and points to its upper limit thereby losing the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and interrupts use 5 bytes. CC(Condition code Register): The condition code register is a 5-bit register that indicates the results of the instruction just executed. The bit is set if it is high. A program can individually test these bits and specific actions can be taken as a result of their states. Following is an explanation of each bit. C(Carry Bit): The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU) occurred during the last arithmetic instruction. This bit is also modified during bit test, shift, rotate, and branch types of instructions. Z(Zero Bit): The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero. N(Negative Bit): The negative bit indicates the result to the last arithmetic, logical, or data manipulation was negative (bit 7 in the result is high). Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 9 of 33 1-888-824-4184 © IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 I(Interrupt Mask Bit) The interrupt mask bit indicates that both the external interrupt and the timer interrupt are disabled (masked). If an interrupt occurs while this bit is set, the interrupt is latched and is processed as soon as the interrupt bit is cleared. H(Half Carry Bit) The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an ADD or ADC operation. Resets: The MPU can be reset by initial power up or by the external reset pin (reset_n). POR(Power On Reset) Power on reset occurs on initial power up. It is strictly for power initialization conditions and should not be used to detect drops in the power supply voltage. There is a 1920 tCYC time out delay from the time the oscillator is detected. If the reset_n pin is still low at the end of the delay, the MPU will remain in the reset state until the external pin goes high. Reset_n The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of tcyc to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise immunity capability. Interrupts: The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer interrupt request, or the software interrupt instruction. When any of these interrupts occur, normal processing is suspended at the end of the current instruction execution. The processor registers are saved on the stack (stacking order shown in Figure 7) and the interrupt mask (I) is set to prevent additional interrupts. Normal processing resumes after the RTI instruction causes the register contents to be recovered from the stack. When the current instruction is completed, the processor checks all pending hardware interrupts and if unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. Masked interrupts are latched for later interrupt service. External interrupts hold higher priority than timer interrupts. At the end of an instruction execution, if both an external interrupt and timer interrupt are pending, the external interrupt is serviced first. The SWI gets executed with the same priority as any other instruction if the hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing flowchart. Copyright © 2007 IA211081401-03 © Page 10 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 RESET SET I BIT ? CLEAR I_CC <= 1 SP <= $007F DDRs <= 0 CLR IRQ_N LOGIC TIMER <= $FF PRESCALER <= $7F TCR <= $7f STACK PC, X, A, CC IRQ_N EDGE ? Y IRQ_N N I <= 1 TCR6=0 AND TCR7=1? PUT 1FFE,1FFF ON ADDRESS BUS CLEAR IRQ_N REQUEST LATCH Y TIMER LOAD PC FROM: SWI: 1FFC/1FFD IRQ_N: 1FFA/1FFB TIMER: 1FF8/1FF9 TIMER WAIT:1FF6/ 1FF7 N FETCH INSTRUCTION Y RESET_N PIN = LOW IN RESET ? N RESET_N PIN = LOW LOAD PC FROM 1FFE/1FFF IS FETCHED INSTRUCTION AN SWI? Y PC+1=>PC SWI N EXECUTE ALL INSTRUCTION CYCLES Figure 8. Reset and Interrupt Processing Flowchart Copyright © 2007 IA211081401-03 © Page 11 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 External Interrupt: If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code register is cleared, the external interrupt occurs. When the interrupt is recognized, the current state of the machine is pushed onto the stack and the condition code register I-bit gets set masking further interrupts until the present one is serviced. The program counter is then loaded with the contents of the interrupt vector, which contains the location of the interrupt service routine. The contents of $1FFA and $1FFB specify the address for this service routine. A functional diagram of the external interrupt is shown in Figure 9 and a mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows two different treatments of the interrupt line (irq_n) to the processor. The first shows several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The second shows single pulses on the interrupt line spaced far enough apart to be serviced. The minimum time between pulses is a function of the length of the interrupt service. After a pulse occurs, the next pulse should not occur until an RTI has occurred. The time between pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes to complete the service routine including the RTI instruction. VDD D INTERRUPT PIN EXTERNAL INTERUPT REQUEST Q C Q I BIT (CCR) R POWER-ON RESET EXTERNAL RESET EXTERNAL INTERRUPT BEING SERVICED Figure 9. Interrupt Functional Diagram Copyright © 2007 IA211081401-03 © Page 12 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Figure 10. Interrupt Mode Diagram Timer Interrupt: If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is generated. When the interrupt is recognized, the current state of the machine is pushed onto the stack and the condition code register I-bit gets set masking further interrupts until the present one is serviced. The program counter is then loaded with the contents of the timer interrupt vector, which contains the location of the timer interrupt service routine. The contents of $1FF8 and $1FF9 specify the address for this service routine. If the MPU is in the wait mode and a timer interrupt occurs, then the contents of $1FF6 and $1FF7 specify the service routine. When the timer interrupt service routine is complete, the software executes an RTI instruction to restore the machine state and starts executing the interrupt program. Software Interrupt: Software interrupt is an executable instruction regardless of the state of the interrupt mask bit (I) in the condition code register. SWI is similar to hardware interrupts. It executes after the other interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD specify the address for this service routine. Low Power Modes: The low power modes consist of the stop instruction and the wait instruction. following paragraphs explain these modes of operation. Copyright © 2007 IA211081401-03 © Page 13 of 33 The www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Stop Modes: The stop instruction places the MPU in low power consumption mode. The stop instruction disables clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and TCR7) are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. The DS and AS output lines go “low” and the RW_n line goes “high”. The multiplexed address/data bus goes to the data input state. The high order address lines remain at the address of the next instruction. External interrupts are enabled by clearing the I bit in the condition code register. All other registers, memory, and I/O remain unaltered. Only an external interrupt or reset will bring the MPU out of the stop mode. Figure 11 shows a flowchart of the stop function. STOP TCR BIT 7 <= 0 TCR BIT 6 <= 1 CLEAR I BIT N RESET? Y N EXTERNAL INTERRUPT? Y FETCH EXTERNAL INTERRUPT OR RESET VECTOR Figure 11. STOP Function Flowchart Copyright © 2007 IA211081401-03 © Page 14 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Wait Mode: The wait instruction places the MPU in low power consumption mode. The wait instruction disables clocking of most internal registers. The DS and AS output lines go “low” and the RW_n line goes “high”. The multiplexed address/data bus goes to the data input state. The high order address lines remain at the address of the next instruction. External interrupts are enabled by clearing the I bit in the condition code register. All other registers, memory, and I/O remain unaltered. Only an external interrupt, timer interrupt, or reset will bring the MPU out of the wait mode. The timer may be enabled to allow a periodic exit from the wait mode. If an external and a timer interrupt occur at the same time, the external interrupt is serviced first. Then, if the timer interrupt request is not cleared in the external interrupt routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MPU is no longer in the wait mode. Figure 12 shows a flowchart of the wait function. WAIT OSCILLATOR ACTIVE, CLEAR I BIT, TIMER CLOCK ACTIVE, N RESET? Y EXTERNAL INTERRUPT? Y N TIMER INTERRUPT? (TCR BIT7 = 1) N Y TCR BIT 6 = 0? N Y FETCH EXTERNAL INTERRUPT, RESET, OR TIMER INTERRUPT (FROM WAIT MODE ONLY) Figure 12. WAIT Function Flowchart Copyright © 2007 IA211081401-03 © Page 15 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Timer: The MPU contains a single 8-bit software programmable counter driven by a 7-bit software programmable prescaler. The counter may be loaded under program control and decrements to zero. When the counter decrements to zero, the timer interrupt request bit in the timer control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an interrupt request is generated. After completion of the current instruction, the current state of the machine is pushed onto the stack. The timer interrupt vector address is then fetched from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7 is fetched. Power-On-Reset causes the counter to set to $FF. NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal clock (AS) or external input. 2. Counter is written to during Data Strobe (DS) and counts down continuously. TIMER (PIN 37) TIMER_n EXT CLK PRESCALER (7 BITS) COUNTER (8 BITS) INTERRUPT CONTROL 2 - TO - 1 MUX INTERRUPT READ WRITE INT CLK ENABLE / DISABLE_n INTERNAL_n / EXTERNAL INTERNAL CLOCK TCR4 TCR5 TCR3 TCR2 TCR1 TCR0 SETTING TCR3 CLEARS PRESCALER TO ÷ 1 SOFTWARE FUNCTIONS Figure 13. Timer Block Diagram Copyright © 2007 IA211081401-03 © Page 16 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 The counter continues to count past zero, falling from $00 to $FF, and continues. The processor may read the counter at any time without disturbing the count by reading the timer data register (TDR). This allows a program to determine the length of time since a timer interrupt has occurred. The timer interrupt request bit remains set until cleared by software. The interrupt is lost if this happens before the timer interrupt is serviced. The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits 0-2 are programmed to choose the appropriate prescaler output, which is used as the count input. The prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation errors. The processor cannot write to or read from the prescaler. Timer Input Mode 1: When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the timer input is disabled. The internal clock mode can be used for periodic interrupt generation as well as a reference for frequency and event measurement. The internal clock is the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait instruction where it goes low. During the wait instruction the internal clock to the timer continues to run at its normal rate. Timer Input Mode 2: When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to form the timer input. This mode can be used to measure external pulse widths. The external pulse turns on the internal clock for the duration of the pulse. The count accuracy in this mode is ±1 clock. Accuracy improves with longer input pulse widths. Timer Input Mode 3: When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled. Timer Input Mode 4: When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the timer input then comes from the external TIMER pin. The external clock can be used to count external events as well as to provide an external frequency for generating periodic interrupts. Copyright © 2007 IA211081401-03 © Page 17 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 TCR (Timer Control Register ($0009)): An 8-bit register that controls functions such as configuring operation mode, setting ratio of the prescaler, and generating timer interrupt request signals. All bits except bit 3 are read/write. Bits TCR5 - TCR0 are unaffected by reset_n. 7 6 5 4 3 2 1 0 TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Reset: 0 1 0 0 0 0 0 0 TCR7 – Timer Interrupt Request Used to indicate the timer interrupt when it is logic one. 1 – Set when the counter decrements to zero or under program control. 0 – Cleared on external reset, POR, STOP instruction, or program control. TCR6 – Timer Interrupt Mask Used to inhibit the timer interrupt. 1 – Interrupt inhibited. Set on external reset, POR, STOP instruction, or program control. 0 – Interrupt enabled. TCR5 – External or Internal Selects input clock source. Unaffected by reset. 1 – External clock selected. 0 – Internal clock selected (AS) (fOSC/5). TCR4 – Timer External Enable Used to enable external timer pin or to enable the internal clock. Unaffected by reset. 1 – Enables external timer pin. 0 – Disables external timer pin. Copyright © 2007 IA211081401-03 © Page 18 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 TCR3 – Prescaler Clear Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location always indicates a zero. Unaffected by reset. TCR2, TCR1, TCR0 – Prescaler select bits Decoded to select one of eight outputs of the prescaler. Unaffected by reset. Prescaler TRC2 0 0 0 0 1 1 1 1 Copyright © 2007 TRC1 0 0 1 1 0 0 1 1 TRC0 0 1 0 1 0 1 0 1 IA211081401-03 © Page 19 of 33 RESET ÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Instruction Set Description The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, readmodify-write, branch, bit manipulation, and control. Register/Memory Instructions: Most of the following instructions use two operands. One is either the accumulator or the index register and the other is obtained from memory. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Function Load A from m em ory Load X from m em ory Store A in m em ory Store X in m em ory A dd m em ory to A A dd m em ory and carry to A Subtract m em ory Subtract m em ory from A w ith B orrow A N D m em ory to A O R m em ory w ith A Exclusive O R m em ory w ith A A rithm etic com pare A w ith m em ory A rithm etic com pare X w ith m em ory B it test m em ory w ith A (logical com pare) Jum p U nconditional Jum p to subroutine M nem onic LDA LD X ST A ST X ADD ADC SU B SB C AND ORA EOR CM P CPX B IT JM P JSR Read-Modify-Write Instructions: These instructions read a memory or register location, modify or test its contents and then write the modified value back to memory or the register. Function Increment Decrement Clear Complement Negate (2's complement) Rotate Left Thru Carry Rotate Right Thru Carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Copyright © 2007 IA211081401-03 © Page 20 of 33 Mnemonic INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Bit Manipulation Instructions: The MPU is capable of altering any bits residing in the first 256 bytes of memory. An additional feature allows the software to test and branch on the state of any bit within these locations. For test and branch instructions the value of the bit tested is placed in the carry bit of the condition code register. Mnemonic n = 0…7 Function Branch if bit n set Branch if bit n clear Set bit n Clear bit n BRSET n BRCLR n BSET n BCLR n Branch Instructions: If a specific condition is met, the instruction branches. If not, no operation is performed. Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear Branch if higher or same Branch if carry set Branch if lower Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit clear Branch if interrupt mask bit set Branch if interrupt line low Branch if interrupt line high Branch to subroutine Copyright © 2007 IA211081401-03 © Page 21 of 33 Mnemonic BRA BRN BHI BLS BCC BHS BCS BLO BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Control Instructions: These are used to control processor operation during program execution. They are register reference instructions. Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-Operation Stop Wait Copyright © 2007 IA211081401-03 © Page 22 of 33 Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Opcode Map Summary: The following table is an opcode map for the instructions used on the MPU. The legend following the table shows how to use the table. Bit Manipulation Branch Read-Modify-Write Control Register/Memory BTB BSC REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 Hi 0 1 2 3 4 5 6 7 8 9 A B C D E F Hi Low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Low 0 0000 BRSET0 5 3 BRCLR0 3 3 BRCLR1 3 BRSET2 3 3 3 BRCLR3 3 B 1011 3 E 1110 F 1111 5 DIR 1 5 5 ROR REL 2 BSC 2 5 IX 2 6 ASR INH 2 3 2 5 DIR 1 INH 1 3 5 3 INH 2 3 IX1 1 6 IX 5 1 IX 1 5 BSET7 BIL 5 BRCLR7 3 BTB 2 5 BCLR7 BSC 2 INH 2 INH 2 Inherent Accumulator Index Register Immediate Direct Extended Copyright © 2007 6 0110 IX1 1 6 STA 3 LDA IX 5 STA 4 7 0111 STA DIR 3 3 EXT 3 4 IX2 2 5 IX1 1 4 IX 3 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 4 2 1 INH 2 2 RSP 1 INH 3 INH DIR 3 EXT 3 IX2 2 IX1 1 IX 2 3 4 3 2 C 1100 JMP JMP JMP JMP JMP 2 DIR 3 EXT 3 IX2 2 IX1 1 IX Relative Bit set/clear Bit test and branch Indexed, no offset Indexed, 1 byte offset Indexed, 2 byte offset LDX 2 4 IMM 2 2 6 NOP BSR 1 INH 2 IMM 2 2 2 1 REL BSC BTB IX IX1 IX2 Legend: 5 STA 4 LDA IX2 2 5 0101 IX 3 A 1010 CLI ORA ORA ORA ORA ORA ORA 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 2 2 3 4 5 4 3 B 1011 SEI ADD ADD ADD ADD ADD ADD 3 5 3 3 6 5 2 2 CLRA CLRX CLR CLR WAIT TXA BIH CLR REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH Abbreviations for Address Modes: 2 STOP REL EXT 3 4 STA 2 BPL DEC DECA DECX DEC DEC REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 3 3 4 3 3 6 4 TST TSTA TSTX TST TST BMS REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 3 DIR 3 IX1 1 5 LDA 3 BIT 2 8 1000 EOR EOR CLC EOR EOR EOR EOR 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 2 2 3 4 5 4 3 9 1001 SEC ADC ADC ADC ADC ADC ADC BCLR5 BMI BSC 2 REL 5 3 5 3 3 6 5 BSET6 BMC INC INCA INCX INC INC BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX BSC 2 IMM 2 4 LDA 4 0100 IX 4 BIT IX2 2 3 AND IX1 1 5 BIT EXT 3 3 LDA TAX 5 BCLR6 BSC 2 5 DIR 3 2 ASR IX1 1 6 IMM 2 4 BIT 3 0011 IX 4 AND IX2 2 3 CPX IX1 1 5 AND EXT 3 3 2 BSET4 BHCC LSL LSLA LSLX LSL LSL BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 3 5 3 3 6 5 BCLR4 BHCS ROL ROLA ROLX ROL ROL BTB 2 DIR 3 BIT LDA IX 4 AND 2 0010 IX 4 CPX IX2 2 3 SBC IX1 1 5 CPX EXT 3 3 AND IMM 2 5 ROR IX1 1 3 ASRX INH 1 3 6 ROR INH 2 3 ASRA DIR 1 5 3 RORX INH 1 5 ASR REL 2 3 3 RORA DIR 1 3 BEQ DIR 3 2 AND 2 3 5 BSET5 BSC 2 5 IMM 2 4 CPX 1 0001 IX 4 SBC IX2 2 3 CMP IX1 1 5 SBC EXT 3 3 CPX 2 REL 2 BRSET7 2 LSR IX1 1 DIR 3 2 INH 4 SBC 0 0000 IX 4 CMP IX2 2 3 SUB IX1 1 5 CMP EXT 3 3 CPX REL BSC 2 DIR 3 4 SUB IX2 2 4 CMP SBC IMM 2 10 SWI IX 1 6 LSR INH 2 5 COM IX1 1 3 LSRX INH 1 6 COM INH 2 3 LSRA 5 5 BRCLR6 3 BTB 2 5 INH A X IMM DIR EXT INH 1 BSC 2 3 3 DIR 1 3 COMX 5 BRCLR5 BTB 2 5 C BRSET6 1100 3 BTB 2 D 1101 3 COMA BTB 2 BRSET5 3 BTB 2 5 IMM 2 5 SUB EXT 3 3 CMP BIT BNE BCLR3 BRSET4 3 BTB 2 5 BRCLR4 2 3 5 BTB 2 5 5 LSR REL 2 BSC 2 5 7 0111 INH 4 SUB DIR 3 2 BCS BSET3 IMM 2 CMP 2 3 5 BTB 2 2 2 COM BCC BCLR2 BRSET3 1 3 SUB SBC REL 2 BSC 2 5 6 0110 INH 6 3 5 BTB 2 IX 1 RTS BLS BSET2 BRCLR2 IX1 1 2 SUB REL BSC 2 5 5 0101 9 RTI 3 5 BTB 2 INH 2 5 NEG BHI BCLR1 5 4 0100 INH 1 6 NEG REL BSC 2 BTB 2 DIR 1 3 NEGX 3 5 BSET1 BTB 2 3 NEGA BRN BSC 2 5 3 0011 A 1010 BTB 2 5 NEG REL 2 5 BCLR0 BRSET1 3 BRA BSC 2 5 2 0010 9 1001 BTB 2 5 1 0001 8 1000 5 BSET0 IX IMM 2 5 JSR DIR 3 3 6 JSR EXT 3 4 LDX LDX DIR 3 EXT 3 7 JSR IX2 2 5 LDX 6 JSR IX1 1 4 LDX IX2 2 5 IX 3 LDX IX1 1 © Page 23 of 33 E 1110 IX 4 5 6 5 4 F 1111 STX STX STX STX STX 2 DIR 3 EXT 3 IX2 2 IX1 1 IX Opcode in Hexadecimal F 1111 Mnemonic Bytes 3 SUB IX 1 Opcode in Binary 0 0000 # of Cycles IA211081401-03 D 1101 JSR Address Mode www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 AC/DC Parameters Absolute maximum ratings: Supply Voltage (VDD)........................….…...………….….………-0.3V to 6V Input Pin Voltage (VIN)…………………………………...-0.3 to VDD+0.3V Operating Temperature……………………………….……....-40°C to 85°C Storage temperature Range (Tstg).................…........….…...…- 55°C to 150°C ESD Protection (HBM)………………………………………………5000V Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability of the device. DC Characteristics (VDD=4.5 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified D C CH ARACTE RISTICS Sym bol V DD VOL V OH IO L IO H Param eter Supply Voltage O utput Voltage, I LO AD ≤ 2m A O utput Current M in M ax U nit 4.5 5.5 V - 0.4 V 3.5 - V - 2 mA - -2 mA V IH H igh Level input Voltage 2 - V V IL Low Level input Voltage - 0.8 V I IH H igh Level input Current - 1 µA I IL Low Level input Current - -1 µA Vt- Schm itt N egative Threshold 1.1 - V Vt+ Schm itt Positive Threshold - 1.87 V - 5 MHz DC 5 MHz Frequency of O peration f O SC Crystal f O SC External Clock Copyright © 2007 IA211081401-03 © Page 24 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Control Timing VSS=0V, TA=TL to TH Parameters I/O Port Timing – Input Setup Time (Figure 14) Input Hold Time (Figure 14) Output Delay Time (Figure 14) Interrupt Setup Time (Figure 15) Crystal Oscillator Startup Time (Figure 16) Wait Recovery Startup Time (Figure 17) Stop Recovery Startup Time (Figure 18) Required Interrupt Release (Figure 15) Timer Pulse Width (Figure 17) Reset Pulse Width (Figure 16) Timer Period (Figure 17) Interrupt Pulse Width Low (Figure10) Interrupt Pulse Period (Figure 10) Oscillator Cycle Period (1/5 of tCYC) (Figure 3) OSC1 Pulse Width High (Figure 3) OSC1 Pulse Width Low (Figure 3) Sym VDD = 5.0V ±10% fOSC = 5MHz Min Typ Max tPVASL 196 - - ns tASLPX tASLPV TILASL tOXOV 0 0.4 - 5 0 100 ns ns μs ms tIVASH - - 2 μs tILASH - - 2 μs tDSLIH tTH, tTL tRL tTLTL tILIH tILIL 0.5 1.05 1.0 1.0 * - 1.0 - μs tCYC μs tCYC tCYC tCYC tOLOL 200 - - ns tOH tOL 75 75 - - ns ns Unit *The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 20 tCYC cycles. Copyright © 2007 IA211081401-03 © Page 25 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Bus Timing VSS=0V, TA=TL to TH (Figure 19) Num 1 2 3 4 8 9 11 16 17 18 19 21 23 24 25 26 27 28 VDD = 5.0V ±10% fOSC = 5MHz 1 TTL, 100pF Load Min Max 1000 DC 587 403 4 9 97 40 11 18 0 0 204 26 185 103 190 203 185 - Parameters Cycle Time Pulse Width, DS Low Pulse Width, DS High Clock Transition RW_n Non-Muxed Address Hold RW_n Delay From DS Fall Non-Muxed Address Delay From AS Rise MPU Read Data Setup Read Data Hold MPU Data Delay, Write Write Data Hold Muxed Address Delay From AS Rise Muxed Address Valid to AS Fall Muxed Address Hold Delay DS Fall to AS Rise Pulse Width, AS High Delay, AS Fall to DS Rise Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10% TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz *NOTE ADDRESS_STROBE tPVASL tASLPX PORT_INPUT tASLPV PORT_OUTPUT *Note: The address strobe of the first cycle of the next instruction. Figure 14. I/O Port Timing Copyright © 2007 IA211081401-03 © Page 26 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 AS n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 DS (NOTE) T DSLIH ADD_BUS_UNMUX[8:12] 1F (FF) 1F (FF) NEXT OP CODE ADDRESS INT ROUTINE LAST ADDRESS INT ROUTINE STARTING ADDRESS T ILASL IRQ_N__TCR7_N SP PCL MUX_ADD_DATA[0:7] SP-1 PCH SP-2 X SP-3 A SP-4 CC NEW PCH 80 NEW PCL NEXT OP CODE FA (IRQ) FB (IRQ) 1ST OP F8 (TIMER) F9 (TIMER) INT ROUTINE RTI OP CODE RW_N Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition of the same interrupt. Figure 15. IRQ_n and TCR7_N Interrupt Timing Figure 16. Power-On-Reset and RESET_n Timing Copyright © 2007 IA211081401-03 © Page 27 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 TIMER COUNTER=$00 tTL tTH tTLTL INT_EXT_CLK TCR7 tIVASH AS n0 n1 n2 n3 n4 n5 n6 n7 DS A[12:8] ADDRESS + 1 OP CODE ADDR OP CODE ADDRESS 1F (FF) 1F (FF) INT ROUTINE STARTING ADDRESS ADDR + 1 8F B[7:0] PCL SP SP-1 PCH SP-2 X A SP-3 SP-4 CC F6 NEW PCHF7NEW PCL WAIT OP CODE 1ST OP CODE INT ROUTINE RW_N Figure 17. Timer Interrupt After WAIT Instruction Timing TIMER COUNTER=$00 tTL tTH tTLTL INT_EXT_CLK TCRB7 tIVASH AS n0 n1 n2 n3 n4 n5 n6 n7 DS A[12:8] ADDRESS + 1 OP CODE ADDR OP CODE ADDRESS 1F (FF) 1F (FF) INT ROUTINE STARTING ADDRESS ADDR + 1 B[7:0] 8E SP PCL SP-1 PCH STOP OP CODE SP-2 X SP-3 A SP-4 CC F6 NEW PCHF7NEW PCL 1ST OP CODE INT ROUTINE RW_N Figure 18. Interrupt Recovery From STOP Instruction Timing Copyright © 2007 IA211081401-03 © Page 28 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 4 4 4 27 26 AS 1 2 DS 28 26 3 4 4 4 8 8 RW_n 11 11 16 9 9 A[12:8] 21 23 25 19 VALID ADDR B[7:0] WRITE 24 18 VALID WRITE DATA 25 17 23 VALID ADDR B[7:0] READ 21 18 23 VALID READ DATA Figure 19. Bus Timing Copyright © 2007 IA211081401-03 © Page 29 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Packaging Information PDIP Packaging TOP E1 E LEAD 1 IDENTIFIER eA 1 C eB LEAD COUNT DIRECTION SIDE VIEW (WIDTH) Lead Count 40 (in Inches) A D Symbol A1 L B B1 e MIN MAX A - .200 A1 .015 - B .015 .020 B1 .040 .060 C .008 .012 D 1.980 2.065 E .580 .610 E1 .520 .560 e SIDE VIEW (LENGTH) eA .580 - eB - .686 L Copyright © 2007 IA211081401-03 © Page 30 of 33 .100 TYP .100 MIN www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 PLCC Packaging D1 E E1 PIN 1 IDENTIFIER & ZONE E3 2 PLCS 1.22/1.07 D D3 TOP VIEW BOTTOM VIEW .81 / .66 LEAD COUNT 44 (in Millimeters) Symbol MIN MAX A 4.20 4.57 A1 2.29 3.04 D1 16.51 16.66 D2 14.99 16.00 A1 A SEATING PLANE .10 e .53 / .33 .51 MIN. D3 R 1.14 / .64 E1 16.51 16.66 E2 14.99 16.00 D2 / E2 SIDE VIEW Copyright © 2007 IA211081401-03 © Page 31 of 33 12.70 BSC E3 12.70 BSC e 1.27 BSC D 17.40 17.67 E 17.40 17.65 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Ordering Information The IA6805E2 is available in two package styles, both standard and RoHS compliant, listed in the table below. Other packages and temperature grades may be available for additional cost and lead time. Order Number IA6805E2-PDW40I-00 IA6805E2-PDW40I-R-00 (RoHS compliant) IA6805E2-PLC44I-00 IA6805E2-PLC44I-R-00 (RoHS compliant) Temperature Grade Industrial Industrial Industrial Industrial Package Type 40 Lead Plastic DIP, 600 mil wide 40 Lead Plastic DIP, 600 mil wide 44 Lead Plastic Leaded Chip Carrier 44 Lead Plastic Leaded Chip Carrier Cross Reference to Original Manufacturers Innovasic Part Number IA6805E2-PDW40I Motorola® Part Number IA6805E2-PLC44I Copyright © 2007 Harris® Part Number MC146805E2CP MC146805E2P MC146805E2CFN MC146805E2FN CDP6805E2CE CDP6805E2E CDP6805E2CQ CDP6805E2Q IA211081401-03 © Page 32 of 33 www.Innovasic.com Customer Support: 1-888-824-4184 IA6805E2 29 August 2007 Microprocessor Unit As of Production Version 00 Errata Production Version 00 1. Functional differences between IA6805E2 and Harris and Motorola Versions: A. Stop mode on IA6805E2 will not halt oscillator. Recovery from stop will be quicker. B. There is a functional difference between the IA6805E2 and the original device instruction sets regarding instructions for BSET and BCLR. Analysis: The instructions, BSET and BCLR (bit set and bit clear), are not supposed to affect the carry flag in the condition code register but in the IA6805E2 they do. Any situations where the BSET or BCLR commands are executed between a decision type instruction (branches) based on the carry flag and the instruction that was to update the carry flag should be considered suspect. Workaround: The workaround selected by the particular user is code dependent. Software will need to be revised to address the instruction set issues noted above. C. There is a functional difference between the IA6805E2 and the original device regarding the external timer input. Analysis: The original device is edge sensitive on this input (negative edge). The IA6805E has a synchronizing register on this input. If the stimulus to this input is a negative pulse less than a clock cycle wide, it is possible that this event will be missed by the timer circuit. Workaround: The workaround selected by the particular user is situation dependent. The input pulse either needs to be a minimum of 1 clock cycle wide or the pulse needs to be centered on the falling edge of the input clock. 2. Observations: A. Original data sheets for Motorola and Harris are inconsistent when describing timer input mode 2. Original parts and Innovasic will AND together the timer input with the inverse of the internal clock (AS). B. Original Harris part would unpredictably “pre-increment” timer counter when writing to timer registers. IA6805E2 will not. C. Original Harris part displays incorrect address on external pins during intermediate cycles (not a functional problem) of multi-cycle instructions when accessing memory at page boundaries. IA6805E2 will not. D. Execution of illegal op-codes on the IA6805E2 will force a system reset. On the original Harris and Motorola parts, execution of illegal op-codes would produce unpredictable results. Copyright © 2007 IA211081401-03 © Page 33 of 33 www.Innovasic.com Customer Support: 1-888-824-4184