REVISIONS LTR DESCRIPTION DATE APPROVED A Activate device type 03. - CFS 07-02-21 Thomas M. Hess B Correct package style in 1.2.2. - CFS 07-04-17 Thomas M. Hess C Update boilerplate to current MIL-PRF-38535 requirements. - PHN 13-12-11 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV C C C C C C C C C C C C C C C C C C C C C PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 REV C C C C C C C C C C C C C C C C C PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REV STATUS OF PAGES PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing CHECKED BY Phu H. Nguyen YY MM DD 06-05-09 APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A CODE IDENT. NO. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 TITLE MICROCIRCUIT, DIGITAL SIGNAL PROCESSORS, MONOLITHIC SILICON DWG NO. V62/06619 16236 C PAGE 1 OF 38 5962-V022-14 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance floating-point digital signal processor microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06619 - Drawing number 1.2.1 Device type(s). 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1/ Device type Generic Circuit function 01 02 03 SM320F2808-EP SM320F2806-EP SM320F2801-EP Digital Signal Processors Digital Signal Processors Digital Signal Processors 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 JEDEC MS-026 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z 1/ Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other Users are cautioned to review the manufacturers data manual for additional user information relating to this device. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 2 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage ranges, (VDDIO, VDD3VFL) (with respect to VSS) .................................................. Supply voltage ranges, (VDDA2, VDDAIO) (with respect to VSSA) .................................................. Supply voltage ranges, (VDD) (with respect to VSS) ................................................................... Supply voltage ranges, (VDD1A18, VDD2A18) (with respect to VSSA) .............................................. Supply voltage ranges, (VSSA2, VSSAIO, VSS1AGND, VSS2AGND) (with respect to VSS) ...................... Input voltage range, (VIN) ......................................................................................................... Output voltage range, (VO) ....................................................................................................... Input clamp current, IIK (VIN < 0 or VIN > VDDIO) ......................................................................... Output clamp current, IOK (VO < 0 or VO > VDDIO) ...................................................................... Operating ambient temperature ranges, (TA) .......................................................................... Junction temperature range TJ ................................................................................................. Storage temperature range, (TSTG)............................................................................................ -0.3 V to +4.6 V -0.3 V to +4.6 V -0.3 V to +2.5 V -0.3 V to +2.5 V -0.3 V to +0.3 V -0.3 V to +4.6 V -0.3 V to +4.6 V ±20 mA 4/ ±20 mA -55°C to +125°C -55°C to +150°C -65°C to +150°C 5/ 5/ 5/ 1.4 Recommended operating conditions. Device supply voltage, I/O, (VDDIO) ........................................................................................... Device supply voltage, CPU (VDD) ............................................................................................ Supply ground, (VSS, VSSIO) ...................................................................................................... ADC supply voltage, 3.3 V (VDDA2, VDDAIO) ............................................................................... ADC supply voltage, 1.8 V (VDD1A18, VDD2A18) ........................................................................... Flash programming supply voltage, (VDD3VFL) ........................................................................... Device clock frequency (system clock), (fSYSCLKOUT) ................................................................. High level input voltage, (VIH) ................................................................................................... Maximum low level input voltage, (VIL) ..................................................................................... Maximum high level output source current, VOH = 2.4 V (IOH) : All I/Os except group 2 ..................................................................................................... Group 2 6/ ................................................................................................................... Maximum low level output sink current, VOL = VOL max (IOL) : All I/Os except group 2 ..................................................................................................... Group 2 6/ ................................................................................................................... Ambient temperature, (TA) ...................................................................................................... Thermal resistance characteristics for case outline X: Parameter 2/ 3/ 4/ 5/ 6/ +3.14 V to +3.47 V +1.71 V to 1.89 V 0V +3.14 V to +3.47 V +1.71 V to +1.89 V +3.14 V to +3.47 V 2 MHz to 100 MHz +2.0 V to VDDIO 0.8 V -4 mA -8 mA 4 mA 8 mA -55°C to +125°C Air Flow 0 lfm 150 lfm 250 lfm 500lfm θJA[°C/W] High k PCB 48.16 40.06 37.96 35.17 ΨJT[°C/W] 0.3425 0.85 1.0575 1.410 θJC 12.89 θJB 29.58 Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the voltage to a diode drop above VDDA2 or below VSSA2 Long term high temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLOUT, EMU0, and EMU1. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 – Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.5 Package life time versus operating junction temperature. The package life time versus operating junction temperature shall be as specified in figure 4. 3.5.6 Typical operational power versus frequency (for device type 01). The typical operational power versus frequency (for device type 01) shall be as specified in figure 5. 3.5.7 Test load circuits. The test load circuits shall be as specified in figure 6. 3.5.8 Timing waveforms. The timing waveforms shall be as shown in figures 7- 27. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 4 TABLE I. Electrical performance characteristics. Test Symbol Test condition 1/ 2/ Limits Min High level output voltage VOH IOH = IOH max Low level output voltage VOL IOL = IOL max Low level input current With pull up V IOH = 50 µA VDDIO – 0.2 -80 All I/Os (including XRS ) 0.4 V -190 µA IIL Pull up disabled High level input current Max 2.4 VDDIO = 3.3 V, VIN = 0 V Unit With pull up IIH VDDIO = 3.3 V, VIN = 0 V ±2 VDDIO = 3.3 V, VIN = VDD ±2 Pull up disabled 38 Off state output current, high impedance state (off state) IOZ Input capacitance Ci µA 80 ±2 VO = VDDIO or 0 V µA 2 Typ pF Current consumption by power supply pins at 100 MHz SYSCLOUT - Device type 01 Mode IDD IDDIO Test condition Typ 6/ Max Operational (Flash) 7/ 195 mA IDLE 8/ 75 mA SWTANDBY 9/ 6 mA HALT 10/ 70 µA 3/ IDD3VFL IDDA18 4/ IDDA33 5/ Typ 6/ Max Typ Max Typ 6/ Max Typ 6/ Max 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA 90 mA 500 µA 2 mA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA 12 mA 100 µA 500 µA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA 60 µA 120 µA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA Current consumption by power supply pins at 100 MHz SYSCLOUT - Device type 02 Operational (Flash) 7/ 195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA IDLE 8/ 75 mA 90 mA 500 µA 2 mA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA SWTANDBY 9/ 6 mA 12 mA 100 µA 500 µA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA HALT 10/ 70 µA 60 µA 120 µA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA Current consumption by power supply pins at 100 MHz SYSCLOUT - Device type 03 Operational (Flash) 11/ 180 mA 210 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA IDLE 8/ 75 mA 90 mA 500 µA 2 mA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA SWTANDBY 9/ 6 mA 12 mA 100 µA 500 µA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA HALT 10/ 70 µA 60 µA 120 µA 2 µA 10 µA 5 µA 50 µA 15 µA 30 µA See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 5 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 1/ 2/ Limits Unit Min Max Clock table and Nonmenclature tc(OSC), Cycle time On-chip oscillator clock XCLKIN 12/ SYSCLKOUT XCLKOUT HSPCLK 13/ 28.6 50 ns Frequency 20 35 MHz tc(CI), Cycle time 10 250 ns Frequency 4 100 MHz tc(SCO), Cycle time 10 500 ns Frequency 2 100 MHz tc(XCO), Cycle time 10 2000 ns Frequency 0.5 100 MHz tc(HCO), Cycle time 10 ns Frequency 100 tc(LCO), Cycle time LSPCLK 13/ ns Frequency 100 tc(ADCCLK), Cycle time ADC clock MHz 10 MHz 80 ns Frequency 12.5 MHz MHz Input clock frequency Input clock frequency fx Resonator 20 35 Crystal 20 35 Without PLL 4 100 With PLL 5 30 External oscillator/clock Source (XCLKIN or X1 pin) Limp mode clock frequency fl 1-5 Typ XCLKIN 14/ timing requirements – PLL Enabled C8 Cycle time, XCLKIN tc(CI) See figure 7 33.3 C9 Fall time, XCLKIN tf(CI) 6 C10 Rise time, XCLKIN tr(CI) 6 C11 Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) tw(CIL) 45 55 C12 Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) tw(CIH) 45 55 ns 200 % See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 6 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 1/ 2/ Limits Unit Min Max 10 250 XCLKIN 14/ timing requirements – PLL disabled C8 Cycle time, XCLKIN tc(CI) See figure 7 C9 Fall time, XCLKIN tf(CI) C10 Rise time, XCLKIN tr(CI) C11 Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) tw(CIL) XCLKIN ≤ 120 MHz 45 55 C12 Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) tw(CIH) XCLKIN ≤ 120 MHz 45 55 Up to 20 MHz 6 20 MHz to 100 MHz 2 Up to 20 MHz 6 20 MHz to 100 MHz 2 ns % XCLKOUT Switching characteristics (PLL Bypassed or Enabled) 15/ 16/ C1 Cycle time, XCLKOUT tc(XCO) C3 Fall time, XCLKOUT tf(XCO) C4 Rise time, XCLKOUT C5 Pulse duration, XCLKOUT low tw(XCOL) H-2 Pulse duration, XCLKOUT high tw(XCOH) H-2 C6 PLL lock time See figure 7 10 ns 2 Typ tr(XCO) 2 Typ tp H+2 H+2 131072tc(OSCCLK) 17/ cycles Reset ( XRS ) timing requirements Pulse duration, stable XCLKIN to XRS high tw(RSL1) 18/ Pulse duration, XRS low tw(RSL2) Pulse duration, reset pulse generated by watchdog Delay time, address/data valid after tw(WDRS) 512tc(OSCCLK) Typ td(EX) 32tc(OSCCLK) Typ See figure 8-10 8tc(OSCCLK) Warm reset cycles 8tc(OSCCLK) XRS high Oscillator start-up time tOSCT 19/ 1 Hold time for boot mode pins th(boot-mode) 200tc(OSCCLK) 10 ms cycles See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test condition 1/ 2/ Limits Unit Min Max GENERAL PURPOSE INPUT/OUTPUT (GPIO) General purpose output switching characteristics (See figure 11) Rise time, GPIO switching low to high tr(GPO) All GPIOs 8 Fall time, GPIO switching high to low tf(GPO) All GPIOs 8 Toggling frequency, GPO pins fGPO ns 25 MHz General purpose input timing requirements (See figure 12-13) Sampling period tw(SP) Input qualifier sampling window tw(IQSW) Pulse duration, GPIO low/high tr(GPI) 21/ IDLE mode timing requirements QUALPDR = 0 QUALPDR ≠ 0 2*tc(SCO) 2*tc(SCO)*QUALPRD 20/ tw(SP)*(n -1) Synchronous mode 2*tc(SCO) With input qualifier tw(IQSW)+ tw(SP)+1tc(SCO) cycles LOW POWER MODE WAKEUP TIMING 22/ (See figure 14) Pulse duration, external wake up tw(WAKE-INT) signal IDLE mode switching characteristics 22/ Without input qualifier With input qualifier 2tc(SCO) 5tc(SCO) + tw(IQSW cycles Delay time, external wake signal to program execution resume 11/ - Wake up from Flash - Flash module in active state Without input qualifier td(WAKE-IDLE) - Wake up from Flash - Flash module in sleep state 20tc(SCO) With input qualifier 20tc(SCO) + tw(IQSW) Without input qualifier 1050tc(SCO) With input qualifier Without input qualifier With input qualifier STANDBY mode timing requirements (See figure 15) tw(WAKE-INT) cycles 1050tc(SCO)+ tw(IQSW) - Wake up from SARAM Pulse duration, external wake up signal cycles 20tc(SCO) 20tc(SCO)+ tw(IQSW) Without input qualification 3tc(OSCCLK) With input qualification 24/ (2+QUALSTDBY)* tc(OSCCLK) cycles cycles STANDBY mode switching characteristics (See figure 15) Delay time, IDLE instruction executed to XCLKOUT low td(IDLE-XCOL) 32tc(SCO) 45tc(SCO) cycles Delay time, external wake signal to program execution resume 23/ - Wake up from Flash - Flash module in active state - Wake up from Flash - Flash module in sleep state - Wake up from SARAM td(WAKE-STBY) Without input qualifier With input qualifier Without input qualifier With input qualifier Without input qualifier With input qualifier 100tc(SCO) 100tc(SCO)+ tw(WAKE-INT) 1125tc(SCO) 1125tc(SCO)+ tw(WAKE-INT) 100tc(SCO) 100tc(SCO)+ tw(WAKE-INT) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test condition 1/ 2/ Limits Min Unit Max LOW POWER MODE WAKEUP TIMING - Continued HALT mode timing requirements Pulse duration, GPIO wake up signal tw(WAKE-GPIO) Pulse duration, XRS wake up signal tw(WAKE-XRS) See figure 16 tOSCST+2tc(OSCCLK) 25/ cycles tOSCST+8tc(OSCCLK) HALT mode switching characteristics Delay time, IDLE instruction executed to XCLKOUT low td(IDLE-XCOL) PLL lock up time Delay time, PLL lock to program execution resume • Wake up from flash - Flash module in sleep state • See figure 16 32tc(SCO) 45tc(SCO) tp 131072tc(OSCCLK) td(WAKE-HALT) 1125tc(SCO) cycles 35tc(SCO) Wake up from SARM ENHANCED CONTROL PERIPHERALS ePWM timing requirements 22/ Asynchronous Sync input pulse width tw(SYCIN) 2tc(SCO) Synchronous cycles 2tc(SCO) With input qualifier 1tc(SCO)+ tw(IQSW) ePWM switching characteristics Pulse duration, PWMx output high/low tw(PWM) 20 Sync output pulse width tw(SYCOUT) Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced high td(PWM)tza Delay time, trip input active to PWM Hi-Z td(TZ-PWM)HZ Trip zone input timing requirements 8tc(SCO) cycles No pin load 25 ns 20 22/ Asynchronous Pulse duration, TZx input low ns tw(TZ) 1tc(SCO) Synchronous cycles 2tc(SCO) With input qualifier 1tc(SCO)+ tw(IQSW) High resolution PWM characteristics at SYSCLOUT = (60 – 100 MHz) Micro edge positioning (MEP) step size 26/ 310 Enhanced capture (eCAP) timing requirement Capture input pulse width tw(CAP) ps 22/ Asynchronous 2tc(SCO) Synchronous 2tc(SCO) With input qualifier cycles 1tc(SCO)+ tw(IQSW) See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test condition 1/ 2/ Limits Min Unit Max ENHANCED CONTROL PERIPHERALS – Continued eCAP switching characteristics Pulse duration, APWMx output high/ low tw(APWMX) Enhanced quadrature encoder pulse (eQEP) timing requirements QEP input period tw(QEPP) QEP index input high time tw(INDEXH) QED index input low time tw(INDEXL) QED strobe high time tw(STROBH) QED strobe input low time tw(STROBL) 20 ns 2tc(SCO) cycles 22/ Asynchronous/synchronous With input qualifier 2(1tc(SCO)+ tw(IQSW)) Asynchronous/synchronous 2tc(SCO) With input qualifier 2tc(SCO)+ tw(IQSW) Asynchronous/synchronous 2tc(SCO) With input qualifier 2tc(SCO)+ tw(IQSW) Asynchronous/synchronous 2tc(SCO) With input qualifier 2tc(SCO)+ tw(IQSW) Asynchronous/synchronous 2tc(SCO) With input qualifier 2tc(SCO)+ tw(IQSW) eQEP switching characteristics Delay time, external clock to counter increment Delay time, QEP input edge to position compare sync output td(CNTR)xin 4tc(SCO) td(PXCSOUT)QEP 6tc(SCO) cycles External ADC start of conversion switching characteristics Pulse duration, ADCSOCAO low tw(ADCSOCAL) See figure 18 32tc(HCO) cycles Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO)+ tw(IQSW) EXTERNAL INTERRUPT TIMING External interrupt timing requirements 22/ Pulse duration, INT input high/ low tw(INT) External interrupt switching characteristics Delay time, INT low/high to interrupt vector fetch td(INT) 22/ See figure 19 12tc(SCO)+ tw(IQSW) cycles 400 kHz 0.3 VDDIO V I2C ELECTRICAL SPECIFICATION AND TIMING I2C timing SCL clock frequency fSCL Low level input voltage VIL High level input voltage VIH 27/ 0.7 VDDIO Input hysteresis VHYS Low level output voltage VOL 3 mA sink current Low period of SCL clock tLOW 27/ 1.3 High period of SCL clock tHIGH 27/ 0.6 Input current with an input voltage between 0.1 VDDIO and 0.9 VDDIO MAX 0.05 VDDIO 0 II 0.4 μs -10 μA 10 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 10 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ 1/ Limits Min Unit Max Min Max SPI MASTER MODE TIMING SPI master mode external timing (clock phase = 0) 35/ 36/ 37/ 38/ 39/ 1 Cycle time, SPICLK 2 Pulse duration, SPICLK high (clock polarity = 0) 3 4 5 8 9 tc(SPC)M See figure 20 SPI when (SPIBRR+1) is even or SPIBRR = 0 or 2 SPI when (SPIBRR+1) is odd and SPIBRR > 3 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) tw(SPCH)M 28/ 29/ 31/ 32/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)M 28/ 29/ 31/ 32/ Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)M 28/ 29/ 31/ 32/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)M 28/ 29/ 31/ 32/ Delay time, SPICLK high to SPISIMO valid (clock polarity = 0) td(SPCH-SIMO)M 10 10 Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) td(SPCL-SIMO)M 10 10 Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) tv(SPCL-SIMO)M 28/ 33/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) tv(SPCH-SIMO)M 28/ 33/ Setup time, SPIOMI before SPICLK low (clock polarity = 0) tsu(SOMI-SPCL)M 35 35 Setup time, SPIOMI before SPICLK high (clock polarity = 1) tsu(SOMI-SPCH)M 35 35 Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) tv(SPCL-SOMI)M 30/ 31/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) tv(SPCH-SOMI)M 30/ 31/ ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 11 TABLE I. Electrical performance characteristics - Continued. No Test Symbol Test condition 2/ 1/ Limits Min Unit Max Min Max SPI MASTER MODE TIMING - Continued SPI master mode external timing (clock phase = 1) ) 35/ 36/ 37/ 38/ 39/ 1 Cycle time, SPICLK 2 Pulse duration, SPICLK high (clock polarity = 0) tw(SPCH)M Pulse duration, SPICLK low (clock polarity = 1) 3 6 7 10 11 tc(SPC)M See figure 21 SPI when (SPIBRR+1) is even or SPIBRR = 0 or 2 SPI when (SPIBRR+1) is odd and SPIBRR > 3 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) 28/ 29/ 31/ 32/ tw(SPCL)M 28/ 29/ 31/ 32/ Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)M 28/ 29/ 31/ 32/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)M 28/ 29/ 31/ 32/ Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) tsu(SIMO-SPCH)M 28/ 28/ Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) tsu(SIMO-SPCL)M 28/ 28/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) tv(SPCH-SIMO)M 28/ 28/ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) tv(SPCL-SIMO)M 28/ 28/ Setup time, SPISOMI before SPICLK high (clock polarity = 0) tsu(SOMI-SPCH)M 35 35 Setup time, SPIOMI before SPICLK low (clock polarity = 1) tsu(SOMI-SPCL)M 35 35 Valid time, SPISOMI data valid after SPICLK high(clock polarity = 0) tv(SPCH-SOMI)M 30/ 28/ Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) tv(SPCL-SOMI)M 30/ 28/ ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 12 TABLE I. Electrical performance characteristics - Continued. No Test Test condition Symbol 1/ 2/ Limits Min Unit Max SPI SLAVE MODE TIMING SPI slave mode external timing (clock phase = 0) 36/ 37/ 38/ 39/ 46/ 12 Cycle time, SPICLK 13 Pulse duration, SPICLK high (clock polarity = 0) tw(SPCH)S 40/ 41/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)S 40/ 41/ Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)S 40/ 41/ Pulse duration, SPICLK high (clock polarity = 1) tw(SPCH)S 40/ 41/ 14 15 16 19 20 tc(SPC)S See figure 22 4tc(LCO) ns Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) td(SPCH-SOMI)S 35 Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) td(SPCL-SOMI)S 35 Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) tv(SPCH-SOMI)S 42/ Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) tv(SPCL-SOMI)S 42/ Setup time, SPISIMO before SPICLK low (clock polarity = 0) tsu(SIMO-SPCL)S 35 Setup time, SPISIMO before SPICLK high (clock polarity = 1) tsu(SIMO-SPCH)S 35 Valid time, SPISIMO before SPICLK low (clock polarity = 0) tv(SPCL-SIMO)S 41/ Valid time, SPISIMO before SPICLK high (clock polarity = 1) tv(SPCH-SIMO)S 41/ SPI slave mode external timing (clock phase = 1) 20/ 21/ 12 Cycle time, SPICLK 13 Pulse duration, SPICLK high (clock polarity = 0) tw(SPCH)S 40/ 41/ Pulse duration, SPICLK low (clock polarity = 1) tw(SPCL)S 40/ 41/ Pulse duration, SPICLK low (clock polarity = 0) tw(SPCL)S 40/ 41/ 41/ 14 Pulse duration, SPICLK high (clock polarity = 1) 17 18 21 22 tc(SPC)S See figure 23 8tc(LCO) tw(SPCH)S 40/ Setup time, SPISOMI before SPICLK high (clock polarity = 0) tsu(SOMI-SPCH)S 43/ Setup time, SPISOMI before SPICLK low (clock polarity = 1) tsu(SOMI-SPCL)S 43/ Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) tv(SPCH-SOMI)S 42/ Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) tv(SPCL-SOMI)S 42/ Setup time, SPISIMO before SPICLK high (clock polarity = 0) tsu(SIMO-SPCH)S 35 Setup time, SPISIMO before SPICLK low (clock polarity = 1) tsu(SIMO-SPCL)S 35 Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) tv(SPCL-SIMO)S ns 41/ 41/ See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 13 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test condition 1/ 2/ Limits Unit Min ON CHIP ANALOG TO DIGITAL CONVERTER ADC electrical characteristics – DC specifications 47/ 48/ Resolution Max 12 Bits 1 ADC clock kHz 12.5 MHz 1- 12.5 MHz ADC clock (6.25 MSPS) ±1.5 LSB 1- 12.5 MHz ADC clock (6.25 MSPS) ±1 Accuracy INL (integral nonlinearity) DNL (Differential nonlinearity) 49/ Offset error 50/ -60 +60 ±4 Typ Offset error with hardware trimming Overall gain error with internal reference 51/ -60 If ADCREFP-ADCREFM = 1 V ±0.1% Overall gain error with external reference +60 -60 +60 Channel to channel offset variation ±4 Typ Channel to channel Gain variation ±4 Typ Analog input Analog input voltage (ADCINx to ADCLO) 52/ 0 3 V ADCLO -5 5 mV ±5 µA Input capacitance 10 Typ Input leakage current pF Internal Voltage reference 51/ VADCREFP – ADCREFP output voltage at the pin based on internal reference 1.275 Typ VADCREFP – ADCREFM output voltage at the pin based on internal reference 0.525 Typ Voltage difference, ADCREFP-ADCREFM 0.75 Typ Temperature coefficient V 50 Typ PPM/°C ADCREFSEL[15:14] = 11b 1.024 Typ V ADCREFSEL[15:14] = 11b 1.500 Typ ADCREFSEL[15:14] = 11b 2.048 Typ External Voltage reference 51/ 53/ VADCREFIN – External reference voltage input on ADCREFIN pin 0.2% or better accurate reference recommended AC specifications Signal to noise ratio + distortion SINAD (100 KHz) Signal to noise ratio SNR (100KHz) 67.5 Typ 68 Typ dB Total harmonic distortion THD (100 KHz) -70 Typ Effective number of bits ENOB 100 KHz) 10.9 Typ Bits Spurious free dynamic range SFDR 100 KHz) 83 Typ dB See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 14 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test condition 1/ 2/ Limits Min Unit Max ON CHIP ANALOG TO DIGITAL CONVERTER - Continued ADC power up Delays 54/ Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled Delay time for power down control to be stable. Bit delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3 register (PWDNADC) is to be set to 1 before any ADC conversions are initiated Sequential sampling mode timing See figure 24-25 5 Typ ms td(BGR) μs 20 td(PWD) 1 ms See figure 26 Sample n Delay time from even trigger to sampling Sample/Hold width/Acquisition width Delay time for first result to appear in the Result register Delay time for successive results to appear in the Result register Simultaneous sampling mode timing Sample n + 1 55/ td(SH) 2.5tc(ADCCLK) tSH (1+Acqps)* tc(ADCCLK) 80 ns with Acqps = 0 Typ 56/ td(schx_n) 4tc(ADCCLK) 320 Typ td(schx_n+1) ns (2+Acqps)* tc(ADCCLK) 160 Typ Sample n + 1 55/ See figure 27 Sample n Delay time from even trigger to sampling td(SH) 2.5tc(ADCCLK) tSH (1+Acqps)* tc(ADCCLK) 80 ns with Acqps = 0 Typ Delay time for first result to appear in the Result register td(schA0_n) 4tc(ADCCLK) 320 Typ Delay time for first result to appear in the Result register td(schB0_n) 5tc(ADCCLK) 400 Typ Delay time for successive result to appear in the Result register td(schA0_n+1) (3+Acqps)* tc(ADCCLK) 240 Typ Delay time for successive results to appear in the Result register td(schB0_n+1) (3+Acqps)* tc(ADCCLK) 240 Typ Sample/Hold width/Acquisition width ns See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 15 TABLE I. Electrical performance characteristics - Continued. Test 1/ Test condition 2/ Min Nf -55°C to 125°C 100 NOTP -55°C to 125°C Symbol Limits Unit Max FLASH TIMING Flash endurance Flash endurance for the array (Write/erase cycles) OTP endurance for the array (Write cycles) Flash parameters at 150 MHz SYSCLKOUT Program time Erase time write 58/ 16 Bit Word 50 Typ µs 16K Sector 500 Typ ms 8K sector 250 Typ ms 4K Sector 120 Typ ms 16K Sector 10 Typ S 8K sector 10 Typ S 4K Sector 10 Typ S 75 Typ mA VDD3VFL current consumption during the Erase/Program cycle Erase IDD3VFLP Program VDD current consumption during the Erase/Program cycle VDDIO current consumption during the Erase/Program cycle Flash/OTP access timing cycles 1 35 Typ IDDP 140 Typ IDDIOP 20 Typ 59/ Paged Flash access time ta(fp) 36 Random access time ta(fr) 36 ta(OTP) 60 OTP access time ns Minimum required Wait States at different frequencies SYSCLKOUT (MHz) SYSCLKOUT (ns) Page Wait state 60/ Random Wait state 60/ 61/ 100 10.00 3 3 75 13.33 2 2 50 20.00 1 1 30 33.33 1 1 25 40.00 0 1 15 66.67 0 1 4 250.00 0 1 See notes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 16 TABLE I. Electrical performance characteristics – Continued. 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ 14/ 15/ 16/ 17/ 18/ 19/ 20/ 21/ 22/ 23/ 24/ 25/ 26/ 27/ 28/ 29/ 30/ 31/ 32/ 33/ 34/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Test conditions are over recommended ranges of supply voltage and operating case temperature unless otherwise specified. Device type: All. IDDIO current is dependent on the electrical loading on the I/O pins. IDDA18 includes current into VDD1A18 and VDD2A18 pins. IDDA33 includes current into VDDA2 and VDDAIO pins. The Typ numbers are applicable over room temperature and nominal voltage. The following peripheral clocks are enabled: 2 ePWM 1/2/3/4/5/6, eCAP 1/2/3/4, eQEP1/ 2, eCAN-A, SCI-A/B, SPI-A, ADC, I C All PWM pins are toggled at 100 KHz. Data is continuous transmitted out of the SCI-A, SCI-B, and eCAN-A ports. The hardware multiplier is exercised. Code is running out of flash with 3 wait states. XCLKOUT is turned off. Flash is powered down. XCLKOUT is turned off. The following peripheral clocks are enabled: 2 eCAN-A, SCI-A, SPI-A, I C Flash is powered down. Peripheral clocks are off. Flash is powered down. Peripheral clocks are off. Input clock is disabled. The following peripheral clocks are enabled: 2 ePWM 1/2/3, eCAP 1/2, eQEP1, eCAN-A, SCI-A/B, SPI-A, ADC, I C All PWM pins are toggled at 100 KHz. Data is continuous transmitted out of the SCI-A, SCI-B, and eCAN-A ports. The hardware multiplier is exercised. Code is running out of flash with 3 wait states. XCLKOUT is turned off. This also applied to the X1 pin if a 1.8 V oscillator is used. Lower LSPCLK and HSPCLK will reduce device power consumption. This applied to the X1 pin also. A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator. In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V. Dependent on crystal/resonator and board design. “n” represents the number of qualification samples as defined by GPxQSELn register. For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. For an explanation of the input qualifier parameters, see General purpose input timing requirements table. This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction, execution of an ISR (triggered by the wake up) signal involves addition latency. QUALSTDBY is a 6-bit field in the LPMCR0 register. See Rest ( XRS ) timing requirements table for an explanation of tOSCST. Maximum MEP step size is based on worst case process, maximum temperature and maximum voltage. MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the HRPWM feature should use MEP scale Factor Optimize (SFO) estimation software functions. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. See manufacturer data for more information. I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately. 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 17 TABLE I. Electrical performance characteristics – Continued. 35/ 36/ 37/ 38/ 39/ 40/ 41/ 42/ 43/ 46/ 47/ 48/ 49/ 50/ 51/ 52/ 53/ 54/ 55/ 56/ 57/ 58/ The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. LSPCLK LSPCLK tc(SPC) = SPI clock cycle time = or 4 (SPIBRR + 1) tc(LCO) = LSPCLK cycle time. Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX Slave mode transmit 12.5 MAX, slave mode receive 12.5 MHz MAX. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 0.5tc(SPC)S – 10 0.5tc(SPC)S 0.75tc(SPC)S 0.125tc(SPC)S The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. Tested at 12.5 MHz ADCCLK. All voltages listed in this table are with respect to VSSA2. Manufacturer specifies that the ADC will have no missing codes. 1 LSB has the weight value of 3.0/4097 = 0.732 mV. A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference depend on the temperature profile of the source used. Voltages above VDDA + 0.3 or below VSS – 0.3 applied to an analog input pin may temporarily affect the conversion of another pin. To avoid this, the analog inputs should be kept within these limits. Manufacturer recommends using high precision external reference for 2.048 V reference. Timings maintain compatibility to the 281x ADC module. The 280x ADC also support driving all 3 bits at the same time and waiting td(BGR) ms before first conversion. At 12.5 MHz ADC clock, tc(ADCCLK) = 80 ns. Acqps value = 0 – 15 ADCTRL1[8:11] Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead. For 100 MHz, PAGE WS = 3 and RANDOM WS = 3 For 75 MHz, PAGE WS = 2 and RANDOM WS = 2 Formulas to compute page wait state and random wait state: t a( fp ) − 1 (round up to the highest integer), or 0 whichever is larger Page Wait State = t c (SCO ) t a( fr ) Random Wait State = − 1 round up to the highest integer), or 1 whichever is larger t c (SCO ) DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 18 Case X Symbol Millimeters Min A A1 A2 0.05 b 0.17 Symbol Millimeters Min Max 1.60 D/E 15.80 16.20 1.45 D1/E1 13.80 14.20 0.25 Typ A3 c Notes: 1. 2. 1.35 Max 0.27 D2/E2 12.00 Typ e 0.50 Typ L 0.45 0.75 0.13 Nom This drawing is subject to change without notice. Falls within JEDEC MS-026 FIGURE 1. Case outlines. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 19 Case X –Device type 01 Pin No Signal name Pin No Signal name Pin No Signal name 1 2 3 GPIO12/ TZ1 /CANTXB/SPISIMOB VSS VDDIO ADCREFIN VDD GPIO29/SCITXDA/ TZ 6 ADCREFM ADCREFP ADCRESEXT 68 69 70 4 35 36 37 38 GPIO33/SCLA/EPWMSYNCO/ 39 VSS2AGND GPIO30/CANRXA GPIO31/CANTXA 40 41 VDD2A18 GPIO14/ TZ3 /SCITXDB/SPICLKB 42 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 71 ADCSOCBO GPIO15/ TZ 4 /SCITXDB/SPISTEB VDD VSS VDD1A18 VSS1AGND VSSA2 VDDA2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 43 44 72 73 74 VSS VDD VSS GPIO11/EPWM6B/SCIRXDB/ ECAP4 GPIO22/EQEP1S/SPICLKC/SCITXDB GPIO23/EQEP1I/SPISTEC/ SCIRXDB TDI TMS TCK 75 GPIO34 GPIO1/EPWM1B/SPISIMOD GPIO2/EPWM2A 76 77 78 TDO GPIO27/ECAP4/EQEP2S/SPIISTEB GPIO24/ECAP1/EQEP2A/SPISIMOB VSS XRS 45 46 47 48 49 50 GPIO16/SPISIMOA/CANTXB/ TZ5 79 80 81 82 83 51 GPIO4/EPWM3A 84 TRST GPIO17/SPISOMIA/CANRXB/ TZ 6 85 VDD 86 87 88 89 X2 VSS X1 VSS 90 91 GPIO25/ECAP2/EQEP2B/SPISOMIB 92 GPIO28/SCIRXDA/ TZ5 93 94 VDD 95 96 GPIO13/ TZ 2 /CANRXB/SPISOMIB VDD3VFL TEST1 52 53 54 55 VDDIO GPIO0/EPWM1A GPIO2/EPWM2B/SPISOMID VSS ADCINA0 ADCLO VSSAIO 56 57 58 59 GPIO5/EPWM3B/SPICLKD/ECAP1 GPIO18/SPICLKA/SCITXDB VSS GPIO6/EPWM4A/EPWMSYNCI/EPWMS YNCO GPIO19/SPISTEA/SCIRXDB GPIO7/EPWM4B/SPISTED/ECAP2 VDD 26 27 28 VDDAIO 60 GPIO8/EPWM5A/CANTXB/ ADCS0CAO ADCINB0 ADCINB1 61 62 GPIO9/EPWM5B/SCITXDB/ECAP3 VSS 29 30 ADCINB2 ADCINB3 63 64 GPIO20/EQEP1A/SPISIMOC/CANTXB GPIO10/EPWM6A/CANRXB/ 31 32 33 34 ADCINB4 ADCINB5 ADCINB6 ADCINB7 65 66 67 ADCSOCBO VDDIO XCLKOUT GPIO21/EQEP1B/SPISPMIC/CANRXB 97 98 99 100 EMU0 EMU1 VDDIO XCLKIN VSS TEST2 GPIO26/ECAP3/EQEP2I/SPICLKB GPIO32/SDAA/EPWMSYNCI/ ADCS0CAO FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 20 Case X –Device type 02 Pin No Signal name Pin No Signal name Pin No Signal name 1 2 3 GPIO12/ TZ1 /SPISIMOB VSS VDDIO ADCREFIN VDD GPIO29/SCITXDA/ TZ 6 ADCREFM ADCREFP ADCRESEXT 68 69 70 4 35 36 37 38 GPIO33/SCLA/EPWMSYNCO/ 39 VSS2AGND GPIO30/CANRXA GPIO31/CANTXA 40 41 VDD2A18 GPIO14/ TZ3 /SCITXDB/SPICLKB 42 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 71 ADCSOCBO GPIO15/ TZ 4 /SCITXDB/SPISTEB VDD VSS VDD1A18 VSS1AGND VSSA2 VDDA2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 43 44 45 46 47 48 49 50 VSS VDD GPIO22/EQEP1S/SPICLKC/SCITXDB GPIO23/EQEP1I/SPISTEC/ SCIRXDB TDI TMS TCK 75 GPIO34 76 77 78 TDO GPIO27/ECAP4/EQEP2S/SPIISTEB GPIO16/SPISIMOA/ TZ5 79 80 81 82 83 GPIO24/ECAP1/EQEP2A/SPISIMOB GPIO4/EPWM3A 84 TRST GPIO17/SPISOMIA/ TZ 6 85 VDD 86 87 88 89 X2 VSS X1 VSS 90 91 GPIO25/ECAP2/EQEP2B/SPISOMIB 92 GPIO28/SCIRXDA/ TZ5 93 94 VDD 95 96 GPIO13/ TZ 2 /SPISOMIB VDD3VFL TEST1 GPIO1/EPWM1B/SPISIMOD GPIO2/EPWM2A VDDIO GPIO0/EPWM1A GPIO2/EPWM2B/SPISOMID VSS 51 52 53 54 55 72 73 74 VSS GPIO11/EPWM6B/SCIRXDB/ ECAP4 ADCINA0 ADCLO VSSAIO 56 57 58 59 GPIO5/EPWM3B/SPICLKD/ECAP1 GPIO18/SPICLKA/SCITXDB VSS GPIO6/EPWM4A/EPWMSYNCI/EPWMS YNCO GPIO19/SPISTEA/SCIRXDB GPIO7/EPWM4B/SPISTED/ECAP2 VDD 26 27 28 VDDAIO 60 GPIO8/EPWM5A/ ADCS0CAO ADCINB0 ADCINB1 61 62 GPIO9/EPWM5B/SCITXDB/ECAP3 VSS 29 30 ADCINB2 ADCINB3 63 64 GPIO20/EQEP1A/SPISIMOC GPIO10/EPWM6A/ ADCSOCBO 31 32 33 34 ADCINB4 ADCINB5 ADCINB6 ADCINB7 65 66 67 VDDIO XCLKOUT GPIO21/EQEP1B/SPISPMIC 97 98 99 100 VSS XRS EMU0 EMU1 VDDIO XCLKIN VSS TEST2 GPIO26/ECAP3/EQEP2I/SPICLKB GPIO32/SDAA/EPWMSYNCI/ ADCS0CAO FIGURE 2. Terminal connections - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 21 Case X –Device type 03 Pin No Signal name Pin No Signal name Pin No Signal name 1 2 3 GPIO12/ TZ1 /SPISIMOB VSS VDDIO ADCREFIN VDD ADCREFM ADCREFP ADCRESEXT 68 69 70 GPIO29/SCITXDA/ TZ 6 35 36 37 38 GPIO33/SCLA/EPWMSYNCO/ 39 VSS2AGND GPIO30/CANRXA GPIO31/CANTXA 40 41 VDD2A18 GPIO14/ TZ3 /SPICLKB 42 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 71 GPIO23/EQEP1I ADCSOCBO GPIO15/ TZ 4 /SPISTEB VDD VSS VDD1A18 VSS1AGND VSSA2 VDDA2 ADCINA7 ADCINA6 TDI TMS TCK 75 GPIO34 GPIO1/EPWM1B GPIO2/EPWM2A 76 77 78 TDO GPIO27/SPIISTEB EMU0 EMU1 VDDIO GPIO24/ECAP1/SPISIMOB VSS XRS 45 46 47 48 49 50 GPIO16/SPISIMOA/ TZ5 79 80 81 82 83 51 GPIO4/EPWM3A 84 TRST VDD VDDIO GPIO0/EPWM1A GPIO2/EPWM2B VSS GPIO17/SPISOMIA/ TZ 6 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLO VSSAIO 52 53 54 55 56 57 58 59 85 GPIO5/EPWM3B/ECAP1 GPIO18/SPICLKA VSS GPIO6/EPWMSYNCI/EPWMSYNCO GPIO19/SPISTEA GPIO7/ECAP2 VDD 86 87 88 89 90 91 X2 VSS X1 VSS XCLKIN GPIO25/ECAP2/SPISOMIB 92 GPIO28/SCIRXDA/ TZ5 26 27 28 VDDAIO 60 GPIO8/ ADCS0CAO VDD ADCINB0 ADCINB1 61 62 GPIO9 VSS 93 94 29 30 ADCINB2 ADCINB3 63 64 GPIO20/EQEP1A 95 96 GPIO10/ ADCSOCBO GPIO13/ TZ 2 /SPISOMIB VDD3VFL TEST1 31 32 33 34 ADCINB4 ADCINB5 ADCINB6 ADCINB7 65 66 67 VDDIO XCLKOUT GPIO21/EQEP1B 19 20 21 22 23 24 25 ADCINA5 72 73 74 VSS VDD 43 44 VSS GPIO11 GPIO22/EQEP1S 97 98 99 100 VSS TEST2 GPIO26/SPICLKB GPIO32/SDAA/EPWMSYNCI/ ADCS0CAO FIGURE 2. Terminal connections - Continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 22 Notes: 1. 43 of the possible 96 interrupts are used on the devices. 2. Not available on the device type 03. 3. Not available on the device type 02 and 03. FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 23 FIGURE 4. Package lifetime versus operating junction temperature. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 24 FIGURE 5. Typical operational power versus frequency (for device type 01). DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 25 Note: 1. 2. Input requirements in the manufacturer are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. The manufacturer data provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. FIGURE 6. Test load circuit. Note: 1. 2. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship in this figure is intended to illustrate the timing parameters only and may differ based on configuration. XCLKOUT configured to reflect SYSCLKOUT. FIGURE 7 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 26 Notes: 1. 2. Upon power up, SYSCLKOUT is OSCCLK/2 Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/8 during this phase. After reset, the boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pins, the boot code branches to destination memory or boot code function. If boot ROM code executes after power on conditions (in debugger environment) the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. FIGURE 8 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 27 XCLKIN X1/X2 OSCCLK/8 XCLKOUT OSCCLK*5 t USER-CODE DEPENDENT w(RSL2) XRS t ADDRESS/DATA/ CONTROL (INTERNAL) USER-CODE EXECUTION d(EX) DON'T CARE t BOOT-ROM EXECUTION STARTS BOOT-MODE PINS PERIPHERAL/GPIO FUNCTION USER-CODE EXECUTION PHASE h(BOOT-MODE) SEE NOTE PERIPHERAL/ GPIO FUNCTION GPIO PINS AS INPUT USER-CODE EXECUTION STARTS I/O PINS USER-CODE DEPENDENT GPIO PINS AS INPUT (STATE DEPENDS ON INTERNAL PU/PD) USER-CODE DEPENDENT WARM RESET Notes: 1. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. FIGURE 9 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 28 FIGURE 10 Timing waveforms. FIGURE 11 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 29 Notes: 1. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value “n” the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2 n SYSCLKOUT cycles, the GPIO pin will be sampled). 2. The qualification period selected via GPxCTRL register applies to groups of 8 GPIO pins. 3. The qualification block can take either three or six samples. The GPxQSELn register selects which sample mode is used. 4. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2)SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT wide pulse ensures reliable recognition. FIGURE 12 Timing waveforms. FIGURE 13 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 30 Note: 1. WAKE INT can be any enabled interrupt, WDINT , XNMI, XRS FIGURE 14 Timing waveforms. Notes: 1. 2. 3. 4. 5. 6. IDLE instruction is executed to put the device into STANBY mode. The PLL block respond to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned off. This 32 cycle delay enables the CPU pipe and any other pending operations to flush properly. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. The external wake up signal is driven active. After a latency period, the STANDBY mode is excited. Normal operation resumes. The device will respond to the interrupt (if enabled). FIGURE 15 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 31 Notes: 1. 2. 3. 4. 5. 6. 7. IDLE instruction is executed to put the device into HALT mode. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is tuned off and the CLKIN to the core is stopped. This 32 cycle delay enables the CPU pipe and any other pending operation to flush properly. Clocks to the device are turned off and the internal oscillator and PLL are shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK(X1/X2 or X1 or XCLKIN) cycles. When CLKIN to the core is enabled, the device will response to the interrupt (if enabled), after a latency. The HALT mode is now exited. Normal operation resumes. FIGURE 16 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 32 Notes: 1. TZ - TZ1 , TZ 2 , TZ3 , TZ 4 , TZ5 , TZ 6 2. PWM refers to all PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM FIGURE 17 Timing waveforms. FIGURE 18 Timing waveforms. FIGURE 19 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 33 1 SPICLK (CLOCK POLARITY=0) 2 3 SPICLK (CLOCK POLARITY=1) 4 5 MASTER OUT DATA IS VALID SPISIMO 9 8 MASTER IN DATA MUST BE VALID SPISOMI SPISTE SEE NOTE SPI MASTER MODE EXTERNAL TIMING(CLOCK PHASE=0) Note: 1. In the master mode, SPISTE goes active 0.5tc(SPC)(minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after receiving edge (SPICLK) of the last data bit. FIGURE 20 Timing waveforms. Note: 1. In the master mode, SPISTE goes active 0.5tc(SPC)(minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after receiving edge (SPICLK) of the last data bit. FIGURE 21 Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 34 Note: 1. In the slave mode, SPISTE signal should be asserted low at least 0.5tc(SPC)(minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after receiving edge (SPICLK) of the last data bit. FIGURE 22. Timing waveforms. Note: 1. In the slave mode, SPISTE signal should be asserted low at least 0.5tc(SPC)(minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after receiving edge (SPICLK) of the last data bit. FIGURE 23. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 35 FIGURE 24. Timing waveforms. Typical values of the circuit components: Switching resistance (RON) : 1 kΩ. 1.64 pF Sampling capacitor (Ch): 10 pF Parasitic capacitance (Cp): 50 Ω Source resistance (Rs): FIGURE 25. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 36 FIGURE 26. Timing waveforms. FIGURE 27. Timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 37 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. 1/ 2/ Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/06619-01XE 01295 SM320F2808PZMEP V62/06619-02XE 2/ SM320F2806PZMEP V62/06619-03XE 01295 SM320F2801PZMEP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. Not yet available from a source of supplied. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV C DWG NO. V62/06619 PAGE 38