V6204607 VID

REVISIONS
LTR
DESCRIPTION
A
Update boilerplate paragraphs to current
requirements. - PHN
DATE
APPROVED
10-01-19
Thomas M. Hess
Prepared in accordance with ASME Y14.24
Vendor item drawing
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REV STATUS
OF PAGES
PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
CHECKED BY
Phu H. Nguyen
YY MM DD
04-02-11
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990
TITLE
MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL
SIGNAL PROCESSOR, MONOLITHIC SILICON
APPROVED BY
Thomas M. Hess
SIZE
CODE IDENT. NO.
A
REV
AMSC N/A
.
DWG NO.
V62/04607
16236
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1
OF
43
5962-V022-10
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor
microcircuit, with an operating temperature range of -40°C to +85°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/04607
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s). 1/
Device type
Generic
01
SM320VC5421-EP
Circuit function
Fixed Point Digital Signal Processor
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
Package style
X
144
Low Profile Quad Flatpack
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
1.3 Absolute maximum ratings. 2/
Supply voltage I/O range, (DVDD) .............................................................................................
Supply voltage core range, (CVDD) ...........................................................................................
Supply voltage analog PLL range, (AVDD) ................................................................................
Input voltage range, (VI) ...........................................................................................................
Output voltage range (VO) .......................................................................................................
Operating case temperature ranges, (TC) ................................................................................
Storage temperature range, (TSTG)............................................................................................
1/
2/
-0.5 V to +4.0 V
-0.5 V to +2.4 V
-0.5 V to +2.4 V
-0.5 V to DVDD+0.5 V
-0.5 V to DVDD+0.5 V
-40°C to +85°C
-65°C to +150°C
Users are cautioned to review the manufacturers data manual for additional user information relating to this device.
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to VSS.
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1.4 Recommended operating conditions. 3/ 4/
Device supply voltage, I/O (DVDD) ..............................................................................
Device supply voltage, core (CVDD) ............................................................................
Device supply voltage, PLL (AVDD) ............................................................................
Supply voltage, GND (VSS) .........................................................................................
High level input voltage, I/O (VIH):
Schmitt triggered inputs, DVDD = 3.3 ±0.3 V ..........................................................
All other inputs ......................................................................................................
Low level input voltage, I/O (VIL):
Schmitt triggered inputs, DVDD = 3.3 ±0.3 V ..........................................................
All other inputs ......................................................................................................
High level output current, (IOH) ...................................................................................
Low level output current, (IOL) .....................................................................................
Operating case temperature (TC) ...............................................................................
Junction to case (RΘJC) ...............................................................................................
Junction to air (RΘJA) ..................................................................................................
+3.0 V to +3.6 V
+1.75 V to +1.98 V
+1.75 V to +1.98 V
0V
0.7DVDD to DVDD
2.0 V to DVDD
0 V to 0.3DVDD
0 V to + 0.8 V
-300 µA maximum
1.5 mA maximum
-40°C to +85°C
5°C/W
56°C/W
2. APPLICABLE DOCUMENTS
JEDEC PUB 95
–
Registered and Standard Outlines for Semiconductor Devices
(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington,
VA 22201-3834 or online at http://www.jedec.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are
as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
____________
3/
4/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
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3.5 Diagrams.
3.5.1
Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Block diagram. The block diagram shall be as specified in figure 3.
3.5.4
Load circuit. The load circuit shall be as specified in figure 4.
3.5.5
Timing waveforms. The timing waveforms shall be as shown in figure 5-25.
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TABLE I. Electrical performance characteristics.
Test
Symbol
1/
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
High level output voltage
2/
VOH
DVDD = 3.3 ±0.3 V, IOH = Max
Low level output voltage
2/
VOL
IOL = Max
Input current in high impedance
TRST
Input current
(VI = VSS to DVDD)
Min
Unit
Max
2.4
V
0.4
V
µA
IIZ
DVDD = Max, VI = VSS to DVDD
-10
10
II
With internal pulldown
-10
35
See pin descriptions
With internal pullups
-35
10
PPD[15:0]
Bus holders enabled, DVDD = Max 3/
-200
200
-10
10
All other input only pins
Supply current, both core CPUs
IDDC
CVDD = 1.8 V, TC = 25°C
fX = 100 MHz
4/
Supply current, pins
IDDP
DVDD = 3.3 V, fCLOCK = 100 MHz 5/
TC = 25°C 6/
Supply current, PLL
IDDA
Supply current, standby
Limits
IDLE2
IDDC
IDLE3
90 TYP 5/
mA
54 TYP
mA
5 TYP
mA
PLL x n mode, 20 MHz input
2 TYP
mA
PLL x n mode, 20 MHz input
600 TYP
µA
Input capacitance
CI
10 TYP
pF
Output capacitance
CO
10 TYP
pF
CLOCK OPTION
Divide by 2 and divide by 4 clock options timing requirements
See figure 5
20
7/
Cycle time, CLKIN
tc(CI)
Fall time, CLKIN
tf(CI)
8
Rise time, CLKIN
tr(CI)
8
Pulse duration, CLKIN low
Pulse duration, CLKIN high
tW(CIL)
5
tW(CIH)
5
ns
Divide by 2 and divide by 4 clock options switching characteristics 8/
Cycle time, CLKOUT
tc(CO)
40
7/
Cycle time, CLKOUT – bypass mode
tc(CO)
40
7/
td(CIH-CO)
3
10
Delay time, CLKIN high to CLKOUT high/low
See figure 5
Fall time, CLKOUT
tf(CO)
2 Typ
Rise time, CLKOUT
tr(CO)
2 Typ
Pulse duration , CLKOUT low
tW(COL)
H-2
H+2
Pulse duration , CLKOUT high
tW(COH)
H-2
H+2
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Limits
Unit
Min
Max
CLOCK OPTION – (CONTINUED).
Multiply by N clock option timing requirements 8/
Integer PLL multiplier N
(N = 1-15)
9/
Cycle time, CLKIN
PLL multiplier N = x.5 9/
PLL multiplier
N = x.5, x.75
See figure 6
tc(CI)
20
9/
200
20
9/
100
20
9/
50
ns
9/
Fall time, CLKIN
tf(CI)
8
Rise time, CLKIN
tr(CI)
8
Pulse duration, CLKIN low
tW(CIL)
5
Pulse duration, CLKIN high
tW(CIH)
5
Multiply by N clock option switching characteristics 8/
Cycle time, CLKOUT
tc(CO)
Delay time, CLKIN high/low to CLKOUT
high/low
See figure 6
10
td(CI-CO)
ns
4
16
Fall time, CLKOUT
tf(CO)
2 Typ
Rise time, CLKOUT
tr(CO)
2 Typ
Pulse duration , CLKOUT low
tW(COL)
H-2
H+2
Pulse duration , CLKOUT high
tW(COH)
H-2
H+2
Transitory phase, PLL lock up time
30
µs
2H-12
ns
tp
EXTERNAL MEMORY INTERFACE TIMING
Memory read timing requirements 14/
Access time, read data access from address
valid 11/
ta(A)M
See figure 7
Access time, read data access from MSTRB
low
ta(MSTRBL)
Setup time, read data before CLOCKOUT low
tsu(D)R
9
Hold time, read data after CLOCKOUT low
th(D)R
0
Hold time, read data after address invalid
th(A-D)R
0
Hold time, read data after MSTRB high
th(D)MSTRBH
0
2H-11
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
EXTERNAL MEMORY INTERFACE TIMING (CONTINUED)
Memory read switching characteristics
Delay time, CLKOUT low to address valid
11/ 12/
-1
5
td(CLKH-A)
-1
6
Delay time, CLKOUT low to MSTRB low
td(CLKL-MSL)
-1
4
Delay time, CLKOUT MSTRB high
td(CLKL-MSH)
-1
4
Hold time, address valid after CLKOUT low 11/ 12/
th(CLKL-A)R
-1
5 13/
Hold time, address valid after CLKOUT lhigh 11/ 13/
th(CLKH-A)R
-1
6 13/
Delay time, CLKOUT high (transaction) to address
valid 11/ 13/
Memory write switching characteristics
td(CLKL-A)
See figure 7
ns
14/
Delay time, CLKOUT high to address valid 11/ 15/
td(CLKH-A)
-1
6
Delay time, CLKOUT low to address valid
td(CLKL-A)
-1
5
Delay time, CLKOUT low to MSTRB low
td(CLKL-MSL)
-1
4
Delay time, CLKOUT low to data valid
td(CLKL-D)W
0
7
Delay time, CLKOUT low to MSTRB high
td(CLKL-MSH)
-1
4
Delay time, CLKOUT high to R/ W low
td(CLKH-RWL)
0
4
Delay time, CLKOUT high to R/ W high
td(CLKH-RWH)
0
4
td(RWL-MSTRBL)
H-2
H+2
th(A)W
-1
6
Hold time, write data valid after MSTRB high
th(D)MSH
H-3
H+3
16/
Pulse duration, MSTRB low 16/
tw(SL)MS
2H-4
tsu(A)W
2H-4
tsu(D)MSH
2H-5
11/ 16/
Delay time, R/ W low to MSTRB low
Hold time, address valid after CLKOUT high
Setup time, address valid before MSTRB low
11/ 16/
11/
Setup time, write data valid before MSTRB high
See figure 8
ns
2H+5
16/
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
READY TIMING FOR EXTERNALLY GENERATED WAIT STATES
Ready timing requirements for externally generated wait states 8/ 17/
Setup time, READY before CLKOUT low
tsu(RDY)
Hold time, READY after CLKOUT low
See figure 9
8
th(RDY)
ns
0
Valid time, READY after MSTRB low 18/
tv(RDY)MSTRB
Hold time, READY after MSTRB low 18/
th(RDY)MSTRB
2H-8
2H
PARALLEL I/O INTERFACE TIMING
Parallel I/O port read timing requirements 14/
Access time, read data access from address valid 19/
ta(A)IO
See figure 10
3H-12
ta(ISTRBL)IO
Access time, read data access from IOSTRB low
Setup time, read data before CLKOUT high
ns
2H-11
tsu(D)IOR
9
Hold time, read data after CLKOUT high
th(D)IOR
0
Hold time, read data after IOSTRB high
th(ISTRBH-D)R
0
Parallel I/O port read switching characteristics
Delay time, CLKOUT low to address valid
19/
td(CLKL-A)
See figure 10
-1
5
Delay time, CLKOUT high to IOSTRB low
td(CLKH-ISTRBL)
0
5
Delay time, CLKOUT high to IOSTRB high
td(CLKH-ISTRBH)
0
5
th(A)IOR
-1
5
Hold time, address after CLKOUT low
19/
ns
Parallel I/O port write switching characteristics
Delay time, CLKOUT low to address valid
-1
5
Delay time, CLKOUT high to IOSTRB low
td(CLKH-ISTRBL)
0
5
Delay time, CLKOUT high to write data valid
td(CLKH-D)IOW
H-5
H+5
Delay time, CLKOUT high to IOSTRB high
td(CLKH-ISTRBH)
0
5
Delay time, CLKOUT low R/ W low
td(CLKL-RWL)
0
4
Delay time, CLKOUT low R/ W high
td(CLKL-RWH)
0
4
Hold time, address valid after CLKOUT low
19/
td(CLKL-A)
19/
See figure 11
th(A)IOW
-1
5
th(D)IOW
H-3
H+7
Setup time, write data before IOSTRB high
tsu(D)IOSTRBH
H-5
H+1
Setup time, address valid before IOSTRB low 19/
tsu(A)IOSTRBL
H-5
H+3
Hold time, write data after IOSTRB high
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
EXTERNAL GENERATED WAIT STATES
Externally generated wait state timing requirements 8/ 20/
Setup time, READY before CLKOUT low
tsu(RDY)
Hold time, READY after CLKOUT low
See figure 12
8
th(RDY)
ns
0
Valid time, READY after IOSTRB low 18/
tv(RDY)IOSTRB
Hold time, READY after IOSTRB low 18/
th(RDY)IOSTRB
3H-9
3H
RESET, BIO , INTERRUPT, AND MP/ MC TIMINGS
Reset, BIO , interrupt, and MP/ MC timing requirements
8/
Hold time, RS after CLKOUT low
th(RS)
Hold time, BIO after CLKOUT low
th(BIO)
0
th(INT)
0
tw(RSL)
4H+5
tw(BIO)A
5H
Pulse duration, INTn , NMI high (asynchronous) 21/
tw(INTH)A
4H
Pulse duration, INTn , NMI low (asynchronous) 21/
tw(INTL)A
4H
tw(INTL)WKP
8
Pulse duration, XIO switched
tw(XIO)
4H
Enable time, after XIO switched
ten(XIO)
Hold time, INTn , NMI after CLKOUT low
Pulse duration, RS low
22/
21/
23/
Pulse duration, BIO low, asynchronous
21/
Pulse duration, INTn , NMI low for IDLE2/IDLE3
wakeup 21/
See figure 13
0
ns
4H+10
tsu(RS)
5
Setup time, BIO before CLKOUT low
tsu(BIO)
9
12
Setup time, INTn , NMI , RS before CLKOUT low
tsu(INT)
9
13
Setup time, RS before CLKIN low
23/
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
HOLD AND HOLDA TIMINGS
HOLD and HOLDA timing requirements 8/
Pulse duration, HOLD low
tw(HOLD)
Setup time, HOLD low/high before CLKOUT low
tsu(HOLD)
HOLD and HOLDA switching characteristics
See figure 14
4H+10
ns
8
8/
Disable time, address, PS , DS , IS high impedance
from CLKOUT high
tdis(CLKL-A)
See figure 14
5
Disable time, R/ W high impedance from CLKOUT high
tdis(CLKL-RW)
5
Disable time, MSTRB , IOSTRB high impedance from
CLKOUT high
tdis(CLKL-S)
5
Disable time, data from CLKOUT high
tdis(CLKL-D)
5
Enable time, address, PS , DS , IS from CLKOUT high
ten(CLKL-A)
2H+5
Enable time, data from CLKOUT high
ten(CLKL-D)
2H+5
ten(CLKL-RW)
2H+5
Enable time, R/ W enable from CLKOUT high
Enable time, MSTRB , IOSTRB enable from CLKOUT
high
ten(CLKL-S)
1
2H+5
Delay time, HOLDA low after CLKOUT high
td(HOLDAL)
0
11H+5
Delay time, HOLDA high after CLKOUT high
td(HOLDAH)
0
5
Pulse duration, HOLDA low duration
tw(HOLDA)
2H-3
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Unit
Min
Max
-1
4
EXTERNAL FLAG (XF) AND TOUT TIMINGS
External flag (XF) and TOUT switching characteristics 8/
Delay time, CLKOUT low to XF high
See figure 15
td(XF)
Delay time, CLKOUT low to XF low
0
4
Delay time, CLKOUT high to TOUT high
td(TOUTH)
-1
5
Delay time, CLKOUT high to TOUT low
td(TOUTL)
-1
5
Pulse duration, TOUT
tw(TOUT)
2H-5
2H+2
ns
GENERAL PURPOSE I/O TIMING
General purpose I/O timing requirements
Setup time, GPIOx input valid before CLKOUT high,
GPIOx configured as general purpose input
tsu(GPIO-COH)
Hold time, GPIOx input valid after CLKOUT high,
GPIOx configured as general purpose input
th(GPIO-COH)
See figure 16
7
ns
0
General purpose I/O switching characteristics
Delay time, CLKOUT high to GPIOx output change.
GPIOx configured as general purpose output
td(COH-GPIO)
See figure 16
-1
5
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
McBSP transmit and receive timing requirements 8/ 24/
Cycle time, BCLKR/X
tc(BCKRX)
Pulse duration, BCLKR/X low or BCLKR/X high
tw(BCKRX)
Hold time, external BFSR high after BCLKR low
Hold time, BDR valid after BCLKX low
Hold time, external BFSX high after BCLKX low
Setup time, external BFSR high before BCLKR low
Setup time, BDR valid before BCLKR low
Setup time, external BFSX high before BCLKX low
See figure 17
th(BCKRL-BFRH)
th(BCKRL-BDRV)
th(BCKXL-BFXH)
tsu(BFRH-BCKRL)
tsu(BDRV-BCKRL)
tsu(BFXH-BCKXL)
BCLKR/X ext
4H
BCLKR/X ext
6
BCLKR int
0
BCLKR ext
4
BCLKR int
0
BCLKR ext
5
BCLKR int
0
BCLKR ext
4
BCLKR int
10
BCLKR ext
4
BCLKR int
10
BCLKR ext
3
BCLKR int
10
BCLKR ext
6
ns
Rise time, BCLKR/X
tr(BCKRX)
BCLKR/X ext
8
Fall time, BCLKR/X
tf(BCKRX)
BCLKR/X ext
8
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
McBSP transmit and receive switching characteristics 8/ 24/
Cycle time, BCLKR/X
tc(BCKRX)
See figure 17
BCLKR/X int
4H
ns
Pulse duration , BCLKR/X high
tw(BCKRXH)
BCLKR/X int
D-4
24/
D+1
24/
Pulse duration, BCLKR/X low
tw(BCKRXL)
BCLKR/X int
C-4
24/
C+1
24/
Delay time, BCLKR high to internal BFSR valid
td(BCKRH-BFRV)
BCLKR int
-3
3
Delay time, BCLKX high to internal BFSX valid
td(BCKXH-BFXV)
BCLKR int
-3
8
BCLKR ext
2
15
BCLKR int
-8
3
BCLKR ext
1
12
BCLKR int
-1
11
BCLKR ext
4
20
Disable time, BCLKX high to BDX high impedance
following last data bit
tdis(BCKXH-BDXHZ)
Delay time, BCLKX high to BDX valid. This applies to
all bits except the first bit transmitted
Delay time, BCLKX high to BDX valid
26/
Only applies to first bit transmitted
when in data delay 1 or 2
(XDATDLY = 01b or 10b) modes
Enable time, BCLKX high to BDX
driven
26/
Only applies to first bit transmitted
when in data delay 1 or 2
(XDATDLY = 01b or 10b) modes
Delay time, BFSX high to BDX valid
26/
Only applies to first bit transmitted
when in data delay 0
(XDATDLY = 00b) mode
Enable time, BFSX high to BDX driven
26/
Only applies to first bit transmitted
when in data delay 0
(XDATDLY = 00b) mode
DXENA = 0
td(BCKXH-BDXV)
DXENA = 1
DXENA = 0
td(BFXH-BDXV)
DXENA = 1
DXENA = 0
11
BCLKR ext
20
BCLKR int
4H+6
BCLKR ext
4H+15
BCLKR int
ten(BCKXH-BDX)
DXENA = 1
DXENA = 0
BCLKR int
ten(BFXH-BDX)
DXENA = 1
5
BCLKR ext
16
BCLKR int
4H
BCLKR ext
4H+12
BFSX int
9
BFSX ext
15
BFSX int
4H
BFSX ext
4H+15
BFSX int
2
BFSX ext
14
BFSX int
4H-1
BFSX ext
2H+5
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test
1/
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Symbol
Limits
Min
Unit
Max
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
McBSP sample rate generator timing requirements 8/
Cycle time, SRGR clock input
tc(BCKS)
See figure 18
2H
ns
Pulse duration, SRGR clock input high
tw(BCKSH)
H-4
H+1
Pulse duration, SRGR clock input low
tw(BCKSL)
H-4
H+1
Rise time, SRGR clock input
tr(BCKS)
8
Fall time, SRGR clock input
tf(BCKS)
8
McBSP sample rate generator switching characteristics
Delay time, from SRGR clock input to SRGR output
td(BCKSH-
See figure 18
3
13
ns
BCLKRXH)
McBSP GENERAL PURPOSE I/O TIMING
McBSP general purpose I/O timing requirements
Setup time, BGPIOx input mode before CLKOUT high
27/
tsu(BGPIO-COH)
Hold time, BGPIOx input mode after CLKOUT high
27/
th(COH-BGPIO)
See figure 19
9
ns
0
McBSP general purpose I/O switching characteristics
Delay time, CLKOUT high to BGPIOx output mode
28/
td(COH-BGPIO)
See figure 19
-5
5
ns
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Limits
Unit
Master
Min
Slave
Max
Min
Max
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
McBSP as SPI master or slave timing requirements (CLKSTP = 10b, CLKXP = 0) 8/ 29/
Setup time, BDR valid before BCLKX low
tsu(BDRV-BCKXL)
Hold time, BDR valid after BCLKX low
th(BCKXL-BDRV)
Setup time, BFSX low before BCLKX high
tsu(BFXL-BCKXH)
Cycle time, BCLKX
See figure 20
tc(BCKX)
th(BCKXL-BFXL)
Delay time, BFSX low to BCLKX high 31/
td(BFXL-BCKXH)
Delay time, BCLKX high to BDX valid
2-12H
4
6+12H
12H
See figure 20
29/
32H
32/
T-5
T+6
C-5
C+5
td(BCKXH-BDXV)
-3
12
Disable time, BDX high impedance following
last data bit from BCLKX low
tdis(BCKXL-BDXHZ)
C-6
C+10
Disable time, BDX high impedance following
last data bit from BFSX high
Delay time, BFSX low to BDX valid
ns
6H+4
10H+19
tdis(BFXH-BDXHZ)
4H+4
8H+17
td(BFXL-BDXV)
4H+4
8H+17
McBSP as SPI master or slave timing requirements (CLKSTP = 11b, CLKXP = 0) 8/
Setup time, BDR valid before BCLKX high
tsu(BDRV-BCKXH)
Hold time, BDR valid after BCLKX high
th(BCKXH-BDRV)
Setup time, BFSX low before BCLKX high
tsu(BFXL-BCKXH)
Cycle time, BCLKX
ns
10
McBSP as SPI master or slave switching characteristics (CLKSTP = 10b, CLKXP = 0) 8/
Hold time, BFSX low after BCLKX low 30/
12
29/
See figure 20
12
2-12H
4
6+12H
10
tc(BCKX)
12H
32H
McBSP as SPI master or slave switching characteristics (CLKSTP = 11b, CLKXP = 0) 8/
29/
Hold time, BFSX low after BCLKX low 30/
C-5
C+6
th(BCKXL-BFXL)
ns
See figure 20
32/
ns
Delay time, BFSX low to BCLKX high 31/
td(BFXL-BCKXH)
T-5
T+5
Delay time, BCLKX low to BDX valid
td(BCKXL-BDXV)
-3
12
6H+4
10H+19
tdis(BCKXL-BDXHZ)
-6
10
6H+4
10H+17
td(BFXL-BDXV)
D-2
D+10
4H+4
8H+17
Disable time, BDX high impedance following
last data bit from BCLKX low
Delay time, BFSX low to BDX valid
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Limits
Unit
Master
Min
Slave
Max
Min
Max
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
McBSP as SPI master or slave timing requirements (CLKSTP = 10b, CLKXP = 1) 8/ 29/
Setup time, BDR valid before BCLKX high
tsu(BDRV-BCKXH)
Hold time, BDR valid after BCLKX high
th(BCKXH-BDRV)
Setup time, BFSX low before BCLKX low
tsu(BFXL-BCKXL)
Cycle time, BCLKX
See figure 21
tc(BCKX)
th(BCKXH-BFXL)
Delay time, BFSX low to BCLKX low 31/
td(BFXL-BCKXL)
Delay time, BCLKX low to BDX valid
2-12H
4
6+12H
12H
See figure 21
29/
32H
32/
T-5
T+6
D-5
D+5
td(BCKXL-BDXV)
-3
12
Disable time, BDX high impedance following
last data bit from BCLKX high
tdis(BCKXH-BDXHZ)
D-6
D+10
Disable time, BDX high impedance following
last data bit from BFSX high
Delay time, BFSX low to BDX valid
ns
6H+4
10H+19
tdis(BFXH-BDXHZ)
4H+4
8H+17
td(BFXL-BDXV)
4H+4
8H+17
McBSP as SPI master or slave timing requirements (CLKSTP = 11b, CLKXP = 1) 8/
Setup time, BDR valid before BCLKX low
tsu(BDRV-BCKXL)
Hold time, BDR valid after BCLKX low
th(BCKXL-BDRV)
Setup time, BFSX low before BCLKX low
tsu(BFXL-BCKXL)
Cycle time, BCLKX
ns
10
McBSP as SPI master or slave switching characteristics (CLKSTP = 10b, CLKXP = 1) 8/
Hold time, BFSX low after BCLKX high 30/
12
29/
See figure 21
12
2-12H
4
6+12H
10
tc(BCKX)
12H
32H
McBSP as SPI master or slave switching characteristics (CLKSTP = 11b, CLKXP = 1) 8/
29/
Hold time, BFSX low after BCLKX high 30/
D-5
D+6
th(BCKXH-BFXL)
ns
See figure 21
32/
ns
Delay time, BFSX low to BCLKX low 31/
td(BFXL-BCKXL)
T-5
T+5
Delay time, BCLKX high to BDX valid
td(BCKXH-BDXV)
-3
12
6H+4
10H+19
tdis(BCKXH-BDXHZ)
-6
10
6H+4
10H+17
td(BFXL-BDXV)
C-2
C+10
4H+4
8H+17
Disable time, BDX high impedance following
last data bit from BCLKX high
Delay time, BFSX low to BDX valid
See notes at end of table.
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16
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
1/
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Limits
Min
Unit
Max
HOST PORT INTERFACE TIMING
HPI16 mode timing requirements
8/
33/
Setup time, HAD valid before DS falling edge 34/ 35/
tsu(HBV-DSL)
Hold time, HAD valid after DS falling edge 34/ 35/
th(DSL-HBV)
5
Setup time, HAD valid before HAS falling edge 34/
tsu(HBV-HSL)
5
Hold time, HAD valid after HAS falling edge 34/
th(HSL-HBV)
5
Setup time, address valid before DS rising edge
(nonmultiplexed write) 35/
tsu(HAV-DSH)
5
Setup time, address valid before DS falling edge
(nonmultiplexed read) 35/
tsu(HAV-DSL)
-(4H+5)
Hold time, address valid after DS rising edge
(nonmultiplexed mode) 35/
th(DSH-HAV)
1
Setup time, HAS low before DS falling edge 35/
tsu(HSL-DSL)
5
Hold time, HAS low after DS falling edge 35/
th(HSL-DSL)
2
Pulse duration, DS low 35/
tw(DSL)
30
Pulse duration, DS high 35/
tw(DSH)
10
Cycle time,
DS rising
edge to next
DS rising
edge 35/
Cycle time,
DS rising
edge to next
DS rising
edge 35/
37/
See figure 22-25
5
ns
Nonmultiplexed or multiplexed mode (no increment)
memory accesses (or writes to the FETCH bit) with
no DMA activity.
Reads
10H+30
Writes
10H+10
Nonmultiplexed or multiplexed mode (no increment)
memory accesses (or writes to the FETCH bit) with
16 bit DMA activity.
Reads
16H+30
Writes
16H+10
Nonmultiplexed or multiplexed mode (no increment)
memory accesses (or writes to the FETCH bit) with
32 bit DMA activity.
Reads
24H+30
Writes
24H+10
Multiplexed (autoincrement) memory accesses (or
writes to the FETCH bit) with no DMA activity.
tc(DSH-DSH)
10H+10
Multiplexed (autoincrement) memory accesses (or
writes to the FETCH bit) with 16 bit DMA activity.
36/
16H+10
Multiplexed (autoincrement) memory accesses (or
writes to the FETCH bit) with 32 bit DMA activity.
24H+10
8H
Cycle time, DS rising edge to next DS rising edge for writes to
DSPINT and HINT
35/
40
Cycle time, DS rising edge to next DS rising edge for HPIC reads,
HPIC XADD bit writes, and address register reads and writes 35/
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Limits
Min
Unit
Max
HOST PORT INTERFACE TIMING (CONTINUED)
HPI16 mode timing requirements (Continued) 8/ 33/
Setup time, HD valid before DS rising edge 35/
tsu(HDV-DSH)W
Hold time, HD valid after DS rising edge, write 35/
th(DSH-HDV)W
1
Setup time, SELA/B valid before DS falling edge 35/
tsu(SELV-DSL)
5
Hold time, SELA/B valid after DS rising edge 35/
th(DSH-SELV)
0
HPI16 mode switching characteristics
Delay time, DS low to HD driven
Delay time,
DS low to
HD valid for
first word of
an HPI read
34/
8/
See figure 22-25
10
ns
33/
34/
td(DSL-HDD)
See figure 22-25
3
20
ns
Case 1a: Memory accesses initiated
immediately following a write when DMAC is
active in 16 bit mode and tw(DSH) was < 18H
32H+20 - tw(DSH)
Case 1b: Memory accesses initiated by an
autoincrement when DMAC is active in 16 bit
mode and tw(DSH) was < 18H
16H+20 - tw(DSH)
Case 1c: Memory accesses not initiated by
an autoincrement (or not immediately
following a write) when DMAC is active in 16
bit mode
Case 1d: Memory accesses initiated by an
autoincrement when DMAC is active in 16 bit
mode and tw(DSH) was ≥ 18H
Case 1e: Memory accesses initiated
immediately following a write when DMAC is
active in 32 bit mode and tw(DSH) was < 26H
Case 1f: Memory accesses initiated by an
autoincrement when DMAC is active in 32 bit
mode and tw(DSH) was < 26H
16H+20
td(DSL-HDV1)
20
36/
48H+20 - tw(DSH)
24H+20 - tw(DSH)
Case 1g: Memory accesses not initiated by
an autoincrement (or not immediately
following a write) when DMAC is active in 32
bit mode
Case 1h: Memory accesses initiated by an
autoincrement when DMAC is active in 32 bit
mode and tw(DSH) was ≥ 26H
24H+20
20
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Test condition
-40°C ≤ TC ≤+85°C
1.75 V ≤ CVDD ≤ 1.98 V
3.0 V ≤ DVDD ≤ 3.6 V
unless otherwise noted
Limits
Min
Unit
Max
HOST PORT INTERFACE TIMING (CONTINUED)
HPI16 mode switching characteristics (Continued) 8/ 33/
Delay time,
HAS low to
HD valid for
first word of an
HPI read
See figure 22-25
Case 2a: Memory accesses initiated
immediately following a write when
DMAC is inactive and tw(DSH) was < 10H
Case 2b: Memory accesses initiated by
an autoincrement when DMAC is
inactive and tw(DSH) was < 10H
20H+20 - tw(DSH)
10H+20 - tw(DSH)
td(DSL-HDV1)
Case 2c: Memory accesses not
initiated by an autoincrement (or not
immediately following a write) when
DMAC is inactive
Case 2d: Memory accesses initiated by
an autoincrement when DMAC is
inactive and tw(DSH) was ≥ 10H
10H+20
36/
20
Case 3: HPIC/HPIA reads
20
Multiplexed reads with autoincrement. Prefetch
completed.
Delay time,
DS high to
HRDY high
35/
(writes and
autoincrement
reads)
td(DSL-HDV2)
3
Memory accesses (or writes to the
FETCH bit) with one or more 16 bit
DMAC channels active
38/
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
38/
16H+5
td(DSH-HYH)
36/
Memory accesses (or writes to the
FETCH bit) with one or more 32 bit
DMAC channels active
Writes to DSPINT and HINT
Valid time, HD valid after HRDY high
20
10H+5
Memory accesses (or writes to the
FETCH bit) when no DMAC is active
24H+5
4H+5
7
tv(HYH-HDV)
th(DSH-HDV)R
0
10
td(COH-HYH)
5
td(DSL-HYL)
12
td(DSH-HYL)
12
Delay time, HAS low to HRDY low, read
td(HSL-HYL)
12
Delay time, CLKOUT rising edge to HINT change
td(COH-HTX)
5
Delay time, DS low to HRDY low
Delay time, DS high to HRDY low
ns
39/
39/
See notes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
1/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by
characterization and/or design.
2/
All input and output voltage levels except RS , INT0 , INT1 , NMI , CLKIN, BCLKX, BCLKR, HAS , HCS , HDS1 , HDS2 , and
3/
4/
5/
6/
7/
8/
9/
10/
HPIRS are LVTTL compatible.
VIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX).
Clock mode: PLL x 1 with external source.
This value is based on 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with the
program being executed.
This value was obtained using the following conditions: external memory writes at a rate 20 million writes per second,
CLKOFF = 0, full duplex operation of all six McBSP at a rate of 10 million bits per second each, and 15 pF loads on all
outputs. For more details on how this calculation is performed, refer to the Calculation of TMS320LC54x Power Dissipation
Application Report (literature number SPRA164).
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at
frequencies approaching 0 Hz.
H = 0.5tc(CO).
N = Multiplication factor.
The multiplication factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is
within the specified range (tc(CO)).
11/
12/
13/
Address, PS , and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read.
In the case of a memory read preceded by a memory write.
14/
15/
16/
17/
MSTRB = 0, H = 0.5tc(CO).
In the case of a memory write preceded by a memory write.
In the case of a memory write preceded by an I/O cycle
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate
wait states by READY, at least two software wait states must be programmed. READY is not sampled until the completion of
the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
18/
19/
20/
Address and IS timings are included in timings referenced as address.
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate
wait states using READY, at least two software wait states must be programmed.
21/
The external interrupts ( INT0 - INT1 , NMI ) are synchronized to the core CPU by way of a two flip-flop synchronizer which
samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 10-0 sequence at the timing that is corresponding to the three-CLKOUT sampling sequence.
22/
If the PLL mode is selected, then at power on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to
ensure synchronization and clock in of the PLL.
23/
RS can cause a change in clock frequency, changing the value of H (see the software programmable phase locked loop
(PLL) section).
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references
of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even.
See manufacturer TMS320C54x DSP reference set, Volume 5: Enhanced peripherals (literature number SPRU302) for a
description of the DX enable (DXENA) and data delay features of the McBSP.
24/
25/
26/
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TABLE I. Electrical performance characteristics - Continued.
27/
28/
29/
30/
31/
32/
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx or BDXx when configured as a general purpose output.
For all SPI slave modes, CLKG is programmed as ½ of the CPU clock by setting CLKSM = CLKGDV = 1
FSRP = FSXP =1. As a SPI master, BFSX is inverted to provide active low slave enable output. As a slave, the active low
signal input on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = BFSRM = 0 for master McBSP
CLKXM =CLKRM = FSXM = BFSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge
of the master clock (BCLKX).
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even.
33/
DS refers to the logical OR of HCS , HDS1 , and HDS2 , and HD refers to any of the HPI data bus pins (HD0, HD1, HD2,
etc.).
34/
HAD stands for HCNTL0, HCNTL11, and HR/ W .
35/
DS refers to either HCS or HDS , whichever is controlling the transfer. Refer to the manufacturer TMS320C54x DSP
Reference set, Volume 5: Enhanced Peripherals (literature number SPRU302) for information regarding logical operation of
37/
the HPI16. These timings are shown assuming that HDS is the signal controlling the transfer.
These timings are for HPI access which do not cross from one subsystem to the other. For access which do cross from one
subsystem to the other, additional cycles are required. A detailed description of these considerations is provided in the
application not Memory Transfer with TMS320VC5420 and TMS320VC5421 DSPs (literature number DPRA620).
In autoincrement mode, WRTE timings are the same as READ timings.
38/
39/
HDS refers to either HDS1 or HDS2 .
HRDY does not go low for other register accesses.
36/
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Case X
Symbol
A
A1
b
c
D/E
Millimeters
Min
Max
Symbol
1.60
D1/E1
1.35
1.45
D2/E2
0.17
0.27
e
0.13 NOM
K
21.80
22.20
Min
Max
19.80
20.20
17.50 TYP
0.50 TYP
0.45
0.75
Notes:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Fall within JEDEC MO-136
FIGURE 1. Case outlines.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
22
Case X
Pin
No.
Signal Name
(non multiplexed)
Signal Name
(multiplexed)
Pin
No.
Signal Name
(non multiplexed)
Signal Name
(multiplexed)
1
PPD7
HD7
37
VSS
2
PPA8
HA8
38
PPD15
HD15
3
PPA0
A _ HINT /HA0
39
PPD14
HD14
4
DVDD
40
VSS
5
PPA9
HA9
41
PPD13
HD13
6
PPD1
HD1
42
PPD12
HD12
7
A _ INT1
43
A_BFSR0
8
A _ NMI
44
A_BDR0
9
IOSTRB
45
A_BCLKR0
10
A_GPIO2/ BIO
46
A_BFSX0
11
A_GPIO1
47
VSS
12
A _ RS
48
CVDD
13
A_GPIO0
49
A_BDX0
14
VSS
50
A_BCLKX0
15
VSS
51
MSTRB
HCS
16
CVDD
52
DS
HDS2
17
A_BFSR1
53
PS
HDS1
18
A_BDR1
54
B_BCLKX0
19
A_BCLKR1
55
B_BDX0
20
A_BFSX1
56
DVDD
21
CVDD
57
VSS
22
VSS
58
B_BFSX0
23
A_BDX1
59
B_BCLKR0
24
A_BCLKX1
60
B_BDR0
25
A_XF
61
CVDD
26
A_CLKOUT
62
VSS
27
HOLDA
63
B_BFSR0
28
TCK
64
R/ W
HR/ W
29
TMS
65
PPA2
HCNTL1/HA2
30
TDI
66
PPA3
HCNTL0/HA3
31
A_GPIO3/A_TOUT
A_ROMEN
TRST
67
SELA/B
PPA18
32
EMU1/ OFF
68
PPD8
HD8
33
DVDD
69
PPD9
HD9
34
A _ INT0
70
PPD10
HD10
35
EMU0
71
PPD11
HD11
36
TDO
72
VSS
FIGURE 2. Terminal connections.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
23
Case X
Pin
No.
Signal Name
(non multiplexed)
Signal Name
(multiplexed)
Pin
No.
Signal Name
(non multiplexed)
Signal Name
(multiplexed)
73
PPA10
HA10
109
PPA17
HA7
74
PPA11
HA11
110
PPA6
HA6
75
DVDD
111
PPA4
HAS /HA4
76
VSS
112
DVDD
77
PPA12
HA12
113
PPA5
HA5
78
PPA13
HA13
114
PPA1
B _ HINT /HA1
79
HPIRS
115
PPD3
HD3
80
HMODE
116
PPD2
HD2
81
B_CLKOUT
117
B_BFSR2
82
B_XF
118
B_BDR2
83
B _ RS
119
VSS
84
XIO
120
CVDD
85
TEST
121
B_BCLKR2
86
VSS
122
B_BFSX2
87
CVDD
123
B_BDX2
88
B_BCLKX1
124
B_BCLKX2
89
B_BDX1
125
VSS
90
VSS
126
AVDD
91
B_BFSX1
127
VSSA
92
B_BCLKR1
128
HOLD
93
VSS
129
CLKIN
94
CVDD
130
DVDD
95
B_BDR1
131
READY
96
B_BFSR1
132
A_BCLKX2
97
B_GPIO0
133
CVDD
98
B_GPIO1
134
VSS
99
B_GPIO2/ BIO
135
A_BCLKR2
100
IS
B_ROMEN
136
A_BDR2
B _ NMI
137
A_BFSX2
B _ INT1
138
A_BDX2
103
B _ INT0
139
A_BFSX2
104
PPA17
HA117
140
PPD6
HD6
105
PPA16
HA16
141
PPD4
HD4
106
VSS
142
PPD5
HD5
107
PPA15
HA15
143
PPD0
HD0
108
PPA14
HA14
144
VSS
101
102
B_GPIO3/B_TOUT
HRDY
FIGURE 2. Terminal connections - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
24
FIGURE 3. Block diagram.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
25
Where:
IOL
IOH
VLoad
CT
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
= 40 pF typical load circuit capacitance.
FIGURE 4. Load circuit.
FIGURE 5. Timing waveforms.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
26
FIGURE 6. Timing waveforms - Continued.
FIGURE 7. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
27
FIGURE 8. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
28
FIGURE 9. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
29
FIGURE 10. Timing waveforms - Continued.
FIGURE 11. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
30
FIGURE 12. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
31
FIGURE 13. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
32
Note:
A[17:16] apply to DMA accesses to extended DATA and PROGRAM memory. The CPU has access to only extended
PROGRAM memory.
FIGURE 14. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
33
FIGURE 15. Timing waveforms - Continued.
FIGURE 16. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
34
FIGURE 17. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
35
FIGURE 18. Timing waveforms - Continued.
Notes:
1.
2.
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general purpose output
FIGURE 19. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
36
FIGURE 20. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
37
FIGURE 21. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
38
Note:
HRDY goes low at these times only after autoincrement reads.
FIGURE 22. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
39
FIGURE 23. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
40
FIGURE 24. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
41
FIGURE 25. Timing waveforms - Continued.
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
42
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.
1/
Vendor item drawing administrative
control number 1/
Device manufacturer
CAGE code
Vendor part number
V62/04607-01XE
01295
SM320VC5421PGE20EP
The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
CAGE code
01295
DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO
Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
SIZE
A
CODE IDENT NO.
16236
REV
A
DWG NO.
V62/04607
PAGE
43