TI TMSDVC5410GGWR100

TMS320VC5410 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS075E
October 1998 -- Revised December 2000
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
(This page has been left blank intentionally.)
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
*
October 1998
Advance Information
Original
A
February 1999
Advance Information
Updated characteristic data
B
June 1999
Production Data
Updated characteristic data
C
January 2000
Production Data
Updated characteristic data
D
May 2000
Production Data
Updated characteristic data
E
November 2000
Production Data
1.
Converted from data sheet format to data manual format.
2.
Removed the TMS320VC5410-120 from this datasheet and created a
separate document (literature number SPRS158) This affectes several places
in this document.
3.
Corrected:
4.
•
Maximum disable time of the BDX signal with external BCLKX in the
switching characteristics table of McBSP serial port timing section.
Improved timing diagrams (Figure 4--21, and Figure 4--22) in the McBSP
serial port timing section.
•
Minimum high--level input voltage (VIHmin) for the HPI databus signals,
HD[7:0] from 2 V to 2.2 V in the recommended operating conditions.
•
Minimum cycle time of CLKOUT in the switching characteristics table of
the divide-by-clock option.
•
Minimum cycle time of X2/CLKIN in the timing requirements table of the
divide-by-two clock option.
•
Maximum rise and fall times of X2/CLKIN in the timing requirements table
of the divide-by-two clock option.
•
Minimum and maximum cycle times for X2/CLKIN in the timing
requirements table of the multiply-by-N clcok option..
•
Several timing values in the switching characteristics table of the HPI8
timing section.
Added:
•
Clarifying paragraph to Section 4.14.1 “McBSP Transmit and Receive
Timings”, regarding the effect of the CLKOUT divide factor on the serial
port timings.
•
BCLKS timings to the timing requirements table, switching
characteristics table, and timing diagrams of the McBSP serial port timing
section.
•
Clarifying sentence to Table 2--4. “Bank--Switching Control Register
Fields”, regarding the effect of the CLKOUT divide factor on the external
memory interface.
•
Clarifying sentences to Section 2.2.6, “Hardware Timer”, regarding the
effect of the CLKOUT divide factor on timer operation.
•
Clarifying footnote to Table 2--5, “CLKMD Pin Configured Clock Options”,
regarding the effect of the CLKMD pins on the on-chip oscillator.
iii
iv
Contents
Contents
Section
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Pin Assignments for the GGW Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
2
2
2
3
6
2
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Programmable Bank-Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
Enhanced Host-Port Interface (HPI8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Multichannel Buffered Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8
Enhanced External Parallel Interface (XIO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
11
12
12
15
15
15
16
18
18
19
21
21
22
25
30
34
3
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Electrical Characteristics Over Recommended Operating Case Temperature Range . . . . . . .
4.4
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2
Divide-By-Two Clock Option -- PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.3
Multiply-By-N Clock Option -- PLL Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.3
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.4
I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
36
37
38
38
39
39
40
41
42
42
43
44
45
October 1998 - December 2000
SPRS075E
v
Contents
Section
4.8
4.9
4.10
4.11
4.12
4.13
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.1
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.2
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host-Port Interface (HPI8) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
50
51
53
54
55
55
58
59
64
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
4.14
5
vi
Page
SPRS075E
October 1998 - December 2000
Figures
List of Figures
Figure
Page
1--1
1--2
176-Ball GGW MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Pin PGE Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
2--1
2--2
2--3
10
12
2--5
2--6
2--7
2--8
2--9
2--10
2--11
2--12
2--13
TMS320VC5410 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory (On-Chip RAM Not Mapped in Program Space and
Data Space, OVLY = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory (On-Chip RAM Mapped in Program Space and
Data Space, OVLY = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Control Register (SWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonconsecutive Memory Read and I/O Read Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Memory Read Bus Sequence (n = 3 reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write and I/O Write Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR and IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
15
16
16
19
23
24
25
27
34
4--1
4--2
4--3
4--4
4--5
4--6
4--7
4--8
4--9
4--10
4--11
4--12
4--13
4--14
4--15
4--16
4--17
4--18
4--19
4--20
4--21
4--22
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Divide-by-Two Clock Option With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonconsecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write (MSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . .
External Flag (XF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
39
40
41
42
43
44
45
46
47
47
48
49
50
51
52
52
53
54
54
57
57
2--4
October 1998 - December 2000
SPRS075E
13
vii
Figures
Figure
4--23
4--24
4--25
4--26
4--27
4--28
4--29
4--30
viii
Page
McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRS075E
58
60
61
62
63
66
67
67
October 1998 - December 2000
Tables
List of Tables
Table
Page
1--1
1--2
Pin Assignments for the GGW and the PGE Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
6
2--1
2--2
2--3
2--4
2--5
2--6
2--7
2--8
2--9
Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Control Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKMD Pin Configured Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
16
16
17
22
29
30
31
34
4--1
4--2
4--3
4--4
4--5
4--6
4--7
4--8
4--9
4--10
4--11
4--12
4--13
4--14
4--15
4--16
4--17
4--18
4--19
4--20
4--21
4--22
4--23
4--24
4--25
4--26
4--27
4--28
4--29
4--30
4--31
4--32
Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-2 Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-2 Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Switching Characteristics for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . .
External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
40
40
41
41
42
42
43
44
44
45
46
46
50
50
51
53
54
55
56
58
58
59
59
60
60
61
61
62
62
64
65
October 1998 - December 2000
SPRS075E
ix
Tables
x
SPRS075E
October 1998 - December 2000
Introduction
1
Introduction
This section describes the main features of the TMS320VC5410 digital signal processor (DSP), lists the pin
assignments, and describes the function of each pin. This data manual also provides a detailed description
section, electrical specifications, parameter measurement information, and mechanical data about the
available packaging.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional
Overview (literature number SPRU307).
1.1
Features
D Advanced Multibus Architecture With Three
D
D
D
D
D
D
D
D
D
D
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
64K x 16-Bit On-Chip RAM Composed of:
-- Four Blocks of 2K × 16-Bit On-Chip
Dual-Access Program/Data RAM
-- Seven Blocks of 8K × 16-Bit On-Chip
Single-Access Program/Data RAM
16K × 16-Bit On-Chip ROM Configured to
Program Memory
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
Instructions With a 32-Bit Long Word
Operand
D Instructions With Two- or Three-Operand
D
D
D
D
D
D
D
D
D
D
D
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
-- Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
-- On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
Internal Oscillator or External Clock
Source
-- One 16-Bit Timer
-- Six-Channel Direct Memory Access
(DMA) Controller
-- Three Multichannel Buffered Serial Ports
(McBSPs)
-- 8-Bit Enhanced Parallel Host-Port
Interface (HPI8)
-- Enhanced External Parallel Interface
(XIO2)
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
176-Ball MicroStar BGA™ (GGW Suffix)
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS)
3.3-V I/O and 2.5-V Core Supply Voltages
†
IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
October 1998 -- December 2000
SPRS075E
1
Introduction
1.2
Description
The TMS320VC5410 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory
bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree
of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In
addition, data can be transferred between data and program spaces. Such parallelism supports a powerful
set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.
The 5410 also includes the control mechanisms to manage interrupts, repeated operations, and function calls.
1.3
Pin Assignments
Figure 1--1 illustrates the ball locations for the 176-ball GGW ball grid array (BGA) package and is used in
conjunction with Table 1--1 to locate signal names and ball grid numbers. Figure 1--2 shows the pin
assignments for the 144-pin PGE low-profile quad flatpack (LQFP) package.
1.3.1 Pin Assignments for the GGW Package
Table 1--1 lists each ball number and its associated signal name for the TMS320VC5410GGW 176-ball BGA
package.
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Figure 1--1. 176-Ball GGW MicroStar BGA™ (Bottom View)
2
SPRS075E
October 1998 -- December 2000
Introduction
1.3.2 Pin Assignments for the PGE Package
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
V SS
A21
CV DD
A9
A8
A7
A6
A5
A4
HD6
A3
A2
A1
A0
DV DD
HDS2
VSS
HDS1
VSS
CVDD
HD5
D15
D14
D13
HD4
D12
D11
D10
D9
D8
D7
D6
DV DD
VSS
A20
A19
The TMS320VC5410PGE 144-pin low-profile quad flatpack (LQFP) is footprint-compatible with several other
C54x™ products. Table 1--1 lists each pin number and its associated signal name.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A18
A17
VSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
VSS
HPIENA
CVDD
VSS
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
NC
CLKMD3
CLKMD2
CLKMD1
VSS
DVDD
BDX1
BFSX1
V SS
BCLKR1
HCNTL0
V SS
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
HCNTL1
BDR2
BCLKX0
BCLKX2
VSS
HINT
CVDD
BFSX0
BFSX2
HRDY
DVDD
V SS
HD0
BDX0
BDX2
IACK
HBIL
NMI
INT0
INT1
INT2
INT3
CV DD
HD1
V SS
BCLKX1
VSS
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
VSS
A22
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
VSS
VSS
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
BDR1
BFSR1
NOTES: A. DVDD is the power supply for I/O pins while VSS and CVDD are power supplies for core CPU.
B. The McBSP pins BCLKS0, BCLKS1, and BCLKS2 are not available on the PGE package.
Figure 1--2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
C54x is a trademark of Texas Instruments.
October 1998 -- December 2000
SPRS075E
3
Introduction
Table 1--1. Pin Assignments for the GGW and the PGE Packages
4
GGW
BALL NO.
SIGNAL
NAME
PGE
PIN NO.
GGW
BALL NO.
SIGNAL
NAME
PGE
PIN NO.
A2
VSS
144
A3
CVDD
142
A4
A8
140
A5
A6
138
A6
A4
136
A7
A2
133
A8
DVDD
130
A9
VSS
126
A10
D14
122
A11
D13
121
A12
DVDD
A13
D9
116
A14
D6
A15
A20
110
A16
CVDD
B1
VSS
1
B4
A9
141
B6
VSS
B3
A21
B5
DVDD
113
143
B7
A3
134
B8
A0
131
B9
HDS2
129
B10
CVDD
125
B11
VSS
B12
D11
118
B13
D8
115
B14
DVDD
112
B15
A19
109
B17
DVDD
C1
VSS
3
C2
A22
2
C4
DVDD
C5
A7
139
C7
DVDD
C9
VSS
128
120
C6
A5
C8
CVDD
137
C10
HD5
124
C11
HD4
C12
D10
117
C13
D7
114
C14
VSS
111
C16
A18
108
C17
A17
107
D1
A10
5
D2
CVDD
D3
DVDD
4
D7
HD6
135
D8
A1
132
D9
HDS1
127
D10
D15
123
106
D11
D12
119
D15
VSS
D16
A16
105
D17
CVDD
E1
A11
7
E2
VSS
E3
HD7
6
E15
D5
E16
D4
103
E17
VSS
F1
A14
10
F2
A13
9
F3
A12
8
F15
D3
102
F16
D2
101
F17
DVDD
G1
HAS
13
G2
CVDD
12
G3
DVDD
G4
A15
11
G15
D0
99
G17
RS
98
H2
HCS
17
G14
D1
G16
VSS
100
H1
VSS
14
104
H3
CVDD
16
H4
VSS
15
H14
X1
96
H15
X2/CLKIN
97
H16
HD3
95
H17
CLKOUT
94
J1
HR/W
18
J2
DS
21
J3
PS
20
J4
READY
19
J14
HPIENA
92
J15
VSS
93
SPRS075E
October 1998 -- December 2000
Introduction
Table 1--1. Pin Assignments for the GGW and the PGE Packages (Continued)
GGW
BALL NO.
SIGNAL
NAME
J16
PGE
PIN NO.
GGW
BALL NO.
SIGNAL
NAME
PGE
PIN NO.
DVDD
J17
CVDD
91
K1
VSS
K2
IS
22
K3
DVDD
K4
R/W
23
K14
TCK
88
K15
TMS
89
K16
VSS
90
K17
TRST
87
L1
MSTRB
24
L2
IOSTRB
25
L3
CVDD
L4
MSC
26
L14
VSS
L15
EMU1/OFF
84
L16
TDO
85
L17
TDI
86
M1
XF
27
M2
HOLDA
28
M3
IAQ
29
M15
HD2
81
M16
TOUT
82
M17
EMU0
83
N1
HOLD
30
N2
BIO
31
N3
MP/MC
32
N15
CLKMD2
78
N16
CLKMD3
79
N17
NC
80
P1
DVDD
33
P2
VSS
34
P3
BCLKS1
P7
HCNTL1
46
P8
BCLKS2
P9
BFSX0
53
P10
HD0
58
P11
VSS
P15
DVDD
75
P16
VSS
76
P17
CLKMD1
77
R1
BDR1
35
R2
BFSR1
36
R4
VSS
40
R5
BCLKR2
42
R6
BFSR2
44
R7
BDR2
47
R8
VSS
50
R9
BFSX2
54
R10
BDX0
59
R11
IACK
61
R12
INT0
64
R13
INT2
66
R14
HD1
69
R16
BFSX1
73
R17
BDX1
74
T1
CVDD
T3
BCLKR1
38
T4
DVDD
T5
BFSR0
43
T6
BDR0
45
T7
CVDD
T8
HINT
51
T9
HRDY
55
T10
VSS
57
T11
BDX2
60
T12
NMI
63
T13
DVDD
T14
CVDD
68
T15
BCLKX1
71
U2
VSS
37
U4
BCLKR0
41
T17
CVDD
U3
HCNTL0
U5
BCLKS0
U6
VSS
U7
BCLKX0
48
U8
BCLKX2
49
52
U10
DVDD
56
U12
HBIL
62
39
U9
CVDD
U11
CVDD
U13
INT1
65
U14
INT3
67
U15
VSS
70
U16
VSS
72
October 1998 -- December 2000
SPRS075E
5
Introduction
1.4
Signal Descriptions
Table 1--2 lists all the signals grouped by function. See Section 1.3 for exact pin locations based on package
type.
Table 1--2. Signal Descriptions
TERMINAL
NAME
I/O†
DESCRIPTION
DATA SIGNALS
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
†
6
(MSB)
O/Z
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
to A22 are multiplexed to address external program space memory. A22--A0 is placed in the high-impedance
state in the hold mode. A22--A0 also goes into the high-impedance state when OFF is low.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
a high-impedance state.
(LSB)
(MSB)
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). D15--D0 is multiplexed to transfer data between the core CPU
and external data/program memory or I/O devices. D15--D0 is placed in high-impedance state when not
outputting data or when RS or HOLD is asserted. D15--D0 also goes into the high-impedance state when OFF
is low.
The data bus has a bus holder feature that eliminates passive components and the power dissipation associated
with them. The bus holder keeps the data bus at the previous logic level when the bus goes into a high-impedance
state. The bus holders on the data bus can be enabled/disabled under software control.
(LSB)
I = Input, O = Output, Z = High-impedance, S = Supply
SPRS075E
October 1998 -- December 2000
Introduction
Table 1--2. Signal Descriptions (Continued)
TERMINAL
NAME
I/O†
DESCRIPTION
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15--A0. IACK also goes into the high-impedance state when OFF is low.
INT0
INT1
INT2
INT3
I
External user interrupt inputs. INT0--INT3 is prioritized and is maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0 --INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM bit or the IMR.
When NMI is activated, the processor traps to the appropriate vector location.
RS
I
Reset. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS is
brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers
and status bits.
I
Microprocessor/microcomputer mode select pin. If active-low at reset (microcomputer mode), MP/MC causes
the internal program ROM to be mapped into the upper 16K words of program memory space. In the
microprocessor mode, off-chip memory and its corresponding addresses (instead of internal program ROM) are
accessed by the DSP.
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.
MP/MC
MULTIPROCESSING SIGNALS
BIO
XF
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
state when OFF is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
I
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the 5410, these lines go into the high-impedance state.
HOLDA
O/Z
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low.
MSC
O/Z
Microstate complete. MSC goes low when the last wait state of two or more internal software wait states
programmed is executed. If connected to the READY line, MSC forces one external wait state after the last
internal wait state has been completed. MSC also goes into the high-impedance state when OFF is low.
READY
HOLD
†
I = Input, O = Output, Z = High-impedance, S = Supply
October 1998 -- December 2000
SPRS075E
7
Introduction
Table 1--2. Signal Descriptions (Continued)
TERMINAL
NAME
I/O†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active-low) when there is an instruction address on the address
bus and goes into the high-impedance state when OFF is low.
OSCILLATOR/TIMER SIGNALS
CLKOUT
O/Z
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKMD1
CLKMD2
CLKMD3
I
Clock mode select signals. CLKMD1 -- CLKMD3 allow the selection and configuration of different clock modes
such as crystal, external clock, PLL mode.
X2/CLKIN
I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low.
TOUT
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0
BCLKR1
BCLKR2
I/O/Z
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
BDR2
I
BFSR0
BFSR1
BFSR2
I/O/Z
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
BCLKX0
BCLKX1
BCLKX2
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BDX0
BDX1
BDX2
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
BFSX2
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
into the high-impedance state when OFF is low.
I
Serial port clock reference. The McBSP can be programmed to use either BCLKS or the CPU clock as a
reference for generation of internal clock and frame sync signals. Pins with internal pullup devices.
NOTE: These pins are not available on the PGE package.
BCLKS0
BCLKS1
BCLKS2
Serial data receive input
MISCELLANEOUS SIGNAL
NC
No connection
HOST-PORT INTERFACE SIGNALS
HD0--HD7
†
8
I/O/Z
Parallel bidirectional data bus. HD0--HD7 is placed in the high-impedance state when not outputting data. The
signals go into the high-impedance state when OFF is low. The HPI data bus has a feature called a bus holder
that eliminates passive components and the power dissipation associated with them. The bus holder keeps the
data bus at the previous logic level when the bus goes into high-impedance state. The bus holder on the HPI
data bus can be enabled/disabled under software control.
I = Input, O = Output, Z = High-impedance, S = Supply
SPRS075E
October 1998 -- December 2000
Introduction
Table 1--2. Signal Descriptions (Continued)
TERMINAL
NAME
I/O†
DESCRIPTION
HOST-PORT INTERFACE SIGNALS (CONTINUED)
HCNTL0
HCNTL1
I
Control inputs
HBIL
I
Byte identification
HCS
I
Chip select
HDS1
HDS2
I
Data strobe
HAS
I
Address strobe
HR/W
I
Read/write
HRDY
O/Z
Ready output. HRDY goes into the high-impedance state when OFF is low.
HINT
O/Z
Interrupt output. When the DSP is in reset, HINT is driven high. HINT goes into the high-impedance state when
OFF is low.
I
HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to
ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus
has holders set. HPIENA is provided with an internal pulldown resistor that is active only when RS is low. HPIENA
is sampled when RS goes high and is ignored until RS goes low again.
HPIENA
SUPPLY PNS
VSS
S
Ground. Dedicated power supply for the core CPU.
CVDD
S
+VDD. Dedicated power supply for the core CPU.
DVDD
S
+VDD. Dedicated power supply for I/O pins.
TEST PINS
TCK
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TRST
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system.
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active-low, puts all output drivers into
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
EMU1/OFF
†
I = Input, O = Output, Z = High-impedance, S = Supply
October 1998 -- December 2000
SPRS075E
9
Functional Overview
2
Functional Overview
C54x cLEAD
56K RAM
Single-Access
Program/Data
Pbus
Dbus
Ebus
Cbus
Pbus
Ebus
Cbus
Dbus
Ebus
Cbus
Dbus
Pbus
P, C, D, E Buses and Control Signals
8K RAM
Dual-Access
Program/Data
16K Program
ROM
MBus
HPI8
TI BUS
RHEA Bus
McBSP0
Enhanced XIO
DMA
logic
McBSP1
MBus
RHEA bus
XIO
RHEA
Bridge
McBSP2
RHEAbus
TIMER
PLL
Clocks
JTAG
Figure 2--1. TMS320VC5410 Functional Block Diagram
2.1
Memory
The 5410 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
2.1.1 On-Chip ROM With Bootloader
The 5410 features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program memory
space.
Customers can arrange to have the ROM of the 5410 programmed with contents unique to any particular
application.
A bootloader is available in the standard 5410 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the
device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard 5410 devices
provide different ways to download the code to accommodate various system requirements:
•
•
•
•
•
10
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space, 8-bit or 16-bit mode
Serial boot from serial ports, 8-bit or 16-bit mode
Host-port interface boot
Warm boot
SPRS075E
October 1998 -- December 2000
Functional Overview
The standard on-chip ROM layout is shown in Table 2--1.
Table 2--1. Standard On-Chip ROM Layout†
DESCRIPTION
ADDRESS RANGE
†
C000h--D4FFh
ROM tables for the GSM EFR speech codec
D500h--D6FFh
256-point complex radix-2 DIT FFT with looped code
D700h--DCFFh
FFT twiddle factors for a 256-point complex radix-2 FFT
DD00h--DEFFh
1024-point complex radix-2 DIT FFT with looped code
DF00h--F7FFh
FFT twiddle factors for a 1024-point complex radix-2 FFT
F800h--FBFFh
Bootloader
FC00h--FCFFh
μ-Law expansion table
FD00h--FDFFh
A-Law expansion table
FE00h--FEFFh
Sine look-up table
FF00h--FF7Fh
Reserved†
FF80h--FFFFh
Interrupt vector table
In the 5410 ROM, 128 words are reserved for factory device-testing purposes. Application code
to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h--FF7Fh
in program space.
2.1.2 On-Chip RAM
The 5410 device contains 8K words × 16-bit on-chip dual-access RAM (DARAM) and 56K words × 16-bit of
on-chip single-access RAM (SARAM).
The DARAM is composed of four blocks of 2K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h--1FFFh
in data space, and can be mapped into program/data space by setting the OVLY bit to one.
The SARAM is composed of seven blocks of 8K words each. Each of these seven blocks is a single-access
memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data
word is written to another SARAM block. The SARAM located in the address range 2000h--7FFFh in data
space can be mapped into program space by setting the OVLY bit to one, while the SARAM located in the
address range 18000h--1FFFFh in program space can be mapped into data space by setting the DROM bit
to one.
2.1.3 On-Chip Memory Security
The 5410 device has a maskable option to protect the contents of on-chip memories. When the ROM-protect
bit is set, no externally originating instruction can access the on-chip memory spaces. In addition, when the
ROM-protect option is enabled, HPI8 read access is limited to address range 0001000h -- 0001FFFh. Data
located outside this range cannot be read through the HPI8. Write access to the entire HPI8 memory map is
still maintained.
October 1998 -- December 2000
SPRS075E
11
Functional Overview
2.1.4 Memory Map
Program
Hex
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080
Hex
010000
Mapped to
Lower Page 0
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM
(OVLY = 1)
External
(OVLY = 0)
1FFF
2000
On-Chip
SARAM1
(OVLY = 1)
External
(OVLY = 0)
7FFF
8000
Program
Hex
0000
007F
0080
1FFF
2000
7FFF
8000
017FFF
018000
Program
Hex
010000
Program
Hex
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
005F
0060
Mapped to
Lower Page 0
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM
(OVLY = 1)
External
(OVLY = 0)
On-Chip
SARAM1
(OVLY = 1)
External
(OVLY = 0)
007F
0080
Data
Memory-Mapped
Registers
Scratch-Pad
RAM
On-Chip
DARAM
(8K Words)
1FFF
2000
On-Chip
SARAM1
(24K Words)
017FFF
018000
7FFF
8000
External
External
External
BFFF
C000
On-Chip
ROM
(16K Words)
FF7F
FF80
FFFF
Interrupts and
Reserved
(External)
FF7F
FF80
01FFFF
Page 0
MP/MC= 1
(Microprocessor Mode)
Interrupts and
Reserved
(On-Chip ROM)
FFFF
Page 1
On-Chip
SARAM2
(DROM = 1)
External
(DROM = 0)
On-Chip
SARAM2
FFFF
01FFFF
Page 1
Page 0
MP/MC= 0
(Microcomputer Mode)
Figure 2--2. Memory Map
2.1.5 Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When the
cells are mapped into program space, the device automatically accesses them when their addresses are
within bounds. When the program-address generation (PAGEN) logic generates an address outside its
bounds, the device automatically generates an external access. The advantages of operating from on-chip
memory are as follows:
•
•
•
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
12
SPRS075E
October 1998 -- December 2000
Functional Overview
2.1.5.1
Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction which allows branching to the appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
2.1.5.2
Extended Program Memory
The 5410 uses a paged extended memory scheme in program space to allow access of up to 8192K of
program memory. In order to implement this scheme, the 5410 includes several features which are also
present on C548/549:
•
•
•
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC
Six extra instructions for addressing extended program space
Program memory in the 5410 is organized into 128 pages that are each 64K in length, as shown in Figure 2--3.
00 0000
01 0000
02 0000
...
7F 0000
Page 0
Page 1
Page 2
Page 127
64K
Words
64K
Words
64K
Words
64K
Words
00 FFFF
01 FFFF
XPC = 0
...
02 FFFF
XPC = 1
XPC = 2
7F FFFF
XPC=127
Figure 2--3. Extended Program Memory
(On-Chip RAM Not Mapped in Program Space and Data Space, OVLY = 0)
When the on-chip RAM is enabled in program space, each page of program memory is made up of two parts:
a common block of 32K words and a unique block of 32K words. The common block is shared by all pages
and each unique block is accessible only through its assigned page. Figure 2--4 shows the common and
unique blocks.
October 1998 -- December 2000
SPRS075E
13
Functional Overview
xx 0000
Page x
xx 7FFF
32K† Words
On-Chip
XPC = xx
00 8000
01 8000
02 8000
7F 8000
Page 0
Page 1
Page 2
...
Page 127
32K Words
External
32K Words
On-Chip
32K Words
External
...
32K Words
External
00 FFFF
01 FFFF
XPC = 0
02 FFFF
XPC = 1
7F FFFF
XPC = 2
XPC=127
† See Figure 2--2 for more information about this on-chip memory region.
NOTE A: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 -- xx 7FFF, regardless of page number, are
mapped to the on-chip RAM at 00 0000 -- 00 7FFF.
Figure 2--4. Extended Program Memory
(On-Chip RAM Mapped in Program Space and Data Space, OVLY = 1)
If the on-chip ROM is enabled (MP/MC = 0), it is enabled only on page 0. It is not mapped to any other page
in program memory.
The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.
To facilitate page-switching through software, the 5410 has six special instructions that affect the XPC:
•
FB[D] pmad (23 bits) -- Far branch
•
FBACC[D] Accu[22:0] -- Far branch to the location specified by the value in accumulator A or
accumulator B
•
FCALL[D] pmad (23 bits) -- Far call
•
FCALA[D] Accu[22:0] -- Far call to the location specified by the value in accumulator A or accumulator B
•
FRET[D] -- Far return
•
FRETE[D] -- Far return with interrupts enabled
In addition to these new instructions, two C54x™ instructions are extended to use 23 bits in the 5410:
•
READA data_memory (using 23-bit accumulator address)
•
WRITA data_memory (using 23-bit accumulator address)
NOTE: All other instructions, software and hardware interrupts do not modify the XPC register
and access only memory within the current page.
14
SPRS075E
October 1998 -- December 2000
Functional Overview
2.1.6 Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
•
•
•
•
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
2.2
On-Chip Peripherals
The 5410 device has the following peripherals:
•
•
•
•
•
•
•
•
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8)
Three multichannel buffered serial ports (McBSPs)
A hardware timer
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
2.2.1 Software-Programmable Wait-State Generator
The software-programmable wait-state generator can extend external bus cycles by up to fourteen CLKOUT
cycles, providing a convenient means of interfacing the 5410 with slower external devices. Devices that
require more than fourteen wait states can be interfaced using the hardware READY line. When all external
accesses are configured for zero wait states, the internal clocks to the wait-state generator are shut off;
shutting off these paths from the internal clocks allows the device to run with lower power consumption.
The software-programmable wait-state generator is controlled by the 16-bit software wait-state register
(SWWSR), which is memory-mapped to address 0028h in data space.
The program and data spaces each consist of two 32K-word blocks; the I/O space consists of one 64K-word
block. Each of these blocks has a corresponding 3-bit field in the SWWSR. These fields are shown in
Figure 2--5 and described in Table 2--2.
The value of a 3-bit field in SWWSR, in conjunction with the software wait-state multiplier (SWSM) bit in the
software wait-state control register (SWCR), specifies the number of wait states to be inserted for each access
in the corresponding space and address range.
•
•
When SWSM = 0, the possible values for the number of wait states are 0, 1, 2, 3, 4, 5, 6, and 7. This is
the default configuration.
When SWSM = 1, the possible values for the number of wait states are 0, 2, 4, 6, 8, 10, 12, and 14.
At reset, SWWSR is set to 7FFFh, and SWSM to 0, configuring seven wait states for all external accesses.
15
SWWSR (0x28)
XPA
R/W
14
12 11
9 8
6
I/O
Data
Data
R/W
R/W
R/W
5
3
2
0
Program
Program
R/W
R/W
R = Read, W = Write, Reset value = 7FFFh
Figure 2--5. Software Wait-State Register (SWWSR)
October 1998 -- December 2000
SPRS075E
15
Functional Overview
Table 2--2. Software Wait-State Register Fields
BIT
NAME
RESET
VALUE
FUNCTION
15
XPA
0
Extended program address control bit. XPA selects the address ranges selected by the program fields.
14--12
I/O
1
I/O space. The field value (0--14) corresponds to the number of wait states for I/O space 0000--FFFFh.
11--9
Data
1
Data space. The field value (0--14) corresponds to the number of wait states for data space
8000--FFFFh.
8--6†
Data
1
Data space. The field value (0--14) corresponds to the number of wait states for data space
0000--7FFFh.
Program space. The field value (0--14) corresponds to the number of wait states for:
5--3
5
3
Program
1
XPA = 0
xx8000--xxFFFFh
XPA = 1
400000h--7FFFFF
Program space. The field value (0--14) corresponds to the number of wait states for:
2--0
2
0
†
Program
1
XPA = 0
xx0000--xx7FFFh
XPA = 1
000000--3FFFFFh
Although this field is present to maintain compatibility with previous TMS320C5000™ platform DSPs, there is no external data space on the 5410
in this address range; therefore, the configuration of this bit field has no effect.
The SWSM bit is located in the software wait-state control register (SWCR), a memory-mapped register
(MMR) at address 0x2B, bit 0 position (LSB). The bit fields of the SWCR are shown in Figure 2--6 and are
described in Table 2--3.
15
1
SWCR (0x2B)
0
Reserved
SWSM
Figure 2--6. Software Wait-State Control Register (SWCR)
Table 2--3. Software Wait-State Control Register Fields
BIT
15--1
NAME
RESET
VALUE
Reserved
--
SWSM
0
FUNCTION
Reserved
Software wait-state multiplier bit.
0
SWSM = 0 Wait states in SWWSR are not multiplied by 2
SWSM = 1 Wait states in SWWSR are multiplied by 2
2.2.2 Programmable Bank-Switching
Programmable bank-switching logic allows the 5410 to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 2--7 and are described in Table 2--4.
15
BSCR (0x29)
14
13
12
11
3
2
1
0
CONSEC
DIVFCT
IACKOFF
Rsvd
HBH
BH
Rsvd
R/W
R/W
R/W
R
R/W
R/W
R
R = Read, W = Write
Figure 2--7. Bank-Switching Control Register (BSCR)
TMS320C5000 is a trademark of Texas Instruments.
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Functional Overview
Table 2--4. Bank-Switching Control Register Fields
BIT
NAME
RESET
VALUE
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
CONSEC†
15
1
CONSEC = 0
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
CONSEC = 1
Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock. This divide factor also extends all timings related to the external
memory interface, and can be used in conjunction with the software wait states to interface to slower parallel devices.
13--14
DIVFCT
11
DIVFCT = 00
CLKOUT is not divided.
DIVFCT = 01
CLKOUT is divided by 2 from the DSP clock.
DIVFCT = 10
CLKOUT is divided by 3 from the DSP clock.
DIVFCT = 11
CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
12
11--3
IACKOFF
1
Rsvd
--
IACKOFF = 0
The IACK signal output off function is disabled.
IACKOFF = 1
The IACK signal output off function is enabled.
Reserved
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
2
HBH
0
HBH = 0
The bus holder is disabled.
HBH = 1
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
1
BH
0
†
Rsvd
0
--
BH = 0
The bus holder is disabled.
BH = 1
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
Reserved
For additional information, see Section 2.2.8, “Enhanced External Parallel Interface (XIO2)”, of this document.
The 5410 has an internal register that holds the MSB of the last address used for a read or write operation
in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address
used for the current read does not match that contained in this internal register, the MSTRB (memory strobe)
signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new
address. The contents of the internal register are replaced with the MSB for the read of the current address.
If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts
are avoided by inserting an extra cycle. For more information, see Section 2.2.8, “Enhanced External Parallel
Interface (XIO2)”, of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
•
•
•
•
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
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Functional Overview
2.2.3 Parallel I/O Ports
Each device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5410 can interface
easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
2.2.4 Enhanced Host-Port Interface (HPI8)
The enhanced host-port interface (HPI8) in the 5410 is an 8-bit parallel port used to interface a host processor
to the DSP. Data can be exchanged between the host processor and the DSP throughout the entire on-chip
memory via the DMA controller. The extended program memory pages are also accessible by both the host
and the DSP. The DSP and the host control the HPI8 activity through the HPI8 control register (HPIC). The
host can address memory through the HPI8 address register (HPIA).
Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether
the high or low byte is being transmitted. Two pins (controlled by the host), HCNTL0 and HCNTL1, indicate
whether the byte being exchanged is the most significant or least significant byte. Control pins (HCNTL0 and
HCNTL1) determine whether the data is directed to the HPIA, the HPIC, or to memory. The DSP can interrupt
the host with a dedicated HINT pin that the host can acknowledge and clear.
The 5410 is the first device in the C5000™ DSP platform in which the HPI8 can address all on-chip memory,
including extended memory pages. Extended memory addresses are defined by a 23-bit address. The HPI8
sets the upper 6 bits of the extended memory address by writing a one to the XHPIA bit in HPIC, and then
writing address bits A[22:16] into HPIA. The lower 16 bits of the extended memory address are set by writing
a zero to XHPIA, followed by writing bits A[15:0] to HPIA. Similar to previous implementations of the HPI, after
a write is performed to XHPIA or HPIA, a memory prefetch is initiated. The XHPIA bit is accessible only to the
host. XHPIA is uninitialized following reset. The host should always initialize XHPIA prior to the first HPI8
access following a device reset.
The HPI8 interface has two data strobes (HDS1 and HDS2), a read/write strobe (HR/W), and an address
strobe (HAS), to enable a glueless interface to a variety of industry-standard host devices. The HPI8 is easily
interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe, and
a read/write strobe, or two separate strobes for read and write.
All memory accesses on the 5410 are in shared-access mode, meaning both the DSP and the host can access
memory. Asynchronous host accesses are resynchronized internally, and in the event that the CPU and the
host both request access to the same memory block, the host has access priority. The HRDY pin provides
handshaking to the host during memory access.
The HPI8 also provides the capability to access memory during reset and power-down states. During reset,
data or application code can be loaded via the HPI8, and the application can be initiated through the HPI option
of the bootloader. During IDLE2/3 states, the HPI8 and the other six DMA channels continue to operate, and
all pending DMA events complete before the DSP stops the clocks. The HPI8 has higher priority than the other
six DMA channels. The HPI8 continues to have access to memory in IDLE2/3 even after the DSP has stopped
the internal clocks as long as X2/CLKIN is maintained. The 5410 HPI8 also remains active during emulation
stop. The HPI8 can access any on-chip RAM on the device. The HPI8 memory map for the 5410 is shown
in Figure 2--8. The HPI8 determines memory location by address only (program or data space is not relevant).
C5000 is a trademark of Texas Instruments.
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Functional Overview
Address (Hex)
000 0000
Reserved
000 005F
000 0060
Scratch-Pad
RAM
000 007F
000 0080
000 1FFF
000 2000
DARAM
SARAM1
000 7FFF
000 8000
Reserved
001 7FFF
001 8000
SARAM2
001 FFFF
Figure 2--8. HPI8 Memory Map
2.2.5 Multichannel Buffered Serial Ports
The 5410 device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct
interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on
the standard serial-port interface found on other C54x™ devices. Like their predecessors, the McBSPs
provide:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSPs have the following capabilities:
•
•
•
•
•
•
Direct interface to:
--
T1/E1 framers
--
MVIP switching-compatible and ST-BUS compliant devices
--
IOM-2 compliant devices
--
AC97-compliant devices
--
IIS-compliant devices
--
Serial peripheral interface (SPI)
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits
μ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
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SPRS075E
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Functional Overview
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
•
•
•
•
•
•
•
BCLKX
BDX
BFSX
BCLKR
BDR
BFSR
BCLKS
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
Receive frame synchronization
External clock reference for the programmable clock generator
The first six pins listed are identical to the previous serial-port interface pins on the C5000™ platform of DSPs.
The BCLKS pin is an additional signal to provide a clock reference to the McBSP programmable clock
generator. As a compatibility option, the 5410 is provided in a 144-pin LQFP package (designated PGE) that
is pin-compatible with the C548/549 devices. BCLKS is not implemented on this package.
On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,
respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).
Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows
DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received
on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register
(RBR). If DRR is empty, the RBR contents are copied into DRR. If not, RBR holds the data until DRR is
available. This structure allows storage of the two previous words while the reception of the current word is
in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
In addition to the standard serial-port functions, the McBSP provides programmable clock and frame
synchronization generation. Among the programmable functions are:
•
•
•
•
•
•
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either μ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received
data is decoded to 2s complement format.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
the multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In
using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus
bandwidth, multichannel selection allows independent enabling of particular channels for transmission and
reception. Up to 32 channels in a bit stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP
is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or
as a slave.
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Functional Overview
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
2.2.6 Hardware Timer
The 5410 device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by
one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer
can be stopped, restarted, reset, or disabled by specific status bits. The counter is clocked directly by the CPU
clock instead of the CLKOUT signal, so that the timer period is not affected by the value of the CLKOUT
divide-down factor. The timer output signal (TOUT) is referenced to the CLKOUT signal, such that the TOUT
timings are dependent upon the state of the CLKOUT divide-down factor. The CLKOUT divide-down factor
is controlled through the DIVFCT field in the bank-switching control register (BSCR).
2.2.7 Clock Generator
The clock generator provides clocks to the 5410 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock
input is then divided by two (DIV mode) to generate clocks for the 5410 device, or the PLL circuit can be used
(PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,
allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,
once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5410
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5410 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note
that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state
of the CLKMD1 -- CLKMD3 pins. The CLKMD pin configured clock options are shown in Table 2--5.
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Functional Overview
Table 2--5. CLKMD Pin Configured Clock Options
†
CLKMD1
CLKMD2
CLKMD3
CLKMD REGISTER
RESET VALUE
0
0
0
0000h
Divide-by-2, with external source
0
0
1
1000h
Divide-by-2, with external source
0
1
0
2000h
Divide-by-2, with external source
0
1
1
--
1
0
0
4000h
Divide-by-2, internal oscillator enabled†
1
0
1
0007h
PLLx1 with external source
1
1
0
6000h
Divide-by-2, with external source
1
1
1
7000h
Reserved
CLOCK MODE
Stop mode
Note that although the CLKMD pins are only sampled during reset (reset pin low) to determine the PLL clock mode, these pins are directly
connected to the enable control of the on-chip oscillator. Accordingly, the state of the CLKMD pins should never be changed unless the reset
pin is low.
2.2.8 Enhanced External Parallel Interface (XIO2)
The 5410 external interface has been redesigned to include several improvements, including: simplification
of the bus sequence, more immunity to bus contention when transitioning between read and write operation,
the ability for external memory access to the DMA controller, and optimization of the power-down modes.
The bus sequence on the 5410 still maintains all of the same interface signals as on previous C54x™ devices,
but the signal sequence has been simplified. Most external accesses now require 3 cycles which consist of
a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
C54x™ devices is available.
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Functional Overview
Figure 2--9 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode,
or single memory reads in consecutive mode. The accesses shown in Figure 2--9 always require 3 CLKOUT
cycles to complete.
CLKOUT
A[22:0]
READ
D[15:0]
R/W
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 2--9. Nonconsecutive Memory Read and I/O Read Bus Sequence
October 1998 -- December 2000
SPRS075E
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Functional Overview
Figure 2--10 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown
in Figure 2--10 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads
performed.
CLKOUT
A[22:0]
READ
D[15:0]
READ
READ
R/W
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 2--10. Consecutive Memory Read Bus Sequence (n = 3 reads)
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SPRS075E
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Functional Overview
Figure 2--11 shows the bus sequence for all memory writes and I/O writes. The accesses shown in Figure 2--11
always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
WRITE
D[15:0]
R/W
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 2--11. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more
information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the C5000™ platform by
switching off the internal clocks to the interface when it is not being used. This power-saving feature is
automatic, requires no software setup, and causes no latency in the operation of the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching
cycles when crossing 32K memory boundaries (see Section 2.2.2, “Programmable Bank-Switching”), the
ability to program up to 14 wait states through software (see Section 2.2.1 “Software-Programmable
Wait-State Generator”), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing down
CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral
devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow
down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides
a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled
through the DIVFCT field in the bank-switching control register (BSCR).
2.2.9 DMA Controller
The 5410 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA allows movements of data to and from internal program/data memory,
internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
October 1998 -- December 2000
SPRS075E
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Functional Overview
2.2.9.1
DMA Features
The DMA has the following features:
•
•
•
•
•
•
•
•
2.2.9.2
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channels source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
be post-decremented, or be adjusted by a programmable value.
Each read or write transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
DMA Memory Map
The DMA memory map, shown in Figure 2--12, allows the DMA transfer to be unaffected by the status of the
MP/MC, DROM, and OVLY bits.
26
SPRS075E
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Functional Overview
Program
Program
Hex
0000
Reserved
007F
0080
Program
Hex
xx0000
Hex
010000
Hex
0000
001F
0020
0021
0022
0023
0024
002F
0030
0031
0032
External
External
External
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003F
0040
0041
0042
0043
0044
0049
004A
004B
004C
005F
0060
BFFF
C000
017FFF
018000
007F
0080
xxFFFF
01FFFF
Page 0
DRR20
DRR10
DXR20
DXR10
Reserved
DRR22
DRR12
DXR22
DXR12
Reserved
RCERA2
XCERA2
Reserved
RCERA0
XCERA0
Reserved
DRR21
DRR11
DXR21
DXR11
Reserved
RCERA1
XCERA1
Reserved
Scratch-Pad
RAM
DARAM
SARAM1
7FFF
8000
FFFF
Reserved
1FFF
2000
SARAM2
On-Chip ROM
Data
Page 1
External
FFFF
Page 2,3,...
Figure 2--12. DMA Memory Map
2.2.9.3
DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
2.2.9.4
DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
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Functional Overview
2.2.9.5
DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
•
•
2.2.9.6
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
•
2.2.9.7
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded
with the DMA global count reload register (DMGCR).
DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
2.2.9.8
DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA mode
control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index DMFRI0
and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer
is the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined
by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
•
28
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfers.
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Functional Overview
2.2.9.9
DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 2--6.
Table 2--6. DMA Interrupts
DINM
IMOD
ABU (non-decrement)
MODE
1
0
At full buffer only
ABU (non-decrement)
1
1
At half buffer and full buffer
Multi-Frame
1
0
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multi-Frame
1
1
At end of frame and end of block (DMCTRn = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
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INTERRUPT
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Functional Overview
2.3
Memory-Mapped Registers
The 5410 has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to
1Fh. Each 5410 device also has a set of memory-mapped registers associated with peripherals. Table 2--7
gives a list of CPU memory-mapped registers (MMRs) available on 5410. Table 2--8 shows additional
peripheral MMRs associated with the 5410.
Table 2--7. CPU Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
DEC
HEX
IMR
0
0
Interrupt mask register
IFR
1
1
Interrupt flag register
2--5
2--5
Reserved for testing
ST0
6
6
Status register 0
ST1
7
7
Status register 1
AL
8
8
Accumulator A low word (15--0)
AH
9
9
Accumulator A high word (31--16)
AG
10
A
Accumulator A guard bits (39--32)
—
BL
11
B
Accumulator B low word (15--0)
BH
12
C
Accumulator B high word (31--16)
BG
13
D
Accumulator B guard bits (39--32)
TREG
14
E
Temporary register
TRN
15
F
Transition register
AR0
16
10
Auxiliary register 0
AR1
17
11
Auxiliary register 1
AR2
18
12
Auxiliary register 2
AR3
19
13
Auxiliary register 3
AR4
20
14
Auxiliary register 4
AR5
21
15
Auxiliary register 5
AR6
22
16
Auxiliary register 6
AR7
23
17
Auxiliary register 7
SP
24
18
Stack pointer register
BK
25
19
Circular buffer size register
BRC
26
1A
Block repeat counter
RSA
27
1B
Block repeat start address
REA
28
1C
Block repeat end address
PMST
29
1D
Processor mode status (PMST) register
XPC
30
1E
Extended program page register
—
31
1F
Reserved
30
SPRS075E
October 1998 -- December 2000
Functional Overview
Table 2--8. Peripheral Memory-Mapped Registers
NAME
ADDRESS
SUB-ADDRESS
DRR20
20h
—
McBSP0 data receive register
McBSP #0
DRR10
21h
—
McBSP0 data receive register
McBSP #0
DXR20
22h
—
McBSP0 data transmit register
McBSP #0
DXR10
23h
—
McBSP0 data transmit register
McBSP #0
TIM
24h
—
Timer register
Timer
PRD
25h
—
Timer period counter
Timer
TCR
26h
—
Timer control register
Timer
—
27h
—
Reserved
SWWSR
28h
—
Software wait-state register
External Bus
BSCR
29h
—
Bank-switching control register
External Bus
—
2Ah
—
Reserved
SWCR
2Bh
—
Software wait-state control register
HPIC
DESCRIPTION
TYPE
External Bus
2Ch
—
HPI control register
2Dh--2Fh
—
Reserved
DRR22
30h
—
McBSP2 data receive register
McBSP #2
DRR12
31h
—
McBSP2 data receive register
McBSP #2
DXR22
32h
—
McBSP2 data transmit register
McBSP #2
DXR12
33h
—
McBSP2 data transmit register
McBSP #2
SPSA2
34h
—
McBSP2 sub-address register
McBSP #2
SPCR12
35h
00h
McBSP2 serial port control register 1
McBSP #2
SPCR22
35h
01h
McBSP2 serial port control register 2
McBSP #2
RCR12
35h
02h
McBSP2 receive control register 1
McBSP #2
RCR22
35h
03h
McBSP2 receive control register 2
McBSP #2
XCR12
35h
04h
McBSP2 transmit control register 1
McBSP #2
XCR22
35h
05h
McBSP2 transmit control register 2
McBSP #2
SRGR12
35h
06h
McBSP2 sample rate generator register 1
McBSP #2
SRGR22
35h
07h
McBSP2 sample rate generator register 2
McBSP #2
MCR12
35h
08h
McBSP2 multichannel register 1
McBSP #2
MCR22
35h
09h
McBSP2 multichannel register 2
McBSP #2
RCERA2
35h
0Ah
McBSP2 receive channel enable register partition A
McBSP #2
RCERB2
35h
0Bh
McBSP2 receive channel enable register partition B
McBSP #2
XCERA2
35h
0Ch
McBSP2 transmit channel enable register partition A
McBSP #2
XCERB2
35h
0Dh
McBSP2 transmit channel enable register partition B
McBSP #2
35h
0Eh
McBSP2 pin control register
McBSP #2
36h--37h
—
Reserved
—
PCR2
—
HPI
SPSA0
38h
—
McBSP0 sub-address register
McBSP #0
SPCR10
39h
00h
McBSP0 serial port control register 1
McBSP #0
SPCR20
39h
01h
McBSP0 serial port control register 2
McBSP #0
RCR10
39h
02h
McBSP0 receive control register 1
McBSP #0
RCR20
39h
03h
McBSP0 receive control register 2
McBSP #0
XCR10
39h
04h
McBSP0 transmit control register 1
McBSP #0
†
Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h
update the sub-addressed register without modifying DMSBAR.
October 1998 -- December 2000
SPRS075E
31
Functional Overview
Table 2--8. Peripheral Memory-Mapped Registers (Continued)
NAME
ADDRESS
SUB-ADDRESS
XCR20
39h
05h
McBSP0 transmit control register 2
McBSP #0
SRGR10
39h
06h
McBSP0 sample rate generator register 1
McBSP #0
SRGR20
39h
07h
McBSP0 sample rate generator register 2
McBSP #0
MCR10
39h
08h
McBSP0 multichannel register 1
McBSP #0
MCR20
39h
09h
McBSP0 multichannel register 2
McBSP #0
RCERA0
39h
0Ah
McBSP0 receive channel enable register partition A
McBSP #0
RCERB0
39h
0Bh
McBSP0 receive channel enable register partition B
McBSP #0
XCERA0
39h
0Ch
McBSP0 transmit channel enable register partition A
McBSP #0
XCERB0
39h
0Dh
McBSP0 transmit channel enable register partition B
McBSP #0
PCR0
39h
0Eh
McBSP0 pin control register
McBSP #0
—
DESCRIPTION
TYPE
3Ah--3Fh
—
Reserved
DRR21
40h
—
McBSP1 Data receive register 2
McBSP #1
DRR11
41h
—
McBSP1 Data receive register 1
McBSP #1
DXR21
42h
—
McBSP1 Data transmit register 2
McBSP #1
McBSP #1
DXR11
43h
—
McBSP1 Data transmit register 1
44h--47h
—
Reserved
SPSA1
48h
—
McBSP1 sub-address register
McBSP #1
SPCR11
49h
00h
McBSP1 serial port control register 1
McBSP #1
SPCR21
49h
01h
McBSP1 serial port control register 2
McBSP #1
RCR11
49h
02h
McBSP1 receive control register 1
McBSP #1
RCR21
49h
03h
McBSP1 receive control register 2
McBSP #1
XCR11
49h
04h
McBSP1 transmit control register 1
McBSP #1
XCR21
49h
05h
McBSP1 transmit control register 2
McBSP #1
SRGR11
49h
06h
McBSP1 sample rate generator register 1
McBSP #1
SRGR21
49h
07h
McBSP1 sample rate generator register 2
McBSP #1
MCR11
49h
08h
McBSP1 multichannel register 1
McBSP #1
MCR21
49h
09h
McBSP1 multichannel register 2
McBSP #1
RCERA1
49h
0Ah
McBSP1 receive channel enable register partition A
McBSP #1
RCERB1
49h
0Bh
McBSP1 receive channel enable register partition B
McBSP #1
XCERA1
49h
0Ch
McBSP1 transmit channel enable register partition A
McBSP #1
XCERB1
49h
0Dh
McBSP1 transmit channel enable register partition B
McBSP #1
McBSP1 pin control register
McBSP #1
—
PCR1
49h
0Eh
4Ah--53h
—
Reserved
DMPREC
54h
—
DMA channel priority and enable control register
DMA
DMSBAR
55h
—
DMA channel sub-address register
DMA
DMSRC0
56h/57h†
00h
DMA channel 0 source address register
DMA
DMDST0
56h/57h†
01h
DMA channel 0 destination address register
DMA
DMCTR0
56h/57h†
02h
DMA channel 0 element count register
DMA
DMSFC0
56h/57h†
03h
DMA channel 0 sync select and frame count register
DMA
DMMCR0
56h/57h†
04h
DMA channel 0 transfer mode control register
DMA
DMSRC1
56h/57h†
05h
DMA channel 1 source address register
DMA
—
†
32
Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h
update the sub-addressed register without modifying DMSBAR.
SPRS075E
October 1998 -- December 2000
Functional Overview
Table 2--8. Peripheral Memory-Mapped Registers (Continued)
NAME
ADDRESS
SUB-ADDRESS
DMDST1
56h/57h†
06h
DMA channel 1 destination address register
DMA
DMCTR1
56h/57h†
07h
DMA channel 1 element count register
DMA
DMSFC1
56h/57h†
08h
DMA channel 1 sync select and frame count register
DMA
DMMCR1
56h/57h†
09h
DMA channel 1 transfer mode control register
DMA
DMSRC2
56h/57h†
0Ah
DMA channel 2 source address register
DMA
DMDST2
56h/57h†
0Bh
DMA channel 2 destination address register
DMA
DMCTR2
56h/57h†
0Ch
DMA channel 2 element count register
DMA
DMSFC2
56h/57h†
0Dh
DMA channel 2 sync select and frame count register
DMA
DMMCR2
56h/57h†
0Eh
DMA channel 2 transfer mode control register
DMA
DMSRC3
56h/57h†
0Fh
DMA channel 3 source address register
DMA
DMDST3
56h/57h†
10h
DMA channel 3 destination address register
DMA
DMCTR3
56h/57h†
11h
DMA channel 3 element count register
DMA
DMSFC3
56h/57h†
12h
DMA channel 3 sync select and frame count register
DMA
DMMCR3
56h/57h†
13h
DMA channel 3 transfer mode control register
DMA
DMSRC4
56h/57h†
14h
DMA channel 4 source address register
DMA
DMDST4
56h/57h†
15h
DMA channel 4 destination address register
DMA
DMCTR4
56h/57h†
16h
DMA channel 4 element count register
DMA
DMSFC4
56h/57h†
17h
DMA channel 4 sync select and frame count register
DMA
DMMCR4
56h/57h†
18h
DMA channel 4 transfer mode control register
DMA
DMSRC5
56h/57h†
19h
DMA channel 5 source address register
DMA
DMDST5
56h/57h†
1Ah
DMA channel 5 destination address register
DMA
DMCTR5
56h/57h†
1Bh
DMA channel 5 element count register
DMA
DMSFC5
56h/57h†
1Ch
DMA channel 5 sync select and frame count register
DMA
DMMCR5
56h/57h†
1Dh
DMA channel 5 transfer mode control register
DMA
DMSRCP
56h/57h†
1Eh
DMA source program page address (common
channel)
DMA
DMDSTP
56h/57h†
1Fh
DMA destination program page address (common
channel)
DMA
DMIDX0
56h/57h†
20h
DMA element index address register 0
DMA
DMIDX1
56h/57h†
21h
DMA element index address register 1
DMA
DMFRI0
56h/57h†
22h
DMA frame index register 0
DMA
DMFRI1
56h/57h†
23h
DMA frame index register 1
DMA
DMGSA
56h/57h†
24h
DMA global source address reload register
DMA
DMGDA
56h/57h†
25h
DMA global destination address reload register
DMA
DMGCR
56h/57h†
26h
DMA global count reload register
DMA
DMGFR
56h/57h†
27h
DMA global frame count reload register
DMA
CLKMD
58h
—
Clock mode register
PLL
59h -- 5Fh
—
Reserved
—
†
DESCRIPTION
TYPE
Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h
update the sub-addressed register without modifying DMSBAR.
October 1998 -- December 2000
SPRS075E
33
Functional Overview
2.4
Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 2--9.
Table 2--9. Interrupt Locations and Priorities
LOCATION
DECIMAL
HEX
NAME
PRIORITY
FUNCTION
RS, SINTR
0
00
1
Reset (hardware and software reset)
NMI, SINT16
4
04
2
Nonmaskable interrupt
SINT17
8
08
—
Software interrupt #17
SINT18
12
0C
—
Software interrupt #18
SINT19
16
10
—
Software interrupt #19
SINT20
20
14
—
Software interrupt #20
SINT21
24
18
—
Software interrupt #21
SINT22
28
1C
—
Software interrupt #22
SINT23
32
20
—
Software interrupt #23
SINT24
36
24
—
Software interrupt #24
SINT25
40
28
—
Software interrupt #25
SINT26
44
2C
—
Software interrupt #26
SINT27
48
30
—
Software interrupt #27
SINT28
52
34
—
Software interrupt #28
SINT29
56
38
—
Software interrupt #29
SINT30
60
3C
—
Software interrupt #30
INT0, SINT0
64
40
3
External user interrupt #0
INT1, SINT1
68
44
4
External user interrupt #1
INT2, SINT2
72
48
5
External user interrupt #2
TINT, SINT3
76
4C
6
Timer interrupt
RINT0, SINT4
80
50
7
McBSP #0 receive interrupt (default)
XINT0, SINT5
84
54
8
McBSP #0 transmit interrupt (default)
RINT2, SINT6
88
58
9
McBSP #2 receive interrupt (default)
XINT2, SINT7
92
5C
10
McBSP #2 transmit interrupt (default)
INT3, SINT8
96
60
11
External user interrupt #3
HINT, SINT9
100
64
12
HPI interrupt
RINT1, SINT10
104
68
13
McBSP #1 receive interrupt (default)
XINT1, SINT11
108
6C
14
McBSP #1 transmit interrupt (default)
DMAC4,SINT12
112
70
15
DMA channel 4 (default)
DMAC5,SINT13
116
74
16
DMA channel 5 (default)
120--127
78--7F
—
Reserved
Reserved
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 2--13.
15--14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
DMAC5
DMAC4
XINT1
RINT1
HINT
INT3
XINT2
RINT2
XINT0
RINT0
TINT
INT2
INT1
INT0
Figure 2--13. IFR and IMR
34
SPRS075E
October 1998 -- December 2000
Documentation Support
3
Documentation Support
Extensive documentation supports all TMS320™ family of DSPs from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000™ platform of DSPs:
•
•
•
•
•
TMS320C54x™ DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete users guides
Development support tools
Hardware and software application reports
The four-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
The reference set describes in detail the TMS320C54x™ DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320™ DSP devices.
For general background information on DSPs and Texas Instruments (TI) devices, see the three-volume
publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012,
SPRA016, and SPRA017).
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320™ DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320™ DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 is a trademark of Texas Instruments.
October 1998 -- December 2000
SPRS075E
35
Electrical Specifications
4
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5410 DSP.
4.1
Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. All supply voltage values (core and I/O) are with respect to
VSS. Figure 4--1 provides the test load circuit values for a 3.3-V device.
Supply voltage I/O range, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.6 V
Supply voltage core range, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 3.75 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.6 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.6 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
4.2
DVDD
Recommended Operating Conditions
Device supply voltage, I/O†
CVDD
Device supply voltage,
VSS
Supply voltage, GND
core†
High-level input voltage, I/O
MAX
3.3
3.6
UNIT
V
2.4
2.5
2.75
V
V
3
DVDD + 0.3
V
RS, INTn, NMI, X2/CLKIN,
BCLKR0, BCLKR1, BCLKR2,
BCLKX0, BCLKX1, BCLKX2,
BCLKS0, BCLKS1, BCLKS2,
HCS, HDS1, HDS2, HAS
CLKMDn, DVDD = 3.30.3 V
2.5
DVDD + 0.3
V
HD[7:0]
2.2
DVDD + 0.3
V
2
DVDD + 0.3
V
All other inputs
†
NOM
3
0
TCK, DVDD = 3.30.3 V
VIH
MIN
VIL
Low-level input voltage
--0.3
IOH
High-level output current
--300
μA
IOL
Low-level output current
1.5
mA
TC
Operating case temperature
100
°C
--40
0.8
V
Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System-level concerns such as bus contention
may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior to the I/O
buffers and then powered down after the I/O buffers.
36
SPRS075E
October 1998 -- December 2000
Electrical Specifications
4.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
High-level output
voltage‡
DVDD = 3.30.3 V, IOH = MAX
VOL
Low-level output
voltage‡
IOL = MAX
IIZ
Input current in high
impedance
VOH
II
Input current
(VI = VSS to VDD)
MIN
‡
§
¶
#
||
MAX
2.4
0.4
V
--175
175
175
μA
DVDD = MAX
MAX, VO = VSS to DVDD
TRST
With internal pulldown
--10
800
HPIENA
With internal pulldown, RS = 0
--10
400
TMS, TCK, TDI,
BCLKS0, BCLKS1,
BCLKS2, HPI§
With internal pullups
--400
10
D[15:0], HD[7:0]
Bus holders enabled, DVDD = MAX,
VI = DVSS to DVDD
--175
175
--10
10
IDDC
Supply current, core CPU
CVDD = 2.5 V, 100 MHz CPU clock,¶
TC = 25°C
IDDP
Supply current, pins
DVDD = 3.3 V, 100 MHz CPU clock,
TC = 25°C
IDD
Supply current,
current
standby
Ci
Co
UNIT
V
A[22:0]
All other input-only pins
†
TYP†
μA
47#
mA
22||
mA
IDLE2
PLL × 2 mode, 50 MHz input, TC = 25°C
2
mA
IDLE3
Divide-by-two mode, CLKIN stopped,
TC = 25°C
5
μA
Input capacitance
10
pF
Output capacitance
10
pF
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0--INT3, NMI, X2/CLKIN, CLKMD0--CLKMD3 are LVTTL-compatible.
All HPI input signals except for HPIENA.
Clock mode: PLL × 2 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
This value was obtained with continuous external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
IOL
50 Ω
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where:
IOL
IOH
= 1.5 mA (all outputs)
= 300 μA (all outputs)
VLoad
CT
= 1.5 V
= 40-pF typical load circuit capacitance
Figure 4--1. 3.3-V Test Load Circuit
October 1998 -- December 2000
SPRS075E
37
Electrical Specifications
4.4
Package Thermal Resistance Characteristics
Table 4--1 provides the thermal resistance characteristics for the recommended package types used on the
TMS320VC5410 DSP.
Table 4--1. Thermal Resistance Characteristics
4.5
PARAMETER
GGW
PACKAGE
PGE
PACKAGE
UNIT
RΘJA
38
56
°C/W
RΘJC
5
5
°C/W
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
38
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or dont care level
SPRS075E
October 1998 -- December 2000
Electrical Specifications
4.6
Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in Section 2.2.7 “Clock
Generator”.
4.6.1 Internal Oscillator with External Crystal
The internal oscillator on the 5410 is enabled by setting the CLKMD[1,2,3] pins to (1,0,0) at reset and
connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock frequency is one-half the
crystals oscillation frequency following reset. Since the internal oscillator can be used as a clock source to the
PLL, the crystal oscillation frequency can be multiplied to generate the CPU clock if desired.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30 Ω and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 4--2. The load capacitors, C1 and C2, should be chosen such that the
equation below is satisfied. CL in the equation is the load specified for the crystal.
CL =
C 1C 2
(C 1 + C 2)
MIN
fx
0†
Input clock frequency
MAX
UNIT
50‡
MHz
†
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
X1
X2/CLKIN
Crystal
C1
C2
Figure 4--2. Internal Divide-by-Two Clock Option With External Crystal
October 1998 -- December 2000
SPRS075E
39
Electrical Specifications
4.6.2 Divide-By-Two Clock Option - PLL Disabled
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 2--5 shows the configuration options for the CLKMD pins that generate the external divide-by-2 clock
option. This external input clock frequency is divided by two to generate the CPU machine cycle.
The external frequency injected must conform to specifications listed in the timing requirements table.
Table 4--2 and Table 4--3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--3).
Table 4--2. Divide-By-2 Option Timing Requirements
MAX
20
†
ns
Fall time, X2/CLKIN
4
ns
Rise time, X2/CLKIN
4
ns
2
†
ns
2
†
ns
Cycle time, X2/CLKIN
tf(CI)
tr(CI)
tw(CIL)
Pulse duration, X2/CLKIN low
tw(CIH)
†
MIN
tc(CI)
Pulse duration, X2/CLKIN high
UNIT
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Table 4--3. Divide-By-2 Option Switching Characteristics
PARAMETER
MIN
TYP
40‡
2tc(CI)
3
6
MAX
UNIT
†
ns
10
ns
tc(CO)
Cycle time, CLKOUT
td(CIH-CO)
Delay time, X2/CLKIN high to CLKOUT high/low
tf(CO)
Fall time, CLKOUT
2
ns
tr(CO)
Rise time, CLKOUT
2
ns
tw(COL)
Pulse duration, CLKOUT low
H--2
H--1
H
ns
tw(COH)
Pulse duration, CLKOUT high
H--2
H--1
H
ns
†
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
‡ It is recommended that the PLL clocking option be used for maximum frequency operation.
tw(CIH)
tw(CIL)
tc(CI)
tr(CI)
tf(CI)
X2/CLKIN
tc(CO)
td(CIH-CO)
tw(COH)
tf(CO)
tr(CO)
tw(COL)
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 4--3. External Divide-by-Two Clock Timing
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4.6.3 Multiply-By-N Clock Option - PLL Enabled
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 2--5 shows the configuration options for the CLKMD pins that generate the external divide-by-2 clock
option. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to
the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for
detailed information on programming the PLL. The external input clock frequency is multiplied by the
multiplication factor N to generate the internal CPU machine cycle.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table.
Table 4--4 and Table 4--5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--4).
Table 4--4. Multiply-By-N Clock Option Timing Requirements
MIN
MAX
20‡
200
PLL multiplier N = x.5†
20‡
100
PLL multiplier N = x.25, x.75†
20‡
50
Integer PLL multiplier N (N =
tc(CI)
Cycle time, X2/CLKIN
1--15)†
UNIT
ns
tf(CI)
Fall time, X2/CLKIN
4
ns
tr(CI)
Rise time, X2/CLKIN
tw(CIL)
Pulse duration, X2/CLKIN low
2
4
ns
ns
tw(CIH)
Pulse duration, X2/CLKIN high
2
ns
†
N is the multiplication factor.
‡ Note that for all values of t
c(CI), the minimum tc(CO) period must not be exceeded.
Table 4--5. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
†
MIN
TYP
10
tc(CI)/N†
3
6
MAX
UNIT
tc(CO)
Cycle time, CLKOUT
ns
td(CI-CO)
Delay time, X2/CLKIN high/low to CLKOUT high/low
tf(CO)
Fall time, CLKOUT
tr(CO)
Rise time, CLKOUT
tw(COL)
Pulse duration, CLKOUT low
H--2
H--1
H
ns
tw(COH)
Pulse duration, CLKOUT high
H--2
H--1
H
ns
tp
Transitory phase, PLL lock-up time
35
ms
10
2
ns
ns
2
ns
N is the multiplication factor.
tw(CIH)
tc(CI)
tw(CIL)
tf(CI)
tr(CI)
X2/CLKIN
td(CI-CO)
tc(CO)
tp
CLKOUT
tw(COH)
tf(CO)
tw(COL)
tr(CO)
Unstable
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 4--4. External Multiply-by-One Clock Timing
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4.7
Memory and Parallel I/O Interface Timing
4.7.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 4--6 and Table 4--7 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5tc(CO) (see Figure 4--5 and Figure 4--6).
Table 4--6. Memory Read Timing Requirements
MIN
†
access†
MAX
UNIT
4H--10
ns
2H--10
ns
ta(A)M1
Access time, read data access from address valid, first read
ta(A)M2
Access time, read data access from address valid, consecutive read accesses†
tsu(D)R
Setup time, read data valid before CLKOUT low
6
ns
th(D)R
Hold time, read data valid after CLKOUT low
0
ns
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 4--7. Memory Read Switching Characteristics
MIN
MAX
td(CLKL-A)
Delay time, CLKOUT low to address valid†
-- 1
4
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
-- 1
4
ns
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
-- 1
4
ns
PARAMETER
†
UNIT
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
CLKOUT
td(CLKL-A)
A[22:0]
td(CLKL-MSL)
td(CLKL-MSH)
ta(A)M1
D[15:0]
tsu(D)R
th(D)R
MSTRB
R/W
PS/DS
Figure 4--5. Nonconsecutive Mode Memory Reads
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Electrical Specifications
CLKOUT
td(CLKL-A)
td(CLKL-MSL)
td(CLKL-MSH)
A[22:0]
ta(A)M1
ta(A)M2
D[15:0]
tsu(D)R
tsu(D)R
th(D)R
th(D)R
MSTRB
R/W
PS/DS
Figure 4--6. Consecutive Mode Memory Reads
4.7.2 Memory Write
Table 4--8 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see
Figure 4--7).
Table 4--8. Memory Write Switching Characteristics
PARAMETER
td(CLKL-A)
†
Delay time, CLKOUT low to address valid†
tsu(A)MSL
Setup time, address valid before MSTRB
td(CLKL-D)W
Delay time, CLKOUT low to data valid
tsu(D)MSH
low†
MIN
MAX
-- 1
4
2H -- 5
UNIT
ns
ns
0
5
ns
Setup time, data valid before MSTRB high
2H -- 5
2H + 5
ns
th(D)MSH
Hold time, data valid after MSTRB high
2H -- 5
2H + 5
ns
td(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
-- 1
4
ns
tw(SL)MS
Pulse duration, MSTRB low
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
2H -- 5
-- 1
ns
4
ns
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
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Electrical Specifications
CLKOUT
td(CLKL-A)
td(CLKL-D)W
tsu(A)MSL
A[22:0]
tsu(D)MSH
th(D)MSH
D[15:0]
td(CLKL-MSL)
td(CLKL-MSH)
tw(SL)MS
MSTRB
R/W
PS/DS
Figure 4--7. Memory Write (MSTRB = 0)
4.7.3 I/O Read
Table 4--9 and Table 4--10 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5tc(CO) (see Figure 4--8).
Table 4--9. I/O Read Timing Requirements
MIN
†
MAX
UNIT
ta(A)M1
Access time, read data access from address valid, first read access†
tsu(D)R
Setup time, read data valid before CLKOUT low
6
ns
th(D)R
Hold time, read data valid after CLKOUT low
0
ns
4H--10
ns
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Table 4--10. I/O Read Switching Characteristics
†
PARAMETER
MIN
MAX
td(CLKL-A)
Delay time, CLKOUT low to address valid†
-- 1
4
ns
td(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
-- 1
4
ns
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
-- 1
4
ns
UNIT
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
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Electrical Specifications
CLKOUT
td(CLKL-A)
td(CLKL-IOSL)
td(CLKL-IOSH)
A[22:0]
ta(A)M1
tsu(D)R
th(D)R
D[15:0]
IOSTRB
R/W
IS
Figure 4--8. Parallel I/O Port Read (IOSTRB = 0)
4.7.4 I/O Write
Table 4--11 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see
Figure 4--9).
Table 4--11. I/O Write Switching Characteristics
PARAMETER
td(CLKL-A)
†
Delay time, CLKOUT low to address valid†
low†
tsu(A)IOSL
Setup time, address valid before IOSTRB
td(CLKL-D)W
Delay time, CLKOUT low to write data valid
tsu(D)IOSH
th(D)IOSH
td(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
tw(SL)IOS
Pulse duration, IOSTRB low
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
MIN
MAX
-- 1
4
2H -- 5
UNIT
ns
ns
0
5
ns
Setup time, data valid before IOSTRB high
2H -- 5
2H + 5
ns
Hold time, data valid after IOSTRB high
2H -- 5
2H + 5
ns
-- 1
4
ns
2H -- 5
-- 1
ns
4
ns
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
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Electrical Specifications
CLKOUT
td(CLKL-A)
A[22:0]
td(CLKL-D)W
td(CLKL-D)W
tsu(A)IOSL
D[15:0]
tsu(D)IOSH
th(D)IOSH
IOSTRB
R/W
IS
Figure 4--9. Parallel I/O Port Write (IOSTRB = 0)
4.8
Ready Timing for Externally Generated Wait States
Table 4--12 and Table 4--13 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--10, Figure 4--11, Figure 4--12, and Figure 4--13).
Table 4--12. Ready Timing Requirements for Externally Generated Wait States†
MIN
MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
5
ns
th(RDY)
Hold time, READY after CLKOUT low
0
ns
low‡
tv(RDY)MSTRB
Valid time, READY after MSTRB
th(RDY)MSTRB
Hold time, READY after MSTRB low‡
4H--8
4H
low‡
tv(RDY)IOSTRB
Valid time, READY after IOSTRB
th(RDY)IOSTRB
Hold time, READY after IOSTRB low‡
ns
ns
4H--8
4H
ns
ns
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 4--13. Ready Switching Characteristics for Externally Generated Wait States†‡
MIN
MAX
td(MSCL)
Delay time, CLKOUT low to MSC low
-- 1
4
ns
td(MSCH)
Delay time, CLKOUT low to MSC high
-- 1
4
ns
PARAMETER
UNIT
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
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Electrical Specifications
CLKOUT
A[22:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 4--10. Memory Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
th(RDY)
tsu(RDY)
READY
tv(RDY)MSTRB
th(RDY)MSTRB
MSTRB
td(MSCL)
td(MSCH)
MSC
Wait States
Generated Internally
Wait State Generated
by READY
Figure 4--11. Memory Write With Externally Generated Wait States
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Electrical Specifications
CLKOUT
A[22:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 4--12. I/O Read With Externally Generated Wait States
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Electrical Specifications
CLKOUT
A[22:0]
D[15:0]
tsu(RDY)
th(RDY)
READY
tv(RDY)IOSTRB
th(RDY)IOSTRB
IOSTRB
td(MSCL)
td(MSCH)
MSC
Leading
Cycle
Wait
States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 4--13. I/O Write With Externally Generated Wait States
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Electrical Specifications
4.9
HOLD and HOLDA Timings
Table 4--14 and Table 4--15 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--14).
Table 4--14. HOLD and HOLDA Timing Requirements
MAX
tw(HOLD)
Pulse duration, HOLD low duration
tsu(HOLD)
Setup time, HOLD before CLKOUT low
MIN
UNIT
4H+10
ns
9
ns
Table 4--15. HOLD and HOLDA Switching Characteristics
MAX
UNIT
tdis(CLKL-A)
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
MIN
5
ns
tdis(CLKL-RW)
Disable time, R/W high impedance from CLKOUT low
5
ns
tdis(CLKL-S)
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
5
ns
ten(CLKL-A)
Enable time, Address, PS, DS, IS valid from CLKOUT low
2H+5
ns
ten(CLKL-RW)
Enable time, R/W enabled from CLKOUT low
2H+5
ns
ten(CLKL-S)
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2H+5
ns
-- 1
4
ns
-- 1
4
ns
PARAMETER
Valid time, HOLDA low after CLKOUT low
tv(HOLDA)
Valid time, HOLDA high after CLKOUT low
tw(HOLDA)
Pulse duration, HOLDA low duration
2H--3
ns
CLKOUT
tsu(HOLD)
HOLD
tsu(HOLD)
tw(HOLD)
tv(HOLDA)
HOLDA
tv(HOLDA)
tw(HOLDA)
tdis(CLKL--A)
ten(CLKL--A)
tdis(CLKL--RW)
ten(CLKL--RW)
tdis(CLKL--S)
ten(CLKL--S)
tdis(CLKL--S)
ten(CLKL--S)
A[22:0]
PS, DS, IS
D[15:0]
R/W
MSTRB
IOSTRB
Figure 4--14. HOLD and HOLDA Timings (HM = 1)
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Electrical Specifications
4.10 Reset, BIO, Interrupt, and MP/MC Timings
Table 4--16 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 4--15,
Figure 4--16, and Figure 4--17).
Table 4--16. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
MAX
UNIT
th(RS)
Hold time, RS after CLKOUT low
0
ns
th(BIO)
Hold time, BIO after CLKOUT low
0
ns
th(INT)
Hold time, INTn, NMI, after CLKOUT low†
0
ns
th(MPMC)
Hold time, MP/MC after CLKOUT low
0
ns
low‡§
tw(RSL)
Pulse duration, RS
4H+5
ns
tw(BIO)S
Pulse duration, BIO low, synchronous
2H+5
ns
tw(BIO)A
Pulse duration, BIO low, asynchronous
4H
ns
tw(INTH)S
Pulse duration, INTn, NMI high (synchronous)
2H+7
ns
tw(INTH)A
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
tw(INTL)S
Pulse duration, INTn, NMI low (synchronous)
2H+7
ns
tw(INTL)A
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
tw(INTL)WKP
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
8
ns
low¶
tsu(RS)
Setup time, RS before X2/CLKIN
tsu(BIO)
Setup time, BIO before CLKOUT low
5
8
12
ns
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
9
13
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
8
ns
†
The external interrupts (INT0--INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1--0--0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 μs to ensure synchronization
and lock-in of the PLL.
§ Note that RS may cause a change in clock frequency, therefore changing the value of H.
¶ The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
X2/CLKIN
tsu(RS)
tw(RSL)
RS, INTn, NMI
tsu(INT)
th(RS)
CLKOUT
tsu(BIO)
th(BIO)
BIO
tw(BIO)S
Figure 4--15. Reset and BIO Timings
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Electrical Specifications
CLKOUT
tsu(INT)
tsu(INT)
th(INT)
INTn, NMI
tw(INTH)A
tw(INTL)A
Figure 4--16. Interrupt Timing
CLKOUT
RS
th(MPMC)
tsu(MPMC)
MP/MC
Figure 4--17. MP/MC Timing
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Electrical Specifications
4.11 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 4--17 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 4--18).
Table 4--17. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(CLKL-IAQL)
Delay time, CLKOUT low to IAQ low
-- 1
4
ns
td(CLKL-IAQH)
Delay time, CLKOUT low to IAQ high
-- 1
4
ns
td(A)IAQ
Delay time, IAQ low to address valid
3
ns
td(CLKL-IACKL)
Delay time, CLKOUT low to IACK low
-- 1
4
ns
td(CLKL-IACKH)
Delay time, CLKOUT low to IACK high
-- 1
4
ns
td(A)IACK
Delay time, IACK low to address valid
3
ns
th(A)IAQ
Hold time, address valid after IAQ high
-- 3
ns
th(A)IACK
Hold time, address valid after IACK high
-- 3
ns
tw(IAQL)
Pulse duration, IAQ low
2H--3
ns
tw(IACKL)
Pulse duration, IACK low
2H--3
ns
CLKOUT
A[22:0]
td(CLKL--IAQH)
td(CLKL--IAQL)
th(A)IAQ
td(A)IAQ
tw(IAQL)
IAQ
td(CLKL--IACKH)
td(CLKL--IACKL)
th(A)IACK
td(A)IACK
IACK
tw(IACKL)
Figure 4--18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
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Electrical Specifications
4.12 External Flag (XF) and TOUT Timings
Table 4--18 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 4--19 and
Figure 4--20).
Table 4--18. External Flag (XF) and TOUT Switching Characteristics
MIN
MAX
Delay time, CLKOUT low to XF high
--1
4
Delay time, CLKOUT low to XF low
--1
4
td(TOUTH)
Delay time, CLKOUT low to TOUT high
--1
4
ns
td(TOUTL)
Delay time, CLKOUT low to TOUT low
--1
4
ns
tw(TOUT)
Pulse duration, TOUT
PARAMETER
td(XF)
2H--10
UNIT
ns
ns
CLKOUT
td(XF)
XF
Figure 4--19. External Flag (XF) Timing
CLKOUT
td(TOUTH)
td(TOUTL)
TOUT
tw(TOUT)
Figure 4--20. TOUT Timing
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Electrical Specifications
4.13 Multichannel Buffered Serial Port Timing
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
4.13.1
McBSP Transmit and Receive Timings
Table 4--19 and Table 4--20 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--21 and Figure 4--22).
Table 4--19. McBSP Transmit and Receive Timing Requirements†
MIN
tc(BCKS)
Cycle time, BCLKS‡
low‡
MAX
UNIT
4H
ns
tw(BCKS)
Pulse duration, BCLKS high or BCLKS
2H--1
ns
tc(BCKRX)
Cycle time, BCLKR, and BCLKX
BCLKR/X ext
4H
ns
tw(BCKRX)
Pulse duration, BCLKR, and BCLKX high or BCLKR, and BCLKX, low
BCLKR/X ext
2H--1
ns
BCLKR int
13
BCLKR ext
4
BCLKR int
0
BCLKR ext
4
BCLKR int
13
BCLKR ext
3
BCLKR int
0
BCLKR ext
5
tsu(BFRH-BCKRL)
Setup time,
time external BFSR high before BCLKR low
th(BCKRL-BFRH)
Hold time,
time external BFSR high after BCLKR low
tsu(BDRV-BCKRL)
Setup time
time, BDR valid before BCLKR low
th(BCKRL-BDRV)
Hold time
time, BDR valid after BCLKR low
tsu(BFXH-BCKXL)
Setup time,
time external BFSX high before BCLKX low
th(BCKXL-BFXH)
Hold time,
time external BFSX high after BCLKX low
tr(BCKRX)
Rise time, BCLKR/X
BCLKR/X ext
8
ns
tf(BCKRX)
Fall time, BCLKR/X
BCLKR/X ext
8
ns
tr(BCKS)
Rise time, BCLKS‡
8
ns
8
ns
tf(BCKS)
Fall time,
BCLKS‡
BCLKX int
13
BCLKX ext
5
BCLKX int
0
BCLKX ext
4
ns
ns
ns
ns
ns
ns
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ The BCLKS pin is not available on all packages. See Section 1.3, “Pin Assignments”, for availability of this pin.
October 1998 -- December 2000
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55
Electrical Specifications
Table 4--20. McBSP Transmit and Receive Switching Characteristics†
PARAMETER
MIN
MAX
1
8
UNIT
td(BCKSH--BCKRXH)
Delay time, BCLKS high to BCLKR/X high for internal BCLKR/X generated from
BCLKS input¶
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X int
4H
tw(BCKRXH)
Pulse duration, BCLKR/X high
BCLKR/X int
D -- 2‡
D‡
ns
BCLKR/X int
2‡
C‡
ns
-- 4
2
ns
ns
tw(BCKRXL)
td(BCKRH-BFRV)
Pulse duration, BCLKR/X low
Dela time
Delay
time, BCLKR high to internal BFSR valid
alid
BCLKR int
BCLKR ext
C --
ns
1
13
BCLKX int
-- 4
2
BCLKX ext
1
13
td(BCKXH-BFXV)
Dela time,
Delay
time BCLKX high to internal BFSX valid
alid
tdis(BCKXH-BDXHZ)
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
BCLKX int
-- 3
5
BCLKX ext
1
15
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
Does not apply to first bit transmitted when in data delay 1 (XDATDLY
= 01b) mode, or in data delay 2 (XDATDLY = 10b) mode.
BCLKX int
0§
6
BCLKX ext
3
15
Delay time, BFSX high to BDX valid
BFSX int
0§
8
ONLY applies to first bit transmitted when in data delay 0 (XDATDLY =
00b) mode
BFSX ext
0
10
td(BFXH-BDXV)
ns
ns
ns
ns
ns
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ Minimum delay times also represent minimum output hold times.
¶ The BCLKS pin is not available on all packages. See Section 1.3, “Pin Assignments”, for availability of this pin.
‡
56
SPRS075E
October 1998 -- December 2000
Electrical Specifications
tc(BCKS)
tw(BCKS)
tr(BCKS)
tw(BCKS)
BCLKS
td(BCKSH--BCKRXH)
tc(BCKRX)
tw(BCKRXH)
tf(BCKS)
tr(BCKRX)
tw(BCKRXL)
BCLKR
td(BCKRH--BFRV)
tf(BCKRX)
td(BCKRH--BFRV)
BFSR (int)
tsu(BFRH--BCKRL)
th(BCKRL--BFRH)
BFSR (ext)
th(BCKRL--BDRV)
tsu(BDRV--BCKRL)
BDR
(RDATDLY=00b)
Bit (n--1)
(n--2)
tsu(BDRV--BCKRL)
(n--3)
(n--4)
th(BCKRL--BDRV)
BDR
(RDATDLY=01b)
Bit (n--1)
(n--2)
tsu(BDRV--BCKRL)
(n--3)
th(BCKRL--BDRV)
BDR
(RDATDLY=10b)
Bit (n--1)
(n--2)
Figure 4--21. McBSP Receive Timings
tc(BCKS)
tw(BCKS)
tw(BCKS)
tr(BCKS)
tf(BCKS)
BCLKS
td(BCKSH--BCKRXH)
tw(BCKRXH)
tc(BCKRX)
tw(BCKRXL)
tr(BCKRX)
tf(BCKRX)
BCLKX
td(BCKXH--BFXV)
td(BCKXH--BFXV)
BFSX (int)
tsu(BFXH--BCKXL)
th(BCKXL--BFXH)
BFSX (ext)
td(BFXH--BDXV)
BDX
(XDATDLY=00b)
Bit 0
Bit (n--1)
td(BCKXH--BDXV)
(n--2)
(n--3)
(n--4)
td(BCKXH--BDXV)
BDX
(XDATDLY=01b)
Bit 0
Bit (n--1)
(n--3)
td(BCKXH--BDXV)
tdis(BCKXH--BDXHZ)
BDX
(XDATDLY=10b)
(n--2)
Bit 0
Bit (n--1)
(n--2)
Figure 4--22. McBSP Transmit Timings
October 1998 -- December 2000
SPRS075E
57
Electrical Specifications
4.13.2
McBSP General-Purpose I/O Timing
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
Table 4--21 and Table 4--22 assume testing over recommended operating conditions (see Figure 4--23).
Table 4--21. McBSP General-Purpose I/O Timing Requirements
MIN
†
MAX
UNIT
tsu(BGPIO-COH)
Setup time, BGPIOx input mode before CLKOUT high†
9
ns
th(COH-BGPIO)
Hold time, BGPIOx input mode after CLKOUT high†
0
ns
BGPIOx refers to BCLKSx, BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 4--22. McBSP General-Purpose I/O Switching Characteristics
PARAMETER
‡
MIN
MAX
0
5
Delay time, CLKOUT high to BGPIOx output mode‡
td(COH-BGPIO)
UNIT
ns
BGPIOx refers to BCLKSx, BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
tsu(BGPIO-COH)
td(COH-BGPIO)
CLKOUT
th(COH-BGPIO)
BGPIOx Input
Mode†
BGPIOx Output
Mode‡
†
‡
BGPIOx refers to BCLKSx, BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKSx, BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 4--23. McBSP General-Purpose I/O Timings
58
SPRS075E
October 1998 -- December 2000
Electrical Specifications
4.13.3
McBSP as SPI Master or Slave Timing
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
4.13.3.1 McBSP as SPI Master or Slave Timing When CLKSTP = 10b and CLKXP = 0)
Table 4--23 and Table 4--24 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--24).
Table 4--23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)†
MASTER
MIN
†
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
th(BCKXL-BDRV)
Hold time, BDR valid after BCLKX low
tsu(BFXL-BCKXH)
Setup time, BFSX low before BCLKX high
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
MAX
UNIT
12
7 -- 12H
ns
0
5 + 12H
ns
10
ns
12H
32H
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4--24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†
PARAMETER
MASTER‡
MIN
SLAVE
MAX
MIN
MAX
UNIT
th(BCKXL-BFXL)
Hold time, BFSX low after BCLKX low§
T -- 7
T+4
ns
td(BFXL-BCKXH)
Delay time, BFSX low to BCLKX high¶
C -- 7
C+5
ns
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
-- 3
4
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
C -- 2
C+3
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H+ 3
6H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H + 2
8H + 17
ns
6H + 4
10H + 15
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
October 1998 -- December 2000
SPRS075E
59
Electrical Specifications
LSB
tsu(BFXL-BCKXH)
BCLKX
th(BCKXL-BFXL)
tc(BCKX)
MSB
td(BFXL-BCKXH)
BFSX
tdis(BFXH-BDXHZ)
td(BFXL-BDXV)
tdis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
td(BCKXH-BDXV)
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 4--24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
4.13.3.2 McBSP as SPI Master or Slave Timing When CLKSTP = 11b and CLKXP = 0)
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
Table 4--25 and Table 4--26 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--25).
Table 4--25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†
MASTER
MIN
†
tsu(BDRV-BCKXH)
Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
tsu(BFXL-BCKXH)
Setup time, BFSX low before BCLKX high
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
MAX
UNIT
12
7 -- 12H
ns
0
5 + 12H
ns
10
ns
12H
32H
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4--26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†
MASTER‡
PARAMETER
SLAVE
MIN
MAX
MIN
MAX
UNIT
th(BCKXL-BFXL)
Hold time, BFSX low after BCLKX low§
C -- 7
C+4
td(BFXL-BCKXH)
Delay time, BFSX low to BCLKX
high¶
T --7
T+5
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
-- 3
4
6H + 4
10H + 15
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
--2
4
6H + 3
10H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
D -- 3
D+5
4H + 2
8H + 17
ns
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
60
SPRS075E
October 1998 -- December 2000
Electrical Specifications
LSB
BCLKX
tc(BCKX)
MSB
tsu(BFXL-BCKXH)
th(BCKXL-BFXL)
td(BFXL-BCKXH)
BFSX
BDX
td(BCKXL-BDXV)
td(BFXL-BDXV)
tdis(BCKXL-BDXHZ)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 4--25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
4.13.3.3 McBSP as SPI Master or Slave Timing When CLKSTP = 10b and CLKXP = 1)
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
Table 4--27 and Table 4--28 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--26).
Table 4--27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†
MASTER
MIN
†
tsu(BDRV-BCKXH)
Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV)
Hold time, BDR valid after BCLKX high
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
tc(BCKX)
Cycle time, BCLKX
SLAVE
MAX
MIN
MAX
UNIT
12
7 -- 12H
ns
0
5 + 12H
ns
10
ns
32H
ns
12H
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4--28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†
PARAMETER
MASTER‡
MIN
SLAVE
MAX
MIN
MAX
UNIT
th(BCKXH-BFXL)
Hold time, BFSX low after BCLKX high§
T -- 7
T+4
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX low¶
D -- 7
D+5
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
-- 3
4
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
D -- 2
D+3
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
2H + 3
6H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H + 2
8H + 17
ns
ns
ns
6H + 4
10H + 15
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
October 1998 -- December 2000
SPRS075E
61
Electrical Specifications
tsu(BFXL-BCKXL)
LSB
tc(BCKX)
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
td(BFXL-BDXV)
tdis(BFXH-BDXHZ)
td(BCKXL-BDXV)
tdis(BCKXH-BDXHZ)
BDX
Bit 0
Bit(n-1)
tsu(BDRV-BCKXH)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXH-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 4--26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
4.13.3.4 McBSP as SPI Master or Slave Timing When CLKSTP = 11b and CLKXP = 1)
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
Table 4--29 and Table 4--30 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--27).
Table 4--29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†
†
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
th(BCKXL-BDRV)
Hold time, BDR valid after BCLKX low
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
tc(BCKX)
Cycle time, BCLKX
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
12
7 -- 12H
ns
0
5 + 12H
ns
10
ns
32H
ns
12H
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4--30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†
PARAMETER
MASTER‡
SLAVE
MIN
MAX
MIN
MAX
UNIT
th(BCKXH-BFXL)
Hold time, BFSX low after BCLKX high§
D -- 7
D+4
ns
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX low¶
T -- 7
T+5
ns
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
-- 3
4
6H + 4
10H + 15
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from BCLKX
high
--2
4
6H + 3
10H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
C -- 3
C+5
4H + 2
8H + 17
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
62
SPRS075E
October 1998 -- December 2000
Electrical Specifications
tsu(BFXL-BCKXL)
LSB
tc(BCKX)
MSB
BCLKX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
BFSX
tdis(BCKXH-BDXHZ)
BDX
td(BCKXH-BDXV)
td(BFXL-BDXV)
Bit 0
Bit(n-1)
tsu(BDRV-BCKXL)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
th(BCKXL-BDRV)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 4--27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
October 1998 -- December 2000
SPRS075E
63
Electrical Specifications
4.14 Host-Port Interface (HPI8) Timing
The HPI8 timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 2.2.2,
“Programmable Bank-Switching”, of this data manual for details on the BSCR register). Any references to
CLKOUT in these timing parameters refer to the CLKOUT timings when no divide factor is selected
(DIVFCT=00b).
Table 4--31 and Table 4--32 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 4--28, Figure 4--29, and Figure 4--30). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2; HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.); and HAD refers to
HCNTL0, HCNTL1, and HR/W.
Write access timings, when the DSP is in reset (HOM), are automatically met by observing the following timing
requirements: tw(DSL), tw(DSH), tsu(HDV-DSH), and th(DSH-HDV)W.
Table 4--31. HPI8 Mode Timing Requirements
MIN
†
low†
MAX
UNIT
tsu(HBV-DSL)
Setup time, HBIL and HAD valid before DS low or before HAS
5
ns
th(DSL-HBV)
Hold time, HBIL and HAD valid after DS low or after HAS low†
5
ns
tsu(HSL-DSL)
Setup time, HAS low before DS low
10
ns
tw(DSL)
Pulse duration, DS low
20
ns
tw(DSH)
Pulse duration, DS high
10
ns
tsu(HDV-DSH)
Setup time, HD valid before DS high, HPI write
5
ns
th(DSH-HDV)W
Hold time, HD valid after DS high, HPI write
3
ns
When HAS is not used (HAS always high), this timing refers to DS
64
SPRS075E
October 1998 -- December 2000
Electrical Specifications
Table 4--32. HPI8 Mode Switching Characteristics
PARAMETER
ten(DSL-HD)
td(DSL-HDV1)
Enable time, HD driven from DS low
Delay time, DS low to HDx valid for first
byte of an HPI read
MIN
MAX
UNIT
2
15
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) < 22H‡
22H+15 – tw(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) ≥ 22H‡
15
Case 1c: Memory access when DMAC
is active in 32-bit mode and tw(DSH) <
30H‡
30H+15 – tw(DSH)
Case 1d: Memory access when DMAC
is active in 32-bit mode and tw(DSH) ≥
30H‡
15
Case 2a: Memory accesses when
DMAC is inactive and tw(DSH) < 12H‡
12H+15 – tw(DSH)
Case 2b: Memory accesses when
DMAC is inactive and tw(DSH) ≥ 12H‡
15
Case 3a: Register accesses or
accesses while the DSP is in reset
(HOM) and tw(DSH) < 20ns
35ns -- tw(DSH)
Case 3b: Register accesses or
accesses while the DSP is in reset
(HOM) and tw(DSH) ≥ 20ns
15
ns
td(DSL-HDV2)
Delay time, DS low to HDx valid for second byte of an HPI read
th(DSH-HDV)R
Hold time, HDx valid after DS high, for a HPI read
tv(HYH-HDV)
Valid time, HDx valid after HRDY high
5
td(DSH-HYL)
Delay time, DS high to HRDY low†
8
ns
td(DSH-HYH1)
Delay time, DS high to HRDY high on first byte
td(DSH-HYH2)
Delay time,
time DS high to HRDY high on
second byte
1
15
ns
5
ns
6H+12
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode‡
22H+12
ns
Case 1b: Memory accesses when
DMAC is active in 32-bit mode‡
30H+12
ns
Case 2: Memory accesses when
DMAC is inactive‡
12H+12
Case 3: Write accesses to HPIC
register and read accesses from HPIC
or HPIA registers
12H+12
ns
td(HCS-HRDY)
Delay time, HCS low/high to HRDY low/high
5
ns
td(COH-HYH)
Delay time, CLKOUT high to HRDY high
10
ns
td(COH-HTX)
Delay time, CLKOUT high to HINT change
10
ns
†
‡
The HRDY output is always high when the HCS input is high, regardless of DS timings.
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times
are affected by DMAC activity.
October 1998 -- December 2000
SPRS075E
65
Electrical Specifications
Second Byte
First Byte
Second Byte
HAS
tsu(HBV-DSL)‡
tsu(HSL-DSL)
th(DSL-HBV)
HAD†
Valid
Valid
tsu(HBV-DSL)‡
th(DSL-HBV)‡
HBIL
HCS
tw(DSH)
tw(DSL)
HDS
td(DSH-HYH1)
td(DSH-HYH2)
td(DSH-HYL)
td(DSH-HYL)
HRDY
ten(DSL-HD)
td(DSL-HDV2)
td(DSL-HDV1)
th(DSH-HDV)R
HD READ
Valid
Valid
tsu(HDV-DSH)
tv(HYH-HDV)
th(DSH-HDV)W
HD WRITE
Valid
Valid
Valid
Valid
td(COH-HYH)
CLKOUT
†
‡
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high), this timing refers to DS
Figure 4--28. Using HDS to Control Accesses (HCS Always Low)
66
SPRS075E
October 1998 -- December 2000
Electrical Specifications
Second Byte
First Byte
Second Byte
HCS
HDS
td(HCS-HRDY)
HRDY
Figure 4--29. Using HCS to Control Accesses
CLKOUT
td(COH-HTX)
HINT
Figure 4--30. HINT Timing
October 1998 -- December 2000
SPRS075E
67
Mechanical Data
5
Mechanical Data
The mechanical package diagrams that follow the tables reflect the most current released mechanical data
available for the designated devices.
68
SPRS075E
October 1998 -- December 2000
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
SNPB
MSL Peak Temp
(3)
Samples
(Requires Login)
TMS320VC5410GGW100
ACTIVE
BGA
MICROSTAR
GGW
176
126
TBD
Level-3-220C-168 HR
TMS320VC5410PGE100
ACTIVE
LQFP
PGE
144
60
Green (RoHS
& no Sb/Br)
TMS320VC5410ZGW100
ACTIVE
BGA
MICROSTAR
ZGW
176
126
Green (RoHS
& no Sb/Br)
SNAGCU
TMSDVC5410GGWR100
OBSOLETE
BGA
MICROSTAR
GGW
176
TBD
Call TI
Call TI
TMX320VC5410GGW100
OBSOLETE
BGA
MICROSTAR
GGW
176
TBD
Call TI
Call TI
CU NIPDAU Level-1-260C-UNLIM
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2012
Addendum-Page 2
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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