AND8280/D NCP1351 Modeling Using the PWM Switch Technique Prepared by: Stéphanie Conseil ON Semiconductor http://onsemi.com APPLICATION NOTE by averaging the voltage and current waveform in the circuitry. He obtained a 3 terminal model (node A, C and P) where: • Node A represents the active node, the switch terminal not connected to the diode • Node C is the common node, the junction between the power switch and the diode • Node P is the passive node, the diode terminal not connected to the switch The input variables are the current in node A, the voltage Vap; the output variables are the current in node C and the voltage Vap (Figure 1). This document describes the average modeling of the NCP1351 a fixed on time / variable off time controller. The advantage of using an average model is that you can perform ac simulations of your power supply to study the stability of your system. Another advantage is that transient simulations with the averaged model are faster compared to transient simulations with a cycle−by−cycle model. The model is very simple to use and can be downloaded from ON website. Presentation of the PWM Switch Technique The Pulse Width Modulation switch model was developed by Vatché Vorpérian (Jet Propulsory Laboratory, Passadena, CA) in 1986. His approach consisted in modeling the switch network alone (power switch + diode) Ic Ia C A Vap Vap P Figure 1. PWM Switch and its Variables The PWM switch is invariant i.e. the PWM switch electrical structure is the same whatever converter we consider. For this reason, we will use a buck−boost converter for the study, because of simplicity but also because the flyback topology where the NCP1351 is used is derived from buck−boost. SW + Vin Modeling the Switching Network Figures 2 and 3 show the switching network in the buck−boost circuit and its equivalent implementation in PWM switch. © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 0 PWM D R L1 C Figure 2. Buck−Boost Converter 1 Publication Order Number: AND8280/D AND8280/D Once the switch network has been identified in the original circuit, a simple rotation of the PWM switch model leads to the final implementation. This step is necessary to unveil the various variables in play. PWM 4 3 a X1 PWMVM d PWM Switch VM + Vin 18 c Averaging the PWM Switch Waveforms NCP1351 is a fixed peak−current variable−toff current− mode converter without internal ramp compensation. We will first consider the DCM mode to derive the equations since further developments will show that the model automatically toggles from DCM to CCM. The method consists of identifying current, voltage waveforms in the switch terminals (Figure 4 and Figure 5) and averaging them over one switching period. p 1 2 Rload 6 C1 220 m L1 33 m Figure 3. PWM Switch in the Buck−boost Converter Ia(t) Ipk Ia(t) VCS/Rsense Vac/L Vac/L Ic(t) VCS/Rsense Ipk Ipk Vac/L d1/TSW Ic(t) VCS/Rsense Vac/L Vcp/L d2/TSW d3/TSW d1/TSW Figure 4. The Current Waveforms in DCM: Ia, Ic ǒ Ǔ d ) d2 VCS V IC + * d2TSW CP 1 * 1 2 Rsense L IPK Vcp + L d2TSW (eq. 3) I Ia + PK d1 2 (eq. 4) I Ic + PK (d1 ) d2) 2 (eq. 5) (eq. 7) d2 expression is derived from Equations (2) and (5) 2LIc d2 + * d1 d1TSWVac (eq. 8) We clamp d2 value between 0.01 and (1– d1). When d2 is equal to (1– d1), we are in CCM [1]. In the NCP1351, the loop controls the switching frequency by adjusting the end−of−charge voltage threshold of the Ct capacitor (see Figure 6). The capacitor is charged by a constant current source ICt and the threshold voltage Vfbint is proportional to the feedback current injected into the FB pin by the optocoupler. The switching period equation is: The average current in terminal A is deduced from equations (4) and (5): d1 Ia + Ic d1 ) d2 d2/TSW d2Vcp d1 + Vac According to Figure 4, the following expressions for the terminal voltages and currents can be easily verified [2]: (eq. 2) Vcp/L The average on−time duty cycle d1 is solved from Equations (2) and (3) It is necessary to clamp the duty cycle d1 value between 0.01 and 0.9 (1 to 90% duty−cycle) to avoid convergence issues. (eq. 1) IPK d1TSW VCS/Rsense Figure 5. The Current Waveforms in CCM: Ia, Ic The average current flowing in the C terminal is given by the following equation [1]: Vac + L Ipk (eq. 6) TSW + http://onsemi.com 2 CtVfbint Ict (eq. 9) AND8280/D VCT 6V Minimum Frequency Vfbint 0.5 V Maximum Frequency TSW TSW Figure 6. The Switching Frequency is Controlled by the Charge of Ct Capacitor NCP1351 is a current mode converter without ramp compensation. The controller is thus subject to subharmonic oscillations when operating in CCM. The subharmonic oscillations are modelled by a capacitor connected between C and P terminal during CCM. The capacitor value is frequency−dependent and is calculated by the following expression [3]: CS + 4 L(pFSW) 2 A behavioral current source is used to model ICS. The model for the peak current compression is shown on Figure 8. The feedback current controls the switching frequency by changing the timing capacitor end−of–charge−voltage Vfbint. To do so, the optocoupler injects current into the FB pin which is actually a bipolar current−mirror input. This current is then adjusted by the feedback loop depending on the operating region (full power, compression or standby). The resulting current flows into a 45 kW resistor which develops a voltage proportional to the FB current. This signal becomes the Ct capacitor ending voltage. Thus, the relation between feedback current Ifb and Vfbint is: (eq. 10) A separate in−line equation disconnects the capacitor during DCM. The electrical implementation of all the equations derived above is shown on Figure 7. Modeling the FB Section To avoid acoustic noise problems, the NCP1351 compresses the peak current as the load becomes lighter. From the datasheet, we can extract the values of CS current as a function of FB current. ICS + Vfbint + Voffset ) 45 kIFB It is also important to model the pin FB current mirror because the dynamic resistance of the input mirror transistor directly influences the loop gain. Figure 7 shows the way we implemented the model of the FB modulator. 250 mA if Ifb t 60 mA 790 mA * 9 Ifb if 60 mA t Ifb t 80 mA (eq. 11) 70 mA if Ifb u 80 mA VFBint FB + Voffset 0.5 D2 1N4148 Vcl_Vfb 6 + 1 2 B1 Current R1 45 k (eq. 12) C4 80 p l(Vlfb) < 42 m 0.4 m: l(Vlfb) − 41.1 m + Figure 7. Feedback Modulator Model http://onsemi.com 3 Vlfb 0 9 X5 NPNV AND8280/D Complete Average Model and Application The complete averaged model of NCP1351 is shown below. Power Section Ia Current A I(VM)*V(d1))/ (V(d1)+V(d2)+1m) C Parameters Lpri = 25 m Rsense = 0.15 Ct = 100 p ICt = 10 m P Im Current Ipk Current VM 6 C1 C = 4*V(Ts)^2/((Lpri)*6.28^2) (1−(V(d1)+V(d2))/2)* V(c,p)*V(d2)*V(TS)/(Lpri) V(CS)/(Rsense) 3 CCM = 1 ≥ Closed CCM = 0 ≥ Open + Time Variable Calculation X3 cl_d1 d1 X2 Config_1 d2x 0.99 TS 17 d d2NC d1 + TS Voltage (Ct)*V(Vfb)/(ICt) d1x Voltage V(d2)*V(c,p)/ (V(a,c)+1m) CCM d2c 1−d1 d1 0.01 + d2 d2 + D2x Voltage d + 0.1 Bstate Voltage 2*I(VM)*(Lpri)/(V(d1)*V(TS) *V(a,c)+1m)−V(d1) V(d2x) < (1−V(d1)) 0: 1 Feedback Section Vfb + + 3 D2 1N4148 Vcl_Vfb 6 VDD FB Voffset 0.5 7 + B1 Current R7 45 k C4 80 p Vlfb 0 16 CS B3 Current l(Vlfb) > 60 m I(V6): 250 m l(Vlfb) < 42 m 0.4 m: l(Vlfb) − 41.1 m X5x NPNV RC (RCS) Figure 8. Complete Averaged Model of NCP1351 http://onsemi.com 4 B3 Current 19 l(Vlfb) < 80 m 790 m−9*I(Vlfb): 70 m + V6 0 + VDD 6 AND8280/D All the elements in Figure 8 are encapsulated into a subcircuit as shown below: 7 6 TS 1 A 4 FB 5 CS 1. if equal to “1”, the converter is in CCM 2. if equal to “0”, the converter is in DCM • Ts and CS respectively indicate the switching period (1 mV = 1 ms) and the CS level. Place voltage probes on the schematic to see their values or display the operation bias points The model expect the values of your primary inductance, sense and CS resistors and the value of the timing capacitor Ct. Defaults values for these parameters are indicated on Figure 9. CCM C 2 P PWM Switch CCM−DCM 3 X1 NCP1351_av Lpri = 33 m Rsense = 0.27 RCS = 3.9 k CT = 100 p The Model in a Flyback Converter Figure 9. The PWM Switch Encapsulated into a Sub Circuit The following schematic describes the NCP1351 averaged model implementation in a flyback converter. This schematic can be downloaded from the website. Then, you will just need to enter your own power supply design values in the different components. • A, C and P are the power terminals. • FB is the feedback input. Connect it to optocoupler emitter. • The CCM pin indicates the operating mode (CCM or DCM): FB TS CCM A VCS X5 PWMCMTS Lpri = 650 m Rsense = 0.9 RCS = 3.9 k CT = 270 p FB CS 7 1 P 6 2 PWM Switch C CCM−DCM 3 X4 XFMR RATIO = −0.125 Vout L1 0.5 m 21 V3 18 Rload 6 R2 0.033 VIN 125 AC = 0 L2 (Lpri) FB 25 Cout 1880 m IC = 12 Vac AC = 1 + Vin 13 R11 0.09 8 + Vout 9 + Rfb 1k Rbias 560 Rupper 38 k 10 X1 Optocoupler Cpole = 6.8 n CTR = 0.768 11 CZ 100 n 12 C4 100 m Rp 2.5 k CP 100 n X2 TL431_G Rlower 10 k Figure 10. The NCP1351 Model in a Flyback Converter Validating the Model: Model versus Reality As an example we implemented a 12 V, 2 A flyback converter with secondary output filter. For the feedback, we have chosen a TL431, but you can also use a zener diode. Rp is the optocoupler pulldown resistor and Cp places a pole in the compensation transfer function. Typical values for these components are shown on the schematic. We have also represented the ESR of output capacitors to be closer to real application and also because it influences the ac response of the power stage. In order to test the model, we built a 20 W buck−boost converter with NCP1351 as the MOSFET controller. The design specifications are: Input voltage: 16 V – 20 V dc Output voltage: 12 V @ 1.7 A As we used a P−channel MOSFET for the power switch, the DRV signal from NCP1351 needs to be inverted. We selected a MC33151 for that purpose. The output power is regulated with a zener diode and an optocoupler. The optocoupler simplifies the FB path as we need to pull the FB up from a negative output voltage. http://onsemi.com 5 AND8280/D VCC D3 MBRD650CT X3 MTD2955 TP1 R10 10 8 VIN VCC 7 6 5 FB 1 R3 3.9 k C6 100 p C13 1m X5 NCP1351 1 C4 220 m 3 FB 4 8 2 7 3 6 4 5 Loop Input R15 330 8 VCC GND Lbb 33 m 18 C5 100 n VCC C3 R12 100 n Rdrv 100 k 2.2 k D2 1AZ11 R7 0.27 Figure 11. The Buck−boost Board Application Schematic Shows an Optocoupler in the FB Chain FB VCC TS CCM A X3 NCP1351_av + VIN 18.33 L2 (Lpri) Vout Vout V2 P 6 1 PWM Switch C CCM−DCM 3 Cin 1000 m Parameters RCS = 3.9 k Lpri = 33 m Rsense = 0.27 VCS FB CS 7 2 Vac AC = 1 + Vin + IP 7 Rfb 340 FB Rload 8.7 R2 0.15 X1 Optocoupler Cpole = 6.8 n CTR = 0.768 4 12 R1 75 m VOUT SFH610A C7 100 n R2 1k 2 TP2 14 MC33151 C1 1000 m Loop Output R4 10 R8 88 m Cout 220 m IC = −12 23 Cp 1m Rp 1k Figure 12. The Buck−boost Model Implemented in SPICE http://onsemi.com 6 VCC 4 10 D1 1AZ11 AND8280/D Operating Point As we said in the previous section, it is important to include the dc resistance of the self and the ESR of the capacitors in the model to better fit reality. We ran operating point simulations for different loads. We obtain the following results for the switching period: Load Current – Iload Simulated Period – Tsw Measured Period – Tsw 1.4 A 11.7 ms 13.7 ms 0.6 A 17 ms 17.4 ms 0.09 A 22.3 ms 21 ms Load Step Response In high current conditions, the forward drop voltage in the diode and the ohmic losses in the MOSFET can degrade the bias point as these effects are not taken into account in our model. However, at a low output current, these losses become negligible and the simulation better fits the measurement. We compared the simulated and the measured response for a load step from 0.5 A to 1.4 A swept with a slew−rate of 10 mA/ms (Figure 13 and Figure 14). Vout Scale : Y = 20 mV / div, X = 1 ms / div Scale : Y = 20 mV / div, X = 1 ms / div Figure 13. Simulated Load Step Response Figure 14. Measured Load Step Response The simulated results are very close to measurements. The first voltage peak corresponding to a transition from 0.5 A to 1.4 A is well predicted with a simulated value of 80 mV versus 70 mV for the measurement. For a transition from 1.4 A to 0.5 A, the model is less precise and the simulation response is 40 mV higher than the measurement. This may come from the internal Cs capacitor that is brutally disconnected between C and P terminal since we are toggling from CCM to DCM. A solution would be to disconnect this capacitor for transient simulations only. Measuring the Loop Response The loop measurement represents an important task to confirm the validity of the assumptions during the theoretical design stage. The measurement principle is shown below: Loop Output VOUT TP1 Power Stage Rload Network Analyzer R4 10 Isolator TP2 Controller NCP1351 R15 330 Loop Input SFH610A VCC D2 1AZ11 Figure 15. Loop Response Measurement Principle http://onsemi.com 7 AND8280/D Results in CCM The voltage injection source is implemented with a wide band isolation device together with a 10 ohm resistor. See reference [4] for more information about this technique. Voltage probes are used to measure the loop input and output signals with respect to ground on either side of the injection point. To obtain correct measurements, it is necessary to choose an operating point outside the peak current compression zone. We have selected Vin = 18 V and a output current of 1.4 A. The switching frequency is 73 kHz. The below figures represent the measured and simulated loop gain and phase for a 1.4 A output current. Low Frequency Gain : 50 dB Gain Phase Phase Margin : 335 0 dB Resonance due to subharmonic oscillations 3.4 kHz Crossover Frequency Figure 16. Measured Loop Response in CCM 1 phase 160 57.0 80.0 37.0 2 gain Low Frequency Gain : 45 dB 0 gain in db(volts) Plot1 phase in degrees Gain Phase Margin : 375 17.0 0 dB −80.0 −3.00 −160 −23.0 10 Phase 3.9 kHz Crossover Frequency 100 1k frequency in hertz Resonance due to subharmonic oscillations 1 10k 2 100k Figure 17. Simulated Loop Response in CCM primary aim was to validate the model, we did not pay a particular attention to improve this figure. The simulated loop response is very close to reality. We have a variation of 10% between measurement and reality, which is acceptable because what we need is an indication about phase margin (greater than 455) and crossover frequency to be sure we will remain stable in all operating cases. In our example, we have a phase margin smaller than 455. This is clearly not acceptable as a design goal but as our Results in DCM We also compared the simulated and measured loop response in DCM for a 0.06 A output current. The input voltage is 18 V and the switching frequency is 33 kHz (Figure 18 and Figure 19). http://onsemi.com 8 AND8280/D Low Frequency Gain : 40 dB Noise Measurement Gain 0 dB Phase Margin : 505 Switching Frequency Phase 740 Hz Crossover Frequency Figure 18. Measured Loop Response in CCM 150 80.0 Low frequency Gain 39 dB 70.0 30.0 −10.0 40.0 gain_dcm in db(volts) Plot1 phase_dcm in degrees 110 0 dB Phase 0 Phase Margin 505 −40.0 Crossover Frequency −80.0 10 Gain 100 723 Hz 1k FREQUENCY (Hz) 10k 100k Figure 19. Measured Loop Response in DCM and compared to measurements: operating point, load step, and loop gain and phase response. There is a good correlation between the model and the measurements. We can conclude that the model is a good tool to predict the small−signal response of a NCP1351−based power supply. This model has been derived using INTUSOFT’s IsSpice and CADENCE’s OrCAD. Both versions are uploaded on ON Semiconductor website (www.onsemi.com). A cycle−by−cycle model also exists and is available from the same location. Again, we have a good correlation between measured and simulated loop response in DCM. The error ratio between simulation and measurement is less than 2%, the model is thus accurate to predict the DCM behavior. Here, we have a greater phase margin because the right half plane zero in the control to output transfer function of the buck−boost disappears, thus improving the system stability. Conclusion An averaged model of NCP1351 has been derived using the PWM Switch modeling technique. The model has been validated by experimental measurements on a buck−boost converter using NCP1351 as the controller. Several aspects of the model have been tested http://onsemi.com 9 AND8280/D References Aerospace and Electronics Systems, Vol 26, N°3, May 1990. 3. Vatché Vorpérian, “Analysis of current−mode controlled PWM converters using the model of the current−controlled PWM switch”, Power Conversion October 1990 proceedings. 4. www.ridleyengineering.com 1. Christophe Basso, “The PWM Switch concept included in mode transitioning SPICE models”, PCIM 2005 2. Vatché Vorpérian, “Simplified Analysis of PWM converters using the model of the PWM switch, Part I (CCM) and II (DCM)”, Transactions on ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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