XILINX XCR3032XL

0
R
XCR3032XL 32 Macrocell CPLD
DS023 (v1.5) January 8, 2002
0
14
Preliminary Product Specification
Features
Description
•
Lowest power 32 macrocell CPLD
•
5.0 ns pin-to-pin logic delays
•
System frequencies up to 200 MHz
•
32 macrocells with 750 usable gates
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge programmable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
•
Available in small footprint packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQFP (36 user I/O)
- 44-pin PLCC (36 user I/O)
TotalCMOS Design Technique for Fast
Zero Power
Optimized for 3.3V systems
- Ultra-low power operation
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
•
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
•
•
•
•
•
•
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Frequency of our
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25°C).
20
Typical ICC (mA)
•
15
10
5
0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
DS023_01_080101
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C
Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz)
0
1
5
10
20
50
100
200
Typical ICC (mA)
0.02
0.13
0.54
1.06
2.09
5.2
10.26
20.3
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DS023 (v1.5) January 8, 2002
Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol
VOH(2)
Parameter
Output High voltage
Test Conditions
VCC = 3.0V to 3.6V, IOH = –8 mA
Min.
2.4
Max.
-
Unit
V
VCC = 2.7V to 3.0V, IOH = –8 mA
IOH = –500 µA
2.0(3)
90% VCC
-
V
V
VOL
IIL(4)
Output Low voltage
Input leakage current
IOL = 8 mA
VIN = GND or VCC
–10
0.4
10
V
µA
IIH(4)
ICCSB
I/O High-Z leakage current
Standby current
VIN = GND or VCC
VCC = 3.6V
–10
-
10
100
µA
µA
ICC
Dynamic current(5,6)
CIN
Input pin capacitance(7)
f = 1 MHz
f = 50 MHz
f = 1 MHz
-
0.25
7.5
8
mA
mA
pF
CCLK
CI/O
Clock input capacitance(7)
I/O pin capacitance (7)
f = 1 MHz
f = 1 MHz
-
12
10
pF
pF
Notes:
1. See XPLA3 family data sheet (DS012) for recommended operating conditions
2. See Figure 2 for output drive characteristics of the XPLA3 family.
3. This parameter guaranteed by design and characterization, not by testing.
4. Typical leakage current is less than 1 µA.
5. See Table 1, Figure 1 for typical values.
6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing.
7. Typical values, not tested.
100
90
IOL (3.3V)
80
70
mA
60
50
IOH (3.3V)
40
30
IOH (2.7V)
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
2
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DS023 (v1.5) January 8, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-5
Symbol
TPD1
Parameter
Min.
Propagation delay time (single p-term)
array)(3)
-7
-10
Max.
Min.
Max.
Min.
Max.
Unit
4.5
-
7.0
-
9.1
ns
5.0
-
7.5
-
10.0
ns
5.0
-
6.5
ns
TPD2
Propagation delay time (OR
TCO
Clock to output (global synchronous pin clock)
TSUF
Setup time (fast input register)
2.5
-
3.0
-
3.0
-
ns
TSU1(4)
Setup time (single p-term)
3.0
-
4.3
-
5.4
-
ns
TSU2
Setup time (OR array)
3.5
-
4.8
-
6.3
-
ns
0
-
0
-
0
-
ns
TH(4)
Hold time
3.5
(4)
Global Clock pulse width (High or Low)
2.5
-
3.0
-
4.0
-
ns
(4)
P-term clock pulse width
4.0
-
5.0
-
6.0
-
ns
Input rise time
-
20
-
20
-
20
ns
Input fall time
-
20
-
20
-
20
ns
Maximum system frequency
-
200
-
119
-
95
MHz
TCONFIG(4)
Configuration time(5)
-
30
-
30
-
30
µs
TINIT(4)
ISP initialization time
-
30
-
30
-
30
µs
TPOE(4)
P-term OE to output enabled
-
7.2
-
9.3
-
11.2
ns
-
7.2
-
9.3
-
11.2
ns
TWLH
TPLH
TR
TL
(4)
(4)
fSYSTEM
(4)
TPOD
(4)
P-term OE to output
TPCO
(4)
P-term clock to output
-
5.5
-
8.3
-
10.7
ns
(4)
P-term set/reset to output valid
-
6.5
-
9.3
-
11.2
ns
TPAO
disabled(6)
Notes:
1. Specifications measured with one output switching.
2. See XPLA3 family data sheet (DS012) for recommended operating conditions.
3. See Figure 4 for derating.
4. These parameters guaranteed by design and/or characterization, not testing.
5. Typical current draw during configuration is 3 mA at 3.6V.
6. Output CL = 5 pF.
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
Internal Timing Parameters(1,2)
-5
Symbol
Parameter
-7
-10
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Buffer Delays
TIN
Input buffer delay
-
0.7
-
1.6
-
2.2
ns
TFIN
Fast Input buffer delay
-
2.2
-
3.0
-
3.1
ns
TGCK
Global Clock buffer delay
-
0.7
-
1.0
-
1.3
ns
TOUT
Output buffer delay
-
1.8
-
2.7
-
3.6
ns
TEN
Output buffer enable/disable delay
-
4.5
-
5.0
-
5.7
ns
-
1.3
-
1.6
-
2.0
ns
Internal Register and Combinatorial Delays
TLDI
Latch transparent delay
TSUI
Register setup time
1.0
-
1.0
-
1.2
-
ns
THI
Register hold time
0.3
-
0.5
-
0.7
-
ns
TECSU
Register clock enable setup time
2.0
-
2.5
-
3.0
-
ns
TECHO
Register clock enable hold time
3.0
-
4.5
-
5.5
-
ns
TCOI
Register clock to output delay
-
1.0
-
1.3
-
1.6
ns
TAOI
Register async. S/R to output delay
-
2.0
-
2.3
-
2.1
ns
TRAI
Register async. recovery
-
3.5
-
5.0
-
6.0
ns
TLOGI1
Internal logic delay (single p-term)
-
2.0
-
2.7
-
3.3
ns
TLOGI2
Internal logic delay (PLA OR term)
-
2.5
-
3.2
-
4.2
ns
-
0.5
-
2.9
-
3.5
ns
Feedback Delays
TF
ZIA delay
Time Adders
TLOGI3
Fold-back NAND delay
-
2.0
-
2.5
-
3.0
ns
TUDA
Universal delay
-
1.2
-
2.0
-
2.5
ns
TSLEW
Slew rate limited delay
-
4.0
-
5.0
-
6.0
ns
Notes:
1. These parameters guaranteed by design and characterization, not testing.
2. See XPLA3 family data sheet (DS012) for timing model.
4
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DS023 (v1.5) January 8, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
Switching Characteristics
VCC
S1
Component
R1
R2
C1
R1
Values
390Ω
390Ω
35 pF
VIN
VOUT
R2
Measurement
TPOE (High)
TPOE (Low)
TP
C1
S1
Open
Closed
Closed
S2
Closed
Open
Closed
Note: For TPOD, C1 = 5 pF. Delay measured at
output level of VOL + 300 mV, VOH – 300 mV.
S2
DS023_03_102401
Figure 3: AC Load Circuit
4.5
+3.0V
90%
10%
TPD (ns)
4.0
0V
TR
1.5 ns
3.5
3.0
1
2
4
8
16
TL
1.5 ns
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
DS023_06_042800
Outputs
DS023_05_061101
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
Pin Descriptions
Table 3: XCR3032XL I/O Pins
Table 2: XCR3032XL User I/O Pins
Total User I/O Pins
Macrocell
PC44
VQ44
CS48
PC44
VQ44
CS48
2
15
25
19
G5
36
36
36
2
16
24
18
F4
Notes:
1. JTAG pins
Table 3: XCR3032XL I/O Pins
6
Function
Block
Function
Block
Macrocell
PC44
VQ44
CS48
1
1
4
42
A2
1
2
5
43
A1
1
3
6
44
C4
Pin Type
PC44
VQ44
CS48
1
4
7(1)
1(1)
B1(1)
IN0 / CLK0
2
40
A3
1
5
8
2
C2
IN1 / CLK1
1
39
B4
1
6
9
3
C1
IN2 / CLK2
44
38
A4
1
7
11
5
D3
IN3 / CLK3
43
37
B5
1
8
12
6
D1
TCK
32
26
E5
1
9
13(1)
7(1)
D2(1)
TDI
7
1
B1
1
10
14
8
E1
TDO
38
32
B7
1
11
16
10
F1
TMS
13
7
D2
1
12
17
11
G1
PORT_EN
10(1)
4(1)
C3(1)
1
13
18
12
E4
VCC
1
14
19
13
F2
3, 15, 23,
35
9, 17, 29,
41
B3, C7,
E2, G4
1
15
20
14
G2
GND
22, 30, 42
16, 24, 36
A5, E3, E6
1
16
21
15
F3
No Connects
-
-
A7, B2,
F6, G3
2
1
41
35
C5
2
2
40
34
A6
2
3
39
33
B6
2
4
38(1)
32(1)
B7(1)
2
5
37
31
D4
2
6
36
30
C6
2
7
34
28
D6
2
8
33
27
D7
2
9
32(1)
26(1)
E5(1)
2
10
31
25
E7
2
11
29
23
F7
2
12
28
22
G7
2
13
27
21
G6
2
14
26
20
F5
Table 4: XCR3032XL Global, JTAG, Port Enable, Power,
and No Connect Pins
Notes:
1. Port Enable is brought High to enable JTAG pins when
JTAG pins are used as I/O. See family data sheet
(DS012) for full explanation.
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DS023 (v1.5) January 8, 2002
Preliminary Product Specification
R
XCR3032XL 32 Macrocell CPLD
Ordering Information
Example:
XCR3032XL -5 VQ 44 C
Device Type
Temperature Range
Number of Pins
Speed Grade
Package Type
Device Ordering Options
Speed
Package
Temperature
-10
10 ns pin-to-pin
delay
PC44
44-pin Plastic Lead Chip Carrier
(PLCC)
C = Commercial
TA = 0°C to +70°C
VCC = 3.0V to 3.6V
-7
7.5 ns pin-to-pin
delay
VQ44
44-pin Very Thin Quad Flat Pack
(VQFP)
I = Industrial
TA = –40°C to +85°C
VCC = 2.7V to 3.6V
-5
5 ns pin-to-pin delay
CS48
48-ball Chip Scale Package
Component Availability
Pins
44
44
48
Type
Plastic PLCC
Plastic VQFP
Plastic BGA
Code
PC44
VQ44
CS48
-5
C
C
C
-7
C,I
C,I
C,I
-10
C, I
C, I
C, I
XCR3032XL
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
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XCR3032XL 32 Macrocell CPLD
Revision History
The following table shows the revision history for this document.
8
Date
Version
Revision
11/18/00
1.0
Initial Xilinx release.
02/05/01
1.1
Removed Timing Model.
04/11/01
1.2
Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers,
Table 1 and updated Figure 1. Added Typical I/V curve, Figure 2; added Table 2: Total User
I/O; changed VOH spec.
04/19/01
1.3
Updated Typical I/V curve, Figure 2: added voltage levels.
08/27/01
1.4
Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical
Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial
packages. Added 200 MHz to Figure 1 and Table 1. changed -5 FSYSTEM to 200 MHz, -5 TF
to 0.5 ns.
01/08/02
1.5
Updated THI spec to correct a typo. Added single p-term setup time (TSU1) to AC Table,
renamed TSU to TSU2 for setup time through the OR array. Updated AC Load Circuit diagram
to more closely resemble true test conditions, added note for TPOD delay
measurement.Updated note 5 in AC Characteristics table lowering typical current draw
during configuration.
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DS023 (v1.5) January 8, 2002
Preliminary Product Specification