250 kSPS, 12-Bit Impedance Converter, Network Analyzer AD5934 Data Sheet FEATURES GENERAL DESCRIPTION Programmable output peak-to-peak excitation voltage to a maximum frequency of 100 kHz Programmable frequency sweep capability with serial I2C interface Frequency resolution of 27 bits (<0.1 Hz) Impedance measurement range from 1 kΩ to 10 MΩ Capable of measuring 100 Ω to 1 kΩ with additional circuitry Phase measurement capability System accuracy of 0.5% 2.7 V to 5.5 V power supply operation Temperature range: −40°C to +125°C 16-lead SSOP package The AD5934 is a high precision impedance converter system solution that combines an on-board frequency generator with a 12-bit, 250 kSPS, analog-to-digital converter (ADC). The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC and a discrete Fourier transform (DFT) is processed by an on-board DSP engine. The DFT algorithm returns a real (R) and imaginary (I) data-word at each output frequency. Once calibrated, the magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated using the following two equations: R2 + I 2 APPLICATIONS Magnitude = Electrochemical analysis Bioelectrical impedance analysis Impedance spectroscopy Complex impedance measurement Corrosion monitoring and protection equipment Biomedical and automotive sensors Proximity sensing Nondestructive testing Material property analysis Fuel/battery cell condition monitoring Phase = tan−1(I/R) A similar device, available from Analog Devices, Inc., is the AD5933, which is a 2.7 V to 5.5 V, 1 MSPS, 12-bit impedance converter, with an internal temperature sensor, available in a 16-lead SSOP. FUNCTIONAL BLOCK DIAGRAM MCLK AVDD DVDD DDS CORE (27 BITS) DAC ROUT SCL SDA VOUT VBIAS I2C INTERFACE Z(ω) AD5934 REAL REGISTER IMAGINARY REGISTER RFB 1024-POINT DFT VIN ADC (12 BITS) GAIN LPF AGND 05325-001 VDD/2 DGND Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved. AD5934 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Performing a Frequency Sweep .................................................... 19 Applications ....................................................................................... 1 Register Map ................................................................................... 20 General Description ......................................................................... 1 Control Register (Register Address 0x80, Register Address 0x81)............................................................................................. 20 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 I2C Serial Interface Timing Characteristics .............................. 6 Absolute Maximum Ratings ............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Start Frequency Register (Register Address 0x82, Register Address 0x83, Register Address 0x84) .................................... 21 Frequency Increment Register (Register Address 0x85, Register Address 0x86, Register Address 0x87) ..................... 21 Number of Increments Register (Register Address 0x88, Register Address 0x89) .............................................................. 22 Typical Performance Characteristics ............................................. 9 Number of Settling Time Cycles Register (Register Address 0x8A, Register Address 0x8B) .................................................. 22 Terminology .................................................................................... 11 Status Register (Register Address 0x8F) .................................. 22 System Description ......................................................................... 12 Real and Imaginary Data Registers (16 Bits—Register Address 0x94, Register Address 0x95, Register Address 0x96, Register Address 0x97) .............................................................................. 23 Transmit Stage ............................................................................. 13 Frequency Sweep Command Sequence ................................... 14 Receive Stage ............................................................................... 14 DFT Operation ........................................................................... 14 Impedance Calculation .................................................................. 15 Magnitude Calculation .............................................................. 15 Gain Factor Calculation ............................................................ 15 Impedance Calculation Using Gain Factor ............................. 15 Gain Factor Variation with Frequency .................................... 15 2-Point Calibration ..................................................................... 16 2-Point Gain Factor Calculation .............................................. 16 Gain Factor Setup Configuration ............................................. 16 Gain Factor Recalculation ......................................................... 16 Gain Factor Temperature Variation ......................................... 17 Impedance Error......................................................................... 17 Measuring the Phase Across an Impedance ........................... 17 Serial Bus Interface ......................................................................... 24 General I2C Timing .................................................................... 24 Writing/Reading to the AD5934 .............................................. 25 Block Write .................................................................................. 25 Read Operations ......................................................................... 26 Typical Applications ....................................................................... 27 Measuring Small Impedances ................................................... 27 Biomedical: Noninvasive Blood impedance Measurement .. 28 Sensor/Complex Impedance Measurement............................ 29 Electro-Impedance Spectroscopy............................................. 29 Layout and Configuration ............................................................. 30 Power Supply Bypassing and Grounding ................................ 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 Rev. C | Page 2 of 32 Data Sheet AD5934 REVISION HISTORY 7/12—Rev. B to Rev. C Changes to Pin 10, Description Column, Table 4 and Pin 11, Description Column, Table 4........................................................... 8 Changes to Table 6 ..........................................................................18 Deleted Choosing a Reference for the AD5934 and Table 17; Renumbered Sequentially ..............................................................30 2/12—Rev. A to Rev. B Deleted Evaluation Board ................................................. Universal Changes to Impedance Error Section ...........................................17 5/8—Rev. 0 to Rev. A Changes to Layout .............................................................. Universal Changes to Features Section, General Description Section, and Figure 1 ............................................................................................... 1 Deleted Table 1; Renumbered Sequentially ................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Changes to Figure 3 and Table 4 ..................................................... 8 Changes to System Description Section and Figure 14..............12 Changes to Figure 16 ......................................................................13 Changes to Frequency Sweep Command Sequence Section and Receive Stage Section ......................................................................14 Changes to Gain Factor Calculation Section and Impedance Calculation Using Gain Factor Section ........................................ 15 Changes to Figure 20 ...................................................................... 16 Changes to Impedance Error Section ........................................... 17 Added Measuring the Phase Across an Impedance Section ..... 19 Added Figure 28 and Figure 29; Renumbered Sequentially ...... 20 Added Table 6; Renumbered Sequentially ................................... 20 Deleted Table 8 ................................................................................ 19 Deleted Table 10 and Table 11 ....................................................... 20 Changes to Table 9 .......................................................................... 22 Deleted Table 14, Table 16, and Table 17 ..................................... 22 Changes to Status Register (Register Address 0x8F) Section .... 24 Added Measuring Small Impedances Section, Figure 37, and Table 16 ............................................................................................. 29 Changes to Table 17 ........................................................................ 32 Added Evaluation Board Section .................................................. 34 Added Figure 40 .............................................................................. 35 Added Figure 41 .............................................................................. 36 Added Figure 42 .............................................................................. 37 Added Figure 43 .............................................................................. 38 Added Table 18 ................................................................................ 39 Changes to Ordering Guide ........................................................... 40 6/05—Revision 0: Initial Version Rev. C | Page 3 of 32 AD5934 Data Sheet SPECIFICATIONS VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 kΩ connected between Pin 5 and Pin 6; feedback resistor = 200 kΩ connected between Pin 4 and Pin 5; PGA gain = ×1, unless otherwise noted. Table 1. Parameter SYSTEM Impedance Range Min 1k Total System Accuracy System Impedance Error Drift TRANSMIT STAGE Output Frequency Range 2 Output Frequency Resolution MCLK Frequency TRANSMIT OUTPUT VOLTAGE Range 1 AC Output Excitation Voltage 3 DC Bias 4 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 2 AC Output Excitation Voltage3 DC Bias4 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 3 AC Output Excitation Voltage3 DC Bias4 DC Output Impedance Short-Circuit Current to Ground at VOUT Range 4 AC Output Excitation Voltage3 DC Bias4 DC Output Impedance Short-Circuit Current to Ground at VOUT SYSTEM AC CHARACTERISTICS Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Wide Band (0 MHz to 1 MHz) Narrow Band (±5 kHz) Y Version 1 Typ Max 10 M Unit Test Conditions/Comments Ω 100 Ω to 1 kΩ requires extra buffer circuitry, see Measuring Small Impedances section 2 V p-p output excitation voltage at 30 kHz, 200 kΩ connected between Pin 5 and Pin 6 0.5 % 30 ppm/°C 1 100 0.1 kHz Hz MHz <0.1 Hz resolution achievable using direct digital synthesis (DDS) techniques Maximum system clock frequency 1.98 1.48 200 ±5.8 V p-p V Ω mA Refer to Figure 4 for output voltage distribution DC bias of the ac excitation signal; see Figure 5 TA = 25°C TA = 25°C 0.97 0.76 2.4 ±0.25 V p-p V kΩ mA See Figure 6 DC bias of output excitation signal; see Figure 7 0.383 0.31 1 ±0.20 V p-p V kΩ mA See Figure 8 DC bias of output excitation signal; see Figure 9 0.198 0.173 600 ±0.15 V p-p V Ω mA See Figure 10 DC bias of output excitation signal; see Figure 11 60 −52 dB dB −56 −85 dB dB 16.776 Rev. C | Page 4 of 32 Data Sheet Parameter RECEIVE STAGE Input Leakage Current Input Capacitance 5 Feedback Capacitance, CFB ANALOG-TO-DIGITAL CONVERTER5 Resolution Sampling Rate LOGIC INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current 6 Input Capacitance POWER REQUIREMENTS VDD IDD, Normal Mode IDD, Standby Mode IDD, Power-Down Mode AD5934 Min Y Version 1 Typ Max Unit Test Conditions/Comments 1 0.01 3 nA pF pF To VIN pin Pin capacitance between VOUT and GND Feedback capacitance around current-tovoltage amplifier; appears in parallel with feedback resistor 12 250 Bits kSPS ADC throughput rate µA pF TA = 25° TA = 25°C V mA mA mA mA µA µA VDD = 3.3 V VDD = 5.5 V VDD = 3.3 V; see the Control Register section VDD = 5.5 V VDD = 3.3 V VDD = 5.5 V 0.7 × VDD 0.3 × VDD 1 7 2.7 10 17 7 9 0.7 1 5.5 15 25 5 8 1 Temperature range for Y version = −40°C to +125°C, typical at +25°C. The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934. The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage. Output Excitation Voltage (V p-p) = [2/3.3] × VDD 4 The dc bias value of the output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage. Output Excitation Voltage (V p-p) = [2/3.3] × VDD 5 Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of currentto-voltage amplifier. 6 The accumulation of the currents into Pin 8, Pin 15, and Pin 16. 2 3 Rev. C | Page 5 of 32 AD5934 Data Sheet I2C SERIAL INTERFACE TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted (see Figure 2). Table 2. Parameter 1 fSCL t1 t2 t3 t4 t5 t6 2 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 250 20 + 0.1 Cb 3 400 t7 t8 t9 t10 t11 Cb Unit Description kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns min ns max ns min pF max SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT, data hold time tHD, DAT, data hold time tSU, STA, setup time for repeated start tSU, STO, stop condition setup time tBUF, bus free time between a stop and a start condition tR, rise time of SDA when transmitting tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line 1 Guaranteed by design and characterization, not production tested. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL. 3 Cb is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD. 2 SDA t9 t3 t10 t11 t4 SCL t6 t2 t5 t7 REPEATED START CONDITION START CONDITION Figure 2. I2C Interface Timing Diagram Rev. C | Page 6 of 32 t1 t8 STOP CONDITION 05325-002 t4 Data Sheet AD5934 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter DVDD to GND AVDD1 to GND AVDD2 to GND SDA/SCL to GND VOUT to GND VIN to GND MCLK to GND Operating Temperatures Extended Industrial Range (Y Grade) Storage Temperature Range Maximum Junction Temperature SSOP Package, Thermal Impedance θJA θJC Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating −0.3 V to +7.0 V −0.3 V to +7.0 V −0.3 V to +7.0 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −65°C to +160°C 150°C 139°C/W 136°C/W 260°C 10 sec to 40 sec Rev. C | Page 7 of 32 AD5934 Data Sheet NC 1 16 SCL NC 2 15 SDA AD5934 14 AGND2 TOP VIEW (Not to Scale) 13 AGND1 12 DGND VOUT 6 11 AVDD2 NC 7 10 AVDD1 MCLK 8 9 DVDD NC 3 RFB 4 VIN 5 NC = NO CONNECT 05325-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES: 1. IT IS RECOMMENDED TO TIE ALL SUPPLY CONNECTIONS (PIN 9, PIN 10, AND PIN 11) AND RUN FROM A SINGLE SUPPLY BETWEEN 2.7V AND 5.5V. 2. IT IS ALSO RECOMMENDED TO CONNECT ALL GROUND SIGNALS TOGETHER (PIN 12, PIN 13, AND PIN 14). Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 to 3, 7 4 Mnemonic NC RFB 5 6 8 9 10 11 12 13 14 15 16 VIN VOUT MCLK DVDD AVDD1 AVDD2 DGND AGND1 AGND2 SDA SCL Description No Connect. Do not connect to this pin. External Feedback Resistor. Connect from Pin 4 to Pin 5. This pin sets the gain of the current-to-voltage amplifier on the receive side. Input to Receive Transimpedance Amplifier. VIN presents a virtual earth voltage of VDD/2. Excitation Voltage Signal Output. The master clock for the system is supplied by the user. Digital Supply Voltage. Analog Supply Voltage 1. Used for powering the analog core. Analog Supply Voltage 2. Used for internal references. Digital Ground. Analog Ground 1. Analog Ground 2. I2C® Data Input. I2C Clock Input. Rev. C | Page 8 of 32 Data Sheet AD5934 TYPICAL PERFORMANCE CHARACTERISTICS 35 30 MEAN = 1.9824 SIGMA = 0.0072 MEAN = 0.7543 SIGMA = 0.0099 25 25 NUMBER OF DEVICES 20 15 10 20 15 10 5 0 1.92 05325-064 5 1.94 1.96 1.98 2.00 2.02 2.04 05325-073 NUMBER OF DEVICES 30 0 0.68 2.06 0.70 0.72 0.74 VOLTAGE (V) Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V 0.80 0.82 0.84 0.86 30 MEAN = 0.3827 SIGMA = 0.00167 MEAN = 1.4807 SIGMA = 0.0252 25 NUMBER OF DEVICES 25 20 15 10 20 15 10 5 0 1.30 05325-072 5 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 0 0.370 1.75 05325-077 NUMBER OF DEVICES 0.78 Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V 30 0.375 0.380 0.385 0.390 0.395 0.400 VOLTAGE (V) VOLTAGE (V) Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V 30 30 MEAN = 0.9862 SIGMA = 0.0041 MEAN = 0.3092 SIGMA = 0.0014 25 NUMBER OF DEVICES 25 20 15 10 15 10 5 05325-066 5 0 0.95 20 0.96 0.97 0.98 0.99 1.00 1.01 1.02 0 0.290 05325-074 NUMBER OF DEVICES 0.76 VOLTAGE (V) 0.295 0.300 0.305 0.310 0.315 VOLTAGE (V) VOLTAGE (V) Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V Rev. C | Page 9 of 32 Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V 0.320 AD5934 Data Sheet 15.8 30 MEAN = 0.1982 SIGMA = 0.0008 14.8 14.3 20 IDD (mA) 15 10 13.8 13.3 12.8 12.3 11.8 05325-070 5 0.194 0.196 0.198 0.200 0.202 0.204 05325-088 NUMBER OF DEVICES 25 0 0.192 AVDD1, AVDD2, DVDD CONNECTED TOGETHER OUTPUT EXCITATION FREQUENCY = 30kHz RFB, Z CALIBRATION = 100kΩ 15.3 11.3 10.8 0 0.206 2 4 8 10 12 14 16 18 Figure 12. Typical Supply Current (IDD) vs. MCLK Frequency Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V 0.4 30 MEAN = 0.1792 SIGMA = 0.0024 VDD = 3.3V TA = 25°C f = 32kHz 0.2 20 15 10 05325-075 5 0 0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205 0 –0.2 –0.4 –0.6 –0.8 05325-028 PHASE ERROR (Degrees) 25 NUMBER OF DEVICES 6 MCLK FREQUENCY (MHz) VOLTAGE (V) –1.0 0 50 100 150 200 250 PHASE (Degrees) VOLTAGE (V) Figure 13. Typical Phase Error Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V Rev. C | Page 10 of 32 300 350 400 Data Sheet AD5934 TERMINOLOGY Total System Accuracy The AD5934 can accurately measure a range of impedance values to less than 0.5% of the correct impedance value for supply voltages between 2.7 V to 5.5 V. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The spurious-free dynamic range refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 Hz to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz, about the fundamental frequency. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental, where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. THD is defined as Rev. C | Page 11 of 32 THD (dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 AD5934 Data Sheet SYSTEM DESCRIPTION MCLK DDS CORE (27 BITS) DAC ROUT COS SIN VOUT VBIAS SCL I2C INTERFACE MICROCONTROLLER SDA Z(ω) AD5934 REAL REGISTER IMAGINARY REGISTER RFB MAC CORE (1024 DFT) PROGRAMMABLE GAIN AMPLIFIER MCLK VIN ADC (12 BITS) LPF ×5 ×1 VDD/2 05325-078 WINDOWING OF DATA Figure 14. Block Overview The AD5934 is a high precision, impedance converter system solution that combines an on-board frequency generator with a 12-bit, 250 kSPS ADC. The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC and DFT processed by an on-board DSP engine. The DFT algorithm returns both a real (R) and imaginary (I) data-word at each frequency point along the sweep. The impedance magnitude and phase is easily calculated using the following equations: Magnitude = R2 + I 2 The AD5934 permits the user to perform a frequency sweep with a user-defined start frequency, frequency resolution, and number of points in the sweep. In addition, the device allows the user to program the peak-to-peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the VOUT and VIN pins. Table 5 gives the four possible output peak-to-peak voltages and the corresponding dc bias levels for each range for 3.3 V. These values are ratiometric with VDD. So for a 5 V supply: Output Excitation Voltage for Range 1 = 1.98 × Phase = tan−1(I/R) To characterize an impedance profile Z(ω), generally a frequency sweep is required such as that shown in Figure 15. Output DC Bias Voltage for Range 1 = 1.48 × 5. 0 = 3 V p−p 3. 3 5. 0 = 2.24 V p − p 3. 3 Table 5. Voltage Levels Respective Bias Levels for 3.3 V 05325-033 IMPEDANCE (Ω) Range No. 1 2 3 4 FREQUENCY (Hz) Figure 15. Impedance vs. Frequency Profile Output Excitation Voltage Amplitude 1.98 V p-p 0.99 V p-p 383 mV p-p 198 mV p-p Output DC Bias Level 1.48 V 0.74 V 0.31 V 0.179 V The excitation signal for the transmit stage is provided on-chip using DDS techniques that permit subhertz resolution. The receive stage receives the input signal current from the unknown impedance, performs signal processing, and digitizes the result. The clock for the DDS is generated from an external reference clock that is provided by the user at MCLK. Rev. C | Page 12 of 32 Data Sheet AD5934 TRANSMIT STAGE Frequency Increment As shown in Figure 16, the transmit stage of the AD5934 is made up of a 27-bit phase accumulator DDS core that provides the output excitation signal at a particular frequency. The input to the phase accumulator is taken from the contents of the start frequency register (see Register Address 0x82, Register Address 0x83, and Register Address 0x84). Although the phase accumulator offers 27 bits of resolution, the start frequency register has the three most significant bits (MSBs) set to 0 internally; therefore, the user has the ability to program only the lower 24 bits of the start frequency register. This is a 24-bit word that is programmed to the on-board RAM at Register Address 0x85, Register Address 0x86, and Register Address 0x87 (see the Register Map section). The required code loaded to the frequency increment register is the result of the formula shown in Equation 2, based on the master clock frequency and the required increment frequency output from the DDS. PHASE ACCUMULATOR (27 BITS) DAC VOUT VBIAS ROUT 05325-034 R(GAIN) Figure 16. Transmit Stage The AD5934 offers a frequency resolution programmable by the user down to 0.1 Hz. The frequency resolution is programmed via a 24-bit word loaded serially over the I2C interface to the frequency increment register. The frequency sweep is fully described by the programming of three parameters: the start frequency, the frequency increment, and the number of increments. Start Frequency This is a 24-bit word that is programmed to the on-board RAM at Register Address 0x82, Register Address 0x83, and Register Address 0x84 (see the Register Map section). The required code loaded to the start frequency register is the result of the formula shown in Equation 1, based on the master clock frequency and the required start frequency output from the DDS. Start Frequency Code = Required Output Start Frequency × 2 27 MCLK 16 (1) For example, if the user requires the sweep to begin at 30 kHz and has a 16 MHz clock signal connected to MCLK, the code that needs to be programmed is given by 30 kHz × 2 27 = 0x3D70A3 Start Frequency Code = 16 MHz 16 The user programs the value of 0x3D to Register Address 0x82, the value 0x70 to Register Address 0x83, and the value 0xA3 to Register Address 0x84. Frequency Increment Code = Required Frequency Increment × 2 27 MCLK 16 (2) For example, if the user requires the sweep to have a resolution of 10 Hz and has a 16 MHz clock signal connected to MCLK, the code that needs to be programmed is given by Frequency Increment Code = 10 Hz 16 MHz ≡ 0x00053E 16 The user programs the value 0x00 to Register Address 0x85, the value 0x05 to Register Address 0x86, and the value 0x3E to Register Address 0x87. Number of Increments This is a 9-bit word that represents the number of frequency points in the sweep. The number is programmed to the on-board RAM at Register Address 0x88 and Register Address 0x89 (see the Register Map section). The maximum number of points that can be programmed is 511. For example, if the sweep needs 150 points, the user programs the value 0x00 to Register Address 0x88 and the value 0x96 to Register Address 0x89. Once the three parameter values are programmed, the sweep is initiated by issuing a start frequency sweep command to the control register at Register Address 0x80 and Register Address 0x81 (see the Register Map section). Bit D2 in the status register (Register Address 0x8F) indicates the completion of the frequency measurement for each sweep point. Incrementing to the next frequency sweep point is under the control of the user. The measured result is stored in the two register groups that follow: 0x94, 0x95 (real data) and 0x96, 0x97 (imaginary data) that should be read before issuing an increment frequency command to the control register to move to the next sweep point. There is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register. This has the benefit of allowing the user to average successive readings. When the frequency sweep has completed all frequency points, Bit D3 in the status register is set, indicating the completion of the sweep. Once this bit is set, further increments are disabled. Rev. C | Page 13 of 32 AD5934 Data Sheet FREQUENCY SWEEP COMMAND SEQUENCE RECEIVE STAGE The following sequence must be followed to implement a frequency sweep: The receive stage comprises a current-to-voltage amplifier, followed by a programmable gain amplifier (PGA), antialiasing filter, and ADC. The receive stage schematic is shown in Figure 17. The unknown impedance is connected between the VOUT and VIN pins. The first stage current-to-voltage amplifier configuration means that a voltage present at the VIN pin is a virtual ground with a dc value set at VDD/2. The signal current that is developed across the unknown impedance flows into the VIN pin and develops a voltage signal at the output of the current-to-voltage converter. The gain of the current-to voltage amplifier is determined by a user-selectable feedback resistor connected between Pin 4 (RFB) and Pin 5 (VIN). It is important for the user to choose a feedback resistance value which, in conjunction with the selected gain of the PGA stage, maintains the signal within the linear range of the ADC (0 V to VDD). Enter standby mode. Prior to issuing a start frequency sweep command, the device must be placed in standby mode by issuing an enter standby mode command to the control register (Register Address 0x80 and Register Address 0x81). In this mode, the VOUT and VIN pins are connected internally to ground so there is no dc bias across the external impedance or between the impedance and ground. 2. Enter initialize mode. In general, high Q complex circuits require a long time to reach steady state. To facilitate the measurement of such impedances, this mode allows the user full control of the settling time requirement before entering start frequency sweep mode where the impedance measurement takes place. An initialize with start frequency command to the control register enters initialize mode. In this mode, the impedance is excited with the programmed start frequency but no measurement takes place. The user times out the required settling time before issuing a start frequency sweep command to the control register to enter the start frequency sweep mode. 3. Enter start frequency sweep mode. The user enters this mode by issuing a start frequency sweep command to the control register. In this mode, the ADC starts measuring after the programmed number of settling time cycles elapses. The user can program an integer number of output frequency cycles (settling time cycles) to Register Address 0x8A and Register Address 0x8B before beginning the measurement at each frequency point (see Figure 24). The DDS output signal is passed through a programmable gain stage to generate the four ranges of peak-to-peak output excitation signals listed in Table 5. The peak-to-peak output excitation voltage is selected by setting Bit D10 and Bit D9 in the control register (see the Control Register section) and is made available at the VOUT pin. RFB R 5×R C R VIN R ADC VDD/2 LPF 05325-038 1. Figure 17. Receive Stage The PGA allows the user to gain the output of the current-tovoltage amplifier by a factor of 5 or 1 depending upon the status of Bit D8 in the control register (see the Register Map section Register Address 0x80). The signal is then low-pass filtered and presented to the input of the 12-bit, 250 kSPS ADC. The digital data from the ADC is passed directly to the DSP core of the AD5934 that performs a DFT on the sampled data. DFT OPERATION A DFT is calculated for each frequency point in the sweep. The AD5934 DFT algorithm is represented by X( f ) = 1023 ∑ n=0 (x(n)(cos(n) − j sin(n))) where: X(f) is the power in the signal at the Frequency Point f. x(n) is the ADC output. cos(n) and sin(n) are the sampled test vectors provided by the DDS core at the Frequency f. The multiplication is accumulated over 1024 samples for each frequency point. The result is stored in two 16-bit registers representing the real and imaginary components of the result. The data is stored in twos complement format. Rev. C | Page 14 of 32 Data Sheet AD5934 IMPEDANCE CALCULATION MAGNITUDE CALCULATION IMPEDANCE CALCULATION USING GAIN FACTOR The first step in the impedance calculation for each frequency point is to calculate the magnitude of the DFT at that point. The next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedance. For this example, assume that the unknown impedance is 510 kΩ. The DFT magnitude is given by R2 + I 2 where: R is the real number stored at Register Address 0x94 and Register Address 0x95. I is the imaginary number stored at Register Address 0x96 and Register Address 0x97. For example, assume the results in the real data and imaginary data registers are as follows at a frequency point: After measuring the unknown impedance at a frequency of 30 kHz, assume that the real data and imaginary data registers contain the following data: Real Data Register = 0xFA3F = −1473 decimal Imaginary Data Register = 0x0DB3 = +3507 decimal Magnitude = ((−1473)2 + (3507)2 ) = 3802.863 The measured impedance at the frequency point is then given by Impedance = Real Data Register = 0x038B = 907 decimal Imaginary Data Register = 0x0204 = 516 decimal Magnitude = 2 = 2 (907 + 516 ) = 1043.506 To convert this number into impedance, it must be multiplied by a scaling factor called the gain factor. The gain factor is calculated during the calibration of the system with a known impedance connected between the VOUT and VIN pins. Once the gain factor is calculated, it can be used in the calculation of any unknown impedance between the VOUT and VIN pins. GAIN FACTOR CALCULATION 1 Ω = 509.791 kΩ 515.819273 × 10 −12 × 3802.863 GAIN FACTOR VARIATION WITH FREQUENCY Because the AD5934 has a finite frequency response, the gain factor also shows a variation with frequency. This variation in gain factor results in an error in the impedance calculation over a frequency range. Figure 18 shows an impedance profile based on a single-point gain factor calculation. To minimize this error, the frequency sweep should be limited to as small a frequency range as possible. 101.5 An example of a gain factor calculation follows, with these assumptions: 101.0 IMPEDANCE (kΩ) Output excitation voltage = 2 V p-p Calibration impedance value, ZCALIBRATION = 200 kΩ PGA gain = ×1 Current-to-voltage amplifier gain resistor = 200 kΩ Calibration frequency = 30 kHz 1 Gain Factor × Magnitude The typical contents of the real data and imaginary data registers after a frequency point conversion would then be VDD = 3.3V CALIBRATION FREQUENCY = 60kHz TA = 25°C MEASURED CALIBRATION IMPEDANCE = 100kΩ 100.5 100.0 99.5 99.0 05325-085 Magnitude = Real Data Register = 0xF064 = −3996 decimal 98.5 54 Imaginary Data Register = 0x227E = +8830 decimal Magnitude = ( − 3996 )2 + (8830)2 = 9692.106 56 58 60 62 64 66 FREQUENCY (kHz) Figure 18. Impedance Profile Using a Single-Point Gain Factor Calculation Gain Factor = 1 Impedance Admittance = Code Magnitude 1 200 kΩ = 515.819 × 10 −12 Gain Factor = 9692.106 Rev. C | Page 15 of 32 AD5934 Data Sheet 2-POINT CALIBRATION GAIN FACTOR SETUP CONFIGURATION Alternatively, it is possible to minimize this error by assuming that the frequency variation is linear and adjusting the gain factor with a 2-point calibration. Figure 19 shows an impedance profile based on a 2-point gain factor calculation. When calculating the gain factor, it is important that the receive stage is operating in its linear region. This requires careful selection of the excitation signal range, current-to-voltage gain resistor and PGA gain. The gain through the system shown in Figure 20 is given by 101.5 Output Excitation Voltage Range × Gain Setting Resistor × PGA Gain ZUNKNOWN 100.5 CURRENT-TO-VOLTAGE GAIN SETTING RESISTOR 100.0 RFB 99.5 VOUT ZUNKNOWN VIN 99.0 05325-086 98.5 54 VDD/2 56 58 60 62 64 66 LPF Figure 20. System Voltage Gain For this example, assume the following system settings: FREQUENCY (kHz) VDD = 3.3 V Gain setting resistor = 200 kΩ ZUNKNOWN = 200 kΩ PGA setting = ×1 Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation 2-POINT GAIN FACTOR CALCULATION This is an example of a 2-point gain factor calculation assuming the following: Output excitation voltage = 2 V p-p Calibration impedance value, ZUNKNOWN = 100.0 kΩ PGA gain = ×1 Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 100 kΩ Calibration frequencies = 55 kHz and 65 kHz The peak-to-peak voltage presented to the ADC input is 2 V p-p. However, had the user chosen a PGA gain of ×5, the voltage would saturate the ADC. GAIN FACTOR RECALCULATION The gain factor must be recalculated for a change in any of the following parameters: Typical values of the gain factor calculated at the two calibration frequencies read Gain factor calculated at 55 kHz is 1.031224 × 10−9. Gain factor calculated at 65 kHz is 1.035682 × 10−9. Difference in gain factor (ΔGF) is 1.035682 × 10−9 − 1.031224 × 10−9 = 4.458000 × 10−12. Frequency span of sweep (ΔF) is 10 kHz. ADC PGA (×1 OR ×5) • • • Therefore, the gain factor required at 60 kHz is given by 4.458000E - 12 × 5 kHz + 1.031224 × 10 -9 10 kHz The required gain factor is 1.033453 × 10−9. The impedance is calculated as previously described in the Impedance Calculation section. Rev. C | Page 16 of 32 Current-to-voltage gain setting resistor Output excitation voltage PGA gain 05325-089 IMPEDANCE (kΩ) 101.0 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz TA = 25°C MEASURED CALIBRATION IMPEDANCE = 100kΩ Data Sheet AD5934 GAIN FACTOR TEMPERATURE VARIATION Where the gain factor is given by The typical impedance error variation with temperature is in the order of 30 ppm/°C. Figure 21 shows an impedance profile with a variation in temperature for 100 kΩ impedance using a 2-point gain factor calibration. 101.5 +125°C 100.5 +25°C 100.0 –40°C 99.5 99.0 98.5 54 VDD = 3.3V CALIBRATION FREQUENCY = 60kHz MEASURED CALIBRATION IMPEDANCE = 100kΩ 56 58 60 62 05325-087 IMPEDANCE (kΩ) 101.0 64 66 1 Admittance Impedance Gain Factor = = Code Magnitude The user must calibrate the AD5934 system for a known impedance range to determine the gain factor before any valid measurement can take place. Therefore, the user must know the impedance limits of the complex impedance (ZUNKNOWN) for the sweep frequency range of interest. The gain factor is simply determined by placing a known impedance between the input/ output of the AD5934 and measuring the resulting magnitude of the code. The AD5934 system gain settings need to be chosen to place the excitation signal in the linear region of the on-board ADC. Because the AD5934 returns a complex output code made up of real and imaginary components, the user is also able to calculate the phase of the response signal through the signal path of the AD5934. The phase is given by the following formula: Phase (rads) = tan−1(I/R) FREQUENCY (kHz) Figure 21. Impedance Profile Variation with Temperature Using a 2-Point Gain Factor Calibration IMPEDANCE ERROR Refer to Circuit Note CN-0217 on the AD5933 product page, which highlights a method to improve accuracy. The EVALAD5933EBZ board can be used to evaluate the AD5934 performance. (3) The phase measured by Equation 3 accounts for the phase shift introduced to the DDS output signal as it passes through the internal amplifiers on the transmit and receive side of the AD5934, along with the low-pass filter, and also the impedance connected between the VOUT and VIN pins of the AD5934. MEASURING THE PHASE ACROSS AN IMPEDANCE The parameters of interest for many users are the magnitude of the impedance (|ZUNKNOWN|) and the impedance phase (ZØ).The measurement of the impedance phase (ZØ) is a 2-step process. The AD5934 returns a complex output code made up of a separate real and imaginary components. The real component is stored at Register Address 0x94 and Register Address 0x95, and the imaginary component is stored at Register Address 0x96 and Register Address 0x97 after each sweep measurement. These correspond to the real and imaginary components of the DFT and not the resistive and reactive components of the impedance under test. The first step involves calculating the AD5934 system phase. The AD5934 system phase can be calculated by placing a resistor across the VOUT and VIN pins of the AD5934 and calculating the phase (using Equation 3) after each measurement point in the sweep. By placing a resistor across the VOUT and VIN pins, there is no additional phase lead or lag introduced to the AD5934 signal path, and the resulting phase is due entirely to the internal poles of the AD5934, that is, the system phase. For example, it is a common misconception to assume that if a user was analyzing a series RC circuit that the real value stored in Register Address 0x94 and Register Address 0x95 and the imaginary value stored in Register Address 0x96 and Register Address 0x97 would correspond to the resistance and capacitive reactance, respectfully. However, this is incorrect because the magnitude of the impedance (|Z|) can be calculated by calculating the magnitude of the real and imaginary components of the DFT given by the following formula: Once the system phase is calibrated using a resistor, the second step involves calculating the phase of any unknown impedance can be calculated by inserting the unknown impedance between the VIN and VOUT terminals of the AD5934 and recalculating the new phase (including the phase due to the impedance) using the same formula. The phase of the unknown impedance (ZØ) is given by Magnitude = R2 + I 2 After each measurement, multiply it by the calibration term and invert the product. Therefore, the magnitude of the impedance is given by the following formula: Impedance = 1 Gain Factor × Magnitude ZØ = (Φunknown − ∇system ) where: ∇system is the phase of the system with a calibration resistor connected between VIN and VOUT. Φunknown is the phase of the system with the unknown impedance connected between VIN and VOUT. ZØ is the phase due to the impedance, that is, the impedance phase. Rev. C | Page 17 of 32 AD5934 Data Sheet As previously outlined, if the user wants to determine the phase angle of the capacitive impedance (ZØ), the user first must determine the system phase response ( ∇system ) and subtract this from the phase calculated with the capacitor connected between VOUT and VIN (Φunknown). Figure 22 shows the AD5934 system phase response calculated using a 220 kΩ calibration resistor (RFB = 220 kΩ, PGA = ×1) and the repeated phase measurement with a 10 pF capacitive impedance. –100 –90 –80 –70 –60 –50 –40 –30 –20 One important point to note about the phase formula used to plot Figure 22 is that it uses the arctangent function that returns a phase angle in radians and, therefore, it is necessary to convert from radians to degrees. –10 0 0 30k 45k 60k 75k 90k 105k FREQUENCY (Hz) 120k Figure 23. Phase Response of a Capacitor 200 Therefore, the correct standard phase angle is dependent upon the sign of the real and imaginary components, which is summarized in Table 6. 180 160 SYSTEM PHASE (Degrees) 15k 05325-091 The excitation signal current leads the excitation signal voltage across a capacitor by −90 degrees. Therefore, an approximate −90 degrees phase difference between the system phase responses measured with a resistor and the system phase responses measured with a capacitive impedance exists. quadrant, the arctangent formula returns a negative angle, and it is necessary to add an additional 180° to calculate the correct standard angle. Likewise, when the real and imaginary components are both negative, that is, when data lies in the third quadrant, the arctangent formula returns a positive angle, and it is necessary to add an additional 180° to calculate the correct standard phase. When the real component is positive and the imaginary component is negative, that is, the data lies in the fourth quadrant, the arctangent formula returns a negative angle, and it is necessary to add an additional 360° to calculate the correct standard phase. PHASE (Degrees) Note that it is possible to calculate the gain factor and to calibrate the system phase using the same real and imaginary component values when a resistor is connected between the VOUT and VIN pins of the AD5934, for example, measuring the impedance phase (ZØ) of a capacitor. 220kΩ RESISTOR 140 120 Table 6. Phase Angle 100 Real Positive Imaginary Positive Quadrant First Phase Angle Positive Negative Second 180° 180° + tan −1 (I −R) × π Negative Negative Third 180° 180° + tan −1 (I −R) × π Negative Positive Fourth 180° 360° + tan −1 (I −R) × π 80 10pF CAPACITOR 60 40 20 0 15k 30k 45k 60k 75k 90k 105k FREQUENCY (Hz) 120k 05325-090 0 Figure 22. System Phase Response vs. Capacitive Phase The phase difference (that is, ZØ) between the phase response of a capacitor and the system phase response using a resistor is the impedance phase of the capacitor (ZØ) and is shown in Figure 23. In addition, when using the real and imaginary values to interpret the phase at each measurement point, care should be taken when using the arctangent formula. The arctangent function only returns the correct standard phase angle when the sign of the real and imaginary values are positive, that is, when the coordinates lie in the first quadrant. The standard angle is taken counterclockwise from the positive real x-axis. If the sign of the real component is positive and the sign of the imaginary component is negative, that is, the data lies in the second tan −1 (I −R) × 180° π Once the magnitude of the impedance (|Z|) and the impedance phase angle (ZØ, in radians) are correctly calculated, it is possible to determine the magnitude of the real (resistive) and imaginary (reactive) components of the impedance (ZUNKNOWN) by the vector projection of the impedance magnitude onto the real and imaginary impedance axis using the following formulas: The real component is given by |ZREAL| = |Z| × cos(ZØ) The imaginary component is given by Rev. C | Page 18 of 32 |ZIMAG| = |Z| × sin(ZØ) Data Sheet AD5934 PERFORMING A FREQUENCY SWEEP PROGRAM FREQUENCY SWEEP PARAMETERS INTO RELEVANT REGISTERS (1) START FREQUENCY REGISTER (2) NUMBER OF INCREMENTS REGISTER (3) FREQUENCY INCREMENT REGISTER PLACE THE AD5934 INTO STANDBY MODE. RESET: BY ISSUING A RESET COMMAND TO THE CONTROL REGISTER, THE DEVICE IS PLACED IN STANDBY MODE. PROGRAM INITIALIZE WITH START FREQUENCY COMMAND TO THE CONTROL REGISTER. AFTER A SUFFICIENT AMOUNT OF SETTLING TIME HAS ELAPSED, PROGRAM START FREQUENCY SWEEP COMMAND IN THE CONTROL REGISTER. POLL STATUS REGISTER TO CHECK IF THE DFT CONVERSION IS COMPLETE. N Y PROGRAM THE INCREMENT FREQUENCY OR THE REPEAT FREQUENCY COMMAND TO THE CONTROL REGISTER. READ VALUES FROM REAL AND IMAGINARY DATA REGISTERS. Y POLL STATUS REGISTER TO CHECK IF FREQUENCY SWEEP IS COMPLETE. N PROGRAM THE AD5934 INTO POWER-DOWN MODE. Figure 24. Frequency Sweep Flowchart Rev. C | Page 19 of 32 05325-047 Y AD5934 Data Sheet REGISTER MAP Table 7. Register Name Control Register Address 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8F 0x94 0x95 0x96 0x97 Start Frequency Frequency Increment Number of Increments Number of Settling Time Cycles Status Real Data Imaginary Data CONTROL REGISTER (REGISTER ADDRESS 0x80, REGISTER ADDRESS 0x81) The AD5934 contains a 16-bit control register (Register Address 0x80 and Register Address 0x81) that sets the control modes. The default value of the control register upon reset is as follows: D15 to D0 is reset to 0xA000 upon power-up. The four MSBs of the control register are decoded to provide control functions, such as performing a frequency sweep, powering down the part, and controlling various other functions defined in the control register map. The user can choose to write only to Register Address 0x80 and to not alter the contents of Register Address 0x81. Note that the control register should not be written to as part of a block write command. The control register also allows the user to program the excitation voltage and set the system clock. A reset command to the control register does not reset any programmed values associated with the sweep (that is, start frequency, number of increments, frequency increment). After a reset command, an initialize with start frequency command must be issued to the control register to restart the frequency sweep sequence (see Figure 24). Table 8. D10 to D9 Control Register Map D10 0 0 1 1 D9 0 1 0 1 Range No. 1 3 4 2 Output Voltage Range 2.0 V p-p typical 200 mV p-p typical 400 mV p-p typical 1.0 V p-p typical Bits D15 to D8 D7 to D0 D23 to D16 D15 to D8 D7 to D0 D23 to D16 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 D7 to D0 D15 to D8 D7 to D0 D15 to D8 D7 to D0 Function Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read only Read only Table 9. D11 and D8 to D0 Control Register Map Bits D11 D8 D7 D6 D5 D4 D3 D2 D1 D0 Description No operation PGA gain; 0 = ×5, 1 = ×1 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Reset External system clock; set to 1 Internal system clock; set to 0 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Table 10. D15 to D12 Control Register Map D15 0 0 0 0 0 1 1 1 1 1 1 Rev. C | Page 20 of 32 D14 0 0 0 0 1 0 0 0 0 1 1 D13 0 0 1 1 0 0 0 1 1 0 0 D12 0 1 0 1 0 0 1 0 1 0 1 Description No operation Initialize with start frequency Start frequency sweep Increment frequency Repeat frequency No operation No operation Power-down mode Standby mode No operation No operation Data Sheet AD5934 Control Register Decode Initialize with Start Frequency This command enables the DDS to output the programmed start frequency for an indefinite time. Initially, it is used to excite the unknown impedance. When the output unknown impedance has settled after a time determined by the user, the user must initiate a start frequency sweep command to begin the frequency sweep. Start Frequency Sweep In this mode, the ADC starts measuring after the programmed number of settling time cycles has elapsed. The user has the ability to program an integer number of output frequency cycles (settling time cycles) to Register Address 0x8A and Register Address 0x8B before the commencement of the measurement at each frequency point (see Figure 24). START FREQUENCY REGISTER (REGISTER ADDRESS 0x82, REGISTER ADDRESS 0x83, REGISTER ADDRESS 0x84) The start frequency register contains the 24-bit digital representation of the frequency from where the subsequent frequency sweep is initiated. For example, if the user requires the sweep to start from a frequency of 30 kHz using a 16.0 MHz clock, the user must program the value 0x3D to Register Address 0x82, the value 0x70 to Register Address 0x83, and the value 0xA3 to Register Address 0x84. Doing this ensures the output frequency starts at 30 kHz. The start frequency code is Start Frequency Code = 30 kHz × 2 27 ≡ 0x3D70A3 16 MHz 16 Increment Frequency The increment frequency command is used to step to the next frequency point in the sweep. This usually happens after data from the previous step is transferred and verified by the DSP. When the AD5934 receives this command, it waits for the programmed number of settling time cycles before beginning the ADC conversion process. Repeat Frequency There is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register. This command allows users to average successive readings. Power-Down Mode The default state at power-up of the AD5934 is power-down mode. The control register contains the code 1010,0000,0000,0000 (0xA000). In this mode, both the output and input pins, VOUT and VIN, are connected internally to GND. The default value of the start frequency register upon reset is as follows: D23 to D0 are not reset at power-up. After the reset command, the contents of this register are not reset. FREQUENCY INCREMENT REGISTER (REGISTER ADDRESS 0x85, REGISTER ADDRESS 0x86, REGISTER ADDRESS 0x87) The frequency increment register contains a 24-bit representation of the frequency increment between consecutive frequency points along the sweep. For example, if the user requires an increment step of 30 Hz using a 16.0 MHz clock, the user must program the value 0x00 to Register Address 0x85, the value 0x0F to Register Address 0x86, and the value 0xBA to Register Address 0x87. The formula for calculating the frequency increment is given by Frequency Increment Code = Standby Mode 10 Hz 27 16 MHz × 2 ≡ 0x00053E 16 This mode powers up the part for general operation. In standby mode, the VIN and VOUT pins are internally connected to GND. Reset A reset command allows the user to interrupt a sweep. The start frequency, number of increments, and frequency increment register contents are not overwritten. An initialize with start frequency command is required to restart the frequency sweep command sequence. Output Voltage Range The user programs the value 0x00 to Register Address 0x85, the value 0x05 to Register Address 0x86, and the value 0x3E to Register Address 0x87. The default value of the frequency increment register upon reset is as follows: D23 to D0 are not reset at power-up. After the reset command, the contents of this register are not reset. The output voltage range allows the user to program the excitation voltage range at VOUT. PGA Gain The PGA gain allows the user to amplify the response signal into the ADC by a multiplication factor of ×5 or ×1. Rev. C | Page 21 of 32 AD5934 Data Sheet NUMBER OF INCREMENTS REGISTER (REGISTER ADDRESS 0x88, REGISTER ADDRESS 0x89) The default value of the number of increments register upon reset is as follows: D8 to D0 are not reset at power-up. After a reset command, the contents of this register are not reset. Table 11. Number of Increments Register Reg Addr 0x88 0x89 Bits D15 to D9 Description Don’t care D8 Number of increments Function Read or write Read or write Number of increments Read or write D7 to D0 Format Integer number stored in binary format Integer number stored in binary format This register determines the number of frequency points in the frequency sweep. The number of frequency points is represented by a 9-bit word, D8 to D0. D15 to D9 are don’t care bits. This register in conjunction with the start frequency register and the frequency increment register determine the frequency sweep range for the sweep operation. The maximum number of increments that can be programmed is 511. NUMBER OF SETTLING TIME CYCLES REGISTER (REGISTER ADDRESS 0x8A, REGISTER ADDRESS 0x8B) The default value of the number of settling time cycles register upon reset is as follows: D10 to D0 are not reset at power-up. After a reset command, the contents of this register are not reset. This register determines the number of output excitation cycles allowed to passthrough the unknown impedance after receipt of a start frequency sweep, increment frequency, or repeat frequency command, before the ADC is triggered to perform a conversion of the response signal. The number of settling time cycles register value determines the delay between a start frequency sweep/ increment frequency/repeat frequency command and the time an ADC conversion commences. The number of cycles is represented by a 9-bit word, D8 to D0. The value programmed into the number of settling time cycles register can be increased by a factor of 2 or 4, depending on the status of Bits D10 to D9. The five most significant bits, D15 to D11, are don’t care bits. The maximum number of output cycles that can be programmed is 511 × 4 = 2044 cycles. For example, consider an excitation signal of 30 kHz, the maximum delay between the programming of this frequency and the time that this signal is first sampled by the ADC is ≈ 511 × 4 × 33.33 µs = 68.126 ms. The ADC takes 1024 samples, and the result is stored as real data and imaginary data in Register Address 0x94 to Register Address 0x97. The conversion process takes approximately 1 ms using a 16.777 MHz clock. STATUS REGISTER (REGISTER ADDRESS 0x8F) The status register is used to confirm that particular measurement tests have been successfully completed. Each of the bits from D7 to D0 indicate the status of a specific functionality of the AD5934. Bit D0 and Bit D4 to Bit D7 are treated as don’t care bits; these bits do not indicate the status of any measurement. The status of Bit D1 indicates the status of a frequency point impedance measurement. This bit is set when the AD5934 completes the current frequency point impedance measurement. This bit indicates that there is valid real data and imaginary data in Register Address 0x94 to Register Address 0x97. This bit is reset on receipt of a start frequency sweep, increment frequency, repeat frequency, or reset command. This bit is also reset at power-up. The status of Bit D2 indicates the status of the programmed frequency sweep. This bit is set when all programmed increments to the number of increments register are complete. This bit is reset at power-up and on receipt of a reset command. Table 12. Status Register 0x8F Control Word 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Description Reserved Valid real/imaginary data Frequency sweep complete Reserved Reserved Reserved Reserved Reserved Table 13. Number of Settling Times Cycles Register Register Address 0x8A 0x8B Bits D15 to D11 D10 to D9 D8 D7 to D0 Description Don’t care 2-bit decode D10 D9 Description 0 0 Default 0 1 No of cycles ×2 1 0 Reserved 1 1 No of cycles ×4 MSB number of settling time cycles Number of settling time cycles Rev. C | Page 22 of 32 Function Read or write Format Integer number stored in binary format Read or write Data Data Sheet AD5934 Valid Real/Imaginary Data This bit is set when data processing for the current frequency point is finished, indicating real/imaginary data available for reading. The bit is reset when a start frequency sweep/increment frequency/repeat frequency DDS command is issued. In addition, this bit is reset to 0 when a reset command is issued to the control register. Frequency Sweep Complete This bit is set when data processing for the last frequency point in the sweep is complete. This bit is reset when a start frequency sweep command is issued to the control register. This bit is also reset when a reset command is issued to the control register. REAL AND IMAGINARY DATA REGISTERS (16 BITS— REGISTER ADDRESS 0x94, REGISTER ADDRESS 0x95, REGISTER ADDRESS 0x96, REGISTER ADDRESS 0x97) These registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point. The values are stored in 16-bit, twos complement format. To convert this number to an actual impedance value, the magnitude, (Real 2 + Imaginary 2 ) , must be multiplied by an admittance/code number (called a gain factor) to give the admittance and the result inverted to give the impedance. The gain factor varies for each ac excitation voltage/gain combination. The default value upon reset: these registers are not reset at power-up or on receipt of a reset command. Note that the data in these registers is only valid if Bit D1 in the status register is set, indicating that the processing at the current frequency point is complete. Rev. C | Page 23 of 32 AD5934 Data Sheet SERIAL BUS INTERFACE Control of the AD5934 is carried out via the I2C-compliant serial interface protocol. The AD5934 is connected to this bus as a slave device under the control of a master device. The AD5934 has a 7-bit serial bus slave address. When the device is powered up, it has a default serial bus address, 0001101 (0x0D). Data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high can be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before performing a read operation, it is sometimes necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. GENERAL I2C TIMING Figure 25 shows the timing diagram for general read and write operations using the I2C-compliant interface. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (SDA) while the serial clock line (SCL) remains high. This indicates that a data stream follows. The slave responds to the start condition and shifts in the next 8 bits, consisting of a 7-bit slave address (MSB first) and an R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). When all data bytes are read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. The slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master writes to the slave device. If the R/W bit is 1, the master reads from the slave device. SCL 0 START CONDITION BY MASTER 0 0 1 1 SLAVE ADDRESS BYTE 0 1 R/W D7 D6 ACKNOWLEDGED BY AD5934 Figure 25. Timing Diagram Rev. C | Page 24 of 32 D5 D4 D3 D2 REGISTER ADDRESS D1 D0 ACKNOWLEDGED BY MASTER/SLAVE 05325-048 SDA Data Sheet AD5934 WRITING/READING TO THE AD5934 The I2C interface specification defines several different protocols for different types of read and write operations. This section describes the protocols used in the AD5934. The figures in this section use the abbreviations shown in Table 14. Condition Start Stop Read Write Acknowledge No acknowledge write byte/command byte Address Pointer 6. The master sends a data byte (a register address to where the pointer is to point). 7. The slave asserts an acknowledge on SDA. 8. The master asserts a stop condition on SDA to end the transaction. S SLAVE ADDRESS W A POINTER COMMAND 1011 0000 REGISTER ADDRESS TO POINT TO A A P Figure 27. Setting Address Pointer to Register Address BLOCK WRITE In this operation, the master device writes a block of data to a slave device (see Figure 28). The start address for a block write must previously have been set. In the case of the AD5934, this is done by setting a pointer to set the register address. 1. The master device asserts a start condition on SDA. Write Byte/Command Byte 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. 4. The master sends an 8-bit command code (1010 0000) that tells the slave device to expect a block write. 5. The slave asserts an acknowledge on SDA. In this operation, the master device sends a byte of data to the slave device. The write byte can either be a data byte write to a Register Address or it can be a command operation. To write data to a register, the command sequence is as follows (see Figure 26): 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 6. The master sends a data byte that tells the slave device the number of data bytes to be sent to it. 7. The slave asserts an acknowledge on SDA. 8. The master sends the data bytes. 9. The slave asserts an acknowledge on SDA after each data byte. 3. The addressed slave device asserts an acknowledge on SDA. 4. The master sends a register address. 5. The slave asserts an acknowledge on SDA. 10. The master asserts a stop condition on SDA to end the transaction. 6. The master sends a data byte. 7. The slave asserts an acknowledge on SDA. SLAVE ADDRESS P 4. The master sends a pointer command code (see Table 15, an address pointer = 1011 0000). 5. The slave asserts an acknowledge on SDA. Code Description This command is used when writing multiple bytes to the RAM; see the Block Write section. This command is used when reading multiple bytes from RAM/memory; see the Block Read section. This command enables the user to set the address pointer to any location in the memory; the data contains the address of the register to which the pointer should be pointing. S A 05325-050 1011 0000 REGISTER DATA W A BLOCK WRITE A NUMBER BYTES WRITE A BYTE 0 Figure 28. Writing a Block Write Rev. C | Page 25 of 32 A BYTE 1 A BYTE 2 A P 05325-051 Block Read A 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. Table 15. Command Codes 1010 0001 REGISTER ADDRESS To set a register pointer, the following sequence is applied: 1. The master device asserts a start condition on SDA. The command codes in Table 15 are used for reading/writing to the interface. They are explained in detail in this section but are grouped within Table 15 for easy reference. Code Name Block Write A In the AD5934, the write byte protocol is also used to set a pointer to a register address (see Figure 27). This protocol is used for a subsequent single-byte read from the same address, block read, or block write starting at that address. User Command Codes Command Code 1010 0000 W Figure 26. Writing Register Data to Register Address Table 14. I2C Abbreviation Table Abbreviation S P R W A A SLAVE ADDRESS S 05325-049 8. The master asserts a stop condition on SDA to end the transaction. AD5934 Data Sheet READ OPERATIONS Block Read The AD5934 uses two I2C read protocols: the receive byte and the block read. In this operation, the master device reads a block of data from a slave device (see Figure 30). The start address for a block read must previously have been set by setting the address pointer. Receive Byte In the AD5934, the receive byte protocol is used to read a single byte of data from a register address whose address has previously been set by setting the address pointer. In this operation, the master device receives a single byte from a slave device as follows (see Figure 29): 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. 3. 4. 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts an acknowledge on SDA. 4. The master receives a data byte. 7. 8. 5. The master asserts a no acknowledge on SDA (the slave needs to check that master has received data). 9. 6. The master asserts a stop condition on SDA and the transaction ends. R A REGISTER DATA A P The master sends the 7-bit slave address followed by the read bit (high). 10. The slave asserts an acknowledge on SDA. 11. The master receives the data bytes. 12. The master asserts an acknowledge on SDA after each data byte. 13. A no acknowledge is generated after the last byte to signal the end of the read. 14. The master asserts a stop condition on SDA to end the transaction. Figure 29. Reading Register Data S SLAVE ADDRESS W A BLOCK READ A The master sends a byte-count data byte that tells the slave how many data bytes to expect. The slave asserts an acknowledge on SDA. The master asserts a repeat start condition on SDA. This is required to set the read bit high. NUMBER BYTES READ A S SLAVE ADDRESS R A Figure 30. Performing a Block Read Rev. C | Page 26 of 32 BYTE 0 A BYTE 1 A BYTE 2 A P 05325-053 SLAVE ADDRESS 6. 05325-052 S 5. The master sends a command code (1010 0001) that tells the slave device to expect a block read. The slave asserts an acknowledge on SDA. Data Sheet AD5934 TYPICAL APPLICATIONS MEASURING SMALL IMPEDANCES The AD5934 is capable of measuring impedance values up to 10 MΩ if the system gain settings are chosen correctly for the impedance subrange of interest. If the user places a small impedance value (≤500 Ω over the sweep frequency of interest) between the VOUT and VIN pins, it results in an increase in signal current flowing through the impedance for a fixed excitation voltage in accordance with Ohm’s law. The output stage of the transmit side amplifier available at the VOUT pin may not be able to provide the required increase in current through the impedance. To have a unity gain condition about the receive side I-V amplifier, the user needs to have a similar small value of feedback resistance for system calibration as outlined in the Gain Factor Setup Configuration section. The voltage presented at the VIN pin is hard biased at VDD/2 due to the virtual earth on the receive side I-V amplifier. The increased current sink/source requirement placed on the output of the receive side I-V amplifier may also cause the amplifier to operate outside of the linear region. This causes significant errors in subsequent impedance measurements. The value of the output series resistance, ROUT, (see Figure 31) at the VOUT pin must be taken into account when measuring small impedances (ZUNKNOWN), specifically when the value of the output series resistance is comparable to the value of the impedance under test (ZUNKNOWN). If the ROUT value is unaccounted for in the system calibration (that is, the gain factor calculation) when measuring small impedances, there is an introduced error into any subsequent impedance measurement that takes place. The introduced error depends on the relative magnitude of the impedance being tested compared to the value of the output series resistance. 2V p-p TRANSMIT SIDE OUTPUT AMPLIFIER R2 DDS VDD 20kΩ VDD/2 RFB 20kΩ 1µF AD8531 AD820 AD8641 AD8627 RFB I-V VIN ZUNKNOWN VDD/2 Figure 31. Additional External Amplifier Circuit for Measuring Small Impedances 05324-148 PGA Table 16. Output Series Resistance (ROUT) vs. Excitation Range Parameter Range 1 Range 2 Range 3 Range 4 Value (Typ) 2 V p-p 1 V p-p 0.4 V p-p 0.2 V p-p Output Series Resistance Value 200 Ω typical 2.4 kΩ typical 1.0 kΩ typical 600 Ω typical Therefore, to accurately calibrate the AD5934 to measure small impedances, it is necessary to reduce the signal current by attenuating the excitation voltage sufficiently and also account for the ROUT value and factor it into the gain factor calculation (see the Gain Factor Calculation section). Measuring the ROUT value during device characterization is achieved by selecting the appropriate output excitation range at VOUT and sinking and sourcing a known current at the pin (for example, ±2 mA) and measuring the change in dc voltage. The output series resistance can be calculated by measuring the inverse of the slope (that is, 1/slope) of the resultant I-V plot. A circuit that helps to minimize the effects of the issues previously outlined is shown in Figure 31. The aim of this circuit is to place the AD5934 system gain within its linear range when measuring small impedances by using an additional external amplifier circuit along the signal path. The external amplifier attenuates the peak-to-peak excitation voltage at VOUT by a suitable choice of resistors (R1 and R2), thereby reducing the signal current flowing through the impedance and minimizing the effect of the output series resistance in the impedance calculations. In the circuit shown in Figure 31, ZUNKNOWN recognizes the output series resistance of the external amplifier which is typically much less than 1 Ω with feedback applied depending upon the op amp device used (for example, AD820, AD8641, AD8531) as well as the load current, bandwidth, and gain. R1 ROUT VOUT The value of the output series resistance depends upon the selected output excitation range at VOUT and has a tolerance from device to device like all discrete resistors manufactured in a silicon fabrication process. Typical values of the output series resistance are outlined in Table 16. The key point is that the output impedance of the external amplifier in Figure 31 (which is also in series with ZUNKNOWN) has a far less significant effect on gain factor calibration and subsequent impedance readings in comparison to connecting the small impedance directly to the VOUT pin (and directly in series with ROUT). The external amplifier buffers the unknown impedance from the effects of ROUT and introduces a smaller output impedance in series with ZUNKNOWN. Rev. C | Page 27 of 32 AD5934 Data Sheet For example, if the user measures ZUNKNOWN that is known to have a small impedance value within the range of 90 Ω to 110 Ω over the frequency range of 30 kHz to 32 kHz, the user may not be in a position to measure ROUT directly in the factory/lab. Therefore, the user may choose to add on an extra amplifier circuit like that shown in Figure 31 to the signal path of the AD5934. The user must ensure that the chosen external amplifier has a sufficiently low output series resistance over the bandwidth of interest in comparison to the impedance range under test (for an op amp selection guide, see www.analog.com/opamps). Most amplifiers from Analog Devices have a curve of closed-loop output impedance vs. frequency at different amplifier gains to determine the output series impedance at the frequency of interest. The system settings are as follows: VDD = 3.3 V VOUT = 2 V p-p R2 = 20 kΩ R1 = 4 kΩ Gain setting resistor = 500 Ω ZUNKNOWN = 100 Ω PGA setting = ×1 To attenuate the excitation voltage at VOUT, choose a ratio of R1/R2. With the values of R1 = 4 kΩ and R2 = 20 kΩ, attenuate the signal by 1/5th of 2 V p-p = 400 mV. The maximum current flowing through the impedance is 400 mV/ 90 Ω = 4.4 mA. The system is subsequently calibrated using the usual method with a midpoint impedance value of 100 Ω, a calibration resistor, and a feedback resistor at a midfrequency point in the sweep. The dynamic range of the input signal to the receive side of the AD5934 can be improved by increasing the value of the I-V gain resistor at the RFB pin. For example, increasing the I-V gain setting resistor at the RFB pin increases the peak-to-peak signal presented to the ADC input from 400 mV (RFB = 100 Ω) to 2 V p-p (RFB = 500 Ω). The gain factor calculated is for a 100 Ω resistor connected between VOUT and VIN, assuming the output series resistance of the external amplifier is small enough to be ignored. When biasing the circuit shown in Figure 31, note that the receive side of the AD5934 is hard-biased about VDD/2 by design. Therefore, to prevent the output of the external amplifier (attenuated AD5934 Range 1 excitation signal) from saturating the receive side amplifiers of the AD5934, a voltage equal to VDD/2 must be applied to the noninverting terminal of the external amplifier. BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE MEASUREMENT When a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes place whereby the impedance of the blood under certain conditions changes. By characterizing this effect across different frequencies, it is possible to detect a specific strain of virus. For example, a strain of the disease exhibits a certain characteristic impedance at one frequency but not at another, resulting in the need to sweep different frequencies to check for different viruses. The AD5934, with its 27-bit phase accumulator, allows for subhertz frequency tuning. The AD5934 can be used to inject a stimulus signal through the blood sample via a probe. The response signal is analyzed and the effective impedance of the blood is tabulated. The AD5934 is ideal for this application because it allows the user to tune to the specific frequency required for each test. 1 16 2 15 3 TOP VIEW 14 (Not to Scale) 4 13 5 12 6 11 7 10 8 9 RFB ADuC702x TOP VIEW (Not to Scale) AD5934 PROBE 7V 2 ADR43x 6 10µF 4 Figure 32. Measuring a Blood Sample for a Strain of Virus Rev. C | Page 28 of 32 05325-057 0.1µF Data Sheet AD5934 SENSOR/COMPLEX IMPEDANCE MEASUREMENT ELECTRO-IMPEDANCE SPECTROSCOPY The operational principle of a capacitive proximity sensor is based on the change of a capacitance in a RLC resonant circuit. This leads to changes in the resonant frequency of the RLC circuit, which can be evaluated as shown Figure 33. The AD5934 has found use in the area of corrosion monitoring. Corrosion in a metal, such as aluminum, which is used in air craft and ships, requires continuous assessment because the metal is exposed to a wide variety of conditions, such as temperature and moisture. The AD5934 offers an accurate and compact solution for this type of measurement compared to the large and expensive existing units on the market. It is first required to tune the RLC circuit to the area of resonance. At the resonant frequency, the impedance of the RLC circuit is at a maximum. Therefore, a programmable frequency sweep and tuning capability is required, which is provided by the AD5934. CHANGE IN RESONANCE DUE TO APPROACHING OBJECT PROXIMITY IMPEDANCE (Ω) RESONANT FREQUENCY Mathematically the corrosion of a metal is modeled using a RC network that consists of a resistance, RS, in series with a parallel resistor and capacitor, RP and CP. A system metal would typically have values as follows: RS is 10 Ω to 10 kΩ, RP is 1 kΩ to 1 MΩ, and CP is 5 µF to 70 µF. FO FREQUENCY (Hz) 05325-058 The frequency range of interest when monitoring corrosion is 0.1 Hz to 100 kHz. Figure 33. Detecting a Change in Resonant Frequency An example of the use of this type of sensor is for a train proximity measurement system. The magnetic fields of the train approaching on the track change the resonant frequency to an extent that can be characterized. This information can be sent back to a mainframe system to show the train location on the network. To ensure that the measurement itself does not introduce a corrosive effect, the metal needs to be excited with minimal voltage, typically in the 200 mV region, which the AD5934 is capable of outputting. A nearby processor or control unit, such as the ADuc702x, would log a single impedance sweep from 0.1 kHz to 100 kHz every 10 minutes and download the results back to a control unit. To achieve system accuracy from the 0.1 kHz to 1 kHz region, the system clock needs to be scaled down from the 16.776 MHz nominal clock frequency to 500 kHz, typically. The clock scaling can be achieved digitally using an external direct digital synthesizer, such as the AD9834, as a programmable divider that supplies a clock signal to MCLK and that can be controlled digitally by the nearby microprocessor. Another application for the AD5934 is in parked vehicle detection. The AD5934 is placed in an embedded unit connected to a coil of wire underneath the parking location. The AD5934 outputs a single frequency within the 80 kHz to 100 kHz frequency range, depending upon the wire composition. The wire can be modeled as a resonant circuit. The coil is calibrated with a known impedance value and at a known frequency. The impedance of the loop is monitored constantly. If a car is parked over the coil, the impedance of the coil changes and the AD5934 detects the presence of the car. Rev. C | Page 29 of 32 AD5934 Data Sheet LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5934 should have separate analog and digital sections, each having its own area of the board. If the AD5934 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5934. The power supply to the AD5934 should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be physically as close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and effective series inductance (ESI); common ceramic types of capacitors are suitable. The 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. C | Page 30 of 32 Data Sheet AD5934 OUTLINE DIMENSIONS 6.50 6.20 5.90 9 16 5.60 5.30 5.00 1 8.20 7.80 7.40 8 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150-AC 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 34. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5934YRSZ AD5934YRSZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 16-Lead Shrink Small Outline Package (SSOP) 16-Lead Shrink Small Outline Package (SSOP) Z = RoHS Compliant Part. Rev. C | Page 31 of 32 Package Option RS-16 RS-16 AD5934 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05325-0-7/12(C) Rev. C | Page 32 of 32