AN84783 - Accurate Measurement Using PSoC 3 and PSoC 5LP Delta-Sigma ADCs.pdf

AN84783
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Author: Nidhin M S
Associated Project: Yes
Associated Part Family: PSoC 3 and PSoC 5LP
Software Version: PSoC Creator™3.1 and higher
For a complete list of the application notes, click here.
AN84783 shows how to increase the accuracy of measurements using the 20-bit Delta-Sigma ADC in PSoC 3 and
PSoC 5LP. Major topics include effective resolution, gain and offset errors, nonlinearity, and accuracy improvement
techniques. A spreadsheet is provided to assist ADC performance analysis and to optimize ADC Component
configuration.
Contents
Introduction
Introduction .......................................................................1
ADC Parameters ...............................................................2
Resolution ....................................................................2
Effective Resolution ......................................................3
Peak-to-Peak Resolution ..............................................3
Offset Error ...................................................................4
Gain Error .....................................................................4
Differential Nonlinearity Error .......................................5
Integral Nonlinearity Error.............................................5
Common-Mode Rejection Ratio ...................................5
Power Supply Rejection Ratio ......................................5
How to Achieve High Accuracy .........................................6
Analog Signal Chain Selection .....................................6
Configuring the ADC for High Accuracy .......................6
Using an External Reference........................................7
Offset and Gain Calibration ..........................................7
Correlated Double Sampling ........................................7
Using Filters on ADC Counts........................................7
PCB Design ..................................................................8
Example Project: DelSig_Analyzer ....................................9
Example Project: DelSig_I2C .......................................... 11
ADC Performance Analyzer Spreadsheet .................. 12
Summary ......................................................................... 17
Related Application Notes ............................................... 17
Worldwide Sales and Design Support ............................. 19
Accurate measurement of physical quantities is important
for many applications. In most measurement systems, you
use a transducer to convert a physical quantity to a
voltage. This voltage is sent through signal conditioning
circuitry, if necessary, and then to an analog-to-digital
converter (ADC).
®
PSoC 3 and PSoC 5LP integrate the signal-conditioning
circuitry, ADC, microcontroller, and other peripherals (such
2
as I C, Segment LCD, PWM, and so on) into a single chip.
You can easily create high-precision analog systems using
the integrated, highly configurable, 20-bit Delta-Sigma
ADC.
The accuracy of an overall measurement system depends
on the accuracy of its components: the transducer, the
PCB and its layout, the noise in the environment, the
signal processing circuitry, and the ADC. This application
note focuses on those portions of the system that are
within PSoC—the signal-processing circuitry and the ADC.
It describes how to configure the PSoC Delta-Sigma ADC
for maximum accuracy. A spreadsheet tool is provided
with this application note to assist with ADC performance
analysis and optimizing ADC Component configuration.
This application note assumes that you are familiar with
developing applications using PSoC Creator™ for PSoC 3
or PSoC 5LP. If you are new to these products, see
AN54181 – Getting Started with PSoC 3 or AN77759 –
Getting Started with PSoC 5LP. If you are new to PSoC
Creator, see the PSoC Creator home page.
A list of related application notes is available in Related
Application Notes on page 17.
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Document No. 001-84783 Rev. *B
1
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
ADC Parameters
This section describes various Delta-Sigma ADC parameters and how they affect measurement accuracy. Table 1 shows a
summary of these parameters. For a complete list of Delta-Sigma ADC specifications, see the Delta-Sigma ADC Component
datasheet.
Table 1. Delta-Sigma ADC Parameters
Max Value
Parameter
Condition
PSoC 3
Maximum resolution
PSoC 5LP
20 bits
20 bits
Offset error
Buffered, 16-bit mode, 25 °C
±0.1 mV
±0.2 mV
Gain error
Range = ±1.024 V, buffered, buffer gain = 1, 16-bit mode, 25 °C
±0.2 %
±0.4 %
Differential nonlinearity
Range = ±1.024 V, unbuffered, 16-bit mode
±1 LSB
±1 LSB
Integral nonlinearity
Range = ±1.024 V, unbuffered, 16-bit mode
±2 LSB
±2 LSB
Common-mode rejection ratio
Range = ±1.024 V, buffered, buffer gain = 1, 16-bit mode
85 dB
85 dB
Power-supply rejection ratio
Range = ±1.024 V, buffered, buffer gain = 1, 16-bit mode
90 dB
90 dB
Table 2. Ideal ADC Voltage Resolution, Range = ±1.024 V
Resolution
The resolution of an ADC is the number of discrete digital
values (numbers or counts) that it can produce over the
analog input range. It is expressed in bits. An ADC with a
resolution of ‘n’ bits can encode an analog input to one of
n
2 different counts.
Resolution can also be expressed as the minimum voltage
that can be resolved by the ADC. This term is known as
voltage resolution. The voltage resolution of an ADC is
given by Equation 1.
where n is the ADC's resolution in bits.
The PSoC Delta-Sigma ADC can achieve a resolution as
high as 20 bits. If the input voltage range is ±1.024 V (the
default for this ADC), the voltage resolution is given by
Equation 2.
The ideal (perfect) voltage resolution of the PSoC DeltaSigma ADC for a range of ±1.024 V is given in Table 2.
Having many bits of resolution does not always mean that
all of the bits are usable. In practice, when you do
continuous measurements of the same input voltage at
high resolutions, the last few bits flicker due to the
presence of noise. So a 20-bit ADC with a noisy amplifier
front end no longer has a 20-bit resolution—the resolution
is limited by the amplifier noise. A high-resolution
application needs a high-resolution system and not just a
high-resolution ADC. The estimated level (RMS value) of
the noise gives the useful resolution of the ADC.
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Bits
Ideal voltage
resolution
Unit
8
8.0
mV
9
4.0
mV
10
2.0
mV
11
1.0
mV
12
0.5
mV
13
0.25
mV
14
125.0
µV
15
62.5
µV
16
31.3
µV
17
15.6
µV
18
7.8
µV
19
3.9
µV
20
2.0
µV
You can use Table 2 and the estimated system noise level
to determine the effective number of bits (ENOB, also
known as effective resolution). If the ADC ideal voltage
resolution is greater than the noise level, then the ADC
can operate at its specified number of bits. For example, if
the noise level is 10 µV and the ADC is operating at 16
bits, the noise level is less than the ideal resolution and
the ADC can in fact operate at 16 bits. However, if the
ADC is operating at 20 bits, the effective resolution is
actually between 17 and 18 bits.
Document No. 001-84783 Rev. *B
2
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Effective Resolution
The previous examples show that to determine the
effective resolution (ENOB) of an ADC you need to know
the system noise level. A simple way to measure the noise
is to determine the dispersion of the output counts of the
ADC. Measure a constant voltage many times and make a
histogram of the ADC output count dispersion, as Figure 1
shows.
Figure 1. Example of ADC Count Dispersion at 16-Bit
Resolution
100
ENOB is a commonly used parameter to indicate ADC
system performance, but it does not necessarily show the
number of bits that do not flicker. To obtain the number of
stable (flicker-free—bits), use peak-to-peak resolution
instead.
Peak-to-Peak Resolution
Peak-to-peak resolution is obtained from peak-to-peak
noise. The difference between the maximum and minimum
ADC counts across many measurements of a constant
voltage input gives the peak-to-peak noise counts (p). Use
Equation 5 to determine the peak-to-peak noise voltage
from the peak-to-peak noise counts (p).
90
count dispersion of an
ideal (noise-free) system
80
Then you
Equation 6.
can
get
peak-to-peak
resolution
from
70
Signal-to-noise ratio (SNR) is another measure of signal
chain performance. SNR is the ratio of RMS signal power
to RMS noise power. For a constant (DC) voltage input,
SNR is calculated as the ratio of maximum input voltage
and RMS noise voltage, as Equation 7 shows.
60
%
50
40
30
SNR is often expressed in decibels, as Equation 8 shows.
20
count dispersion of
a noisy system
10
16164
16163
16161
16162
16160
16159
16158
16157
16155
16156
16154
16153
16152
16151
16150
0
Counts
The RMS value of the system noise level in counts is
given by the standard deviation (σ) of the ADC’s output
counts. The RMS noise in counts is converted to RMS
noise in volts by Equation 3.
where n is the ADC's resolution in bits.
Then, you can get the ENOB from Equation 4.
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Document No. 001-84783 Rev. *B
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Figure 3. Gain Error
The input offset voltage of the ADC causes a
measurement error known as offset error. For example,
Figure 2 shows the transfer characteristics of an ideal
ADC and an ADC with an offset error. The red line
indicates the characteristics of an 8-bit ADC operating with
an input voltage range of 0 to 1.024 V with an offset of
32 mV.
256
224
160
128
The offset error causes a fixed additive error in all
measurements. It also causes a shift in the ADC input
voltage range. For example, the 32-mV offset shown in
Figure 2 brings the maximum input voltage down from
1.024 V to 992 mV.
You can get the offset of the ADC by measuring the ADC
output value for a zero input voltage.
Figure 2. Offset Error
256
96
64
Ideal ADC
32
0
0
0.128
0.256
0.384
0.512
0.640
0.768
0.896
1.024
Input Voltage (Volts)
The blue line shows the ideal transfer characteristics, and
the red line shows the characteristics with a gain error of
15 percent (K = 1.15).
Equation 11 gives the combined transfer function of an
ADC with gain and offset errors.
224
ADC with 32mV offset
192
Counts
ADC with 15% gain error
(K=1.15)
192
Counts
Offset Error
160
128
96
Figure 4 shows a plot of the combined transfer function.
64
Ideal ADC
Figure 4. Combined ADC Transfer Function
32
0
0
0.128
0.256
0.384
0.512
0.640
0.768
0.896
256
1.024
224
Input Voltage (Volts)
ADC with gain and offset
errors
192
Table 1 on page 2 shows the maximum offset voltages of
Delta-Sigma ADCs in PSoC 3 and PSoC 5LP.
Counts
160
128
96
64
Gain Error
Ideal ADC
32
Gain error is the deviation of the ADC characteristics from
the ideal slope of the ADC transfer function. Equation 9
gives the ideal ADC transfer function.
0
0
0.128
0.256
0.384
0.512
0.640
0.768
0.896 1.024
Input Voltage (Volts)
Table 1 on page 2 shows the maximum gain errors of
Delta-Sigma ADCs in PSoC 3 and PSoC 5LP.
where n is the ADC's resolution in bits.
Any multiplicative factor 'K' causes a gain error, as
Equation 10 shows.
You can reduce the gain and offset errors by calibrating
the ADC. See Offset and Gain Calibration for more details.
Figure 3 shows a plot of Equations 9 and 10 for an 8-bit
ADC measurement with an input range of 0 to 1.024 V.
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Document No. 001-84783 Rev. *B
4
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Differential Nonlinearity Error
Common-Mode Rejection Ratio
When the input voltage changes from one voltage level to
the next adjacent level, an ideal ADC steps up or down
one LSB without skipping a count or holding the same
count. Differential nonlinearity (DNL) error describes the
maximum deviation from the ideal step size of 1 LSB
between ADC counts corresponding to two adjacent input
analog levels across the entire input range.
When the ADC is in differential mode, the ADC input
voltage is the difference between the voltages on two
inputs: + input and – input. The common-mode rejection
ratio (CMRR) of an ADC in differential mode is the ability
of the ADC to filter out the input signals that are common
to both inputs.
DNL errors can cause inaccurate count values at specific
analog input levels. DNL is a function of the ADC
architecture and is difficult to calibrate. Figure 5 shows an
example of ADC characteristics with DNL.
Figure 5. DNL Example
In most applications, the relevant information is contained
in the voltage difference between two differential inputs,
and the noise is common to both terminals. Therefore, an
ADC with high CMRR rejects the noise common to both
terminals while preserving the relevant differential signal
information.
CMRR is often expressed in decibels, as Equation 12
shows.
16
Count 12 missing
14
Counts
12
10
8
Ideal ADC
6
Short step
DNL = 2 LSB
4
Power Supply Rejection Ratio
Non-monotonic,
Missing count 8
2
Long step
0
0
4
8
12
16 20 24 28
32 36 40 44
where ADM is the gain of the differential mode signals and
ACM is the gain of the common-mode signals.
48 52 56 60 64
Input Voltage (mV)
Integral Nonlinearity Error
When DNL errors add up, they create an integral
nonlinearity (INL) error. An INL error is a measure of the
worst case deviation of the ADC transfer function from the
ideal ADC transfer function.
Power supply rejection ratio (PSRR) describes the amount
of noise from the power supply that an ADC can reject. In
a practical ADC, a change in power supply voltage may
cause a change in the ADC’s output counts. This change
in output counts is generally seen as an input voltage
change produced by the power supply voltage change.
PSRR is calculated as the ratio of the change in supply
voltage to the corresponding change in the (differential)
ADC input voltage. It is often expressed in decibels, as
Equation 13 shows.
Figure 6 shows an example of an ideal ADC output (blue
line) and an ADC with INL (red line).
Figure 6. INL Example
16
INL = 2 LSB
(maximum
deviation)
12
Counts
8
4
0
ADC transfer
function with INL
-4
-8
-12
Ideal ADC transfer
function
-16
-64 -56 -48 -40 -32 -24 -16 -8 0 8 16 24 32 40 48 56 64
Input Voltage (mV)
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Document No. 001-84783 Rev. *B
5
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
How to Achieve High Accuracy
This section explains different techniques to improve the accuracy of ADC measurements.
Analog Signal Chain Selection
Configuring the ADC for High Accuracy
The accuracy of ADC measurements depends not only on
the ADC but also on the front-end analog system. If
analog front-end components have a lower accuracy than
the ADC, they determine the overall measurement
accuracy.
Figure 8 shows a configuration of the Delta-Sigma ADC
Component for high accuracy.
Figure 8. ADC Configuration
First, look at an example of poor signal chain selection.
Figure 7 shows a signal chain in which a Programmable
Gain Amplifier (PGA) Component is used to amplify the
input voltage of a Delta-Sigma ADC.
Figure 7. Signal Chain Example
1
2
3
4
5
The PSoC 3 and PSoC 5LP PGA has an input offset
voltage of 10 mV, a gain error of ±2.5 percent (at a gain of
16), a DC output nonlinearity of ±0.01 percent for the fullscale range, and a PSRR of 48 dB. Even though the ADC
has significantly better specifications, the overall system
performance is limited by the PGA. Therefore, this setup is
not recommended for high-precision measurements.
Similarly, if you use one of the PSoC Opamp Components
as a front-end amplifier, the Opamp specifications dictate
the overall system performance. Instead, you should use
the built-in input buffer of the Delta-Sigma ADC, which
provides high impedance as well as a gain of 1, 2, 4, or 8.
See the next section to know how to configure the ADC
input buffer.
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6
In this example, the ADC is configured for a continuous
sampling rate of 100 sps. For 20-bit continuous sampling,
sample rates from 8 to 187 samples per second are
possible.
Set other configuration parameters as follows:
1.
Conversion Mode: Select this mode for continuous
conversion if you have a single input channel. Do not
use this mode when multiple signals are multiplexed
and measured with a single ADC. If you have multiple
input channels, you should use Multi-Sample or MultiSample (Turbo) mode. See the Delta-Sigma ADC
Component datasheet to learn how to use these
modes.
2.
Resolution: Select the maximum value of 20 bits for
high-precision applications.
3.
Input Mode: Select differential input mode to improve
CMRR and reduce external noise that is common to
both input terminals.
Document No. 001-84783 Rev. *B
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
4.
Input Range: Select the delta-sigma modulator gain.
Table 3 lists differential ranges and the corresponding
gains.
Table 3. ADC Modulator
Input Range
Modulator Gain
6.
You can use calibration techniques to correct any gain
error or offset error that varies from one device to another.
This can eliminate the gain and offset errors from the
entire signal chain.
The Delta-Sigma ADC in PSoC has a post-processing
block consisting of gain and offset calibration registers.
Calibration can be applied to the ADC by writing the
appropriate values into these registers. For more
information, see AN68403 – PSoC 3 and PSoC 5LP
Analog Signal Chain Calibration.
Input ± 6 * Vref
0.167
Input ± 2 * Vref
0.5
Input ± Vref
1
Input ± 0.5 * Vref
2
Input ± 0.25 * Vref
4
Correlated Double Sampling
Input ± 0.125 * Vref
8
Input ± 0.0625 * Vref
16
The offset and gain correction from the previous section is
valid at a specific temperature; however, both offset and
gain error change with temperature. Correlated double
sampling (CDS) can reduce the offset drift with
temperature.
When the Input ± Vref range is selected, the deltasigma modulator operates at unity gain. This
configuration yields the highest accuracy; it uses the
internal 1.024-V reference. As the delta-sigma
modulator gain increases, the gain error also
increases.
5.
Offset and Gain Calibration
Buffer Mode: The Delta-Sigma ADC has a built-in
buffer that gives gain and high input impedance to the
ADC. You should use this buffer if your input signal
requires amplification or impedance matching. If the
input source is strong and has low output impedance,
then you do not require the high input impedance of
the buffer. In that case, you can bypass the buffer to
eliminate buffer noise.
Reference: The 1.024-V reference yields the best
accuracy among the internal references available in
PSoC 3 and PSoC 5LP. You can add an external
capacitor on port 0[3] or port 3[2] to decrease the
reference noise. See the Delta-Sigma ADC
Component datasheet for information on selecting a
suitable bypass capacitor value.
Using an External Reference
The accuracy of the ADC measurements also depends on
the accuracy of the voltage reference. The internal
1.024-V voltage reference in PSoC 3 and PSoC 5LP has
an accuracy of 0.1 percent and a maximum temperature
drift of 30 ppm/°C. For most applications, this reference is
sufficient.
CDS is a signal-processing technique that is used to
suppress low-frequency (1/f) noise and null any offset. For
more information on correlated double sampling, see
AN66444 – PSoC 3 and PSoC 5LP Correlated Double
Sampling to Reduce Offset, Drift, and Low Frequency
Noise.
Using Filters on ADC Counts
Filtering the output counts of the ADC decreases the noise
in the counts, and increases the number of flicker-free bits.
You should use a filter that is suitable for your
requirement. For example, if you want 17 flicker-free bits
from a 20-bit conversion, use a filter that decreases the
(20 - 17)
peak-to-peak noise to 2
= 8 counts.
You can use either the digital filter block (DFB) in PSoC 3
and PSoC 5LP or firmware to filter the ADC counts.
Firmware filters are commonly used because they are
easy to implement. For more information on firmware
filters, see AN2099 – PSoC 1, PSoC 3, PSoC 4, and
PSoC 5LP Single-Pole Infinite Impulse Response (IIR)
Filters.
If you require a higher accuracy, you can connect a highprecision external voltage reference generator such as
LM4140 to port 0[3] or port 3[2]. The value of the external
reference voltage should be within 0.9 to 1.3 V. Change
the "Reference" option in the Component configuration to
External Vref and set the value of Vref (see step 6 in the
previous ADC configuration).
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Document No. 001-84783 Rev. *B
7
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
PCB Design
Poorly designed printed circuit boards can significantly limit the performance of an ADC-based measurement system. The
following is a list of important rules to keep in mind when designing high-precision mixed-signal boards.
1.
Consider separate analog and digital supplies.
2.
Use four-layer boards with power planes, if possible.
3.
Separate analog and digital signals and components on the board, if possible. Designate "Analog" and "Digital" areas of
the PCB.
4.
Do not run analog signals parallel to clocks or fast digital signals.
5.
Keep analog signals close to the ground plane to minimize inductive crosstalk.
6.
Use guard traces to isolate analog and digital signals.
7.
If analog and digital signals must cross, make the intersection at 90 degrees to minimize coupling capacitance. Keep
bypass capacitors as close to ICs as possible. Also, make sure that bypass connections to power signals are lowimpedance. Avoid long traces into a high-impedance input, as they act as antennas.
For more details, see AN57821 – PSoC 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations and
AN61290 – PSoC 3 and PSoC 5LP Hardware Design Considerations.
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Document No. 001-84783 Rev. *B
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Example Project: DelSig_Analyzer
RMS noise in input voltage
Mean value of input voltage





Maximum value of ADC counts

SNR
Maximum value of input voltage
This project supports the CY8CKIT-030 and CY8CKIT-050
development kits.
This PSoC Creator example project does performance
analysis of the PSoC Delta-Sigma ADC. By making many
continuous measurements of a constant input voltage, the
project calculates several parameters:





Mean value of ADC counts


Minimum value of input voltage
Minimum value of ADC counts
Peak-to-peak noise in ADC counts
Peak-to-peak noise in voltage
ENOB
Peak-to-peak resolution
Figure 9 shows the TopDesign schematic of this example
project.
Standard deviation in ADC counts
Figure 9. Delta-Sigma Analyzer TopDesign
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Document No. 001-84783 Rev. *B
9
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
The ADC is configured for a resolution of 20 bits and a
sample rate of 100 sps. The CPU calculates the ADC
parameters from 512 consecutive ADC samples. The
calculated parameters are then displayed on the character
LCD. Figure 10 shows the firmware flow for this project.
4.
Press SW2 on the development kit to start the ADC
conversion and calculation of parameters. The LCD
shows the message "Reading Samples, Please Wait"
until calculations are finished.
5.
Use the CapSense buttons on the development kit to
toggle the ADC parameter displays. The parameter
menu is arranged in the following order.
Figure 10. DelSig_Analyzer Firmware Flow













Boot
Scan CapSense
and SW2
SW2
Pressed?
N
Display the
parameter selected
by the CapSense
buttons
Y
Read 512
ADC samples and
calculate parameters
Follow these steps to view the ADC parameters on the
character LCD:
®
6.
Mean value of ADC counts
Mean value of input voltage
Maximum value of ADC counts
Maximum value of input voltage
Minimum value of ADC counts
Minimum value of input voltage
Standard deviation in ADC counts
RMS noise in input voltage
Peak-to-peak noise in ADC counts
Peak-to-peak noise in voltage
ENOB
Peak-to-peak resolution
SNR
Try repeating the analysis with different voltage
sources or ADC Component configurations.
1.
Build the project and program the PSoC device.
2.
Connect a 10-µF capacitor between pin P0[3] and
GND to bypass the internal reference.
You can easily adapt this project to test the performance
of your hardware design.
3.
Make external connections as Figure 9 on page 9
shows. Connect the low-noise, constant voltage
source between pins P4[6] (Pin_Input_Pos) and P4[7]
(Pin_Input_Neg). Make sure that this voltage is within
the ADC’s range (±1.024 V).
If your PCB does not have any CapSense buttons, edit the
project and replace the CapSense buttons with
mechanical buttons. If you do not have a character LCD in
your design, you can send the calculated ADC parameters
2
through I C or UART and view them using a PC.
Note This project measures the analog performance of
your entire signal chain, including the input, board layout,
and any other components in front of the ADC. You should
make sure that your input voltage is noise-free if you are
testing the system performance. DC power supplies and
potentiometers are usually very noisy. You can use a lownoise, precision voltage reference IC to generate the input
voltage. In this case, make sure that the noise level of the
reference is well below the noise floor of the system.
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Document No. 001-84783 Rev. *B
10
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Example Project: DelSig_I2C
This example project, together with the ADC Performance Analyzer Spreadsheet included with this application note, calculates
the same parameters as those in Example Project: DelSig_Analyzer. You can also view the ADC count noise and ADC count
dispersion (histogram) using the spreadsheet. Figure 11 shows the TopDesign schematic of this example project.
Figure 11. DelSig_I2C TopDesign
The ADC is configured for a resolution of 20 bits and a
sample rate of 100 sps. This project buffers 512
consecutive ADC samples in RAM and then sends them to
2
the PC through the I C interface and the MiniProg3. You
can then use the ADC Performance Analyzer Spreadsheet
to calculate the required parameters.
Figure 12. DelSig_Analyzer Firmware Flow
Boot
Read SW2
Figure 12 shows the firmware flow of this project.
SW2
Pressed?
N
Y
Read 512 ADC
samples. Turn on the
LED4.
Send the samples to
PC via I2C
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Document No. 001-84783 Rev. *B
11
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
ADC Performance Analyzer Spreadsheet
A CY8CKIT-030 or CY8CKIT-050, and a MiniProg3, are
required to use this spreadsheet. Follow these steps:
1.
Program the CY8CKIT-030 or CY8CKIT-050 with the
example project DelSig_I2C.
2.
Connect a 10-µF capacitor between pin P0[3] and
GND to bypass the internal reference.
3.
Make external connections as Figure 11 on page 11
shows. Connect a low-noise, constant voltage source
to
pins
P4[6]
(Pin_Input_Pos)
and
P4[7]
(Pin_Input_Neg). Make sure that this voltage is within
the ADC’s range (±1.024 V).
Note This project measures the analog performance of
your entire signal chain, including the input, board layout,
and any other components in front of the ADC. You should
make sure that your input voltage is noise free if you are
testing the system performance. DC power supplies and
potentiometers are usually very noisy. You can use a lownoise, precision voltage reference IC to generate the input
voltage. In this case, make sure that the noise level of the
reference is well below the noise floor of the system.
4.
Press SW2 on the development kit to start ADC data
buffering. LED4 on the development kit turns on when
the acquisition is complete.
5.
Connect the SDA (P12[1]), SCL (P12[0]), and GND
pins to the SDAT, SCLK, and GND terminals of the
MiniProg3.
6.
Connect the MiniProg3 to the PC using a USB cable.
7.
Open the Bridge Control Panel (Start > All
Programs > Cypress > Bridge Control Panel),
select the MiniProg3 from the connected devices (a),
set the proper voltage (b), and toggle the power (c),
as Figure 13 shows.
The Bridge Control Panel software enables you to
view data collected from various communication
protocols. The PSoC Creator installer automatically
installs this tool along with PSoC Creator.
Figure 13. Powering the MiniProg3
a
b
c
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
8.
In Bridge Control Panel, click the "Open commands file" button, as Figure 14 shows. Then select the
BridgeControlPanel_Script.iic file associated with this application note and click OK.
Figure 14. Opening Command File
9.
Right-click on the status window and select the "Clear Window" option, as Figure 15 shows.
Figure 15. Read ADC Data
10. Click Send in the Bridge Control Panel, as Figure 16 shows, to read the buffered ADC data from the PSoC device.
Figure 16. Read ADC Data
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
11. After the Bridge Control Panel reads the ADC counts from the PSoC device, the status window shows the ADC data as
ASCII characters. Select all of these characters (you can click at the beginning of the first line and drag down, as Figure
17 shows), and then press [Ctrl] [C] to copy the data.
Figure 17. Copying Acquired Data
12. Open the ADC Performance Analyzer Spreadsheet, go to the "Sample Data" tab, single-click on the cell highlighted in
Figure 18, and paste the data copied from the Bridge Control Panel (press [Ctrl] [V]).
Figure 18. Entering Data into Spreadsheet Tool
13. If you have made changes to the example project, edit the values of Voltage Range, Maximum input voltage, and
Resolution. Otherwise keep the default values.
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
14. Go to the "Results" page to view the ADC parameters, as Figure 19 shows.
Figure 19. Results Page
15. Click on the "Graph" page to view the ADC value versus sample number graph, as Figure 20 shows. This graph illustrates
the noise in ADC counts.
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Figure 20. Graph of ADC Counts
16. Go to the "Histogram" page to view the histogram that shows ADC count dispersion, as Figure 21 shows.
Figure 21. Histogram of ADC Counts
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Summary
Related Application Notes
PSoC 3 and PSoC 5LP integrate a high-precision, highly
configurable, 20-bit Delta-Sigma ADC and a variety of
other analog and digital peripherals that can be used to
create high-performance analog systems.
AN68403 – PSoC 3 and PSoC 5LP Analog Signal Chain
Calibration
This application note has shown that the overall accuracy
of a system depends on the accuracy of its components:
the transducer, the PCB and its layout, the noise in the
environment, and the signal processing circuitry as well as
the ADC itself.
This application note has also shown that you can
increase the accuracy of ADC measurements by properly
designing the analog signal chain, properly configuring the
ADC Component, using an external reference, using filters
on the ADC counts, calibrating offset and gain, using
correlated double sampling, and properly designing the
PCB.
Two projects are included that demonstrate how to
measure and calculate various parameters to determine
the actual performance of an ADC-based system.
AN66444 – PSoC 3 and PSoC 5LP Correlated Double
Sampling to Reduce Offset, Drift, and Low Frequency
Noise
AN57821 – PSoC 3, PSoC 4, and PSoC 5LP Mixed Signal
Circuit Board Layout Considerations
AN2099 – PSoC 1, PSoC 3, PSoC 4, and PSoC 5LP
Single-Pole Infinite Impulse Response (IIR) Filters
AN61290 – PSoC 3 and PSoC 5LP Hardware Design
Considerations
About the Author
Name:
Nidhin M S
Title:
Application Engineer
Background:
Nidhin graduated from GEC Thrissur
with a Bachelor's degree in Electronics
and Communication Engineering.
Note that PSoC 5LP has SAR ADCs in addition to a DeltaSigma ADC. The techniques described in this application
note can be adapted and applied to a SAR ADC–based
system.
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Document No. 001-84783 Rev. *B
His technical interests are analog
signal processing, low-power design,
and capacitive touch sensing.
17
Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
Document History
Document Title: Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs - AN84783
Document Number: 001-84783
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
3956316
NIDH
04/05/2013
New application note
*A
4621893
NIDH
01/22/2015
Added information on conversion modes
*B
4651285
NIDH
02/04/2015
Added information on how to use ADC to get accurate readings when the input to
ADC is multiplexed
Minor edits throughout the document
Updated template
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Document No. 001-84783 Rev. *B
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Accurate Measurement Using PSoC® 3 and PSoC 5LP Delta-Sigma ADCs
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