AN2155 PSoC® EMI Design Considerations Author: Dennis Seguine Associated Project: No Associated Part Family: All PSoC 1, PSoC 3, PSoC 4, and PSoC 5LP parts Software Version: NA Related Application Notes: Click here. To get the latest version of this application note, or the associated project file, please visit http://www.cypress.com/go/AN2155. ® AN2155 discusses how to design PSoC array-based systems for compliance with EMC standards, promoting easier qualification of new designs and a more robust, low-cost system design. 1 Introduction Every electronic device is required to comply with specific limits for emitted energy and susceptibility to external upsets. These limits are specified by the FCC in the U.S. and by similar regulatory bodies in other countries. The regulations help ensure that electronic devices will not interfere with each other; for example, your computer will not interfere with your television, or worse, a hospital X-ray machine or ventilator will not corrupt the operation of a critical medical monitor. Modern high-speed digital electronics are capable of generating very high-speed signals that have the potential to radiate substantial amounts of noise. CMOS analog and digital circuits have essentially infinite input impedance. As a result, they can be sensitive to external fields, so suitable precautions must be taken to ensure their proper operation in the presence of large amounts of radiated and conducted (interfering) energy. This application note outlines the basic specifications involved and provides guidance for secure and compliant designs. If you are new to PSoC, refer to the following documents to learn about the device and the available tools: 2 AN75320 – Getting Started with PSoC 1 AN54181 – Getting Started with PSoC 3 AN79953 – Getting Started with PSoC 4 AN77759 – Getting Started with PSoC 5LP Specifications Computing devices are regulated in the U.S. by the FCC under 47 CFR Part 15, Subpart B, “Unintentional Radiators.” The standards for Europe and the rest of the world are adapted from CENELEC. These regulations are covered by the CISPR standards (dual labeled as “EN xxxxx”) for emissions and the IEC standards (also dual labeled as “EN xxxxx”) for immunity and safety concerns. The general emission’s specification is EN 55022 for computing devices. This standard covers both radiated and conducted emissions. Medical devices in the U.S. are not regulated by the FCC, but rather by FDA rules, which include the requirements of EN 55011, the European norm for medical devices. Devices that contain motor controls are covered by EN 55014, and lighting devices are covered by EN 50015. These specifications have essentially similar performance limitations for radiated and conducted emissions. Radiated and conducted immunity (susceptibility) performance requirements are specified by several sections of EN 61000-4. This standard also covers line voltage transients, ESD, and safety issues. www.cypress.com Document No. 001-35343 Rev. *C 1 PSoC® EMI Design Considerations Each section of the electronics industry has its own additional standards. For example, power meters are covered by EN 61036, which calls out specific performance parameters with EN 55022. Power-line communication devices are covered by EN 50065, which includes voltage-level allowances in certain bands and restrictions on harmonic energy from signaling frequencies. 3 Emissions 3.1 Radiated Emissions result primarily as a consequence of digital transients on inputs and outputs. To the greatest extent possible, the bandwidth of digital outputs should be limited. The PSoC 1 device has an I/O limited to 12 MHz by the global bus structure. PSoC 3, 4, and 5LP devices limit the I/Os to 33 MHz, with a selectable slew rate. This clocking limitation provides a first line of defense against radiated emissions. PSoC devices CY8C22xxx, CY8C24xxx, CY8C27xxx, CY8C3xxx, CY8C4xxx, CY8C5xxx and all planned future generations provide the option to enable slower rise and fall times, which limits harmonic energy in the digital outputs. This option is not available in the earlier generation parts, CY8C25xxx and CY8C26xxx. High-speed traces on the board should be kept as short as practical. If the signal leaves the board to drive an external load, it should have a series-terminating resistor at the chip to provide the necessary bandwidth limit. Fifteen to 50 ohms is usually sufficient on high-speed lines. Note that a digital output that is at a logic one is directly connected (by the output P-channel FET's RDS(ON)) to VDD. Thus, the VDD bus is directly connected to the output, and any high-frequency noise that appears on the V DD bus will also appear on the output. It is important to provide a wellcoupled, high-frequency bypass capacitor from VDD to VSS at the PSoC chip. The capacitor bypass traces should be very short, and ground and power planes should be used where possible. ® If you are using CapSense , the capacitive touch sensing feature in PSoC, refer to AN64846 – Getting Started with CapSense for EMI considerations. 3.2 Conducted Emissions result as a function of comparatively low-frequency RF conduction into the power supply system. Placing high-frequency bypass capacitors at the PSoC power pins and a bulk bypass capacitor to support large instantaneous load demands near the PSoC device effectively prevents decoupling of the PSoC chip and its direct loads from the power system. Switching power supply transients are not a PSoC chip problem per se, but they represent the bulk of conducted emissions. Standard design practices for reducing this noise include the use of differential and common mode inductors on the input power connection and the use of high-voltage capacitors from the AC line and AC neutral to earth ground. 4 Susceptibility 4.1 Radiated Electrical energy can influence system measurements and potentially the operation of the processor core. The interference enters the PSoC chip at the printed circuit board level through the pins. Radiated energy is highly unlikely to interfere directly with the chip. Careful board layout, as well as a good PSoC project design, will prevent upsets from radiated energy. These steps include the following: 1. Minimize source impedances (where possible) of signal sources coming to the chip. 2. Minimize loop areas of input signal traces. 3. Use ground planes where possible. 4. Set unused outputs to strong digital output, with logic state to zero. www.cypress.com Document No. 001-35343 Rev. *C 2 PSoC® EMI Design Considerations 4.2 Conducted Electrical energy influences system measurements and upsets the operation of the processor core by driving the PSoC chip's power supply out of range. Power-line inputs should be protected with common mode and differential mode chokes, along with transient voltage suppressors such as metal-oxide varistors (MOVs). For more details, see the following application notes: 5 AN57821 – PSoC 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations AN80994 – PSoC 3, PSoC 4, and PSoC 5LP EMC Best Practices and Recommendations EMI Testing Radiated emission measurements are made first in an anechoic chamber to generate a list of suspect frequencies. The equipment under test is then relocated to an open area test site. Radiated emission measurements are made at the EUT azimuth and antenna height such that the maximum radiated emission level will be detected. This requires the use of a turntable and an antenna positioner that can adjust the antenna’s height as well as shift its orientation from horizontal to vertical. Conducted emission measurements are made over the frequency range from 150 kHz to 30 MHz to determine the line-to-ground radio noise voltage conducted from the device power input terminals that are directly (or indirectly via a separate transformer or power supplies) connected to a public power network. Equipment is tested with power cords that are normally used or that have electrical or shielding characteristics that resemble the cords normally used.. Radiated immunity is measured in a shielded anechoic chamber large enough to contain the system under test and allow adequate control over field strength. The system under test is maintained in uniform field strength. Frequency stepping and power requirements are as specified in the relative standards. The output of the system under test is monitored for disturbance. Conducted immunity is tested by applying the RF signal to external power and signal cables with clamps that surround the cable. In this case, the power and signal cables act as passive, receiving antenna networks. 6 Design Example Cypress development kits are examples of PSoC designs that pass required EMI tests. Figure 1 shows the CY8CKIT-044 PSoC 4 M-Series Pioneer Kit. Figure 1. CY8CKIT-044 You can download the kit design files from the CY8CKIT-044 web page for more information. www.cypress.com Document No. 001-35343 Rev. *C 3 PSoC® EMI Design Considerations Figure 2 and Figure 3 show the radiated emission from the kit in the frequency range of 30 MHz to 1 GHz. Figure 2. Spectral Diagram Measured by a Vertical Antenna Figure 3. Spectral Diagram Measured by a Horizontal Antenna 7 Summary Designing for electromagnetic emissions and susceptibility is a system-level consideration. This application note covered a few generic considerations. The test methodologies for radiated and conducted cases of emission and susceptibility were also described. 8 Related Application Notes AN75320 – Getting Started with PSoC 1 AN54181 – Getting Started with PSoC 3 AN79953 – Getting Started with PSoC 4 AN77759 – Getting Started with PSoC 5LP AN57821 – PSoC 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations AN80994 – PSoC 3, PSoC 4, and PSoC 5LP EMC Best Practices and Recommendations www.cypress.com Document No. 001-35343 Rev. *C 4 PSoC® EMI Design Considerations 9 Design References Designing for EMC considerations is an important and exhaustively published topic. Following are the author’s favorite references: Henry Ott, Noise Reduction Techniques in Electronic Systems, 2nd Edition. John Wiley & Sons. William D. Kimmel and Daryl D. Gerke, Electromagnetic Compatibility in Medical Equipment: A Guide for Designers and Installers. IEEE Press. David Terrell and R. Kenneth Keenan, Digital Design for Interference Specifications: A Practical Handbook for EMI Suppression. Newnes. About the Author Name: Dennis Seguine. Title: Applications Engrg MTS www.cypress.com Document No. 001-35343 Rev. *C 5 PSoC® EMI Design Considerations Document History Document Title: AN2155 – PSoC® EMI Design Considerations Document Number: 001-35343 Revision ECN Orig. of Change Submission Date Description of Change ** 1513664 VED 11/02/2007 Recataloged Application Note *A 3223359 KANT 04/07/2011 Updated title. Updated Abstract. Updated introduction. *B 4363701 QVS 04/28/2014 Updated in new template. Completing Sunset Review. *C 4787186 NIDH 06/18/2015 Included PSoC 4 information Corrected typo Added references to related application notes Updated template Removed the example of obsolete kit and replaced it with CY8CKIT-044 www.cypress.com Document No. 001-35343 Rev. *C 6 PSoC® EMI Design Considerations Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Wireless/RF cypress.com/go/wireless Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support PSoC is a registered trademark and PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone Fax Website : 408-943-2600 : 408-943-4730 : www.cypress.com © Cypress Semiconductor Corporation, 2007-2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-35343 Rev. *C 7