Index

INDEX
INDEX
■
SUBJECT INDEX
■
ANALOG DEVICES PARTS INDEX
Index-a
INDEX
Index-b
INDEX
Subject Index
A
AA Alkaline Battery Discharge
Characteristics, 10.14
Absolute value amplifier, 3.29
Active and Passive Electrical Wave Catalog,
2.42
AD185x, multibit sigma-delta DAC, 4.11
AD260/AD261:
digital isolators
key specifications, 10.38
schematic, 10.38
AD820, op amp, 3.8-9
AD1819B SoundPort, codec, for
audio/modem, 9.37-38
AD1836, mixed-signal IC, codec, 9.38-39
AD1852, sigma-delta audio DAC, 3.17
AD1853:
dual 24-bit DAC, 4.12
sigma-delta audio DAC, 3.17
AD1854, sigma-delta audio DAC, 3.17
AD1877:
16-bit sigma-delta ADC
characteristics, 3.16
FIR filter characteristics, 3.17
AD189x, sample rate converters, 6.35
AD77xx, 24-bit sigma-delta ADC, low
frequency/high resolution, filters,
3.17
AD77XX-Series Data Sheets, 3.33
AD773x, 24-bit ADC, with PGA, 1.5
AD977x, 14-bit TxDAC, 4.6
AD983x, 10-bit DDS system, 4.16
AD985x, 14-bit TxDAC, 4.6
AD5322:
12-bit dual DAC
block diagram, 8.18
power-down feature, 8.17
serial interface, 8.18-19
AD5340:
12-bit parallel input DAC
block diagram, 8.10
interface diagram, 8.12
wait states, 8.11
AD6521, voiceband/baseband mixed-signal
CODEC, 9.21-22
AD6522, DSP-based baseband processor,
9.21-22
AD6523, Zero-IF Transceiver, 9.23
AD6524, Multi-Band Synthesizer, 9.23
AD6600, diversity receiver ADC, 9.30
AD6622, quad digital TSP, 9.30-31
AD6624, quad digital RSP, 9.30-31
AD6640:
12-bit ADC
with MagAmps, 3.24-25
multitone testing, diagram, 2.30
AD6644, 14-bit ADC, 9.30-31
AD7722, 16-bit ADC, 10.15
AD7725:
16-bit sigma-delta ADC
with on-chip PulseDSP filter, 6.2
programmable digital filter, 9.40-42
block diagram, 9.41
Systolix PulseDSP, 9.41
sigma-delta ADC, with Systolix PulseDSP
processor, 3.19-20
AD7730, sigma-delta ADC, 10.15
AD7731, sigma-delta ADC, 10.15
AD7853/7853L:
12-bit ADC, block diagram, 8.16
serial ADC interface, 8.17
AD7853L:
serial clock, 8.15-17
output timing, 8.16
AD7854/AD7854L:
12-bit ADC
block diagram, 8.5
interface diagram, 8.6-7
key interface timing comparisons, 8.5-6
AD7858/59:
12-bit ADC, 3.8-9
SAR ADC, circuit, 3.8-9
AD7892, 12-bit SAR ADC, 10.15
AD9042:
12-bit ADC, NPR, diagram, 2.32
12-bit wideband ADC, high SFDR,
2.27-28
AD9201, 10-bit, dual-channel ADC, 8.22-23
AD9220:
12-bit ADC, SINAD and ENOB, diagram,
2.25
12-bit CMOS ADC, latency or pipeline
delay, 3.27
AD9221, 12-bit CMOS ADC, latency or
pipeline delay, 3.27
AD9223, 12-bit CMOS ADC, latency or
pipeline delay, 3.27
AD9288-100, 8-bit dual ADC, functional
diagram, 3.32
AD9410, 10-bit flash ADC, interpolation,
diagram, 3.23
AD9761, 10-bit, dual channel DAC, 8.22-23
AD9772:
14-bit interpolating DAC, 9.31
14-bit oversampling interpolating
TxDAC, 4.9-10
block diagram, 4.10
14-bit TxDAC, 4.6
Index-1
INDEX
diagram, 4.6
SFDR, 2.39-40
TxDAC 14-bit DAC, 9.30-31
AD9850, DDS/DAC synthesizer system,
diagram, 4.16
AD73322:
block diagram, 8.19-20
simplified interface timing, 8.21
AD73422, dspConverter, specifications, 8.22
AD20msp430:
baseband processing chipset, 9.21-23
components, 9.22-23
construction, 9.21
Adams, R.W., 3.33, 3.34
Adaptive filter, 6.35-39
basic concept, 6.35-36
speech compression and synthesis, 6.36
ADC, 1.2
1-bit, comparator, 3.11
3-bit unipolar, transfer characteristics,
2.8-9
10-bit, theoretical NPR, 2.32
11-bit, theoretical NPR, 2.32
12-bit
pipelined architecture, diagram, 3.7
theoretical NPR, 2.32
24-bit, with PGAs, 1.5
analog bandwidth, 2.25-26
analog input, 2.10
bit-per-stage, 3.1
boot memory select, 8.2
communications application, SFDR, 2.26
conversion complete output, 8.1-2
conversion process, 2.2
convert start, 8.1-2
data memory address, 8.4
data memory select, 8.2
digital output, grounding, 10.22-24
DNL errors, 2.22
DSP applications, 3.1-35
high speed architectures, 3.2
sigma-delta, 3.2
successive approximation, 3.1-9
types, 3.1
dynamic performance, quantification,
2.21
ENOB versus frequency, diagram, 2.26
equivalent input referred noise, 2.20-21
excess DNL, and missing codes, 2.12-13
flash, 3.1
high speed, pipelined, latency, 3.6, 3.8
ideal 12-bit
FFT, noise floor, 2.19
SFDR sampling clock to input
frequency ratio, 2.18
ideal, distortion and noise, 2.15-19
ideal N-bit
Index-2
dynamic performance analysis,
diagram, 2.17
errors, 2.15
quantization noise, diagram, 2.16
input/output memory select, 8.2
low power/low voltage, design issues, 3.1
memory address bus, 8.2
memory read, 8.2
memory select line, 8.2
non-ideal 3-bit, transfer function,
diagram, 2.13
non-monotonic, 2.12
normalized signal to reference, 2.10
output, quantization, 2.7
output enable/read, 8.2
oversampling ratio, 3.11
pipelined, 3.1
latency or pipeline delay, 3.25
timing, diagram, 3.7
practical
distortion and noise, 2.19-20
noise and distortion sources, 2.20
processor interrupt request line, 8.1-2
program memory select, 8.2
quantization error, 2.9-10
quantization uncertainty, 2.9-10
quantized output, 2.9, 2.10
ripple, 3.1
sampling clock jitter, 2.33
sampling frequency, versus antialiasing
characteristics, 2.5
SAR, 3.3
external high frequency clock, 3.6
fundamental timing, 3.5
resolutions, table, 3.5
typical timing, 3.5
sigma-delta, 3.1-2, 3.9-21
circuitry, 3.9-10
as oversampling converter, 2.6
programmable digital filter, 9.40-42
VLSI technology, 3.9
see also Sigma-delta ADC
sign-magnitude, use, 2.10
single-tone sinewave FFT testing, 2.18
SNR decrease with input frequency, 2.33
static transfer functions, DC errors,
2.7-14
subranging, 3.1
pipelined converter, 3.6
successive approximation, 3.1-9
basic, 3.3
resolutions, table, 3.5
see also SAR ADC
thermal noise, 2.20-21
Address bus, DAC, 8.9
ADI DSP collaborative, 7.54
INDEX
ADI modified Harvard architecture, in
microprocessor, 7.6-7
ADI SHARC floating point DSPs, 7.26-30
ADMC300, motor controller, 9.34
ADMC331, motor controller, 9.34
ADMC401, motor controller, 9.34
ADMCF326, motor controller, 9.34
ADMCF328:
motor controller, 9.34
block diagram, 9.35
ADP1148:
synchronous buck regulator, 10.46-50
circuit, 10.47-48
driving ADP3310
circuit diagram, 10.49
waveforms, 10.50
filtered output, 10.49
output waveform, 10.47-48
ADP3310, linear LDO regulator, 10.47,
10.49-50
ADPCM, adaptive pulse code modulation,
1.2
ADSL, 9.11-16
advantages, 9.12-13
block diagram, 9.13
data transmission capability, 9.15
definition, 9.12
installation advantages, 9.14
modem, block diagram, 9.15
modems, three-channel approach, 9.13-14
ADSP-21ESP202, codec, embedded speech
processing, 9.36-37
ADSP-21mod870:
digital modem processor, 9.10
expanding central office capability, 9.9
in voice-based RAS modem, 9.8-9
ADSP-21xx:
16-bit fixed point DSP core, 7.6-23
arithmetic, signed fractional format,
7.23-24
assembly code for FIR filter, 1.8
buses, 7.10-11, 7.11
computational units, 7.11-13
core architecture
diagram, 7.9
summary, 7.10
data address generators and program
sequencer, 7.13-14
digital filter example, 7.7-10
DSP optimized, 7.9
FIR filter assembly code, 7.8
fixed-point DSP, 7.7-8
FIR filter, 6.11-12
assembly code, 6.13
internal buses, 7.10-11
internal peripherals, powerdown, 7.18
memory-write cycle timing diagram, 8.7-8
on-chip peripherals, 7.14-23
byte DMA port, 7.17
internal DMA, 7.17
SPORTs, 7.16
read-cycle, timing diagram, 8.3
serial ports
block diagram, 8.13
features, 8.13
operation, 8.12-14
SPORTs, 7.16
ADSP-218x:
architecture, 7.15
byte memory interface, 7.17
DSP, EZ-ICE, 7.49
implementation, multi-channel VOIP
server, diagram, 9.11
interface with CODEC, 8.20-22
internal direct-memory-access port, 7.16
memory-mapped peripherals, 7.16
modified Harvard architecture, 7.16
multiple core devices, 7.22
on-chip peripherals, memory interface,
7.15
roadmap, 7.22
VisualDSP software, 7.52
ADSP-219x:
architecture, 7.19
code compatibility with ADSP-218x, 7.19
key specifications, 7.20
roadmap, 7.23
VisualDSP software, 7.52
ADSP-2100, core in ADSP-218x
architecture, 7.15
ADSP-2100 EZ-KIT Lite Reference Manual,
7.55, 8.25
ADSP-2100 Family EZ Tools Manual, 7.55,
8.25
ADSP-2100 Family Users Manual, 3rd
Edition, 7.55, 8.25
ADSP-2106x:
characteristics, 7.28
external ports, 7.29
host interface, 7.29
I/O processor, 7.29
IEEE Standard P1149.1 Joint Test Action
Group standard, 7.30
instruction set, 7.28
internal memory, 7.30
multiprocessing systems, 7.29
on-chip DMA, 7.30
SHARC processors, 7.26-27
Super Harvard Architecture, 7.26-28
ADSP-2106x SHARC EZ-KIT Lite Manual,
7.55, 8.25
ADSP-2106x SHARC User's Manual, 2nd
Edition, July 1996, 7.55, 8.25
ADSP-2116x:
Index-3
INDEX
32-bit DSP, second-generation, 7.31
SIMD core architecture, 7.31-36
diagram, 7.31
SIMD DSP, 7.33
SIMD features, 7.32
ADSP-2189M:
69-tap FIR filter, design example, 6.22
75 MIPS DSP
filter subroutine, 6.12
throughput time, 6.28
75 MIPS processor, 6.20
EZ-KIT Lite, 7.47
fixed-point DSP, 6.1
key timing specifications, 8.9-10
parallel read timing, 8.4, 8.7
parallel write interface, timing
specifications, 8.11
serial port, receive timing diagram,
8.14-15
system interface, full memory mode,
diagram, 8.24
ADSP-21000 Family Application Handbook,
5.25, 6.40
ADSP-21060L SHARC, DSP output rise and
fall times, 10.58
ADSP-21065L:
connected to ADC and DAC, 8.22-23
EZ-KIT Lite, 7.48
SHARC, DSP benchmarks, 7.34
ADSP-21065L SHARC EZ-LAB User's
Manual, 7.55, 8.25
ADSP-21065L SHARC User's Manual, Sept.
1, 1998, 7.55, 8.25
ADSP-21160:
16-channel audio mixer, SIMD
architecture, 9.40
32-bit SHARC, key features, 7.32
DSP, BGA package locations, 10.54-55
integrated peripherals, 7.32
SIMD/multiple channels, DSP
benchmarks, 7.34
SISD, DSP benchmarks, 7.34
ADSP-21160 SHARC DSP Hardware
Reference, 7.55, 8.25
ADSP-21160M, EZ-KIT Lite, 7.47
ADSP-TS001:
features, 7.40
TigerSHARC
16-bit fixed-point DSP, 5.18-19
architecture, 7.36-44
benchmarks, 7.44
diagram, 7.38
ADuM1100A, digital isolator, 10.36-37
Advanced mobile phone service see AMPS
Agilent HCPL-7720, 10.36
Aiken, Howard, 7.7
Alfke, P., 10.14
Index-4
Aliasing, 2.2-3
frequency domain, representation, 2.3
All-pole lattice filter, parameters, from
speech samples, 6.38-39
Alternate framing mode, 8.14
Aluminum electrolytic capacitor, 10.40-41
Amplifier Applications Guide (1992), 2.43,
3.35
Amplitude shift keying, POTS, 9.2
Analog bandwidth, ADC, 2.25-26
Analog cellular basestation, 9.27-28
Analog Devices Inc., 16-bit DSP, roadmap,
7.22
Analog Devices' Motor Control Website, 9.44
Analog filter:
frequency response, 6.4
popular types, 6.24, 6.27-28
requirements, 6.3
for oversampling, 4.10
versus digital, 6.3
Analog front end, 8.19-22
Analog receiver design, 9.26-27
Analog return current, 10.16-17
Analog signal:
characteristics, 1.1-2
discrete time sampling, 2.2-7
diagram, 2.1
normalized ratio, 2.9
quantization, 2.2
diagram, 2.1
sampling, aliasing, 2.3
Analog superheterodyne receiver, 9.27
Andreas, D., 3.33
ANSI/IEEE Standard 754-1985, floating
point arithmetic, 7.24-25
Anti-imaging filter, 6.2
Antialiasing filter, 6.2
baseband sampling, oversampling, 2.5
requirements, relaxing, 2.6
specifications, 2.4-5
Aperture delay, 2.33-35
Aperture jitter, 2.33-35, 10.25
Apex-ICE, 7.48-49
USB simulator, 7.49
Application of Digital Signal Processing in
Motion Control Seminar (2000),
9.44
Architecture:
computer
ADI modified Harvard, 7.6
Harvard, 7.6-7
Von Neumann, 7.6
Arithmetic logic unit:
in DSP, 7.4
features, 7.11
Armstrong, Edwin H., Major, 9.27
INDEX
The ARRL Handbook for Radio Amateurs,
4.17
Asymmetric digital subscriber line see
ADSL
Audio system, synthesized, 1.3
Auto-correlation, 1.3
Automotive/home theater, using 32-bit
SHARC, 9.39
B
Backplane ground plane, 10.18
Baines, Rupert, 9.43
Baker, Bonnie, 10.34
Ball grid array, 10.54
Band filter, 10.46
Bandpass filter:
design, 6.23-24
from lowpass and highpass filters, 6.24
Bandpass sampling, 2.6-7
Bandpass sigma-delta ADC, undersampling,
3.18
Bandstop filter:
design, 6.23-24
equivalent impulse response, 6.23
from lowpass and highpass filters, 6.24
Baseband data signal, POTS, 9.2
Baseband sampling:
antialiasing filter, 2.4-6
oversampling, 2.5
Nyquist zone, 2.6
Basestation, block diagram, 9.30
Basis function, 5.3
correlation, DFT, 5.4
BDC binary coding, data converters, 2.10
Bennett, W.R., 2.42
Bessel filter, 6.24, 6.27-28
Best straight line, 2.11-12
Best, R.E., 4.17
Bilinear transformation, 6.28
Binary ADC:
3-bit
diagram, 3.29
input and residue waveforms, 3.29
single-stage, diagram, 3.28
Binary coding, data converters, 2.10
Binary DAC, 5-bit, architectures, diagram,
4.4
Bingham, John, 9.43
Bipolar converter, types, 2.10
Biquad, in IIR filter, 6.25
Bit reversal:
for 8-point DFT, 5.14
algorithm, 5.11-14
Bit-per-stage ADC, 3.27-32
diagram, 3.27
Blackman window function, 5.22-23
Blackman, R.B., 2.43
Block floating point, in FFT, 5.17
Boot memory select, ADC, 8.2
Bordeaux, Ethan, 7.55, 10.1
Boser, B., 3.33
Boyd, I., 9.43
Branch target buffer, 7.39, 7.41
Brannon, Brad, 9.43
Brokaw, Paul, 10.34
Bryant, James, 2.1, 3.1, 3.9, 4.1, 10.15,
10.34
Buck regulator, 10.46-50
Buffer register, 10.22-23
Bus:
data memory address, 7.10
data memory data, 7.10
data transfer, 7.10-11
internal result, 7.10-13
program memory address, 7.10
program memory data, 7.10
Buss wire, 10.16
Butterfly, 5.11-12
DIF FFT, 5.15
DIT FFT, 5.12
Butterworth filter, 4.9, 6.24, 6.27-28
characteristics, 2.5
Byrne, Mike, 10.15
C
Cage jack, 10.16
Calhoun, George, 9.43
Capacitive coupling, doublet glitch, 2.37
Capacitor:
equivalent circuit, pulse response, 10.43
finite ESR, 10.42-43
parasitic elements, 10.43
types, 10.40-42
Card entry filter, 10.46
Carrier, 2.23
Cascaded biquads, 6.25
Cauer filter, 6.27-28
CCD image processing, 1.5
CDMA, digital telephone system, 9.17
Cellular phone:
basic system, diagram, 9.16
frequency reuse, diagram, 9.16
Ceramic, capacitor, 10.40-42
Charpentier, A., 3.33
Chebyshev filter, 1.6, 6.2-3, 6.24, 6.27-28
Chestnut, Bill, 10.39
Chip select, DAC, 8.9
Circular buffering:
DSP application, 7.5
DSP requirement, 7.5
in FIR filter, 6.10
FIR filter, 7.5
in FIR filter, output calculation, 6.11
FIR filter pseudocode, in DSP, 7.8
Index-5
INDEX
Clelland, Ian, 10.56
Clock distribution:
end-of-line termination, diagram, 10.62
source terminated transmission lines,
diagram, 10.63
Cluster multiprocessing, 7.34
SHARC family, 7.36
CMOS IC, secondary I/O ring, diagram, 10.9
CMOS IC output driver, configuration,
10.3-4
Code division multiple access see CDMA
Code transition noise, and DNL, effects,
2.14
Codec, 1.5, 8.1
interfacing, 8.19-22
sampling rate, 8.20
voiceband/audio applications, 9.36-40
CODEC and DSP, in voiceband and audio,
9.36-40
COder/DECoder, 8.1
Coding, types, 2.10
Coleman, Brendan, 2.43
Colotti, James J., 2.43
Comfort noise insertion, 9.20
Communications, external port, versus link
port, 7.35
Computational unit:
arithmetic logic, 7.11
multiplier-accumulator, 7.11-12
shifter, 7.11-12
Computer, general purpose, Von Neumann
architecture, 7.6
Computing applications:
CISC, 7.2
data manipulation, 7.1
mathematical calculation, 7.1
RISC, 7.2-3
tabular summary, 7.1
Concentrator, 9.7
Connelly, J.A., 10.34
Convert start, ADC, 8.1-2
Convolution, 1.3
loop, 6.12
Convolving, filter responses, 6.23
Cooley, J.W., 5.10, 5.25
Cosier, G., 9.43
Coussens, P.J.M., 9.43
Crystal Oscillators, 10.34
D
DAC, 1.2
3-bit switched capacitor, diagram, 3.4
3-bit unipolar, transfer characteristics,
2.8-9
address bus, 8.9
binary weighted, 4.1
in CD player, use of interpolation, 6.33
Index-6
chip select, 8.9
conversion process, 2.2
current output, diagram, 4.2
in direct digital synthesis, 4.9
distortion, specification, 2.38
DNL errors, 2.22
double-buffered, latches, 4.7
DSP applications, 4.1-17
dynamic performance, 2.35-41
high-speed, 4.9
interpolating, 4.9-10
interrupt request, 8.9
ladder networks, 4.1
logic, 4.7-8
low distortion, architectures, 4.3-7
memory select, 8.9
midscale glitch, diagram, 2.37
monotonicity, 2.12
non-ideal 3-bit, transfer function,
diagram, 2.13
non-monotonic, and DNL, 2.12
output, quantization, 2.7
reconstruction, output, 2.41
segmented voltage, diagram, 4.3
settling time, applications, 2.38
sigma-delta, 4.11-12
1-bit, in CD players, 4.9
sin(x)/x frequency rolloff, 2.41
static transfer functions, DC errors,
2.7-14
structures, 4.1-3
transitions, with glitch, 2.36
voltage output, Kelvin divider, 4.1
write, 8.9
Damping resistor:
EMI/RFI minimization, 10.60
series, for SHARC DSP interconnections,
10.60
DashDSP, motor controllers, 9.34-35
Data address generator:
features, 7.13
mode status register, 7.13
Data converter:
analog bandwidth specification, 2.26
applications, 2.8
DC errors, 2.10, 2.10-11
DC performance, 2.15
gain error, diagram, 2.11
integral and differential non-linearity
distortion effects, 2.22-23
offset error, diagram, 2.11
sampling and reconstruction systems, 2.8
Data manipulation, by computer, 7.1
Data memory address, ADC, 8.4
Data memory address bus, 7.10
Data memory buffer, circular, 7.5
Data memory data bus, 7.10
INDEX
Data memory select, ADC, 8.2
Data reduction algorithms, in signal
processing, 1.2
Data sampling, 2.1-44
block diagram, 2.1
distortion and noise, 2.15-19
FFT, 2.1-2
quantization error, 3.10
quantization noise, 3.10
real-time system, 2.1
Data scrambling, in sigma-delta DAC, 4.11
Data-flow multiprocessing, 7.34
Dattorro, J., 3.33
DC error, types, 2.10
DDS, 4.12-16
basic architecture, 4.13
code-dependent glitches, 2.38
DAC, 4.3
distortion, contributors, 2.39
problems, 4.13
system, flexible, diagram, 4.14
tuning equation, 4.15
Dead time, DAC settling time, 2.35
Decimation, 3.10, 3.11
multirate filter, diagram, 6.31
Decimation-in-frequency, DIF, 5.13-14
Decimation-in-time, DIT, 5.11
Decoupling, localized, diagram, 10.52
Decoupling points, diagram, 10.24
Deglitching, 3.25
Del Signore, B.P., 3.33
Delta phase register, 4.14
Designing for EMC (Workshop Notes), 10.65
DFT, 5.1-8
8-point, 5.9, 5.12
using DIT, 5.12-13
applications, 5.2
basis functions, 5.3
butterfly operation, 5.11-12
characteristics, 5.4
complex, 5.5
equations, 5.6
from real, 5.7
input/output, 5.6
real/imaginary values, 5.7
equations, real versus imaginary, 5.8
expansion, 5.9-10
FIR filter, 6.15
fundamental analysis equation, 5.3
inverse, 5.5
output spectrum, 5.3
real, 5.5
input/output, 5.6
real versus imaginary
equations, 5.7-8
output conversion, 5.8
relationship, 5.7-8
sampled time domain signal, 5.3
versus FFT, 5.11
DIF:
butterfly, 5.13-14
decimation-in-frequency, 5.13-14
Differential non-linearity:
DNL, 2.12
from encoding process, 2.22
DIGI-KEY, 10.56
Digital cellular basestation, 9.28-31
Digital cellular basestations, advantages,
9.28
Digital cellular telephone, 9.16-20
GSM system, 9.18-20
Digital communications services see DCS
Digital correction, for subranging ADC, 3.24
Digital filter, 6.1-39
coefficient values, 6.1
design procedure, 6.1
diagram, 6.2
filter coefficient modification, 6.35
frequency response, 6.4
general equation, 6.25-26
lattice, 6.5
moving average, 6.5-10
programming ease in ADSP-21xx, 7.7-8
real-time, 6.1, 6.3
processing requirements, 6.4
requirements, 6.3
types, 6.5
versus analog, 6.3
Digital filtering, 3.10
Digital FIR filter, 1.6
Digital isolation:
by LED/photodiode optocouplers, 10.36
by LED/phototransistor optocouplers,
10.35
Digital isolation technique, 10.35-38
Digital isolator, 10.36-38
Digital mobile radio, standards, 9.18
Digital receiver, characteristics, 9.27-28
Digital return current, 10.16-17
Digital signal, characteristics, 1.1-2
Digital Signal Processing Applications
Using the ADSP-2100 Family, 5.25,
6.40, 9.43
Digital signal processor see DSP
Digital system, with ADC, quantization
noise, 2.31
Digital telephone system, CDMA and
TDMA, 9.17
Digital transmission, using adaptive
equalization, 6.37
Direct data scrambling, in sigma-delta
DAC, 4.11-12
Direct digital synthesis see DDS
Direct form 1 biquad filter, diagram, 6.26
Index-7
INDEX
Direct IF to digital conversion, 2.6-7
Direct memory access, DSP controller, 8.22
Direct-memory-access see DMA
Discontinuous transmission, 9.18-19, 9.20
Discrete Fourier transform see DFT
Discrete time Fourier series, 5.1
Discrete time sampling, 2.2
analog signal, 2.2-7
Distortion, DAC performance, 2.35-41
Distortion and noise, practical ADCs,
2.19-20
DIT:
decimation-in-time, 5.11
FFT, algorithm, 5.11, 5.13
Dither signal, 2.18
DMA, internal, in ADSP-21xx, 7.17
DNL:
ADC and DAc errors, 2.22
converter error, definition, 2.12
differential non-linearity, 2.12
Doernberg, Joey, 2.43
Double precision, 64-bit, floating point
arithmetic, 7.25
Double-buffered DAC:
advantages, 4.7-8
diagram, 4.8
latches, 4.7
Doublet glitch, 2.37
DSP, 1.2, 7.1-3
16-bit, fixed-point family, history, 7.20-22
32-bit, second-generation, 7.31
ADSP-21xx, characteristics, 1.6-8
analog versus digital, 1.4-5
options, diagram, 1.5
applications, 9.1-44
summary, 9.42
arithmetic
fixed-point versus floating point,
7.23-26
fixed-point versus floating-point,
7.23-26
characteristics, 7.2
code, compilation, 7.45
and computer applications, 7.1
core voltage, 10.2
development tools, 7.46
dot-product, 7.2
efficiency, 7.18
evaluation and development tools,
7.45-54
VisualDSP and VisualDSP++, 7.51-54
fundamental mathematical operation, 7.3
grounding, 10.29-30
hardware, 7.1-55
high density, localized decoupling,
10.53-55
interfacing, 8.1-25
Index-8
interfacing I/O ports, analog front ends,
and CODECS, 19-22
internal phase-locked loops, grounding,
10.29-30
kernel, 7.1-2
optimization, 7.6
output rise and fall times, diagram, 10.58
parallel interfacing, 8.1-12
block diagram, 8.8
reading data from memory-mapped
peripheral ADCs, 8.1-7
to external ADC, block diagram, 8.2
writing data to memory-mapped DACs,
8.7-12
practical example, 1.5-8
requirements, 7.3-6
circular buffering, 7.5
dual operand fetch, 7.4-5
extended precision, 7.4
fast arithmetic, 7.4
summary, 7.6
zero overhead looping, 7.5-6
sampled data, block diagram, 2.1
serial interfacing, 8.12-19
serial ADC, 8.14-19
serial DAC, 8.17-19
system interface, 8.23-24
using VLSI, 1.4
voiceband/audio applications, 9.36-40
DSP Designer's Reference (DSP Solutions),
7.55, 8.25
DSP Navigators: Interactive Tutorials about
Analog Devices' DSP
Architectures, 7.55
DSP Navigators: Interactive Tutorials about
Analog Device's DSP
Architectures, 8.25
Dual operand fetch:
DSP application, 7.4-5
DSP requirement, 7.4-5
Duracell MN1500 "AA" alkaline battery,
discharge characteristics, 10.2
Dynamic performance analysis, ideal N-bit
ADC, 2.17
Dynamic range compression, 1.4
E
Echo, voiceband telephone connection, 9.2
Eckbauer, F., 3.33
EDN's Designer's Guide to Electromagnetic
Compatibility, 10.65
Edson, J.O., 2.42, 3.34
Effective aperture delay time, 2.34
diagram, 2.35
Effective number of bits see ENOB
Eichhoff Electronics, Inc., 10.57
Electrolytic capacitor:
INDEX
characteristics, 10.40-41
impedance versus frequency, diagram,
10.44
Elliptic filter, 6.24, 6.27-28
characteristics, 2.5
Embedded speech processing, 9.36-37
EMC Design Workshop Notes, 10.56
End point, 2.11-12
Engelhardt, E., 3.33
ENOB, 2.21, 2.24-25, 3.10
ADC, effective resolution, 3.10
definition, 3.10
Equiripple FIR filter design, program
inputs, 6.19-20
Equivalent input referred noise, thermal
noise, 2.20-21
Error voltage, 10.17
Euler's equation, 5.3
Extended precision:
DSP application, 7.4
DSP requirement, 7.4
floating point arithmetic, 7.25
External clock jitter, 10.25
External port, versus link port, in
communications, 7.35
EZ-ICE, in-circuit simulator, 7.48
EZ-KIT Lite, 7.45-46, 7.53
EZ-LAB, evaluation board, 7.45
F
Fair-Rite, 10.44-46
Fair10.Rite Linear Ferrites Catalog, 10.56
Fairchild 74VCX164245, 16-bit low voltage
dual logic
translators/transceivers, 10.10-13
Faraday shield, 10.22
Fast arithmetic:
DSP application, arithmetic logic unit, 7.4
DSP requirement, 7.4
Fast Fourier transform see FFT
Fast logic, and analog circuits, 10.59
FDMA:
frequency division multiple access, 1.2
telephone system, 1.2
FDMA communications link, NPR testing,
2.30
Ferguson, P. Jr., 3.34
Ferguson, P.F. Jr., 3.33
Ferrite, 10.44
beads, 10.16, 10.20, 10.29, 10.30
impedance, 10.45-46
suitable for high-frequency filters, 10.45
FFT, 2.1, 5.1-25, 5.9-17
8-point DIF, 5.15
8-point DIT algorithm, 5.13
and DFT, 5.10
DIF, 5.13-14
FIR filter, 6.15
first Nyquist zone aliases, 2.4
floating point DSP, 5.18
frame-based systems, 5.18
hardware implementation and
benchmarks, 5.17-18
noise floor determination, 5.19
processing gain, 2.18-19, 5.20
processor, 5.17
radix-2, 5.16
radix-2 complex, hardware benchmark
comparisons, 5.18
radix-4, DIT butterfly, 5.16-17
real-time
considerations, 5.20
DSP requirements, 5.18-20
processing, 5.19
sinewave
integral number of cycles, 5.21
nonintegral number of cycles, 5.22
spectral leakage and windowing, 5.21-24
twiddle factors, 5.9-10
versus DFT, 5.11
Film capacitor, 10.40-42
Filter:
analog, for oversampling, 4.10
analog versus digital, 6.2-4
frequency response comparison, 1.7
antialiasing, specifications, 2.4-5
band, 10.46
bandpass, design, 6.23-24
bandstop, design, 6.23-24
baseband antialiasing, 2.4-6
Butterworth, characteristics, 2.5
capacitor, types, 10.40
Chebyshev, 1.6
corner frequency, 2.4
design, and FFT, 5.1
digital, diagram, 1.6
digital FIR, 1.6
elliptic, characteristics, 2.5
FIR versus IIR, comparisons, 6.30
high frequency, 10.51
high-frequency, ferrites, 10.45
highpass, design, 6.23-24
impulse convolving, 6.23
lowpass, analog versus digital, in
sampled data system, 1.5-6
power supply, 10.39-57
rolloff, sharpness, 6.9
switching supply, summary, 10.51
transfer function, 3.13
Filtering, 1.3, 1.4
FilterWizard, compiler, 9.41
Finite amplitude resolution due to
quantization, 2.2
Finite impulse response see FIR
Index-9
INDEX
FIR filter, 6.5-30
4-tap, output calculation, via circular
buffer, 6.11
arbitrary frequency response, design,
6.17-18
CAD design programs, 6.18-19
characteristics, 6.14
circular buffering, 6.10-13
in circular buffering, 7.5
circular buffering, fixed boundary RAM,
6.10
coefficients, 6.15
compared with IIR filter, 6.30
computational efficiency increase, 6.32
design
Fourier series method, with
windowing, 6.17
frequency sampling method, 6.17-18
fundamental concepts, 6.13
Parks-McClellan program, 6.18-22
programming ease in ADSP-21xx, 7.7-8
windowed-sinc method, 6.16
designing, 6.13-24
implementation, circular buffering,
6.10-13
impulse response, and coefficients, 6.14
Momentum Data Systems design
frequency response, 6.21
impulse response, 6.22
step response, 6.21
N-tap, general form, 6.9-10
output decimation, 6.32
program outputs, 6.20
pseudocode, 6.12, 7.7-8
simplified diagram, 6.10
transfer function
frequency domain, 6.15
time domain, 6.15
versus IIR filter, 6.30
First-order sigma-delta ADC, 3.12
Fisher, J., 3.33
Fixed-point:
16-bit, fractional format, 7.24
DSP arithmetic, 7.23-26
versus floating point, DSP arithmetic,
7.23-26
Flash ADC:
10-bit, diagram, 3.23
limited to 8-bits, 3.22
parallel ADCs, 3.21
diagram, 3.22
problems, 3.21
Flash converter, 3.21-23
Floating-point:
DSP arithmetic, 7.23-26
versus fixed point arithmetic, 7.26
Folding converter, 3.29
Index-10
Fourier series, 5.1
FIR filter design, windowing, 6.17
Fourier transform, 5.1, 6.15
and time domain signal, 5.2
Fourier, Jean Baptiste Joseph, 5.1
FPBW, full power bandwidth, 2.26
Framing mode, 8.14
Freeman, D.K., 9.43
Frequency division multiple access, FDMA,
1.2
Frequency domain, versus time domain,
6.13, 6.15
Frequency sampling method, FIR filter
design, 6.17-18
Frequency synthesis, using PLLs and
oscillators, diagram, 4.12
Fu, Dennis, 9.43
Full memory mode, 8.23
Full power bandwidth, FPBW, 2.26
Full-duplex hands-free car kit, diagram,
9.36
Fully decoded DAC:
5-bit, diagram, 4.4
diagram, 4.2
G
Gain error, 2.10
Galand, C., 9.43
Ganesan, A., 3.33, 3.34
Gardner, F.M., 4.17
Gaussian noise, 2.20-21, 2.30
Gaussian-filtered minimum-shift keying,
9.26
Geerling, Greg, 7.1
General DSP Training and Workshops,
7.55, 8.25
General purpose aluminum electrolytic
capacitor, 10.40-41
Gerber files, 10.33
Ghausi, M.S., 2.44
Gibbs effect, 5.1
Glitch:
code-dependent, effects, 2.38
DAC performance, 2.35-41
definition, 2.36
energy, 2.37
and harmonic distortion and SFDR,
prediction, 2.39
impulse area, 2.37
Global System for Mobile Communication
see GSM
Glue logic, 8.1
Gold, B., 5.25, 6.40
Gold, Bernard, 2.44
Gosser, Roy, 2.42, 3.34
Graham, M., 10.14
Graham, Martin, 10.34, 10.65
INDEX
Grame, Jerald, 10.34
Gray bit, 3.30
Gray code binary coding, data converters,
2.10
Gray, A.H., Jr., 6.40
Gray, G.A., 2.42
Ground loop, 10.20, 10.35
Ground plane, 10.30
decoupling high frequency current, 10.15
impedance, 10.20
low-impedance return path, 10.15-16
printed circuit board, 10.17-18
Ground screen, 10.19
Grounded-input histogram, 2.20-21
Grounding:
DSP, internal phase-locked loops,
diagram, 10.30
mixed signal devices, in multicard
system, 10.27-29
mixed signal systems, 10.15-34
mixed-signal ICs, 10.15
multiple ground pins, 10.32
philosophy, summary, 10.31
points, diagram, 10.24
separate analog and digital grounds,
10.19-20
single-card versus multicard, concepts,
10.26-27
Groupe Speciale Mobile see GSM
GSM, block diagram, 9.18-19
GSM handset:
components, 9.21-26
using SoftFone baseband processor, and
Othello radio, 9.21-26
H
Hageman, Steve, 10.56
Half-flash ADC, 3.23
Hamming window function, 5.22-23
Hanning window function, 5.22-23
Hard limiter, 2.29
Hardware design, techniques, 10.1-65
Harmonic distortion, 2.23-24
DAC, 2.38
definition, 2.23
products, location, diagram, 2.23
Harmonic sampling, 2.6-7
Harmonic undersampling, 2.7
Harrington, M.B., 9.44
Harris, Fredrick J., 2.43, 5.25, 6.40
Harris, Steven, 3.34
Harvard architecture:
in DSP, 7.5
in microprocessor, 7.6-7
Hauser, Max W., 3.34
Haykin, S., 6.40
HDTV, high definition television, 1.2
Heise, B., 3.33
Hellwig, K., 9.43
Henning, H.H., 2.42, 3.34
Higgins, Richard J., 1.9, 2.44, 5.25, 6.40,
7.55, 8.25
High definition television, HDTV, 1.2
High density DSP:
localized decoupling
diagram, 10.53
using BGA packages, 10.54
High Speed Design Techniques (1996), 3.35
High speed logic, 10.58-65
High-level language support, architectural
features, 7.42
High-speed interfacing, 8.22-23
Highpass filter:
design, 6.23-24
using lowpass FIR, 6.23
Hilton, Howard E., 2.44
Hodges, David A., 2.43
Hofmann, R., 9.43
Honig, Michael L., 6.40
Horvath, Johannes, 10.1
Host memory mode, 8.23
HP Journal, 2.43-44
HP Product Note, 2.43
I
IC, low-voltage mixed signal, 10.2
IEEE Trial-Use Standard for Digitizing
Waveform Recorders, 2.44
IF sampling, 2.6-7
IIR biquad filter:
basic, 6.25
simplified notations, 6.27
IIR elliptic filter, 6.30
IIR filter, 6.24-27
analog counterparts, 6.24
CAD design, using Fletcher-Powell
algorithm, 6.28
characteristics, 6.25
compared with FIR filter, 6.30
design techniques, 6.27-29, 6.29
direct form implementation, 6.26
feedback, 6.5
IIR filter, 6.24-27
implementation, 6.25
throughput considerations, 6.29
versus FIR filter, 6.30
IMD:
measurement, 2.28
second- and third-order, diagram, 2.29
two tone intermodulation distortion,
2.28-30
Impulse invariant transformation, 6.28
IMT-2000 protocol, 7.36
In-circuit simulator, 7.48
Index-11
INDEX
Indirect field-oriented control, 9.32
Induction motor:
control, 9.32-35
block diagram, 9.33
Infinite impulse response see IIR
Information, in signal, 1.2
Input filtering, 1.5
Input noise rejection, 1.5
Input/output memory select, ADC, 8.2
Instruction register, data address
generator, 7.14
Integral linearity error, measurement,
2.11-12
Integral sample-and-hold, 2.19
Interface:
2.5V/3.3V, diagram, 10.13
3.3V/2.5V, 10.10-13
diagram, 10.11-12
Interfacing, high-speed, 8.22-23
Interference, components, 10.39
Intermodulation distortion, DAC, 2.38
Internal aperture jitter, 10.25
Internal result bus, 7.10-13
Interpolation:
frequency domain effects, 6.33-34
implementation example, 6.33-34
multirate filter, 6.32-33
Interrupt request, DAC, 8.9
Intranet, 9.7
I.Q. convention, 7.24
IRQ, 8.1
J
Jantzi, S.A., 3.33
JEDEC, 10.14
specification, for packaging, 7.20
standards bureau, 10.5
Jitter:
aperture, 10.25
effects, 2.33
external clock, 10.25
internal apeture, 10.25
sampling clock, 10.25
Johnson noise, 2.8
Johnson, H., 10.14
Johnson, Howard W., 10.34, 10.65
Joint Electron Device Engineering Council
see JEDEC
Jung, Walt, 10.39, 10.56
K
Kelvin divider, 4.1
disadvantages, 4.1-2
ladder network, 4.3
Kelvin-Varley divider, string DAC, 4.3
Kerr, Richard J., 4.17
Index-12
Kester, Walt, 1.1, 2.1, 2.43, 3.1, 3.35, 4.1,
5.1, 6.1, 7.1, 8.1, 9.1,
10.1, 10.15, 10.34-35, 10.39
Kettle, P., 9.44
King, Dan, 7.1, 8.1
Koch, R., 3.33
L
Lagrange, Joseph Louis, 5.1
Laker, K.R., 2.44
Lane, Chuck, 2.42, 3.34
Laplace transform, 6.15
conversion to z-transform, 6.28
Laplace, Pierre Simon de, 5.1
Latency, 3.25
Lattice filter, 6.5
Leaded ferrite bead, 10.44
Least significant bit:
definition, 2.7
quantization, chart, 2.8
size, 2.8
Least-mean-square algorithm, for filter
coefficients, 6.36
Lee, Hae-Seung, 2.43
Lee, Wai Laing, 3.33
Lee, W.L., 3.33
Levine, Noam, 7.1
Linear Design Seminar (1995), 2.42, 3.33,
3.34
Linear integrity error, 2.11
Linear predictive coding see LPC
Linear settling time, DAC settling time,
2.35
Linearity errors, 2.10
Link descriptor file see LDF
Link port, versus external port, in
communications, 7.35
Link port multiprocessing, 7.34
LMS, least-mean-square, 6.36
Logarithmic pulse code modulation, 9.19
Logic:
CMOS IC output driver, configuration,
10.3-4
high speed, 10.58-65
Logic translating transceiver:
diagram, 10.11
voltage compliance, 10.11
Long term prediction see LTP
Low voltage interface, 10.1-14
Low Voltage Logic Alliance, standards, 10.5
Low voltage logic level, standards, 10.4-5
Low voltage mixed-signal IC, 10.2
Low-pass filter, LPF, 3.11
Lowpass filter, design of other filters, 6.23
LPC, 6.36-37
in all-pole lattice filter, 6.38-39
model of speech production, 6.37
INDEX
speech companding system, 6.38
speech processing system, 9.19
speech system, digital filters, 6.38
LPF:
analog, in sigma-delta ADC, 3.13
low-pass filter, 3.11
LQFP, new package designation, 7.20
Lucey, D.J., 9.44
LVTTL, logic level, 10.4
Lyne, Niall, 9.44
M
McClellan, J.H., 6.40
MagAmp, 3.29
3-bit folding ADC
block diagram, 3.31
functional equivalent circuit, 3.30
input and residue waveforms, 3.31
Magnitude amplifier, 3.29
Magnitude-amplifier architecture,
MagAmp, 3.24
Mahoney, Matthew, 2.44
Main lobe spreading, 5.22
Manolakis, Dimitris G., 5.25, 6.40
Markel, J.D., 6.40
Marsh, Dick, 10.56
Matched z-transform, 6.28
MathCad 4.0 software package, 2.44
Mathematical calculation, by computer, 7.1
Matsuya, Y., 3.33, 3.34
Maximally flat filter, 6.27
Mayo, J.S., 2.42, 3.34
Meehan, Pat, 2.43
Memory address bus, ADC, 8.2
Memory read, ADC, 8.2
Memory select:
ADC, 8.2
DAC, 8.9
Messerschmitt, David G., 6.40
Microcontroller, 7.1-3
characteristics, 7.2
MicroConverter, precision analog circuitry,
1.3
Microprocessor, 7.1-3
architectures, comparison, 7.6
characteristics, 7.2
Million operations per second see MOPS
Millions of instructions per second see MIPS
miniBGA package, 7.20-21
Minimum 4-term Blackman-Harris window
function, 5.22-23
MIPS, 7.2, 7.18
Missing codes:
in ADC, 2.12-13
defining, 2.14
Mitola, Joe, 9.43
Mixed Signal Design Seminar (1991), 3.33
Mixed signal processing, 1.4
Mixed-signal device:
grounding, 10.26-27
diagram, 10.27
Mixed-signal IC:
grounding, multiple printed circuit
boards, 10.28-29
high digital currents, grounding, 10.28-29
low digital current, grounding and
decoupling, 10.21-22
low digital currents, grounding, 10.27-28
Mobile telephone service, superheterodyne
receiver, diagram, 9.27
Mode status register, data address
generator, 7.13
Modem:
full-duplex, 9.1
half-duplex, 9.1
high performance, telephone service,
9.1-7
high speed, 1.2
RAS, 9.7-10
standards, chart, 9.3
V.90 analog
block diagram, 9.4
details, 9.6
V.90 analog versus V.34, diagram, 9.7
Momentum Data Systems, QED1000
program, for FIR filter design, 6.18
Momentum Data Systems, Inc., 6.40
Montrose, Mark, 10.34, 10.65
MOPS, 7.18
Moreland, Carl, 2.42, 3.34
Morley, Nick, 9.43
Morris, Jesse, 7.1
Morrison, Ralph, 10.34
Motchenbacher, C.D., 10.34
Motherboard, grounding, 10.18-19
Motor control, 9.32-35
fully integrated, DashDSP, 9.35
Motor Control Products, Application Notes,
and Tools, 9.44
Moving average filter, 6.5-10
calculating output, 6.7
diagram, 6.6
frequency response, 6.8
noise, 6.6-8
step function response, 6.6-7
MSP, 1.4
Multi-channel high frequency
communication system, NPR, 2.31
Multi-channel VOIP server, 9.10-11
Multi-tone SFDR, measurement, 2.29
Multicard mixed-signal system, grounding,
10.18-19
Multilayer ceramic chip caps, 10.42
Multiplier-accumulator unit, features, 7.12
Index-13
INDEX
Multiplying DACs, 4.3
Multipoint ground, diagram, 10.19
Multiprocessing, using SHARCs, 7.34-36
Multirate filter, 6.31-35
decimation, 6.31
interpolation, 6.31
Murden, Frank, 2.42, 3.34
Murray, Aengus, 9.44
N
Narrowband, 9.27
Network:
LAN, 1.2
local area, 1.2
Nicholas, Henry T. III, 4.17
NMOS FET, bus switches, interfacing,
10.6-8
Noise:
and grounding, 10.22
power supply, 10.39-57
Noise power ratio see NPR
Noise shaping, using analog filter, 3.13
Non-ideal ADC, 3-bit, transfer function,
diagram, 2.13
Non-ideal DAC, 3-bit, transfer function,
diagram, 2.13
Normal framing mode, 8.14
NPR, 2.30-32
measurement, diagram, 2.31
NPR, 2.30-32
theoretical, for various ADCs, 2.32
Numerically controlled oscillator, 4.13
block diagram, 4.14
Nyquist band, 3.10
Nyquist bandwidth, 2.15, 2.17
aliasing, 2.4
definition, 2.4
Nyquist criteria, 2.2
Nyquist frequency, 2.41, 9.5
Nyquist zone, 2.4, 2.26-27
baseband sampling, 2.6
spurious frequency component, 2.4
O
Offset binary coding, data converters, 2.10
Offset error, 2.10
1's complement binary coding, data
converters, 2.10
Oppenheim, A.V., 5.25, 6.40
Optocoupler, 10.35
Optoisolator, 10.35
OS-CON Aluminum Electrolytic Capacitor
93/94 Technical Book, 10.56
OS-CON electrolytic capacitor, 10.40-41,
10.43
Othello:
radio, chipset, 9.21
Index-14
radio receiver
advantages, 9.24
block diagram, 9.24-25
compactness, advantages, 9.26
superhomodyne architecture, 9.23-24
Ott, Henry, 10.34, 10.56
Output enable/read, ADC, 8.2
Output ripple, reduction, 10.50
Oversampling, 3.10
and baseband antialiasing filter, 2.5
definition, 2.16-17
ratio, 3.11
P
Parallel ADC, diagram, 3.22
Parallel peripheral device:
read interface, key requirements, 8.3
write interface, key requirements, 8.9
Parasitic capacitance, 10.43
Parasitic inductance, 10.22
Parks-McClellan program:
equiripple FIR filter design, program
inputs, 6.19-20
FIR filter, 6.28
design, 6.18-22
Parks, T.W., 6.40
Parzefall, F., 3.33
Passband ripple, 6.2
in filter, 1.6
Pattavina, Jeffrey S., 10.34
Peak glitch area, 2.37
Peak spurious spectral content, ADC, 2.26
Pentium-Series, 7.2
Pericom Semiconductor Corporation, 10.14
Permanent magnet synchronous machine,
9.33
PGA, programmable gain amplifier, 1.5
Phase accumulator, 4.14
Phase jitter, 2.33
Phase-locked loop, PLL, 4.12
Phase-Locked Loop Design Fundamentals,
4.17
PIC, 7.2
Picocell, 9.30
Pin socket, 10.16
Pipeline delay, 3.25
Pipelined ADC, 3.23-27
12-bit CMOS ADC, block diagram, 3.26
error correction, 3.25-26
Pipelined subranging ADC, 12-bit, digital
error correction, block diagram,
3.25
Plain Old Telephone Service see POTS
PMOS transistor current switch, diagram,
4.7
Point of presence see POP
Polyester, capacitor, 10.40-41
INDEX
POP, 9.8
POTS:
block diagram, 9.2
hybrid curcuit, 9.1
Power inverter, 9.32
Power plane, 10.15-17
Power supply:
filtering, 10.39-57
localized high frequency
filter, 10.51-53
construction guidelines, 10.52-53
noise reduction, 10.39-57
pins, decoupling, 10.16
separate for analog and digital circuits,
10.23
PowerPC, 7.2
Practical Analog Design Techniques (1995),
2.42, 3.34
Practical Design Techniques for Power and
Thermal Management, 10.57
Practical Design Techniques for Sensor
Signal Conditioning, 1.9
Printed circuit board:
double-sided versus multilayer, 10.17-18
ground plane, 10.17
impedance, calculation, 10.59
mixed-signal system, layout guidelines,
10.31-33
"motherboard", grounding, 10.18-19
trace termination, 10.58
Proakis, John G., 5.25, 6.40
Processing gain:
definition, 2.16-17
FFT, 2.18-19
Processor interrupt request line, ADC, 8.1-2
Program memory address bus, 7.10
Program memory data bus, 7.10
Program memory select, ADC, 8.2
Program sequencer:
data address generator, 7.14
features, 7.14
Programmable gain amplifier, PGA, 1.5
Prom splitter, 7.45
Pseudocode, FIR filter, using DSP with
circular buffering, 7.8
Pulse code modulation, 9.3
Q
QEDesign, 9.41
filter package, 3.20
QS3384 Data Sheet, 10.14
QS3384 QuickSwitch, 10.7-8
transient response, diagram, 10.8
Quadrature amplitude modulation, 9.26
diagram, 9.5
POTS, 9.3
Quantization:
effects on ideal ADC, 2.15
size of LSB, chart, 2.8
Quantization error, 2.9-10
signal, 2.15
Quantization noise:
in digital system with ADC, 2.31
for ideal N-bit ADC, diagram, 2.16
shaping, 3.10
in sigma-delta ADC, 3.14
spectrum, diagram, 2.16
Quantization uncertainty, 2.9-10
QuickSwitch, in bidirectional interface,
10.6-8
R
Rabiner, Lawrence, 2.44
Rabiner, L.R., 5.25, 6.40, 6.41
RAMDAC, 1.3
Ramierez, Robert W., 2.43
Ramirez, R.W., 5.25
RAS:
equipment, 9.10
modem, 9.7-10
as Internet gateway, diagram, 9.8
on-switch based, 9.9
RAS/VOIP servers, 9.10
Receive data register, 8.14
Receive frame sync, 8.14
Receive shift register, 8.14
Reconstruction, definition, 2.14
Reconstruction filter, 6.2
Recovery time, DAC settling time, 2.35
Recursive filter, 6.24
Recursive-least-squares algorithm, for filter
coefficients, 6.36
Reference frame theory, 9.33
Regular pulse excitation see RPE
Reidy, John, 2.43
Remez exchange algorithm, 6.18-19
Remote access server see RAS
Remote network access, 9.7
Rempfer, William C., 10.34
Ripple, passband, in filter, 1.6
Ripple ADC, 3.27-32
diagram, 3.27
RISC, and DSP, 7.3
RLS, recursive-least-squares, 6.36
Roche, P.J., 9.44
Rolloff:
sharpness, 6.9
sidelobe, 5.22
Root-sum-square, RSS, 2.24
Rorabaugh, C. Britton, 5.25, 6.40, 7.55, 8.25
Rosso, M., 9.43
Ruscak, Steve, 2.42
Index-15
INDEX
S
Sample rate converter, using interpolator
and decimator, 6.35
Sample-and-hold see SHA
Sampled data system, definition, 2.14
Sampling:
above first Nyquist zone, 2.7
bandpass, 2.6-7
harmonic, 2.6-7
IF, 2.6-7
rate versus bandwidth, 2.7
Sampling clock, 10.24-26
ground planes, diagram, 10.26
jitter, effect on SNR, 10.25
Sampling rate, increased, 1.5
Samueli, Henry, 4.17
SAR, 3.2
SAR ADC, 3.3
external high frequency clock, 3.6
fundamental timing, 3.5
resolutions, table, 3.5
switched capacitor, 3.8
with switched capacitor DAC, 3.3
typical timing, 3.6
Sauerwald, Mark, 10.34
Scannell, J.R., 9.44
Schafer, R.W., 5.25, 6.40, 6.41
Schmid, Hermann, 2.42, 3.34
Schmitt trigger, 10.38
Schottky diode, 10.7, 10.20, 10.29, 10.30
Segmentation, in thermometer DAC, 4.5
Segmented DAC, 4.2-3
10-bit, diagram, 4.5
Segmented voltage DAC, segmented
voltage, 4.3
Sensor:
as analog device, 1.4
in industrial data acquisition and control
systems, 1.3
uses, 1.1-2
Serial ADC, 3.27-32
diagram, 3.27
to DSP interface, 8.14-17
Serial clock, 8.14
Serial DAC, to DSP interface, 8.17-19
Serial ports, in ADSP-21xx, 7.16
Serial-Gray, ADC architecture, 3.29
Settling time:
DAC performance, 2.35-41
diagram, 2.36
periods, 2.35
SFDR, 2.17, 2.21, 2.26-28, 2.35-41
ADC, definition, 2.26
DAC
distortion, 2.38
performance, 2.35-41
test setup, 2.40
Index-16
diagram, 2.27
sampling clock to input frequency ratio,
for ideal 12-bit ADC, 2.18
SHA, 2.19-20
and aperture jitter, 2.33
SHARC:
32-bit, key features, 7.32
architecture, 7.27
coding, 7.33
decoupling, 10.53
DSP
evaluation device, 7.48-49
floating and fixed point arithmetic,
7.25
DSP benchmarks, 7.34
family roadmap, 7.33
FFT butterfly processing, 7.26
floating point DSP, 7.26-30
floating-point DSP, 7.26-30
key features, 7.27
multi-function instruction, 7.33
multiprocessing, 7.34-36
multiprocessor communication, examples,
7.35
program sequencer, 7.26
VisualDSP++ software, 7.52
SHARC DSP:
32-bit floating point, 9.38-39
bi-directional transmission, source
termination, diagram, 10.63
Sheingold, Dan, 2.44
Sheingold, Daniel H., 1.9, 3.34
Shifter unit, features, 7.12
Shunt resistance, 10.43
Sidelobe, 5.22
Sigma-delta ADC:
bandpass filters, 3.18-19
characteristics, table, 3.10
first-order, diagram, 3.12
fixed internal digital filter, 3.19
and missing codes, 2.14
multi-bit
diagram, 3.18
flash ADC with DAC, 3.17-18
noise shaping, 3.12-13
order versus oversampling, 3.14-15
oversampling, 3.20
converter, 2.6
programmable digital filter, 9.40-42
quantization noise shaping, 3.14
second-order, block diagram, 3.15
settling time, and digital filter, 3.16
SNR, 3.20
summary, 3.21
Sigma-delta audio DAC, 3.17
Sigma-delta DAC, 4.11-12
architecture, diagrams, 4.11
INDEX
high resolution, oversampling, 4.11
Sign-magnitude bipolar converter, 2.10
Signal:
amplitude, 1.2
analog, 1.1
bandwidth
aliasing, 2.2
Nyquist criteria, 2.2
characteristics, table, 1.1
conditioning, 1.1
analog signal processor, 1.4
sensors, 1.1-2
successive approximation ADCs, 3.2
continuous aperiodic, 5.1
continuous periodic, 5.1
sinusoidal waves, 5.1
definition, 1.1, 1.2
digital, 1.1-2
frequency, 1.2
processing
frequency compression, 1.2
information extraction, 1.2
methods, 1.4-5
mixed, 1.4
real-time, comparison chart, 1.8
reasons, 1.3
real-world
generation, 1.3
origins, 1.1-2
processing, 1.2-3
units of measurement, 1.1-2
recovery, 1.3
sampled aperiodic, 5.1
sampled periodic, 5.1
spectral content, 1.2
timing, 1.2
units of measurement, table, 1.1
Signal-to-noise ratio see SNR
Signal-to-noise-and-distortion ratio, SINAD,
2.21, 2.24-25
Signed fractional format, DSP arithmetic,
7.23
Signed integer format, DSP arithmetic, 7.23
Silence descriptor, 9.20
SINAD, 2.21, 2.24-25
conversion to ENOB, equation, 2.25
Singer, Larry, 2.42
Single precision, floating point arithmetic,
standard, 7.25
single-instruction, multiple data see SIMD
Single-instruction, single-data see SISD
Sinusoidal wave, continuous periodic signal,
5.1
SISD, older DSP architecture, 7.31
Sluyter, R.J., 9.43
Small signal bandwidth, 2.25
Smith, Steven W., 5.25, 6.40, 7.55, 8.25
Snelgrove, M., 3.33
SNR, 2.15, 2.21, 2.24-25
decrease with input frequency in ADC,
2.33
definition, 2.15
degradation, from external clock jitter,
10.25
due to aperture and sampling clock jitter,
diagram, 2.34
SNR-without-harmonics, calculation, 2.25
Sodini, C.G., 3.33
SoftCell:
chipset
block diagram, 9.30
for digital phone receivers, 9.29
SoftFone, baseband processor, chipset, 9.21
Software development environment, 7.51
Software simulator, for debugging, 7.45
Southcott, C.B., 9.43
Spectral inversion, in filter design, 6.23
Spectral leakage:
FFT, 5.21
windowing, 5.23
Spectral reversal, in filter design, 6.23
Speech:
compression, adaptive filter use, 6.36
encoder/decoder, 9.18-19
processing, standards, 9.18-19
synthesis, adaptive filter use, 6.36
synthesized, 1.3
SPORT:
in ADSP-21xx, 7.16
transfer rate, 8.20
Spurious free dynamic range see SFDR
SSBW, small signal bandwidth, 2.25
Stacked-film capacitor, 10.40, 10.42
Star ground, 10.16, 10.19, 10.26
Static branch prediction logic, 7.39
Static superscalar, 7.39
Stearns, S.D., 6.40
Stopband ripple, 6.2
String DAC:
diagram, 4.2
disadvantages, 4.1-2
Kelvin divider, 4.1
Subranging ADC, 3.23-27
8-bit, diagram, 3.24
12-bit, digitally corrected, block diagram,
3.25
digital correction, 3.24
Successive approximation ADC, 3.1-9
basic, 3.3
Successive approximation register see SAR
SUMMIT-ICE, PCI emulator, 7.50
Super Harvard Architecture, for 32-bit DSP,
7.27-28
Superheterodyne architecture, 9.23-24
Index-17
INDEX
Superhomodyne architecture:
diagram, 9.24-25
operation, 9.25-26
Supply voltage reduction, 10.1
Surface mount ferrite bead, 10.44
Swanson, E.J., 3.33
Switching capacitor, characteristics,
10.40-41
Switching regulator, 10.46-51
filtering, experiment, 10.46-50
noise, reduction tools, 10.40
Switching supply, filter, summary, 10.51
Switching time, DAC settling time, 2.35
System Applications Guide (1993), 2.43,
3.33, 3.35
Systolix FilterExpress, 9.41
Systolix PulseDSP, 9.41
filter core, 6.2
processor, 3.19-20
T
T-Carrier system, 1.2
Tantalum electrolytic capacitor, 10.40-41
Tantalum Electrolytic Capacitor SPICE
Models, 10.57
Tantalum Electrolytic and Ceramic
Capacitor Families, 10.56
Tant, M.J., 2.42
TDMA, 1.2
Telephone, FDMA, 1.2
Tesla, Nikola, 9.32
THD+N, 2.23-24
definition, 2.24
THD, 2.21, 2.23-24
definition, 2.24
Thermal noise, equivalent input referred
noise, 2.20-21
Thermometer code, 3.21
Thermometer DAC:
5-bit, diagram, 4.4
diagram, 4.2
disadvantage, 4.5
segmentation, 4.5
Thevenin impedance, 10.61
Thompson filter, 6.27-28
TigerSHARC:
ADSP-TS001 static superscalar DSP,
7.36-44
architecture, 7.38
branch target buffer, 7.39, 7.41
features, 7.39
flexibility, 7.36
key features, 7.37
multiprocessor key elements, 7.36-37
static branch prediction logic, 7.39
static superscalar, 7.39
development tools, 7.53
Index-18
DSP, 9.30-31
key features, 7.40
multiprocessing implementation, sample
configuration, 7.42-43
peak computation rates, 7.41
roadmap, 7.43
Time division multiple access see TDMA
Time domain, versus frequency domain,
6.13, 6.15
Time sampling, analog signal, 2.2-7
Total harmonic distortion see THD
Total harmonic distortion plus noise see
THD+N
TQFP package designation, new
designations, 7.20
Transmission line:
controlled impedance microstrip,
termination, 10.61
termination at both ends, 10.64
Transmit data register, 8.14
Transmit shift register, 8.14
TREK-ICE, Ethernet emulator, 7.50
TTL, logic level, 10.4
Tukey, J.W., 2.43, 5.10, 5.25
Twiddle factors, 5.9-10
Two tone intermodulation distortion, IMD,
2.28-30
2's complement binary coding, data
converters, 2.10
Type 1 Chebyshev filter, 6.27-28
Type 2 Chebyshev filter, 6.27
Type 5MC Metallized Polycarbonate
Capacitor, 10.56
Type 5250 and 6000-101K chokes, 10.56
Type EXCEL leaded ferrite bead EMI filter,
and type EXC L leadless
ferrite ead, 10.56
Type HFQ Aluminum Electrolytic Capacitor
and type V Stacked Polyester
Film Capacitor, 10.56
U
Undersampling, 2.6-7
diagram, 2.6
harmonic sampling, 2.7
Nyquist zone, 2.6
Unipolar converter, 2.9-10
Unsigned fractional format, DSP
arithmetic, 7.23
Unsigned integer format, DSP arithmetic,
7.23
Using the ADSP-2100 Family, 7.55, 8.25
V
Vary, P., 9.43
VCX device, 10.9
74VCX164245 Data Sheet, 10.14
INDEX
Vector control, 9.32-33
Very Large Scale Integration, VLSI, 1.4
Very long instruction word, in SHARC
architecture, 7.37
Video raster scan display system, 1.3
Virtual-IF transmitter, in AD6523, 9.23
VisualDSP++, DSP development software,
7.51
VisualDSP:
DSP development software, 7.51
test drive, 7.53
Viterbi algorithm, 9.6
Viterbi decoder, 9.5
Voice activity detector, 9.20
Voice over the Internet protocol, 7.42
Voice-over-Internet-provider see VOIP
Voltage:
identification pin, 10.1
low, interfaces, 10.1-14
supply, reduction, 10.1
Voltage compliance, 10.5-6
definition, 10.6
internally created, 10.8-10
considerations, 10.9-10
Voltage tolerance, 10.5-6
definition, 10.5-6
internally created, 10.8-10
Voltage-controlled-oscillator, 4.12
Von Neumann architecture, 7.6
W
Waldhauer, F.D., 2.42, 3.29, 3.34
Waurin, Ken, 7.1
Weaver, Lindsay A., 4.17
Weeks, Pat, 2.43
Welland, D.R., 3.33
Wepman, Jeffery, 9.43
Wideband, 9.27
Widrow, B., 6.40
Window function, 5.22-23, 5.23, 6.16
characteristics, 5.24
frequency responses, 5.24
Windowed-sinc method:
FIR filter design, 6.16
responses, diagrams, 6.16
Witte, Robert A., 2.43
Wooley, Bruce, 3.33
Worst harmonic, 2.23-24
Write, DAC, 8.9
X
xDSL protocol, 7.36
Analog Devices Parts Index
AD260/AD261, 10.36-38
AD820, 3.8-9
AD974, 3.5
AD2S80A, 9.33-34
AD2S82A, 9.33-34
AD2S83A, 9.33-34
AD2S90A, 9.33-34
AD185x, 4.11
AD189x, 6.35
AD1819B, 1.5, 9.37-38
AD1836, 9.38-39
AD1852, 3.17
AD1853, 3.17, 4.12
AD1854, 3.17
AD1877, 3.16-17
AD1890, 6.35
AD1891, 6.35
AD1892, 6.35
AD1893, 6.35
AD1896, 6.35
AD5322, 8.17-19
AD5340, 8.10-12
AD6521, 9.21-22
AD6522, 9.21-22
AD6523, 9.22-23, 9.25
AD6524, 9.22-23, 9.25
AD6600, 9.30
AD6622, 9.30-31
AD6624, 9.30-31
AD6640, 2.29-30, 3.24-25
AD6644, 9.30-31
AD7472, 3.5
AD77xx, 3.17
AD773x, 1.5
AD977x, 4.6
AD983x, 4.16
AD984x, 1.5
AD985x, 4.6
AD7660, 3.5
AD7664, 3.5
AD7722, 10.15
AD7725, 3.19, 6.2, 9.40-42
AD7730, 10.15
AD7731, 10.15
AD7853/7853L, 8.15-18
AD7853L, 8.15-17
AD7854/AD7854L, 8.4-7
AD7856/67, 3.5
AD7858/59, 3.5, 3.8-9
AD7861, 9.33
AD7862, 9.33
AD7863, 9.33
Index-19
INDEX
AD7864, 9.33
AD7865, 9.33
AD7887/88, 3.5
AD7891, 3.5
AD7892, 10.15
AD9042, 2.27, 2.31-32
AD9201, 8.22-23
AD9220, 2.24-25, 3.26
AD9221, 3.26
AD9223, 3.26
AD9288-100, 3.32
AD9410, 3.23
AD9761, 8.22-23
AD9772, 2.39, 4.6, 4.9-10, 9.30-31
AD9814, 1.5
AD9815, 1.5
AD9850, 4.15-16
AD73311, 8.1
AD73322, 1.5, 8.1, 8.19-22, 9.36
AD73422, 8.21-22
AD74222-80, 8.21-22
AD20msp430, 9.21-23
AD20msp910, 9.12, 9.15
AD20msp918, 9.15
ADMC200/ADMC201, 9.33
ADMC300, 9.34
ADMC326, 9.34
ADMC328, 9.34
ADMC331, 9.34
ADMC401, 9.34
ADMCF5xx, 9.35
ADMCF326, 9.34
ADMCF328, 9.34
ADP1148, 10.46
ADP3310, 10.47, 10.49-50
ADP33xx, 9.22
ADP34xx, 9.22
ADSP-21ESP202, 9.36-37
ADSP-21mod870, 9.8-10
ADSP-21mod970, 9.10
ADSP-21mod980, 9.10
ADSP-21modxxx, 9.9
ADSP-21msp5x, 7.21
ADSP-21xx, 1.6-8, 6.11-13, 6.28, 7.2, 7.4,
7.6-24, 8.1-3, 8.7-8, 8.12-
Index-20
14, 9.5, 9.8, 9.33, 10.9
ADSP-210x, 7.21
ADSP-216x, 7.21
ADSP-217x, 7.18, 9.34-35
ADSP-218x, 7.7, 7.11, 7.15, 7.18, 7.22, 7.49,
7.51-53, 8.20-22, 9.5,
9.8, 9.10-11, 9.22, 9.36-38
ADSP-218xL/M, 10.1
ADSP-219x, 7.7, 7.11, 7.19-21, 7.23, 7.51-53,
9.35
ADSP-2100, 7.9, 7.15
ADSP-2105, 7.16
ADSP-2106x, 7.26-30
ADSP-2111, 7.21
ADSP-2116x, 7.31-36
ADSP-2181/3, 7.21
ADSP-2183, 9.15
ADSP-2184/L, 7.21
ADSP-2185/L/M, 7.21
ADSP-2185L/86L, 8.21-22
ADSP-2186/L, 7.21
ADSP-2187L/M, 7.21
ADSP-2188M, 7.20, 7.21, 9.10-11
ADSP-2189M, 5.18, 6.1, 6.12, 6.20, 6.22,
6.28, 7.21, 7.47, 8.2-7, 8.912, 8.14-15, 8.23-24
ADSP-21000, 7.26-27
ADSP-21060, 7.29-30, 7.33
ADSP-21060L, 10.58
ADSP-21061, 7.29-30, 7.33
ADSP-21062, 7.29-30, 7.33
ADSP-21065, 7.29-30, 7.33
ADSP-21065L, 7.27, 7.34, 7.48, 8.22-23,
9.38-39
ADSP-21160, 5.18, 7.27, 7.31-32, 7.34, 7.36,
9.39-40, 10.29-31, 10.54-55
ADSP-21160M, 7.33, 7.47
ADSP-21161N, 7.33
ADSP-TS001 TigerSHARC, 5.18-19,
7.36-44, 9.30-31
ADuM1100A, 10.36-37
ADuM1100B, 10.36-37
EZ-ICE, 7.48
EZ-KIT Lite, 7.45-48
EZ-LAB, 7.45