1M x 16-Bit Dynamic RAM 1k & 4k Refresh (Hyper Page Mode- EDO) HYB5116165BSJ -50/-60/-70 HYB5118165BSJ -50/-60/-70 Advanced Information • • • • • • • • • • • • 1 048 576 words by 16-bit organization 0 to 70 °C operating temperature Performance: -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 84 104 124 ns tHPC Hyper page mode (EDO) cycle time 20 25 30 ns Single + 5 V (± 10 %) supply Low power dissipation max. 1100 active mW ( HYB5118165BSJ-50) max. 990 active mW ( HYB5118165BSJ-60) max. 880 active mW ( HYB5118165BSJ-70) max. 550 active mW ( HYB5116165BSJ-50) max. 495 active mW ( HYB5116165BSJ-60) max. 440 active mW ( HYB5116165BSJ-70) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and Self Refresh Hyper page mode (EDO) capability All inputs, outputs and clocks fully TTL-compatible 1024 refresh cycles / 16 ms for HYB5118165BSJ (1k-Refresh) 4096 refresh cycles / 64 ms for HYB5116165BSJ (4k-Refresh) Plastic Package: P-SOJ-42-1 400 mil Semiconductor Group 1 1.96 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM The HYB 5116(8)165BSJ is a 16 MBit dynamic RAM organized as 1 048 576 words by 16-bits. The HYB 5116(8)165BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116(8)165BSJ to be packaged in a standard SOJ 42 plastic package with 400 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type Ordering Code Package Descriptions HYB 5116165BJ-50 on request P-SOJ-42-1 400 mil DRAM (access time 50 ns) HYB 5116165BJ-60 on request P-SOJ-42-1 400 mil DRAM (access time 60 ns) HYB 5116165BJ-70 on request P-SOJ-42-1 400 mill DRAM (access time 70 ns) HYB 5118165BJ-50 Q67100-Q1107 P-SOJ-42-1 400 mil DRAM (access time 50 ns) HYB 5118165BJ-60 Q67100-Q1108 P-SOJ-42-1 400 mil DRAM (access time 60 ns) HYB 5118165BJ-70 Q67100-Q1109 P-SOJ-42-1 400 mil DRAM (access time 70 ns) Pin Names A0-A9 Row Address Inputs for HYB5118165BSJ A0-A9 Column Address Inputs for HYB5118165BSJ A0-A11 Row Address Inputs for HYB5116165BSJ A0 to A7 Column Address Inputs for HYB5116165BSJ RAS Row Address Strobe OE Output Enable I/O1-I/O16 Data Input/Output UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe WE Read/Write Input VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. not connected Semiconductor Group 2 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM P-SOJ-42-1 Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. N.C. A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 400 mil Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11 A10 A0 A1 A2 A3 Vcc HYB3118165BSJ HYB3116165BSJ Pin Configuration Semiconductor Group 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 3 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM I/O16 I/O1 I/O2 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 OE 16 16 Column Address Buffer(8) 8 Data out Buffer Column 8 Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 16 256 x16 12 Row 12 RAS Address Buffers(12) 12 Row Decoder 4096 Memory Array 4096x256x16 No. 1 Clock Generator Voltage Down Generator Block Diagram for HYB 5116165BSJ Semiconductor Group 4 VCC VCC (internal) HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM I/O16 I/O1 I/O2 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 OE 16 16 Column Address Buffer(10) 10 Data out Buffer Column 10 Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (10) 16 1024 x16 10 Row 10 RAS Address Buffers(10) 10 Row Decoder 1024 Memory Array 1024x1024x16 No. 1 Clock Generator Voltage Down Generator Block Diagram for HYB 5118165BSJ Semiconductor Group 5 VCC VCC (internal) HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 °C Storage temperature range.........................................................................................– 55 to 150 °C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics( note : values in brackets for HYB5118165BSJ) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 2 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current (0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V) IO(L) – 10 10 µA 1) Average VCC supply current: ICC1 -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling: tRC = tRC min.) – – – 100(200) mA 90 (180) mA 80 (160) mA 2) 3) 4) Standby VCC supply current (RAS = CAS = VIH) ICC2 – 2 – Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling, CAS = VIH, tRC = tRC min.) ICC3 – – – 100(200) mA 90 (180) mA 80 (160) mA Semiconductor Group 6 mA 2) 4) HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM DC Characteristics( note : values in brackets for HYB5118165BSJ) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 2 ns Parameter Symbol Average VCC supply current, ICC4 during hyper page mode: -50 ns version -60 ns version -70 ns version (RAS = VIL, CAS, address cycling:tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling: tRC = tRC min.) ICC6 Average Self Refresh Current ICC7 Limit Values min. max. Unit Test Condition – – – 70 (90) 55 (75) 45 (60) mA mA mA – 1 mA – – – 100(200) mA 90 (180) mA 80 (160) mA _ 1 2) 3) 4) 1) 2) 4) mA (CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc - 0.2V or 0.2V) Capacitance TA = 0 to 70 °C,VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11) CI1 – 5 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1-I/O16) CIO – 7 pF Semiconductor Group 7 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter 16E Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. common parameters Random read or write cycle time tRC 84 – 104 – 124 – ns RAS precharge time tRP 30 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 8 10k 10 10k 12 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 8 – 10 – 12 – ns RAS to CAS delay time tRCD 12 37 14 45 14 53 ns RAS to column address delay tRAD 10 25 12 30 12 35 ns RAS hold time tRSH 13 15 – 17 – ns CAS hold time tCSH 40 50 – 60 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 1 50 ns Refresh period for HYB5116165 tREF – 64 – 64 – 64 ms Refresh period for HYB5118165 tREF – 16 – 16 – 16 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 13 – 15 – 17 ns 8, 9 Access time from column address tAA – 25 – 30 – 35 ns 8,10 OE access time – 13 – 15 – 17 ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 0 17 ns 12 7 Read Cycle Semiconductor Group tOEA 8 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter 16E Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. Output turn-off delay from OE tOEZ 0 13 0 15 0 17 ns 12 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 10 – 13 – 15 – ns 14 OE high to data delay tODD 10 – 13 – 15 – ns 14 Write command hold time tWCH 8 – 10 – 10 – ns Write command pulse width tWP 8 – 10 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – 17 – ns Write command to CAS lead time tCWL 13 – 15 – 17 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 8 – 10 – 12 – ns 16 Read-write cycle time tRWC 113 – 138 – 162 – ns RAS to WE delay time tRWD 64 – 77 – 89 – ns 15 CAS to WE delay time tCWD 27 – 32 – 36 – ns 15 Column address to WE delay time tAWD 39 – 47 – 54 – ns 15 OE command hold time tOEH 10 – 13 – 15 – ns Hyper page mode (EDO) cycle time tHPC 20 – 25 – 30 – ns CAS precharge time tCP 8 – 10 – 10 – ns Access time from CAS precharge tCPA – 27 – 32 – 37 ns Output data hold time tCOH 5 – 5 – 5 – ns RAS pulse width in EDO mode tRAS 50 200k 60 200k 70 200k ns CAS precharge to RAS Delay tRHPC 27 – – – Write Cycle 15 Read-modify-Write Cycle Hyper Page Mode (EDO) Cycle Semiconductor Group 9 32 37 ns 7 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter 16E Limit Values Symbol -50 min. Unit Note -60 max. min. -70 max. min. max. Hyper Page Mode (EDO) Read-modify-Write Cycle Hyper page mode (EDO) readwrite cycle time tPRWC 58 – 68 – 77 – ns CAS precharge to WE tCPWD 41 – 49 – 56 – ns CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns tCPT 35 – 40 – 40 – ns RAS pulse width tRASS 100k _ 100k _ 100k _ ns 17 RAS precharge tRPS 95 _ 110 _ 130 _ ns 17 CAS hold time tCHS -50 _ -50 _ -50 _ ns 17 CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Self Refresh Cycle Semiconductor Group 10 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA,tCPA, tOEA . tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh Semiconductor Group 11 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM Semiconductor Group 12 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRAS tRP V IH RAS VIL tCSH V IH UCAS LCAS VIL tRAD tASR tCRP tRSH tCAS tRCD tRAL tCAH tASC tASR V Address IH VIL Column Row Row tRCH tRAH tRCS tRRH V WE IH VIL tAA tOEA V OE I/O (Inputs) IH VIL tCDD tDZC tODD tDZO V IH tCAC VIL tCLZ V OH I/O (Outputs) V Hi Z tOFF tOEZ Valid Data Out Hi Z OL tRAC WL1 “H” or “L” Read Cycle Semiconductor Group 13 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD tRSH tCAS V IH UCAS LCAS VIL tRAD tASR Address V IH tRAL Row OE . Row tCWL tWCS t WP IH VIL tWCH tRWL V IH VIL tDS I/O (Inputs) tASR Column VIL V WE tCAH tASC tRAH tCRP tDH V IH Valid Data In VIL V OH I/O (Outputs) V Hi Z OL WL2 “H” or “L” Write Cycle (Early Write) Semiconductor Group 14 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD V IH UCAS LCAS VIL tRAD tASR tCRP tRSH tCAS tCAH tASC tRAL tASR . V IH Address V IL Row tCWL tRWL tWP tRAH V WE Row Column IH VIL tOEH V OE IH tODD tDS tOEZ VIL tDZO tDZC I/O (Inputs) tDH V IH Valid Data VIL tCLZ tOEA V OH I/O (Outputs) V Hi-Z Hi-Z OL “H” or “L” WL3 Write Cycle (OE Controlled Write) Semiconductor Group 15 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRWC tRAS RAS V IH tRP tCSH VIL tRSH tCAS tRCD V tCRP IH CAS VIL tRAH tCAH tASR tASC tASR V IH Address VIL Row Column Row tCWL tRWL tAWD tRAD tCWD tRWD tWP V IH WE VIL tAA tRCS tOEH tOEA V IH OE VIL tDS tDZO tDZC I/O (Inputs) tDH V IH Valid Data in VIL tCLZ tODD tCAC tOEZ V OH I/O (Outputs) VOL Data Out tRAC “H” or “L” WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 16 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRP tRAS V tRCD IH RAS tRHCP VIL tRSH tHPC tCRP tCAS tCP tCAS tCRP tCAS V IH UCAS LCAS VIL tCSH tASR Address tRAH tASC tRAL tCAH V IH VIL Row Column 1 tASC tCAH tASC tCAH Column 2 Column N tRAD tRRH tRCH tRCS WE VIH VIL tOES OH V tCPA tCPA tOFF tOEA V OE tCAC tAA tCAC tAA OL tRAC tAA tCAC tOEZ tCOH tCLZ V I/O IH (Output) V IL Data Out 1 Data Out 2 Data Out N WL5 “H” or “L” Hyper Page Mode (EDO) Read Cycle Semiconductor Group tCOH 17 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRP tRAS V tRHCP tRCD IH RAS VIL tRSH tHPC tCRP tCAS tCAS tCP tCRP tCAS V IH UCAS LCAS VIL tCSH tASR tRAH tASC tRAL tCAH tASC tCAH tASC tCAH Column 2 Column N V IH Address VIL Row Addr Column 1 tRAD tWCS tCWL tCWL tWCH tWCS tWCH tWP tWP WE VIH tRWL tCWL tWCS tWCH tWP VIL V OE OH V OL tDS tDH tDS tDH tDS tDH V IH I/O (Input) V IL Data In 1 Data In 2 “H” or “L” WL8 Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group Data In N 18 Semiconductor Group 19 IH IH IH IH V IH V IL V V IL V V IL V V IL V V IL IH Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle OL OH I/O (Outputs) V V I/O (Inputs) V IL OE WE Address UCAS LCAS RAS V tASR Row tRAH tRAD tRAC tCAS tAA tOEA tCAC Data In tDS tOEH tCLZ tOEZ tWP tDS tDH Data In tODD Data Out tOEA tAWD tCPA tAA tDZC tCAS tPRWC tCPWD tCWD tCAH Column tASC tCP tCWL tWP tOEZ tDH tODD Data Out tAWD tRWD tCWD Column tASC tCAH tDZC tCLZ tDZO tRCS tRCD tCSH tRASP tOEH tDZC tCWL tAWD tCAC tAA tCLZ tCPA tRAL Data Out tDS tDH tOEH tRWL tCWL tWP Data In tODD tCPWD tCWD tOEA Column tASC tCAH tCAS tRSH tCRP Row tASR tRP HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM WL17 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRAS RAS tRP V IH VIL tCRP tRPC UCAS LCAS V IH VIL tRAH tASR tASR V Address IH Row VIL Row V OH I/O (Outputs) V HI-Z OL “H” or “L” WL9 RAS-Only Refresh Cycle Semiconductor Group 20 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRP tRAS tRP V RAS IH VIL tRPC tCSR tCRP tCP UCAS LCAS tRPC tCHR V IH VIL tWRP tWRH V WE IH VIL tOEZ V IH OE VIL tCDD I/O (Inputs) V IH VIL tODD V OH I/O (Outputs)VOL HI-Z tOFF “H” or “L” WL10 CAS-Before-RAS Refresh Cycle Semiconductor Group 21 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRC RAS tRP tRAS V tRP tRAS IH VIL tRSH tRCD tCRP tCHR V UCAS LCAS IH tRAD VIL tWRP tASC tASR tRAH tASR tWRH tCAH V Address IH VIL Column Row Row tRRH tRCS V WE IH VIL tAA tOEA V OE IH VIL tDZC tCDD tDZO tODD V I/O (Inputs) IH VIL tCAC tOFF tCLZ tOEZ tRAC V OH I/O (Outputs) V Valid Data Out HI-Z OL “H” or “L” WL11 Hidden Refresh Cycle (Read) Semiconductor Group 22 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRC tRC tRP RAS tRP tRAS V IH tRAS VIL tRCD tRSH tCHR tCRP V UCAS LCAS IH VIL tRAD tRAH tASC tCAH tASR tASR V Address IH VIL Row tWCS tWRP tWCH tWRH tWP V WE Row Column IH VIL tDS tDH V I/O (Input) IH Valid Data V IL V OH I/O (Output) V OL HI-Z “H” or “L” WL12 Hidden Refresh Cycle (Early Write) Semiconductor Group 23 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRASS tRP RAS tRPS V IH VIL tRPC tCP V UCAS LCAS tCRP tCHS tCSR IH VIL tWRP tWRH V WE OE IH VIL V IH VIL tCDD I/O (Inputs) V IH VIL tODD tOEZ V OH I/O (Outputs) V OL HI-Z tOFF “H” or “L” WL13 CAS before RAS Self Refresh Cycle Semiconductor Group 24 HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM tRP tRAS Read Cycle: RAS V IH V IL UCAS LCAS tRSH tCAS tCP tCHR tCSR V IH V IL tRAL tASC Address V IH Column V IL tWRP WE OE I/O (Inputs) I/O (Outputs) V IL tWRH tRRH tOEA tRCS V IH V IL tDZC V IH V IL tODD tDZO VOH VOL V IH V IL OE V IH V IL I/O (Inputs) V IH tWCS tWRH tDH Data In HI-Z CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group tRWL tCWL tWCH V IL V IH V IL tOEZ Data Out tDS 25 tCDD tOFF tCLZ Write Cycle: I/O (Outputs) Row tAA tCAC V IH tWRP WE tASR tCAH tRCH HYB 5116(8)165BSJ-50/-60/-70 1M x 16-EDO DRAM Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD) 1) 10.3 -0.3 B 0.81 max. 1.27 0.43 9.4 +- 0.1 0.18 A 0.08 42x 11.2 + - 0.25 +- 0.15 25.4 42 22 1 GPJ05853 21 1) 27.43 -0.25 A Index marking 1) does not include plastic or metal protusion of 0.15 max per side Semiconductor Group 26 0.18 B