stpm32

STPM32, STPM33, STPM34
ASSP for metering applications with up to four independent 24-bit
2 order sigma-delta ADCs, 4 MHz OSF and 2 embedded PGLNA
nd
Datasheet - production data
• Twin precision voltage reference: 1.18 V with
independent programmable TC, 30 ppm/°C
typ.
• Internal low drop regulator @ 3 V (typ.)
• QFN packages
QFN24L 4x4x1
QFN32L 5x5x1
• Operating temperature: from -40 °C to +85 °C
Description
Features
• Active power accuracy:
– <0.1% error over 5000: 1 dynamic range
– <0.5% error over 10000: 1 dynamic range
• Exceeds 50-60 Hz EN 50470-x, IEC 62053-2x,
ANSI12.2x standard requirements for AC watt
meters
• Reactive power accuracy:
– <0.1% error over 2000:1 dynamic range
• Dual mode apparent energy calculation
• Instantaneous and averaged power
• RMS and instantaneous voltage and current
• Under and overvoltage detection (sag and
swell) and monitoring
• Overcurrent detection and monitoring
• UART and SPI serial interface with
programmable CRC polynomial verification
• Programmable LED and interrupt outputs
The STPM3x is an ASSP family designed for high
accuracy measurement of power and energies in
power line systems using the Rogowski coil,
current transformer or shunt current sensors. The
STPM3x provides instantaneous voltage and
current waveforms and calculates RMS values of
voltage and currents, active, reactive and
apparent power and energies. The STPM3x is a
mixed signal IC family consisting of an analog and
a digital section. The analog section consists of
up to two programmable gain low-noise low-offset
amplifiers and up to four 2nd order 24-bit sigmadelta ADCs, two bandgap voltage references with
independent temperature compensation, a low
drop voltage regulator and DC buffers. The digital
section consists of digital filtering stage, a
hardwired DSP, DFE to the input and a serial
communication interface (UART or SPI). The
STPM3x is fully configurable and allows a fast
digital system calibration in a single point over the
entire current dynamic range.
• Four independent 24-bit 2nd order sigma-delta
ADCs
Table 1. Device summary
• Two programmable gain chopper stabilized
low-noise and low-offset amplifiers
Order code
Package
Packing
STPM34TR
QFN32L 5x5x1
Tape and reel
• Bandwidth 3.6 kHz @ -3 dB
STPM33TR
QFN32L 5x5x1
Tape and reel
• Vcc supply range 3.3 V±10%
STPM32TR
QFN24L 4x4x1
Tape and reel
• Supply current Icc 4.3 mA (STPM32)
• Input clock frequency 16 MHz, Xtal or external
source
October 2015
This is information on a product in full production.
DocID026142 Rev 3
1/121
www.st.com
Contents
STPM32, STPM33, STPM34
Contents
1
Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Pin programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Typical application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2
Measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3
ADC offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4
Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1
General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.2
Functional description of the analog part . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3
8.4
2/121
8.2.1
Power management section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2.2
Analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2.3
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2.4
Power-on-reset (POR) and enable (EN) . . . . . . . . . . . . . . . . . . . . . . . . 36
Functional description of the digital part . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.1
Digital front end (SDSx bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.2
Decimation block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.3
Filter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3.4
DC cancellation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3.5
Fundamental component filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3.6
Reactive filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Functional description of hardwired DSP . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID026142 Rev 3
STPM32, STPM33, STPM34
9
8.4.1
Active power and energy calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4.2
Fundamental active power and energy calculation . . . . . . . . . . . . . . . . 43
8.4.3
Reactive power and energy calculation . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.4
Apparent power and energy calculation . . . . . . . . . . . . . . . . . . . . . . . . 46
8.4.5
Sign of power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4.6
Calculation of power and energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.4.7
RMS calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.4.8
Zero-crossing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.4.9
Phase meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.4.10
Sag and swell detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.4.11
Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.4.12
AH accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.4.13
Status bits, event bits and interrupt masks . . . . . . . . . . . . . . . . . . . . . . 61
8.5
Functional description of communication peripheral . . . . . . . . . . . . . . . . 65
8.6
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.6.1
Synchronization and remote reset functionality . . . . . . . . . . . . . . . . . . . 67
8.6.2
SPI peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.6.3
UART peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.6.4
UART/SPI status register and interrupt control register . . . . . . . . . . . . . 74
Application design and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.1
Application design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.1.1
9.2
10
11
Contents
Example: current transformer case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Application calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.2.1
Voltage and current calibration (CHVx, CHCx bits) . . . . . . . . . . . . . . . . 80
9.2.2
Phase calibration (PHVx, PHCx bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.2.3
Power offset calibration (OFAx, OFAFx, OFRx, OFSx bits) . . . . . . . . . . 85
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.1
Register map graphical representation . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.2
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.3
UART/SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
10.4
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.1
QFN24L 4x4x1 mm 0.5 pitch package information . . . . . . . . . . . . . . . . .116
DocID026142 Rev 3
3/121
121
Contents
STPM32, STPM33, STPM34
11.2
12
4/121
QFN32L 5x5x1 mm 0.5 pitch package information . . . . . . . . . . . . . . . . .118
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DocID026142 Rev 3
STPM32, STPM33, STPM34
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STPM34, STPM33, STPM32 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programmable pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Suggested external components in metering applications . . . . . . . . . . . . . . . . . . . . . . . . . 25
Convention table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Temperature compensation parameter typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Current channel input preamplifier gain selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LPWx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
STPM3x internal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STPM3x basic calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STPM3x current voltage LSB values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Voltage sag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Voltage swell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Current swell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Tamper tolerance setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
AH accumulator LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Live events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Communication pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Communication session structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SPI control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSBfirst example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSBfirst and MISO line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LSBfirst programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CRCenable programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
UART control register US_REG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
UART control register US_REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Baud rate register examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
UART/SPI status and interrupt control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Example 1 design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Example 1 calculated data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LPWx bits, Cp, LED frequency relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Calibration target values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Calibrator calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Phase-delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Power offset LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Register map legend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Row 0, DSP control register 1 (DSP_CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Row 1, DSP control register 2 (DSP_CR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Row 2, DSP control register 3 (DSP_CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Row 3, DSP control register 4 (DSP_CR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Row 4, DSP control register 5 (DSP_CR5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DocID026142 Rev 3
5/121
121
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
6/121
STPM32, STPM33, STPM34
Row 5, DSP control register 6 (DSP_CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Row 6, DSP control register 7 (DSP_CR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Row 7, DSP control register 8 (DSP_CR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Row 8, DSP control register 9 (DSP_CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Row 9, DSP control register 10 (DSP_CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Row 10, DSP control register 11 (DSP_CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Row 11, DSP control register 12 (DSP_CR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Row 12, digital front end control register 1 (DFE_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Row 13, digital front end control register 2 (DFE_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Row 14, DSP interrupt control mask register 1 (DSP_IRQ1) . . . . . . . . . . . . . . . . . . . . . . 106
Row 15, DSP interrupt control mask register 2 (DSP_IRQ2) . . . . . . . . . . . . . . . . . . . . . . 107
Row 16, DSP status register 1 (DSP_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Row 17, DSP status register 2 (DSP_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Row 18, UART/SPI control register 1 (US_REG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Row 19, UART/SPI control register 2 (US_REG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Row 20, UART/SPI control register 3 (US_REG3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Row 21, DSP live event 1 (DSP_EV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Row 22, DSP live event 2 (DSP_EV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
QFN24L 4x4x1 mm 0.5 pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 117
QFN32L 5x5x1 mm 0.5 pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 119
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DocID026142 Rev 3
STPM32, STPM33, STPM34
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STPM34 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STPM33 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STPM32 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STPM34 pinout (top view), QFN32L 5x5x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STPM33 pinout (top view), QFN32L 5x5x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STPM32 pinout (top view), QFN24L 4x4x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SPI enable and disable timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
UART enable and disable timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output load circuit for enable and disable times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STPM34 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Active energy error vs. current gain=2x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Active energy error vs. current gain=16x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Active energy error vs. frequency gain=2x integrator off . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Active energy error vs. frequency gain=16x integrator off . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reactive energy error vs. current gain=2x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reactive energy error vs. current gain=16x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reactive energy error vs. frequency gain=2x integrator off . . . . . . . . . . . . . . . . . . . . . . . . 28
Reactive energy error vs. frequency gain=16x integrator off . . . . . . . . . . . . . . . . . . . . . . . 28
Active energy error vs. current gain=16x integrator on. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reactive energy error vs. current gain=16x integrator on. . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power management internal connection scheme and polarization. . . . . . . . . . . . . . . . . . . 32
Temperature compensation typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Analog front end internal scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Block diagram of the modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Different oscillator circuits (a): with quartz; (b): with external source . . . . . . . . . . . . . . . . . 35
Clock feed for multiple devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Power-on-reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Global startup reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DSP block functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Filter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DSP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Active power and energy calculation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fundamental active power and energy calculation block diagram . . . . . . . . . . . . . . . . . . . 44
Reactive power and energy calculation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Apparent power and energy calculation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power sign status bit delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RMS block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Zero-crossing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Zero-crossing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Phase meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Sag and swell detection blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Sag detection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Swell detection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AH accumulation block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AH accumulation thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Single communication time frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Memory data organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DocID026142 Rev 3
7/121
121
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
8/121
STPM32, STPM33, STPM34
Latching and reset through SYN pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Latching through SYN pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
UART frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Phase shift error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
QFN24L 4x4x1 mm 0.5 pitch outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
QFN24L 4x4x1 mm 0.5 pitch recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
QFN32L 5x5x1 mm 0.5 pitch outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
DocID026142 Rev 3
STPM32, STPM33, STPM34
1
Schematic diagram
Schematic diagram
Figure 1. STPM34 block diagram
CLKOUT/
ZCR
2nd
order
ΣΔ
modulator
VIP1
VIN1
2nd
order
ΣΔ
modulator
VIP2
VIN2
LED1
LED2 INT1
Decimation
Phase
compensation
Decimation
Phase
compensation
INT2
Filters
nd
2
order
ΣΔ
modulator
IIP1
PLNA
IIN1
2nd
order
ΣΔ
modulator
IIP2
PLNA
Decimation
Phase
compensation
Decimation
Phase
compensation
EN
DSP
IIN2
VDDD
LDR 1.2 V
VRefC2
VOLTAGE
REFERENCE
VRefV2
VRefC1
VOLTAGE
VCC
LDR 3.0 V
OSC 16 MHz
REFERENCE
SPI/UART
VRefV1
VDDA
VREF2 VREF1
XTAL1 XTAL2
SCS MISO/ MOSI/
TXD RXD
SCL
SYN
GIPG1303141224LM
DocID026142 Rev 3
9/121
121
Schematic diagram
STPM32, STPM33, STPM34
Figure 2. STPM33 block diagram
CLKOUT/
ZCR
VIP1
2nd
order
ΣΔ
VIN1
modulator
IIP1
2
order
ΣΔ
Decimation
LED2 INT1
LED1
INT2
EN
Phase
compensation
nd
PLNA
IIN1
Decimation
Phase
compensation
modulator
Filters
DSP
nd
IIP2
PLNA
IIN2
2
order
ΣΔ
Phase
modulator
Decimation
compensation
VDDD
VRefC2
VOLTAGE
REFERENCE
LDR 1.2 V
VRefV2
VRefC1
VCC
VOLTAGE
REFERENCE
LDR 3.0 V
OSC 16 MHz
SPI/UART
VRefV1
VDDA
VREF2 VREF1
XTAL1 XTAL2
SCS MISO/ MOSI/
TXD RXD
SCL
SYN
GIPG1303141235LM
10/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Schematic diagram
Figure 3. STPM32 block diagram
CLKOUT/
ZCR
LED2 INT1
LED1
EN
nd
2
order
ΣΔ
VIP1
VIN1
Decimation
Phase
compensation
modulator
Filters
DSP
nd
IIP1
PLNA
2
order
ΣΔ
Decimation
modulator
IIN1
Phase
compensation
VDDD
LDR 1.2 V
VRefC1
VCC
VOLTAGE
REFERENCE
LDR 3.0 V
OSC 16 MHz
VRefV1
VDDA
VREF1
XTAL1 XTAL2
SPI/UART
SCS MISO/ MOSI/
TXD RXD
SCL
SYN
GIPG1303141239LM
DocID026142 Rev 3
11/121
121
Pin configuration
2
STPM32, STPM33, STPM34
Pin configuration
VDDD
GNDD
GNDD
27
26
25
SCL
30
SCS
28 SYN
MOSI/RXD
31
29
MISO/TXD
32
Figure 4. STPM34 pinout (top view), QFN32L 5x5x1
CLKOUT/ZCR
1
24
NC
CLKIN/XTAL2
2
23
VCC
XTAL1
3
22
GND_REG
LED1
4
21
VDDA
LED2
5
20
GNDA
INT1
6
19
VREF2
INT2
7
18
GND_REF
EN
8
17
VREF1
9
10
11
12
13
14
15
16
VIP1
VIN1
IIP1
IIN1
IIN2
IIP2
VIN2
VIP2
STPM34
GIPG1303141253LM
12/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Pin configuration
GNDD
NC
26
25
SCS
SYN
29
VDDD
SCL
30
27
MOSI/RXD
31
28
MISO/TXD
32
Figure 5. STPM33 pinout (top view), QFN32L 5x5x1
CLKOUT/ZCR
1
24
NC
CLKIN/XTAL2
2
23
VCC
XTAL1
3
22
GND_REG
LED1
4
21
VDDA
LED2
5
20
GNDA
INT1
6
19
VREF2
INT2
7
18
GND_REF
EN
8
17
VREF1
14
15
IIP2
NC
NC
16
13
11
IIP1
IIN2
10
VIN1
IIN1 12
9
VIP1
STPM33
GIPG1303141257LM
MISO/TXD
MOSI/RXD
SCL
SCS
SYN
VDDD
24
23
22
21
20
19
Figure 6. STPM32 pinout (top view), QFN24L 4x4x1
CLKOUT/ZCR
1
18
GNDD
CLKIN/XTAL2
2
17
VCC
XTAL1
3
16
GND_REG
LED1
4
15
VDDA
LED2
5
14
GNDA
INT1
6
13
GND_REF
7
8
9
10
11
12
EN
VIP1
VIN1
IIP1
IIN1
VREF1
STPM32
DocID026142 Rev 3
GIPG1303141303LM
13/121
121
Pin configuration
STPM32, STPM33, STPM34
Table 2. STPM34, STPM33, STPM32 pin description
Description and
multiplexed function
STPM33
STPM32
Name
1
1
1
CLKOUT/ZCR
-Zero-crossing output
-System clock output
From 0 to VCC
Multifunctional
2
2
2
CLKIN/XTAL2
-Input of external clock
-External crystal input 2
From 0 to VCC
Oscillator
3
3
3
XTAL1
-External crystal input 1
From 0 to VCC
Oscillator
4
4
4
LED1
-Pulse output 1
-Primary current SD
bitstream
From 0 to VCC
Multifunctional
5
5
5
LED2
-Pulse output 2
-Secondary current SD
bitstream
From 0 to VCC
Multifunctional
6
6
6
INT1
-Interrupt 1
-Primary voltage SD
bitstream
From 0 to VCC
Multifunctional
7
7
INT2
-Interrupt 2
-Secondary voltage SD
bitstream
From 0 to VCC
Multifunctional
8
8
7
EN
Enable pin
From 0 to VCC
Signal
9
9
8
VIP1
Positive voltage primary
input
From -0.3 V to
0.3 V
Signal
10
10
9
VIN1
Negative voltage primary
input
From -0.3 V to
0.3 V
Signal
11
11
10
IIP1
Positive current primary
input
From -0.3 V to
0.3 V
Signal
12
12
11
IIN1
Negative current primary
input
From -0.3 V to
0.3 V
Signal
13
13
IIN2
Negative current secondary From -0.3 V to
input
0.3 V
Signal
14
14
IIP2
Positive current secondary
input
From -0.3 V to
0.3 V
Signal
15
-
VIN2
Negative voltage secondary From -0.3 V to
input
0.3 V
Signal
16
-
VIP2
Positive voltage secondary
input
From -0.3 V to
0.3 V
Signal
17
17
12
VREF1
Output of voltage reference
1
From 1.16 V to
1.18 V
Power
18
18
13
GND_REF
19
19
20
20
14/121
14
Voltage range
Functional
section
STPM34
Analog ground of VREF
VREF2
Output of voltage reference
2
GNDA
Analog ground (shield)
DocID026142 Rev 3
Power
From 1.16 V to
1.18 V
Power
Power
STPM32, STPM33, STPM34
Pin configuration
Table 2. STPM34, STPM33, STPM32 pin description (continued)
Description and
multiplexed function
STPM33
STPM32
Name
21
21
15
VDDA
22
22
16
GND_REG
23
23
17
VCC
Voltage supply
24
15, 16,
24, 25
-
NC
Not connected
25, 26
26
18
GNDD
Digital ground
27
27
19
VDDD
Output of voltage regulator
1.2 V
28
28
20
SYN
Synchronization pin
From 0 to VCC
SPI
29
29
21
SCS
Chip-select SPI/UART
select
From 0 to VCC
SPI/UART
30
30
22
SCL
SPI clock
From 0 to VCC
SPI
31
31
23
MOSI/RXD
SPI master OUT slave IN
UART RX
From 0 to VCC
SPI/UART
32
32
24
MISO/TXD
SPI master IN slave OUT
UART TX
From 0 to VCC
SPI/UART
Output of voltage regulator
Voltage range
Functional
section
STPM34
3.0 V
Ground
DocID026142 Rev 3
Power
Power
From 3.0 V to
3.6 V
Power
Power
Power
15/121
121
Absolute maximum ratings
3
STPM32, STPM33, STPM34
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
Value
Unit
-0.3 to 4.2
V
-0.3 to VCC + 0.3
V
-0.7 to 0.7
V
Human body model (all pins)
±2
kV
Current injection latch-up immunity
100
mA
Operating junction temperature range
-40 to 85
°C
Junction temperature
-40 to 150
°C
Storage temperature range
-55 to 150
°C
VCC
DC input voltage
VID
Any pin input voltage
VIA
Analog pin input voltage (VIP, VIN, IIP, IIN)
ESD
ILATCH
TOP
Tj
TSTG
Note:
Parameter
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. All values are referred to GND.
Table 4. Thermal data
Symbol
RthJA
Note:
16/121
Parameter
Package
Value
QFN32L 5x5x1
30
QFN24L 4x4x1
20
Thermal resistance junction-ambient
°C/W
This value is referred to single-layer PCB, JEDEC standard test board.
DocID026142 Rev 3
Unit
STPM32, STPM33, STPM34
4
Electrical characteristics
Electrical characteristics
VCC = 3.3 V, CL=1 µF between VDDA and GNDA, CL = 4.7 µF between VDDD and GNDD,
CL= 1 µF between VCC and GND, CL = 100 nF between VREF1, 2 and GNDREF, FCLK = 16
MHz, TAMB = 25 °C, EN = VCC, SPI/UART not used, unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
2.95
3.3
3.65
V
General section
VCC
ICC
FCLK
Operating supply
voltage
Operating current
STPM32
4.3
STPM33
5.0
STPM34
5.9
STPM34
Primary channel ON: ENVREF1 = 1,
enV1 = enC1 = 1
Secondary channel OFF: ENVREF2 =
0, enV2 = enC2 = 0
4.5
STPM34
Primary current channel ON only:
ENVREF1 = 1, enV1 = 0, enC1 = 1
Secondary channel OFF: ENVREF2 =
0, enV2 = enC2 = 0
4.0
Nominal frequency
mA
16
MHz
2.5
V
1
uA
Power management (VDDA, VDDD, GNDA, GNDD, GND_REG, EN)
VPOR
Power-on-reset on VCC
ISTBY
Standby current
consumption
VDDA
Analog regulated
voltage
2.85
V
VDDD
Digital regulated
voltage
1.2
V
50
dB
1.18
V
30
ppm/°
C
±25
ppm/°
C
PSRRREGS
Power supply rejection
ratio (1)
EN=GND
50 Hz
On-chip reference voltage (VREF1, VREF2)
VREF
TC
TCstep
Reference voltage
No load on VREF, TC = 010 (default)
Temperature
coefficient(2)
Default
TC programmable
step(2)
DocID026142 Rev 3
17/121
121
Electrical characteristics
STPM32, STPM33, STPM34
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
-300
+300
V
-300
-150
-75
-37.5
+300
+150
+75
+37.5
Analog inputs (VIP1, VIN1, VIP2, VIN2, IIP1, IIN1, IIP2, IIN2)
Voltage channels (VIP1-VIN1, VIP2VIN2)
VMAX
Maximum input signal
levels
Voff
Amplifier offset(2)
ZVin
Voltage channel input
impedance(1)
ZIin
Current channel input
differential
impedance(1)
Channel gain error
GERR
Crosstalk(1)
Current channels (IIP1-IIN1, IIP2-IIN2)
Gain 2X
Gain 4X
Gain 8X
Gain 16X
Shorted and grounded input
mV
1
mV
8
MΩ
Gain 2X
Gain 4X
Gain 8X
Gain 16X
90
170
300
510
kΩ
Input VMAX/2
±5
%
Voltage to current channels
-120
Current to voltage channels
-120
dB
Digital I/O (CLKOUT/ZCR, XTAL1, CLKIN/XTAL2, LED1, LED2, INT1, INT2)
VIH
Input high-voltage
VIL
Input low-voltage
VCC = 3.2 V
VOH
Output high-voltage
IO = -1 mA, CL= 50 pF, VCC = 3.2 V
VOL
Output low-voltage
IO = +1 mA, CL= 50 pF, VCC = 3.2 V
0.75
VCC
3.3
V
-0.3
0.6
V
VCC-0.4
V
0.4
V
Energy measurement accuracy
AP
RP
Over dynamic range 5000:1
PGA = 2 to 16
0.1
Over dynamic range 10000:1
PGA = 2 to 16
0.5
Reactive power
Over dynamic range 2000:1
PGA = 2 to 16
0.1
Voltage RMS
Over dynamic range 1:200
0.5
Current RMS
Over dynamic range 1:500
0.5
Effective bandwidth
-3 dB, HPF = 1
Active power
%
%
RMS
fBW
4
3600
Hz
Sigma-delta ADC performance
OSF
DR
18/121
Oversampling
frequency
4
Decimation ratio
1/512
DocID026142 Rev 3
MHz
STPM32, STPM33, STPM34
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Fs
FBW
BW
Parameter
Test conditions
Min.
Sampling frequency
Typ.
Max.
7.8125
Flat band
<0.05 dB allowed ripple
2
Effective bandwidth
-3 dB, HPF=0
0
Unit
kHz
kHz
3600
Hz
DC measurement accuracy
PSRRAC
Power supply AC
rejection(2)
Voltage input shorted
Current input shorted
VCC = 3.3 V±150 mVp @ 1 kHz
65
dB
SPI timings(3)
t_en
Time between selection
and clock
50
ns
t_clk
Clock period
50
ns
t_cpw
Clock pulse width
25
ns
t_setup
Set-up time before
slave sampling
10
ns
t_hold
Hold time after slave
sampling
40
ns
tpZL
Enable to low level time
tpLZ
Disable from low level
time
VCC = 3.3 V± 10%,
VIN = 0 to 3 V, 1 MHz,
Rise time = fall time = 6 ns
RL = 1 KOhm, CL = 50 pF
see Figure 10
25
ns
15
ns
UART timings(3)
t1
CS enable to RX start
5
ns
t2
Stop bit to CS disable
1
µs
t3
CS disable to TX idle hold time
tpZH
Enable to high level
time
tpHZ
Disable from high level
time
250
VCC = 3.3 V± 10%,
VIN = 0 to 3 V, 1 MHz,
Rise time = fall time = 6 ns
RL = 1 KOhm, CL = 50 pF
see Figure 10
ns
21
ns
11
ns
SYN timings(3)
t_ltch
Time between
de-selection and latch
20
ns
t_lpw
Latch pulse width
4
µs
t_w
Time between two
consecutive latch
pulses
4
µs
t_rpw
Reset pulse width
4
µs
DocID026142 Rev 3
19/121
121
Electrical characteristics
STPM32, STPM33, STPM34
Table 5. Electrical characteristics (continued)
Symbol
t_rel
t_startup
Parameter
Test conditions
Typ.
Max.
Unit
Time between pulse
and selection
40
ns
Time between poweron and reset
35
ms
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Guaranteed by application.
20/121
Min.
DocID026142 Rev 3
STPM32, STPM33, STPM34
Electrical characteristics
Figure 7. SPI timings
t_en
SCS
t_clk
t_cpw
SCL
MOSI
t_setup
t_hold
t_lpw
t_rpw
SYN
t_ltch
t_w
t_rel
GIPG2503141109LM
Figure 8. SPI enable and disable timing diagrams
QV
6&6
QV
9
9
9
WS=/
*1'
WS/=
0,62
9FF
9
92/ 9
92/
*,3*/0
DocID026142 Rev 3
21/121
121
Electrical characteristics
STPM32, STPM33, STPM34
Figure 9. UART enable and disable timing diagrams
QV
QV
9
6&6
9
9
WS=+
*1'
WS+=
92+ 9
92+
9
0,62
*1'
*,3*/0
Figure 10. Output load circuit for enable and disable times
3UREH
0,62
.RKP
9FF
*1'
S)
3UREHDQGERDUGFDSDFLWDQFHLQFOXGHG
22/121
DocID026142 Rev 3
*,3*/0
STPM32, STPM33, STPM34
4.1
Electrical characteristics
Pin programmability
Table 6. Programmable pin functions
Name
Multiplexed function
Functional description
System clock signal
Clock signals (DCLK, SCLK, MCLK, CLKIN)
Zero-crossing
Line voltage/current zero-crossing
CLKOUT/ZCR
I/O
Output
Primary channel energies (A, AF, R, S)(1)
Programmable pulse 1
Secondary channel energies (A, AF, R, S)
Primary ± secondary channel energies (A, AF,
R, S)
LED1
SD out current (DATI1)
Output
Sigma-delta bitstream of primary current
channel
Primary channel energies (A, AF, R, S)
Programmable pulse 2
Secondary channel energies (A, AF, R, S)
Primary ± secondary channel energies (A, AF,
R, S)
LED2
SD current (DATI2)
Sigma-delta bitstream of secondary current
channel
Interrupt
Programmable interrupt 1
SD voltage (DATV1)
Sigma-delta bitstream of primary voltage
Interrupt
Programmable interrupt 2
SD out voltage (DATV2)
Sigma-delta bitstream of secondary voltage
SPI/UART select
Serial port selection at power-up
Chip-select
SPI/UART chip-select
INT1
Output
Output
INT2
Output
SCS
Output
SPI master OUT slave IN SPI
MOSI/RXD
Input
UART RX
UART
SPI master IN slave OUT SPI
MISO/TXD
Output
UART TX
UART
1. A: active wideband; AF: active fundamental; R: reactive; S: apparent.
DocID026142 Rev 3
23/121
121
Typical application example
5
STPM32, STPM33, STPM34
Typical application example
Figure 11 below shows the reference schematic of an application with the following
properties:
•
Constant pulses CP = 41600 imp/kWh
•
INOM = 5 A
•
IMAX = 90 A
Typical values for current sensor sensitivity are indicated in Table 7.
For more information about the application dimensioning and calibration please refer to
Section 9.
Figure 11. STPM34 application schematic
NC
VCC
GNDreg
VDDA
GNDA
VREF2
GNDref
VREF1
24
23
22
21
20
19
18
17
1
Vref2
Vref1
9
10
11
12
13
14
15
16
R2
2
22K
C8
C9
100n
150p
R14
270K
Vp1
R13
C24
270K
22n
R26
C34
470R
22n
R24
270K
1
470R
Enable/RST
R12
J9
2
R25
270K
Vp2
R15
Vn2
2
Vcc
Vn1
J4
3
J11
Vref 1-2
Vref2
100R R3
3
Vcc
C30
CKout/ZCR
XTAL2
U3
CKin/XTAL1
LED1
STPM33/34
LED2
INT1
INT2
EN
C23
100u 10V
C29
1
2
3
4
5
6
7
8
16MHz
100n
1u
1M
C17
15p
C22
100n
Y1
R4
Vref1
1
Ex
VP1
VN1
IP1
IN1
IN2
IP2
VN2/NC
VP2/NC
1 Int1
2 Int2
3 Led2
4 En/Rst
5 Led1
6 Gnd
7 Ckin
8 Ckout/ZCR
Ex
MISO
MOSI
SCL
SCS
SYN
VDDD
GNDD
GNDD-NC
C16
15p
4.7u
32
31
30
29
28
27
26
25
DIGITAL I/O
100n
C28
TXD
C32
C15 150p
C20
150p
RXD
1
3
5
7
DC Supply
C19
1
2
100R R11
C14 150p
2
4
6
8
J7
Vcc
C31
2
4
6
8
10
C13 150p
J5
100n
J6
150p
SPI
C12 150p
R5
4.7K
C27
R6
4.7K
C26
10K 10K 10K 10K
C11 150p
C21
C10 10n
150p
LED2
C18
DL2
1 NC
2 MOSI
3 Gnd
4 MISO
5 SCS
6 SCL
7 NC
8 SYN
9 NC
10 Vcc
R10
150p
LED1
R9
1
3
5
7
9
DL1
R8
100n
R7
SCS
150p
Vcc
R23
270K
J10
270K
line2
1
L1
1
L2
R17
Ip1
Ip2
1K
J8
RS1
BKW-M-R0003-5.0
C25
C33
10n
10n
1
R20
1K
R21
6R
VAC 4626-X002
N
R18
0R
In1
In2
1K
T2
R22
1K
GIPG040320140930LM
24/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Typical application example
Table 7. Suggested external components in metering applications
Function
Component
Line voltage
interface
Resistor
divider
Description
R to R ratio VRMS=230 V
1:1650
R to R ratio VRMS=110 V
1:830
Rogowski coil
Line current
interface
CT
Current to voltage ratio kS
Shunt
Note:
Value
Tolerance
±1%
0.15
±5%
2.4
±5%
0.3
±5%
Unit
50 ppm/°C
V/V
50 ppm/°C
mV/A
Above listed components refer to typical metering applications. The STPM3x operation is
not limited to the choice of these external components.
DocID026142 Rev 3
25/121
121
Terminology
STPM32, STPM33, STPM34
6
Terminology
6.1
Conventions
The lowest analog and digital power supply voltage is named GND and represents the
system ground. All voltage specifications for digital input/output pins are referred to GND.
The highest power supply voltage is named VCC. The highest core power supply is internally
generated and is named VDDA. Positive currents flow to a pin. Sinking current means that
the current is flowing to the pin and it is positive. Sourcing current means that the current is
flowing out of the pin and it is negative. A positive logic convention is used in all equations.
Table 8. Convention table
6.2
Type
Convention
Example
Pins
All capitals
VDDA
Internal signal
All capitals are italic
VDDA
Configuration bit
All capitals are underlined
ROC1
Register name
All capitals are bold
DSP_CR1
Measurement error
The power measurement error is defined by the following equation:
Equation 1
measuredpower – truepower
e% = ---------------------------------------------------------------------------------truepower
All measurements come from the comparison with a higher class power (0.02% error) meter
reference. Output bitstream of modulator is indicated as bsV and bsC for voltage and
current channel respectively.
6.3
ADC offset error
This is the error due to DC component associated with the analog inputs of the A/D
converters. Due to the internal automatic DC offset cancellation, the STPM3x measurement
is not affected by DC components in voltage and current channel. DC offset cancellation is
implemented in DSP thanks to a dedicated HPF.
6.4
Gain error
The gain error is due to the signal channel gain amplifiers. This is the difference between
the measured ADC code and the ideal output code. The difference is expressed as
percentage of the ideal code.
26/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
7
Typical performance characteristics
Typical performance characteristics
Active energy error is measured at T = 25 °C, over phi (0°, 60°, -60°)
Reactive energy error is measured at T = 25 °C, over phi (90°, -90°, 60°, -60°)
Figure 12. Active energy error vs. current
gain=2x integrator off
Figure 13. Active energy error vs. current
gain=16x integrator off
1
1
phi=0°
0.8
0.8
0.6
phi=-60°
phi=+60°
phi=0°
0.6
phi=+60°
phi=-60°
0.4
0.4
0.2
error[%]
error[%]
0.2
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0.01
0.1
1
10
100
-1
0.01
Current Amplitude to full -scale ratio [%]
GIPG1403141112LM
Figure 14. Active energy error vs. frequency
gain=2x integrator off
0.1
1
10
Current Amplitude to full - scale ratio [%]
100
GIPG1403141120LM
Figure 15. Active energy error vs. frequency
gain=16x integrator off
1
1
phi=0°
phi=+60°
phi=-60°
0.8
0.6
0.6
0.4
0.4
0.2
0.2
error [%]
error [%]
phi=0°
phi=+60°
phi=-60°
0.8
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
45
50
55
Frequency [Hz]
60
65
-1
45
GIPG1403141123LM
DocID026142 Rev 3
50
55
Frequency [Hz]
60
65
GIPG1403141129LM
27/121
121
Typical performance characteristics
STPM32, STPM33, STPM34
Figure 16. Reactive energy error vs. current
gain=2x integrator off
Figure 17. Reactive energy error vs. current
gain=16x integrator off
1
1
0.8
0.8
0.6
0.6
phi=+60°
phi=-60°
phi=+90°
phi=-90°
0.4
0.2
error[%]
error[%]
0.2
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0.01
phi=+60°
phi=-60°
phi=+90°
phi=-90°
0.4
0.1
1
Current Amplitude to full - scale ratio [%]
10
-1
0.01
100
0.1
1
Current amplitude to full -scale ratio [%]
10
GIPG1403141132LM
Figure 18. Reactive energy error vs. frequency
gain=2x integrator off
100
GIPG1403141135LM
Figure 19. Reactive energy error vs. frequency
gain=16x integrator off
1
1
phi=+90°
phi=-90°
phi=+60°
phi=-60°
0.8
0.6
phi=+90°
phi=-90°
phi=+60°
phi=-60°
0.8
0.6
0.4
0.4
error [%]
0.2
error [%]
0.2
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
45
-1
45
50
55
Frequency [Hz]
60
65
GIPG1403141137LM
28/121
DocID026142 Rev 3
50
55
Frequency [Hz]
60
65
GIPG1403141141LM
STPM32, STPM33, STPM34
Typical performance characteristics
Figure 20. Active energy error vs. current
gain=16x integrator on
Figure 21. Reactive energy error vs. current
gain=16x integrator on
1
1
phi=0°
phi=-60°
phi=+60°
0.8
0.8
0.6
0.6
0.4
0.2
0.2
error [%]
error [%]
phi=+60°
phi=-60°
phi=+90°
phi=-90°
0.4
0
-0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0.010
0.100
1.000
10.000
Current amplitude to full -scale ratio [%]
100.000
-1
0.010
GIPG1403141143LM
DocID026142 Rev 3
0.100
1.000
10.000
Current amplitude to full - scale ratio [%]
100.000
GIPG1403141145LM
29/121
121
Theory of operation
STPM32, STPM33, STPM34
8
Theory of operation
8.1
General operation description
The STPM3x product family measures up to two line voltages and two line currents to
perform active, reactive and apparent power and energy, RMS and instantaneous values,
and line frequency information measurement of a single, split or poly-phase metering
system.
The STPM3x generates up to two independent train pulse output signals proportional to the
active, reactive, apparent or cumulative power. It also generates up to two programmable
interrupt output signals.
The internal register map and the configuration registers can be accessed by SPI or UART
interface.
The STPM3x converts analog signals, through four independent channels in parallel via
sigma-delta analog-to-digital converters, into a binary stream of sigma-delta signals with the
appropriate not overlapped control signal generator.
This technique fits to measure electrical line parameters (voltage and current) via analog
signals from voltage sensors and current sensors (inductive Rogowski coil, current
transformer or shunt resistors). Current channel inputs are connected, through external antialiasing RC filter, to a Rogowski coil or current transformer (CT) or shunt current sensor
which converts line current into the appropriate voltage signal. Each current channel
includes a low-noise voltage preamplifier with a programmable gain. Voltage channels are
connected to a line voltage modulator (ADC). All channels have quiescent zero signal point
on GND, so the STPM3x samples differential signals on both channels with their zero point
around GND.
The converted sigma-delta signals feed an internal decimation filter stage that decimates 4
MHz bitstreams of a factor 512 allowing a 3.6 kHz bandwidth at -3 dB. The 24-bit voltage
and current data feed an internal configurable filtering block and the hardwired DSP that
performs the final computation of metrology quantities.
The STPM3x also includes two programmable temperature compensated bandgap
reference voltage generators and low drop supply voltage regulator. All reference voltages
are designed to eliminate the channel crosstalk.
The mode of operation and configuration of the device can be selected by dedicated
configuration registers.
30/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
8.2
Theory of operation
Functional description of the analog part
The analog part of the STPM3x consists of the following sections:
•
•
8.2.1
Power management section:
–
Reference voltage generators with programmable independent temperature
compensation
–
+3 V low drop supply voltage regulator
–
+1.2 V low drop supply voltage regulator
Analog front end section:
–
Preamplifiers in the two current channels
–
2nd order sigma-delta modulators
•
Clock generator
•
Power-on-reset (POR)
Power management section
Supply pins for the analog part are: VCC, VDDA, VDDD and GND.
GND pins represent the reference point.
VCC pin is the power supply input namely +3.3 V to GND_REG, it has to be connected to
GND_REG via a 1 µF capacitor.
VDDA and VDDD are analog output pins of internal +3.0 V and +1.2 V low drop voltage
regulators.
At least 1 µF capacitor should be connected between VDDA and GNDA. At least 1 µF
(better 4.7 µF) capacitor should be connected between VDDD and GNDD. The input of the
mentioned regulators is VCC.
There are two voltage references embedded in the STPM33 and STPM34, while the
STPM32 embeds a single reference.
It is possible to switch off each reference voltage and each voltage or current channel
independently for power saving purpose.
EN_REF1 and EN_REF2 bits in DSP_CR1 and DSP_CR2 switch on/off the voltage
reference.
To disable a single voltage or current channel, enV1, enC1 bits for primary channel and
enV2, enC2 for secondary channel should be cleared in DFE_CR1 and DFE_CR2
respectively. Switching off some channels allows an operating current reduction as reported
in Table 5.
As described in Figure 22, two EN_REF1 and EN_REF2 bits enable the voltage references;
if a unique voltage reference is used, one of these two bits must be disabled and VREF1
and VREF2 pins must be shorted; if an external reference is used both bits must be disabled
and the external reference must be connected to VREF1, VREF2 pins. VREF1 and VREF2
outputs should be connected to GNDREF via a 100 nF capacitor independently.
DocID026142 Rev 3
31/121
121
Theory of operation
STPM32, STPM33, STPM34
Figure 22. Power management internal connection scheme and polarization
VDDD
TC2
VRefC2
ENVREF1
4.7 uF
VOLTAGE
REFERENCE
LDR 1.2 V
VRefV2
GNDD
TC1
VRefC1
ENVREF2
3.3 V
1 μF
VCC
VOLTAGE
REFERENCE
LDR 3.0 V
VRefV1
GND_REG
GNDA
VREF2
VDDA GNDREF
VREF1
100 nF
1 uF
100 nF
GIPG1303141315LM
Temperature compensated reference voltage generators produce VREF1 = VREF2 = 1.18
V at default settings. The primary voltage reference is always on and supplies the voltage
and the primary current channel, the secondary voltage reference is by default in on-state
and supplies the secondary channel.
These reference temperature compensation curves can be selected through three
configuration bits: TCx[2:0] (DSP_CR1 and DSP_CR2).
Table 9. Temperature compensation parameter typical values
32/121
TCx0
TCx1
TCx2
VREF (V)
TC_VREF (ppm/°C)
0
0
0
1.16
-50
0
0
1
1.17
-25
0
1
0
1.18
0 (default)
0
1
1
1.19
25
1
0
0
1.2
50
1
0
1
1.21
75
1
1
0
1.22
100
1
1
1
1.225
125
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Figure 23. Temperature compensation typical curves
1.24
TC=000
TC=001
TC=010
TC=011
TC=100
TC=101
TC=110
TC=111
1.23
reference voltage [V]
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
-40
8.2.2
-20
0
20
40
Temperature [°C]
60
80
GIPG1403141153LM
Analog front end
Analog channel inputs of voltages VIP1, VIN1, VIP2, VIN2 and currents IIP1, IIN1; IIP2, IIN2
are fully differential.
Voltage channels have a preamplification gain of 2, which defines the maximum differential
voltage on voltage channel inputs to ± 300 mV.
Current channels have a programmable gain selectable among 2, 4, 8 and 16, which
defines the maximum differential voltage on current channel to ±300 mV, 150 mV, 75 mV or
±37.5 mV respectively. The selection is given by GAINx[1:0] (DFE_CR1, DFE_CR2) bits as
described in the following table:
Table 10. Current channel input preamplifier gain selection
GAINx0
GAINx1
Gain
Differential input
0
0
X2
±300 mV
0
1
X4
±150 mV
1
0
X8
±75 mV
1
1
X16
±37.5 mV
The oversampling frequency of the modulators is 4 MHz, the output bitstreams of the 2nd
order sigma-delta modulators relative to the voltage and to the two current channels are
available on INT and LED output pins through the proper configuration (see configuration bit
map).
DocID026142 Rev 3
33/121
121
Theory of operation
STPM32, STPM33, STPM34
Figure 24. Analog front end internal scheme
nd
2
order
ΣΔ
modulator
VIPx
VINx
bsV
DFE
GAINx [1:0]
nd
IIPx
PLNA
IINx
2
order
ΣΔ
modulator
bsC
GIPG1303141321LM
PLNA uses the chopping technique to cancel the intrinsic offset of the amplifier.
A dedicated block generates chopper frequencies for voltage and current channels.
The amplified signals are fed to the 2nd order sigma-delta modulator.
The analog-to-digital conversion in the STPM3x is carried out using four 2nd order sigmadelta converters. A pseudo-random block generates pseudo-random signals for voltage and
current channels. These random signals implement the dithering technique in order to decorrelate the output of the modulators and avoid accumulation points on the frequency
spectrum. The device performs A/D conversions of analog signals on four independent
channels in parallel.
Figure 25. Block diagram of the modulator
Dithering
1st integrator
input
-
a1
∫
2nd integrator
-
comparator
stream out
∫
a2
D/A
GIPG1303141326LM
34/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
The sigma-delta modulators convert the input signals into a continuous serial stream of “1”
and “0” at a rate determined by the sampling clock. In the STPM3x, the oversampling clock
is equal to 4 MHz.
1-bit DAC in the feedback loop is driven by the serial data stream. DAC output is subtracted
from the input signal and from the integrated error. If the loop gain is high enough, the
average value of DAC output (and therefore the bitstream) can approach to the input signal
level. When a large number of samples are averaged, a very precise value of the analog
signal is obtained. This average is described in DSP section.
The converted sigma-delta bitstreams of voltage and current channels are fed to the internal
hardwired DSP unit, which decimates, filters and processes those signals in order to boost
the resolution and to yield all necessary signals for computations.
8.2.3
Clock generator
All the internal timing of the STPM3x is based on the input clock signal, namely 16 MHz.
This signal can be provided in two different ways:
1.
External quartz: the oscillator works with an external crystal
2.
External clock: the XTAL2 pin can be fed by an external 16 MHz clock signal
The clock generator is powered by the analog supply and is responsible for two tasks. The
former delays the turn-on of some function blocks after POR in order to help a smooth start
of external power supply circuitry by keeping off all major loads. The latter provides all
necessary clocks for analog and digital parts.
Figure 26. Different oscillator circuits (a): with quartz; (b): with external source
CLKOUT/ZCR
CLKOUT/ZCR
CLKIN/XTAL2
CLKIN/XTAL2
XTAL1
XTAL1
1 MΩ
15 pF
16 MHz 15 pF
GIPG1303141329LM
From the external 16 MHz clock, the entire clock tree is generated. All internal clocks have
50% duty cycle.
DocID026142 Rev 3
35/121
121
Theory of operation
STPM32, STPM33, STPM34
Table 11. Clock tree
CLK name
Name
Typical value
Description
Input clock
CLKIN
16 MHz
External clock
Master clock
MCLK
4 MHz
Master root clock
Analog sampling
clock
SCLK
4 MHz
OSF of sigma-delta modulators
Decimated clock
DCLK
7.8125 kHz
Sampling frequency of instantaneous voltage and
current values
CLKOUT pin can be used to feed another STPM3x device clock with 16 MHz, when multiple
STPM3x are used in cascade as shown in Figure 27.
Figure 27. Clock feed for multiple devices
XTAL1
XTAL1
CLKOUT/ZCR
CLKIN/XTAL2
CLKIN/XTAL2
CLKIN/XTAL2
CLKOUT/ZCR
CLKOUT/ZCR
XTAL1
1 MΩ
15 pF
15 pF
GIPG2503141257LM
8.2.4
Power-on-reset (POR) and enable (EN)
The STPM3x contains a power-on-reset (POR) circuit which delays the startup of the digital
domain about 750 µs. If VCC supply is less than 2.5 V the STPM3x goes to the inactive
state, all functions are blocked asserting a reset condition. This is useful to assure the
correct device operation during the power-up and power-down.
POR sequence is illustrated in Figure 28: after the start of two LDOs and internal PowerOK
signals are asserted, the analog block first and the digital block after start the processing.
36/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Figure 28. Power-on-reset sequence
EN
VDDD
LDR 1.2 V
PowerOK_1.2 V
POR
PowerOK_3.0 V
VDDA
VCC
LDR 3.0 V
CLKIN
XTAL1
16 MHz Osc
OSC
XTAL2
GIPG1303141331LM
The STPM3x also has an enable pin (EN) which works as follows:
•
EN is high: when the power is on and EN pin raises, the device is enabled and starts
after POR procedure as above described.
•
EN is low: when the power is on and EN pin has a transition high to low, the device is
disabled. It stops and the internal digital memory is deleted so a new initialization is
needed when EN goes back to high.
After POR, to ensure a correct initialization, it is recommended to perform a reset of DSP
and communication peripherals through three SYN pulses (see Section 8.6.1) and a single
SCS pulse, as shown in the figure below. SCS pulse can be performed before or after SYN
pulses, but minimum startup time before reset (as indicated in Table 5) has to be respected.
Figure 29. Global startup reset
6&6
WBUSZ
6<1
WBVWDUWXS
9&&
*,3*/0
DocID026142 Rev 3
37/121
121
Theory of operation
8.3
STPM32, STPM33, STPM34
Functional description of the digital part
Each voltage and current channel has an independent digital signal processing chain, which
is composed of:
–
Digital front end (DFE)
–
Phase compensation
–
Decimation
–
Filters
–
Calibration
The outcoming signals are fed to a common hardwired DSP, which processes the metrology
data.
Figure 30. DSP block functional description
1
1
SCLK
SCLK
Phase
compensation
1
24
SCLK
Decimation
DFE
1
1
SCLK
SCLK
Phase
compensation
Calibration
DCLK
1
SCLK
24
DCLK
DSP
Filters
24
Calibration
DCLK
24
DCLK
GIPG1403141159LM
8.3.1
Digital front end (SDSx bits)
This block synchronizes and checks the sigma-delta bitstreams of voltage and current
signals.
Each channel sigma-delta stream has an SDSx status bit associated, which is cleared if the
stream is correct, while it is set if the bitstream is stuck to 0 or 1 (this is the case of an input
waveform saturating the dynamic input of the sigma-delta modulator).
To set SDSx bit, sigma-delta (Ʃ∆) stream should be stuck to 0 or 1 for a time between:
tƩ∆stuck = 2/(MCLK/256)=128 μs … tƩ∆stuck = 3/(MCLK/256)=192 μs.
Outputs are stored on bit number: 20, 24 of DSP_SR1,2 and 13, 20 of DSP_EV1,2.
If SDSx=1, the instantaneous values of voltage current are set on positive or negative
maximum value, according to sigma-delta stream. In this case active powers and energies
are calculated with those values of signals.
If sigma-delta stream of voltage channel is stuck, the reactive energy is zero.
8.3.2
Decimation block
The decimation block operates a serial decimation of three sigma-delta serial bitstreams
coming from three modulators of voltage, primary and secondary current channels.
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
The decimation ratio, out of the filter cascade, is 512 so that outputs of this block are parallel
24-bit data at a rated frequency of 7.8125 kHz.
The decimation block has a magnitude response -3 dB band of 3.6 kHz and a 2.0 kHz flat
band.
8.3.3
Filter block
The block includes:
•
DC cancellation filter (BHPFVx, BHPFCx bits)
•
Rogowski coil Integrator (ROCx bit)
•
Fundamental harmonic component filter
Figure 31. Filter block diagram
CHVx [11:0] Vx Data [23:0] VxFund[23:0]
BHPFVx
Vx[23:0]
HPF
LPF
CHCx [11:0] CxData [23:0] Cx Fund[23:0]
BHPFCx
Cx [23:0]
HPF
Reactive
filter
ROCx
ROCOIL
INT
LPF
GIPG1403141207LM
8.3.4
DC cancellation filter
This block removes the DC component of signal from voltage and current signals.
It is a selectable block which can be bypassed in case of particular needs with BHPFVx and
BHPFCx bits in DSP_CR1 and DSP_CR2.
The filter has a passband at -3 dB of 8 Hz
BHPFVx = 0: voltage HPF is included for x channel
BHPFVx = 1: voltage HPF is bypassed for x channel
BHPFCx = 0: current HPF is included for x channel
BHPFCx = 1: current HPF is bypassed for x channel
Rogowski coil Integrator
ROCx bit in DSP_CR1 and DSP_CR2 selects the type of current sensors (CT, shunt or
Rogowski coil):
DocID026142 Rev 3
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121
Theory of operation
STPM32, STPM33, STPM34
ROCx = 0: channel x current sensor is CT or shunt
ROCx = 1: channel x current sensor is Rogowski coil
In case of ROCx = 1, integrator filter is included to integrate current signal coming from
Rogowski coil current sensor. Rogowski coil integrator is selectable independently for each
current channel.
8.3.5
Fundamental component filter
This low-pass filter on the voltage and current signals is used to calculate: zero-crossing,
period, phase-angles and fundamental active and reactive energy. Filtered voltage and
current components are available on DSP_REG6, DSP_REG7, DSP_REG8, DSP_REG9
named VxFund and CxFund.
8.3.6
Reactive filter
Reactive filter introduces a delay in current and voltage streams respectively; these signals
are used to calculate reactive power and energy.
Input streams for reactive filter are VxFund and CxFund signals.
8.4
Functional description of hardwired DSP
From the decimation and filtering block, signals are fed to hardwired DSP to compute the
following quantities for primary and secondary channels:
•
Active power and energy wideband 0 Hz(4 Hz)-3.6 kHz
•
Active power and energy fundamental 45-65 Hz
•
Reactive power and energy
•
Apparent power and energy from RMS data
•
Apparent power vectorial calculation
•
Signal measurement: RMS, period, zero-crossing, phase-delay, sag and swell, tamper
Each power signal is accumulated in the correspondent energy register every 7.8125 kHz.
Energy registers are up-down counters. The accumulation is signed so that the negative
energy is subtracted from the positive energy. When the measured power is positive, the
energy register increases its content from 0x00000000 up to the maximum value,
0xFFFFFFFF, then it rolls from 0xFFFFFFFF back to 0x00000000.
Vice versa, when the power is negative, the register decreases its content; from
0x00000000 rolls to 0xFFFFFFFF and continues decreasing till 0x00000000.
To monitor each energy register overflow and power sign, status bits are available on
DSP_SR1 and DSP_SR2.
When a selectable threshold is reached, a pulse is generated on LED pin.
This threshold is selectable through a set of configuration bit (LPWx[3:0] in DSP_CR1 and
DSP_CR2) as shown in Table 12. For each bit configuration, LED signal goes high when the
two selected bits commute to 10 and goes low when the two selected bits change to 11.
Maximum LED pulse width is anyway fixed to 81.92 ms (640 periods of 7812.5 Hz clock).
40/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Table 12. LPWx bits
LPWx
LED_PWM
0000
0,0625
0001
0,125
0010
0,25
0011
0,5
0100
1
0101
2
0110
4
0111
8
1000
16
1001
32
1010
64
1011
128
1100
256
1101
512
1110
1024
1111
2048
The signal chain for each power, energy calculations and related frequency conversion are
explained in the following section.
DocID026142 Rev 3
41/121
121
PLNA
2nd
order ΣΔ
42/121
DocID026142 Rev 3
INx
modulator
IIPx
VIPx
VINx
Phase
Phase
Compens.
bsC
Compens.
bsV
HPF
Decimation
HPF
ROCOIL
INT
LPF
Vx Data [23:0]
CHVx[11:0]
CxData [23:0]
CHCx [11:0]
BHPFCx ROCx
Cx[23:0]
Decimation
Vx[23:0]
BHPFVx
LPF
Filter
Reac.
Cx Fund[23:0]
Vx Fund[23:0]
RMS
Σ
APMx
Σ
2
X
X2
LPF
R LED
A LED
Σ
CxRMS Data [16:0]
Offset
VxRMS Data [14:0]
LPF
LPF
RMS
Offset
Offset
Offset
√¯
F LED
AEMx
Σ
S LED
Theory of operation
STPM32, STPM33, STPM34
Figure 32. DSP block diagram
modulator
2nd
order ΣΔ
GIPG1703140842_1LM
STPM32, STPM33, STPM34
8.4.1
Theory of operation
Active power and energy calculation
The signal chain for the active power, energy calculations and related frequency conversion
are shown in Figure 33. The instantaneous power signal p(t) is generated by multiplying the
current and voltage signals. This value can be compensated by the active power offset
calibration block (OFAx[8:0] in DSP_CR9 and DSP_CR11 registers). DC component of the
instantaneous power signal (average power) is then extracted by LPF (low-pass filter) to
obtain the active power information.
Figure 33. Active power and energy calculation block diagram
CHVx [11:0]
BHPFVx
Vx[23:0]
bsV
VIPx
VINx
ADC
Vx Data [23:0]
OFAx[9:0]
HPF
Phase
Compensation
PHx Active Power[28:0]
CHCx[11:0]
BHPFCx
IIPx
I Nx
ADC
LPF
LED
PHx Active Energy[31:0
HPF
Phase
Σ
PHxMomentary Active Power[28:0]
Cx[23:0]
bsC
PLNA
ROCx
Offset
ROCOIL
INT
CxData [23:0]
Compensation
GIPG1703140852LM
The active power is calculated simultaneously and independently for primary and secondary
current channels.
Results of the calculated quantities are stored in the registers as follows:
EP1 = primary current channel active energy PH1 ACTIVE Energy[31:0]
P1 = primary current channel active power PH1 Active Power[28:0]
p1(t) = primary current channel instantaneous active power PH1 Momentary Active
Power[28:0]
EP2 = secondary current channel active energy PH2 Active Energy[31:0]
P2 = secondary current channel active power PH2 Active Power[28:0]
p2(t) = secondary current channel instantaneous active power PH2 Momentary Active
Power[28:0]
Active power measurements have a bandwidth of 3.6 kHz and include the effects of any
harmonic within that range.
8.4.2
Fundamental active power and energy calculation
The signal chain for the fundamental active power, energy calculations and related
frequency conversion are shown in Figure 34. The signal flow is the same as the active
energy wideband, but voltage and current waveforms are filtered to remove all harmonic
components but the first (45-65 Hz). Power value can be compensated by the active power
offset calibration block (OFAFx[8:0] in DSP_CR9 and DSP_CR11).
DocID026142 Rev 3
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121
Theory of operation
STPM32, STPM33, STPM34
Figure 34. Fundamental active power and energy calculation block diagram
CHVx [11:0]
BHPFVx
bsV
VIPx
VINx
ADC
Vx[23:0]
Phase
Vx Data [23:0]
LPF VxFund[23:0]
OFAFx[9:0]
HPF
Compensation
PHx Fundamental Power[28:0]
BHPFCx
IIPx
IINx
bsC
PLNA
ADC
Cx [23:0]
Phase
Offset
CHCx[11:0]
ROCx
CxData [23:0]
HPF
ROCOIL
INT
LPF
LPF
Σ
LED
PHx Momentary
PHxFundamental Energy[31:0 ]
Fundamental Power[28:0]
Cx Fund[23:0]
Compensation
GIPG1703140903LM
Results of the calculated quantities are stored in the registers as follows:
EF1 = primary current channel active fundamental energy PH1 Fundamental Energy[31:0]
F1 = primary current channel active fundamental Power PH1 Fundamental Power[28:0]
f1(t) = primary current channel instantaneous active fundamental power PH1 Momentary
Fundamental Power[28:0]
EF2 = secondary current channel active fundamental energy PH2 Fundamental
Energy[31:0]
F2 = secondary current channel active fundamental power PH2 Fundamental Power[28:0]
f2(t) = secondary current channel instantaneous active fundamental power PH2 Momentary
Fundamental Power[28:0]
The fundamental active power measurements have a bandwidth of 80 Hz.
8.4.3
Reactive power and energy calculation
The signal chain for the reactive power, energy calculations and related frequency
conversion are shown in Figure 35. The instantaneous reactive power signal is generated
by multiplying the filtered signals of current and voltage. This value can be compensated by
the reactive power offset calibration block (OFRx[8:0] in DSP_CR10 and DSP_CR12). The
DC component of the instantaneous power signal is extracted from LPF to obtain the
reactive power information.
44/121
DocID026142 Rev 3
IINx
IIPx
VINx
VIPx
PLNA
ADC
ADC
bsC
bsV
Phase
Compensat.
Phase
Compensat.
Cx[23:0]
Vx[23:0]
HPF
BHPFCx
HPF
BHPFVx
ROCOIL
INT
ROCx
Cx Data [23:0]
CHCx [11:0]
Vx Data [23:0]
CHVx [11:0]
LPF
LPF
CxFund[23:0]
Vx Fund[23:0]
Reactive
Filter
LPF
LED
PHx ReactiveEnergy[31:0]
Σ
PHx Reactive Power[28:0]
PHx Momentary Reactive Power[28:0]
Offset
OFRx[9:0]
STPM32, STPM33, STPM34
Theory of operation
Figure 35. Reactive power and energy calculation block diagram
DocID026142 Rev 3
GIPG2603141329LM
45/121
121
Theory of operation
STPM32, STPM33, STPM34
Results of the calculated quantities are stored in the registers as follows:
EQ1 = primary current channel reactive energy PH1 Reactive Energy[31:0]
Q1 = primary current channel reactive power PH1 Reactive Power[28:0]
q1(t) = primary current channel instantaneous reactive power PH1 Momentary Reactive
Power[28:0]
EQ2 = secondary current channel reactive energy PH2 Reactive Energy[31:0]
Q2 = secondary current channel reactive power PH2 Reactive Power[28:0]
q2(t) = secondary current channel instantaneous active power PH2 Momentary Reactive
Power[28:0].
8.4.4
Apparent power and energy calculation
The signal chain for the apparent power, energy calculations and related frequency
conversion are shown in Figure 36. The apparent power signal S is generated in two ways:
•
Vectorial methodology uses the scalar product of active and reactive power. The active
power is selectable through the active power mode bit (APMx in DSP_CR1 and
DSP_CR2) between wideband or fundamental.
Equation 2
S vec =
•
2
P +Q
2
RMS methodology uses the product of RMS data of voltage and current. This value can
be compensated by the apparent power offset calibration block (OFSx[8:0] in
DSP_CR10 and DSP_CR12).
Equation 3
SRMS = V RMS ⋅ I RMS
The apparent energy is calculated from vectorial or from RMS apparent power according to
AEMx configuration bit in DSP_CR1 and DSP_CR2.
Figure 36. Apparent power and energy calculation block diagram
APMx
PHxFundamental Power[28:0]
PHx Active Power[28:0]
0
X2
PHxApparent VectorialPower[28:0]
1
√¯
PHxReactive Power[28:0]
AEMx
X2
1
OFSx [9:0]
Σ
0
S LED
VxRMS Data [14:0]
PHxApparent Energy[31:0]
Offset
PHx Apparent RMS Power[28:0]
Cx RMS Data [16:0]
GIPG2803141114LM
Results of the calculated quantities are stored in the registers as:
46/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
ES1 = primary current channel apparent energy PH1 Apparent Energy[31:0]
S1RMS = primary current channel apparent RMS power PH1 Apparent RMS Power[28:0]
S1vec = primary current channel apparent vectorial power PH1 Apparent Vectorial
Power[28:0]
ES2 = secondary current channel apparent energy PH2 Apparent Energy[31:0]
S2RMS = primary current channel apparent RMS power PH2 Apparent RMS Power[28:0]
S1vec = primary current channel apparent vectorial power PH2 Apparent Vectorial
Power[28:0]
8.4.5
Sign of power
Power measurements are signed calculations. Negative power indicates that energy has
been injected into the grid. DSP_SR1, DSP_SR2 status registers and DSP_EV1, DSP_EV2
registers include sign indication bits for each calculated power.
If the sign of power is negative, the sign bit is set.
SIGN = 0: positive power
SIGN = 1: negative power
In the calculation of the sign, a delay equal to half line period is included.
If the period of signal is T = 20 ms (f = 50 Hz), the applied delay is 10 ms.
Figure 37. Power sign status bit delay
Power
t < T/2
t = T/2
t = T/2
Sign
GIPG2803141118LM
8.4.6
Calculation of power and energy
In the following section, constant parameters, coming from the device architecture, are
used:
Table 13. STPM3x internal parameters
Parameter
Value
Voltage reference
VREF =1.18 [V]
Decimation clock
DCLK=7812.5 [Hz]
Integrator gain
(for Rogowski coil only)
kint = 1
if ROC bit = 0 in DSP_CR1,2
kint = 0.8155773
if ROC bit = 1 in DSP_CR1,2
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47/121
121
Theory of operation
STPM32, STPM33, STPM34
Basic calculations are listed in Table 14:
Table 14. STPM3x basic calculations
Parameter
Voltage
Current shunt
Current CT
Current Rogowski coil
Gain
AV = 2
AI = 16
AI = 2
AI = 16
Calibrators(1)
calV = 0.875
Sensitivity
Voltage at channel
inputs
R2
--------------------[V/A]
R1 + R2
Input active power
kS = RShunt [Ω]
Rb
k S = ------- [V/A]
N
kint = 1
AV
V ΔΣ = V inV ⋅ ---------V ref
kS = kRoCoil [V/A]
V inC = k S ⋅ I[V]
R2
V inV = -------------------- ⋅ V[V]
R1 + R2
Integrator gain (for
Rogowski coil sensor
only)
Σ∆ bitstream(2)
calI = 0.875
kint = 0.8155773
AI
VΔΣ = V inC ⋅ ---------V ref
AI
V ΔΣ = VinC ⋅ -----------------------V ref ⋅ K int
P in = V ⋅ I ⋅ cos ϕ = V ⋅ I[W]
Active power
LED frequency at rated
power (3)
Constant pulse
R2
A V ⋅ AI ⋅ cal V ⋅ cal I
DClk
pulses
1
C P = --- ⋅ -------------------- ⋅ k int ⋅ k S ⋅ ----------------------------------------------- ⋅ ------------------------------ ------------------2
LED_PWM
Ws
2 R1 + R2
V
ref
Pulse value
Power register
normalized
Energy register
normalized
48/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Table 14. STPM3x basic calculations (continued)
Parameter
Voltage
Current shunt
Current CT
Current Rogowski coil
2
P pulse
Vref ⋅ ( 1 + R 1 ⁄ R2 )
W
LSB P = ---------------- -----------⋅ DClk = -----------------------------------------------------------------------------------29
28 LSB
k int ⋅ A V ⋅ A I ⋅ k S ⋅ cal V ⋅ cal I ⋅ 2
2
Power LSB value
2
Energy LSB value
P pulse
V ref ⋅ ( 1 + R1 ⁄ R 2 )
Wh
LSBE = ---------------= -----------------------------------------------------------------------------------------------------------------------------------18
17 LSB
3600 ⋅ DClk ⋅ k int ⋅ A V ⋅ A I ⋅ k S ⋅ cal V ⋅ cal I ⋅ 2
2
1. CHVx and CHCx calibrator bits introduce in the signal processing a correction factor of ±12,5% (with an attenuation from
0,75 to 1). In order to have the maximum available up/down correction range, by default calibrator values are in the middle
of their range (0x800) corresponding to an attenuation factor calV = calI = 0,875.
2. Ʃ∆ bitstream should be kept lower than 0.5 (50%) to minimize modulator distortions.
3. LED_PWM is the LED frequency divider that can be set through LPWx bits in DSP_CR1 and DSP_CR2 control registers
for primary and secondary current channels respectively. Default value is 1. Please refer to Table 36.
For each power register, a configurable offset value (default = 0) can be added to the
instantaneous power p(n) through OFA[9:0], OFAF[9:0], OFR[9:0], OFAS[9:0] bits in this
way:
Equation 4
′
p ( n ) = p ( n ) + ( –1 )
8.4.7
OFx [ 9 ]
⋅ OFx [ 8:0 ] × 2
2
RMS calculation
RMS block calculates RMS currents and voltages on each phase every second, according
to the following formulas:
Equation 5
V RMS =
1 t0 + T
--- 
v ( t ) dt
T t0
I RMS =
1 t0 + T
--- 
i ( t ) dt
T t0
Equation 6
with T = 200 ms.
RMS block architecture is shown in Figure 38:
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121
Theory of operation
STPM32, STPM33, STPM34
Figure 38. RMS block
/
-
LPF
1/2
LPF
GIPG2803141121LM
If the cut-off frequency of an LP filter is set much below the input signal spectrum, it can be
considered as an average operator. In this case and according to the figure, the first LP filter
averages its input signal which is produced by division and multiplication:
Equation 7
2
X
R =  ------
 R
By assumption, the feedback signal R is DC type and therefore, it can be extracted from the
average operation and the above equation can be rearranged into:
Equation 8
2
R = (X )
By a square-root operation on both sides of previous equation we get:
Equation 9
R =
2
(X )
which is RMS value exact definition.
With an AC input signal:
Equation 10
50/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
The LP filter cuts the 2nd harmonic component of input signal multiplying it by a dumping
factor:
Equation 11
Equation 12
R result is a DC signal plus the 2nd harmonic ripple with the amplitude of α/2.
For dumping factor | α |<<1:
Equation 13
A
R ∼ ------2
RMS data are available in DSP_REG14 and DSP_REG15 registers.
Raw data are also available for post-processing by MCU in registers from DSP_REG2 to
DSP_REG9.
By taking into account the internal parameters in Table 13 and the analog front end
components in Table 14, LSB values of voltage and current registers are the following:
Table 15. STPM3x current voltage LSB values
Parameter
Value
Voltage RMS LSB value
V ref ⋅ ( 1 + R1 ⁄ R 2 )
LSB VRMS = ----------------------------------------------[V]
15
cal V ⋅ AV ⋅ 2
Current RMS LSB value
V ref
LSB IRMS = --------------------------------------------------------[A]
17
cal I ⋅ AI ⋅ 2 ⋅ k S ⋅ k int
Instantaneous voltage normalized
( – 1 ) ⋅ 2 ⋅ v ( n ) [ 23 ] + v ( n ) [ 22:0 ]
v ( n ) ⁄ Vnorm = --------------------------------------------------------------------------------------23
2
23
Instantaneous current normalized
23
( – 1 ) ⋅ 2 ⋅ i ( n ) [ 23 ] + i ( n ) [ 22:0 ]
i ( n ) ⁄ Inorm = ----------------------------------------------------------------------------------23
2
DocID026142 Rev 3
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121
Theory of operation
STPM32, STPM33, STPM34
Table 15. STPM3x current voltage LSB values (continued)
Parameter
Value
Instantaneous voltage LSB value
Vref ⋅ ( 1 + R 1 ⁄ R 2 )
[V]
LSB VMOM = ----------------------------------------------23
cal V ⋅ A V ⋅ 2
V ref
LSBIMOM = -------------------------------------------------------- [A]
23
cal I ⋅ A I ⋅ 2 ⋅ k S ⋅ k int
Instantaneous current LSB value
8.4.8
Zero-crossing signal
Zero-crossing signals of voltage and current come from fundamental values of voltage and
current and output from LPF filter. Resolution of the zero-crossing signal is 8 μs given by
FCLK clock = 125 kHz.
Figure 39. Zero-crossing generation
FClk 125 kHz
ZRC_V
VxFund[23:0]
ZCR detector
ZRC_I
CxFund[23:0]
GIPG2803141125LM
ZRC signal is delayed by an instantaneous voltage current signal: 5.1 ms (typical), as
shown in Figure 40:
Figure 40. Zero-crossing signal
Signal
ZRC
GIPG2803141129LM
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DocID026142 Rev 3
STPM32, STPM33, STPM34
8.4.9
Theory of operation
Phase meter
Phase meter detects:
•
The period of the voltage line
•
The phase-angle delay between voltage and current
Figure 41. Phase meter
FClk 125kHz
PHx PERIOD[11:0]
ZRC_V
Period
PER_ERR
and
Phase-angle
detector
Cx_PHA [11:0]
ZRC_I
GIPG2803141133LM
Period measurement
Starting from ZRC signals, line period and voltage/current phase shift are calculated.
Period information for the two phases is located in DSP_REG1 register.
The measurement of the period is from ZRC signal of voltage channel. The period is
calculated like an average of last eight measured periods.
The initial values of period are set on 0x9C4 (2500). LSB of period is 8 μs given by FCLK
clock = 125 kHz. Limits to consider the correct period are between 0x600 (1536) and 0x800
(3840) corresponding to a frequency range between 32.55 and 81.38 Hz.
If the voltage signal frequency is out of this range, PER_ERR status bit is set in
DSP_SR1/2.
PER_ERR = 0: period in the range
PER_ERR = 1: period out of range
PER_ERR bit can be also set when a sag event is detected.
When PER_ERR bit is set, PHx_PERIOD[11:0] is not updated and keeps the previous
correct value.
Setting the default line frequency through REF_FREQ bit in register DSP_CR3 speeds up
the period calculation algorithm convergence.
Phase-angle measurement
From the period information, the device calculates phase-delay between voltage and
current for the fundamental harmonic.
Cx_PHA[11:0] data for primary and secondary channel are located in DSP_REG17 and
DSP_REG19 respectively.
Phase-angle φ in degrees can be calculated from the register value as follows:
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Theory of operation
STPM32, STPM33, STPM34
Equation 14
Resolution at 50 Hz is:
Equation 15
When PER_ERR bit is set, Cx_PHA[11:0] is not updated and keeps the previous correct
value.
8.4.10
Sag and swell detection
The device can detect and monitor the undervoltage (also called voltage dip or sag) and the
overvoltage or overcurrent events (swell).
A 4-bit event register stores every time that the sag or swell condition is verified. The event
history is stored in DSP_EV1 and DSP_EV2 registers as SAGx_EV[3:0], SWVx_EV[3:0]
and SWCx_EV[3:0]. From the event register, interrupts can be generated, and the event
duration is stored in time registers: from DSP_REG16 to DSP_REG19.
To correctly detect the event, thresholds have to be set from DSP_CR5 to DSP_CR8 as
explained below.
To clear event history and time registers, once the event has been detected, ClearSS bit in
DSP_CR1, DSP_CR2 has to be set. This bit is reset automatically.
To avoid a race condition on digital counters, a time threshold CLRSS_TO[3:0] (ClearSS
time-out) can be set to delay the reset of ClearSS bit. LSB of this timeout is 8 μs.
Status bits are also available in case of sag and swell events in DSP_SR1 and DSP_SR2,
they can give the information about the sag/swell event start or end and generate an
interrupt if masked in DSP_IRQ1 and DSP_IRQ2 registers.
54/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Figure 42. Sag and swell detection blocks
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Voltage sag detection
To detect a voltage sag, the fundamental component of voltage is compared to the 10-bit
threshold SAG_THRx[9:0] in DSP_CR5 and DSP_CR7 for primary and secondary channel
respectively.
An internal time counter is incremented until momentary voltage value is below the
threshold. Sag event is recorded when the timer counter reaches a programmable value set
by SAG_TIME_THR[13:0] bits in DSP_CR3. This time threshold is unique for both
channels.
When a sag event is detected, LSB of SAGx_EV[3:0] event register and SAG_Start bit are
set in the interrupt status register and an interrupt is generated.
If sag event ceases, SAGx_EV register is left shifted and zero is added as LSB, besides,
SAG_end bit in the interrupt status register is set as well.
The duration of the event is stored in SAGx_TIME[14:0] in DSP_REG16 and DSP_REG18
for primary and secondary voltage channel respectively.
If the overflow of SAG_TIME register occurs, SAGx_EV register is left shifted and its LSB is
set, as shown in figure below.
LSB of time registers is 8 μs.
To disable sag detection, the SAG_THRx register must be set to zero.
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Theory of operation
STPM32, STPM33, STPM34
Figure 43. Sag detection process
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Voltage/current swell detection
To detect a voltage or a current swell, the fundamental component of signal is compared to
the 10-bit threshold SWV_THRx[9:0] and SWC_THRx[9:0] in DSP_CR5, DSP_CR6,
DSP_CR7, and DSP_CR8.
When the signal overcomes the threshold, a swell event is detected and LSB of
SWVx_EV[3:0] or SWCx_EV[3:0] event register is set. At the same time, SWELL_Start bit is
set in the interrupt status register and an interrupt can be generated.
If the swell event ceases, SWV_EV or SWC_EV register is shifted and its LSB is set to zero,
also SWELL_End bit in the interrupt status register is set.
The duration of the event is stored in SWV_TIME[14:0] or SWC_TIME[14:0] in registers
from DSP_REG16 to DSP_REG19 for primary and secondary voltage and current channel
respectively.
If the overflow of SWV_TIME or SWC_TIME register occurs, the related SWVx_EV and
SWCx_EV register is left shifted and its LSB is set, as shown in figure below.
LSB of time registers is 8 μs.
To disable swell detection, the registers SWV_THRx and SWC_THRx must have maximum
value 0x3FF.
56/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Figure 44. Swell detection process
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Sag and swell threshold calculation
Thresholds for sag voltage detection are calculated below, according to the following input
parameters:
VL: line voltage nominal RMS value
VSAG: target RMS value of sag voltage
R1, R2: voltage divider resistors
AV = 2, voltage channel gain
DSAG = 210, length of sag threshold register
calV = 0.875, calibrator mid value
Table 16. Voltage sag
Parameter
Value
SAG peak voltage
Input signal
Percentage of FS input
V SAG
R2
V in_SAG_peak ( FS ) = -------------- ⋅ AV ⋅ 2 ⋅ cal V ⋅ -------------------Vref
R1 + R2
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Theory of operation
STPM32, STPM33, STPM34
Table 16. Voltage sag (continued)
Parameter
Value
Register value
V SAG
R2
SAG = -------------- ⋅ AV ⋅ 2 ⋅ cal V ⋅ -------------------- ⋅ D SAG [ HEX ]
Vref
R1 + R2
( R 1 + R 2 ) ⋅ V ref
LSBSAG = ------------------------------------------------------------------ [ V ]
A V ⋅ 2 ⋅ R 2 ⋅ cal V ⋅ D SAG
Register LSB RMS value
To calculate the filtering time for the sag event, we consider the time in which the nominal
instantaneous voltage is below the sag threshold, that is:
Equation 16
V SAG 1000
time = 2 ⋅ arc sin  -------------- ⋅ ------------- [ ms ]
 V L  2πf L
To correctly distinguish between normal sinusoidal voltage and sag event, the filtering time
should be added to this component, for example half line period (10 ms at 50 Hz). Since
LSB of SAG_TIME_THRx register is 8 μs (FCLK = 125 kHz), the value to set is:
Equation 17
In the same way:
VSWELL: target RMS value of swell voltage
AV: voltage sensor gain
DSWELL = 210, length of swell threshold register
calV = 0.875, calibrator mid value
Following the above calculation we obtain the hexadecimal value of voltage swell threshold:
Table 17. Voltage swell
Parameter
Value
Register value
V SWELL
R2
SWELL V = --------------------- ⋅ A V ⋅ 2 ⋅ -------------------- ⋅ cal V ⋅ D SWELL [ HEX ]
V ref
R1 + R2
Register LSB RMS value
58/121
V ref ⋅ ( R 1 + R 2 )
LSB SWELL = ------------------------------------------------------------------------- [ V ]
A V ⋅ 2 ⋅ R 2 ⋅ cal V ⋅ D SWELL
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
For the current swell, an analogue procedure can be followed:
ISWELL: target RMS value of swell current
kS: current sensor sensitivity [V/A]
AI: current sensor gain
calI = 0.875, calibrator mid value
The swell threshold is:
Table 18. Current swell
8.4.11
Parameter
Value
Register value
ISWELL
SWELL C = ------------------- ⋅ AI ⋅ 2 ⋅ k S ⋅ cal I ⋅ D SWELL [ HEX ]
V ref
Register LSB RMS value
V ref
LSB SWELL = --------------------------------------------------------------------- [ A ]
A I ⋅ 2 ⋅ k S ⋅ cal I ⋅ D SWELL
Tamper detection
The device includes a tamper detection module (the STPM34 and STPM33 only).
To enable this feature, TMP_EN bit and TMP_TOL[1:0] tamper tolerance have to be set in
DSP_CR3. Tamper detection feature is disabled by default. It is possible to choose among
four different tolerances according to Table 19:
Table 19. Tamper tolerance setting
TMP_TOL[1:0]
Tamper tolerance
0x00
TOL = 12.5%
0x01
TOL = 8.33%
0x10
TOL = 6.25%
0x11
TOL = 3.125%
Tamper module monitors active energy registers of the two channels. Tamper condition is
detected when the absolute value of the difference between the two active energy values is
greater than the chosen percentage of the averaged value. This occurs when the following
equation is satisfied:
Equation 18
|EnergyCH1 - EnergyCH2| > TOL * |EnergyCH1 + EnergyCH2|
where TOL is selected according to Table 19.
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Theory of operation
STPM32, STPM33, STPM34
Detection threshold is much higher than the accuracy difference of the current channels,
which should be less than 0.2%, but, some headroom should be left for possible transition
effect, due to accidental synchronism of load current change at the rate of energy sampling.
Tamper circuit works if energies associated with the two current channels are both positive
or negative, if two energies have different sign, a warning flag “TAMPER OR WRONG” in
DSP_SR1 or DSP_SR2 is set.
The channel with higher energy is signaled by PHx TAMPER status bit in DSP_SR1 or
DSP_SR2.
When internal signals are not good enough to perform the calculations, for example line
period is out or range or sigma-delta signals from analog section are stuck at high or low
logic level, the tamper module is disabled and its state is set to normal.
8.4.12
AH accumulation
In this particular tamper, the neutral wire is disconnected from the meter and the STPM3x
does not sense the voltage anymore, while it keeps sensing the current information. In these
conditions, AH accumulator can be used by the microcontroller to regularly calculate the
billing based on a nominal voltage value due to the following equation:
Equation 19
Energy = AH_ACC[31:0]·LSBAH_ACC·VNOM[Wh]
If voltage is too low (sag event detected) or period is wrong (PER_ERR = 1) and RMS value
of current is high enough, RMS current is accumulated in the register AH_ACC[31:0]. Value
in PHx AH_ACC[31:0] register is increased with a DCLK frequency.
Figure 45. AH accumulation block
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The accumulation of current values is controlled by AH status bit. AH bit is set when
PER_ERR = 1 and real values of current overcome an upper threshold set in AH_UPx[11:0]
in DSP_CR9 and DSP_CR11. This bit is cleared when RMS current drops below
AH_DOWNx[11:0] threshold in DSP_CR10 and DSP_CR12.
To stabilize the current accumulation, SAG event should be monitored by setting some
thresholds in the related register.
60/121
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Figure 46. AH accumulation thresholds
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Table 20. AH accumulator LSB
8.4.13
Parameter
Value
AH accumulator register LSB
LSB IRMS ⋅ 2
LSB AH_ACC = -------------------------------- [ Ah ]
3600 ⋅ DClk
AH threshold register LSB
LSB AH_UP = LSBAH_DOWN = LSBIRMS ⋅ 2 [ A ]
5
Status bits, event bits and interrupt masks
The device detects and monitors events like sag and swell, tamper, energy register
overflow, power sign and errors, generating an interrupt signal on INTx pins when the
masked event is triggered.
When the event is triggered, the correspondent bit is set in two registers:
•
Live event register DSP_EV1,2
•
Status (also called interrupt) register DSP_SR1,2
To output the interrupt on INTx pins, the correspondent bit should be set in the interrupt
control mask register DSP_IRQ1,2
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Theory of operation
STPM32, STPM33, STPM34
Live event register
In live event registers (DSP_EV1 and DSP_EV2), events are set and cleared by DSP at the
sampling rate DCLK = 7,8125 kHz.
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Table 21. Live events
Bit
Internal signal
Description
Sign total active power
0
1
Sign total reactive power
PH1+PH2 events(1)
2
Overflow total active energy
3
Overflow total reactive energy
4
Sign active power
5
Sign active fundamental power
6
Sign reactive power
7
Sign apparent power
PHx events
8
Overflow active energy
9
Overflow active fundamental energy
10
Overflow reactive energy
11
Overflow apparent power
12
Current zero-crossing
13
Current sigma-delta bitstream stuck
14
Current AH accumulation
15
Cx events
16
Current swell event history
17
18
19
Voltage zero-crossing
20
Voltage sigma-delta bitstream stuck
21
Voltage period error (out of range)
22
23
Voltage swell event history
24
Vx events
25
26
27
Voltage sag event history
28
29
30
Reserved
31
Reserved
1. Valid for the STPM33 and STPM34 only.
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Theory of operation
STPM32, STPM33, STPM34
Status interrupt register
When an event is detected, DSP sets the status register (DSP_SR1 and DSP_SR2) bits
that remain latched, even if the event ceases, until they are cleared to zero by a write
operation.
Table 22. Status register
Bit
Internal signal
Sign total active power
0
1
Description
PH1+PH2 status(1)
Sign total reactive power
2
Overflow total active energy
3
Overflow total reactive energy
4
Sign secondary channel active power
5
Sign secondary active fundamental power
6
Sign secondary reactive power
7
PH2 IRQ status(1)
Sign secondary apparent power
8
Overflow secondary channel active energy
9
Overflow secondary channel active fundamental energy
10
Overflow secondary channel reactive energy
11
Overflow secondary channel apparent energy
12
Sign primary channel active power
13
Sign primary channel active fundamental power
14
Sign primary channel reactive power
15
Sign primary channel apparent power
PH1 IRQ status
16
Overflow primary channel active energy
17
Overflow primary channel active fundamental energy
18
Overflow primary channel reactive energy
19
Overflow primary channel apparent energy
20
Current sigma-delta bitstream stuck
21
AH1 - accumulation of current
Cx IRQ status
22
Current swell detected
23
Current swell end
24
Voltage sigma-delta bitstream stuck
25
Voltage period error
26
Voltage sag detected
Vx IRQ status
64/121
27
Voltage sag end
28
Voltage swell detected
29
Voltage swell end
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Table 22. Status register (continued)
Bit
30
Internal signal
Tamper status(1)
31
Description
Tamper
Tamper or wrong connection
1. Valid for the STPM33 and STPM34 only.
Interrupt control mask register
Each bit in the status register has a correspondent bit in DSP_IRQ1, DSP_IRQ2 interrupt
mask registers. For each bit set, the relative event detection is output on INT1, INT2 pins
respectively. In the STPM32, DSP_IRQ1 is mapped on INT1 pin only.
Status bits can be monitored by an external microcontroller application, in fact when INTx
pin triggers, the application reads the relative status register content and clears it.
Note:
Power sign status bits generate level interrupts.
8.5
Functional description of communication peripheral
The STPM3x can be interfaced to a control unit through a programmable communication
peripheral which can be:
•
4-pin SPI
•
2-pin UART
The serial communication peripherals share same pins so that they cannot be used at the
same time.
Interface selection is implemented through an internal detection system that, at the device
startup, detects which of the two communication interfaces has to be used. This feature
allows communication to be quickly established with minimal initialization.
Auto-detection works at startup, (power-up or EN pin transition from low to high) by
monitoring SCS pin status and automatically selecting the communication interface that
matches the configuration:
•
If SCS pin is held low the communication method is SPI
•
If SCS pin is held high the communication interface is UART
After the selected communication interface is established, the interface is locked to prevent
the communication method from changes, and SCS pin is used as chip-select for the
device.
Pins used by the serial communication peripheral are listed in Table 23:
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Theory of operation
STPM32, STPM33, STPM34
Table 23. Communication pin description
Name
8.6
Function
SPI connection
UART connection
SYN
Synchronization
GPIO (optional), VCC at
startup
GPIO (optional), VCC at startup
SCS
Chip-select
-Start-up interface selection
at GND
-Chip-select at GND
-Start-up interface selection at
VCC
-Chip-select at VCC
SCL
Clock
SPI CLK
Not used
MOSI/RXD
Data in
SPI MOSI
UART RX
MISO/TXD
Data out
SPI MISO
UART TX
Communication protocol
A single communication session consists of 4+1 (optional CRC) bytes full-duplex data
sequence organized as follows:
Table 24. Communication session structures
Byte
Master-side transmitted data
Slave-side transmitted data
1
ADDRESS for 32-bit register to be read
2
ADDRESS for 16-bit register to be written Previously requested data byte 2 out of 4
3
DATA for 16-bit register to be written, LSB Previously requested data byte 3 out of 4
4
DATA for 16-bit register to be written, MSB Previously requested data byte MSB
5 (optional)
Master CRC verification packet
Previously requested data byte LSB
Slave CRC verification packet
The above information is exchanged between master and slave in the same communication
session, or transaction. SPI master can issue a read-request and a write-request (optional).
The master initiates the communication sending the STPM3x a frame see Table 24 (read
address - write address - LS data byte - MS data byte - optional CRC).
Two command codes are provided:
•
Dummy read address 0xFF increments by one the internal read pointer
•
Dummy write address 0xFF specifies that no writing is requested (the two following
incoming data frames are ignored)
Upon the reception of a frame, the STPM3x replies to master data sending the 32-bit
register addressed during the previous communication session; during the first session the
slave sends, by default, the 32-bit data stored into the first (row 0) memory register. Data are
organized in 8-bit packets so that the least significant byte is sent first and the most
significant byte is sent last.
A final 8-bit CRC packet is sent to master to verify no data corruption has occurred during
the transmission from slave to master. The CRC feature, enabled by default, can be
controlled by a configuration bit into US_REG1 memory row (read address 0x24, write
address 0x24).
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
If CRC bit in US_REG1 is cleared, the communication consists of 4 bytes only.
Write-requests are executed immediately after the transaction has completed, while readrequests are fulfilled at the end of the next transaction only, because the sent read-address
has just set the internal register pointer to deliver data during the following transaction.
So, while one transaction is enough to write data into memory, at least two transactions are
needed to read selected data from memory.
Data bytes are swapped with respect to the order of the byte, since during transmission, the
3rd byte sent to MOSI line is the least-significant (LS) byte (bits [7:0]) and the 4th byte is the
most-significant (MS) byte of the data to be written (bits [15:8]).
On MISO line, the first data byte received is the least-significant (LS, bits [7:0]) and the last
is the most-significant (MS, bits [31:24]) of the record, as shown below.
Figure 47. Single communication time frame
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Data and configuration registers are organized into 32-bit rows in the internal memory, but
can only be accessed 16-bit at a time for writing operations.
The address space is 70 rows wide, so there are 70 32-bit addressable elements for reading
operations; since the first 21 configuration registers are writable, there are 42 (=21x2) 16-bit
addressable elements for writing operations.
Figure 48. Memory data organization
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Two different codes are used for the read address space and write address space, which
can be found in the register map.
8.6.1
Synchronization and remote reset functionality
Data into read-only registers are updated internally by DSP with frequency: 7,8125 kHz
(clock frequency measure). Latching is used to sample the updated results into transmission
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Theory of operation
STPM32, STPM33, STPM34
latches. The transmission latches are flip-flops holding the data in the communication
interface.
Data latching can be implemented in three ways:
•
Using SYN and SCS pin
•
Writing the channel latch bits before each reading (S/W Latchx in DSP_CR3)
•
Writing auto-latch bit (S/W Auto Latch in DSP_CR3) to automatically latch data
registers every clock measure period (128 μs)
The remote reset can be performed in two ways:
•
Using SYN and SCS pin
•
Writing the reset bit (S/W reset in DSP_CR3)
SYN pin: latching, reset and global reset
Latching of internal memory registers can be carried out by producing pulses of a given
width on SYN pin while SCS line is high as depicted in Figure 49.
If a single pulse on SYN is detected, latch occurs.
If two consecutive pulses are detected, a reset of measurement registers occurs and the
counters are reset, as well.
If three consecutive pulses are detected, a global reset occurs, the configuration is also
reset and the chip must be initialized again.
Note:
To ensure a correct initialization of DSP, it is recommended to perform a global reset
through three SYN pulses at startup and before setting configuration bits.
Figure 49. Latching and reset through SYN pulses
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Latch pulse width and other SPI timings are reported in Table 5.
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STPM32, STPM33, STPM34
Theory of operation
Figure 50. Latching through SYN pulses
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Software latch
Writing S/W Latchx configuration bits of DSP_CR3 register can latch data into transmission
latches. These two bits latch channel 1 and channel 2 data registers respectively; once set,
they latch data and are automatically reset. By setting S/W Auto Latch bit, latching is
performed automatically at the rate of sampling clock, so data latching, before each reading
request, is no longer necessary.
Software reset
Writing SW Reset configuration bit in DSP_CR3 brings the configuration registers to their
default values. Data registers are not reset. This bit is automatically cleared after this action.
8.6.2
SPI peripheral
The device implements a full-duplex communication protocol using MISO, MOSI ports for
data exchange, SCL for clock port, SCS port for data exchange activation and SYN for
internal register data latching and resetting, when no data activation is set (SCS in off-state).
Latching and resetting can also be performed by setting the related bits in DSP_CR3
register.
With refernce to the general SPI protocol, the peripheral is configured to work according to
the following settings: cpol=1, cpha=1.
SPI control register
US_REG1 register contains 16-bits with all the configuration parameters of t SPI and UART
interfaces of the STPM3x.Table 25 describes SPI related bits:
Table 25. SPI control register
Bit position in row
Name
Description
Default value
15
LSBfirst
Little(1) or big(0) - endian for bit
transmission in data-byte
0
14
CRCenable
Enable/disable CRC feature
1
CRCPolynomial
Polynomial used to validate transmitted
and received data
[7:0]
0x07
LSBfirst: endianness of data-byte transmission and reception
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Theory of operation
STPM32, STPM33, STPM34
CRCenable: enables the optional CRC feature
CRCPolynomial: default polynomial used is 0x07 (x8+x2+x+1)
SPI timings
Any single transaction timing follows the scheme in Figure 5.
For consecutive writing transactions, a minimum time interval of 4 μs has to be taken into
account in order to avoid overrun issues.
For latch and consecutive read transactions a minimum time interval of 4 μs has to be taken
into account in order to avoid overrun issues.
Examples
All frames in the following examples do not contain CRC byte, which has to be added just in
case the feature has not been disabled previously. After that CRC has been disabled, the
frame consists of four bytes only.
To write bits from 31 to 16 (most significant bits) in row 1 with data byte 0xABCD and read
row 2 in the following transaction, the first four bytes of the transmission (without CRC) are:
04_03_CD_AB
To receive data from register 04 the master should send the frame:
FF_FF_FF_FF
To write lower (least significant) 16-bits in row 3 with data #AABB and read back from the
same row:
06_06_BB_AA
And then
FF_FF_FF_FF
To receive
The sent frame changes according to LSBfirst setting:
Table 26. LSBfirst example
LSBfirst = 0
04_03_CD_AB
LSBfirst = 1
20_C0_B3_D5
MISO line is valid as well. In this case, there is a full-reverse data transmission when
LSBfirst=1, since data bit reception order changes as shown in the following table:
Table 27. LSBfirst and MISO line
70/121
Byte[0]
Byte[1]
Byte[2]
Byte[3]
LSBfirst = 0
[7:0]
[15:8]
[23:16]
[31:24]
LSBfirst = 1
[0:7]
[8:15]
[16:23]
[24:31]
DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
LSBfirst can be programmed using the transactions (other configuration bits involved in the
transaction are set to their default states):
Table 28. LSBfirst programming
LSBfirst = 1
24_24_07_CO
LSBfirst = 0
24_24_EO_02
The transaction to write LSBfirst=0 is byte-reversed, since the system has moved from the
LSBfirst=1 condition. The read address is set so to read in the following transaction the
content of US_REG1.
Following the frames to enable/disable CRC feature:
Table 29. CRCenable programming
CRCenable = 1
24_24_07_40
CRCenable = 0
24_24_07_00
To reset status bits, the following frame should be sent:
28_29_00_00
which resets all 16-bits (SPI and UART status registers). To clear SPI status bits only, SPImaster can send 1 s sequence to UART status bit register. Referring to the previous
example, this leads to the following transaction:
28_29_FF_00
Events are associated to interrupts so that, when the correspondent event mask bit in SPI
IRQ register is activated, INT line is sensitive to that event.
For example, to activate CRC error interrupt (bit 12, related to status bit 28), the mask
0x1000 has to be written to write address 0x28 by the following transaction:
28_28_00_10
8.6.3
UART peripheral
The STPM3x provides the UART interface, which allows a communication using two singledirection pins only; this reduces the cost of isolated communication, where required, since
two low cost opto-isolators are needed for this purpose.
Main features of this interface are:
•
Full-duplex, asynchronous communication
•
Low-level sequential data exchange protocol (1 start, 8 data, 1 stop)
•
NRZ standard format (mark/space)
•
Fractional baud rate generator system (to offer a wide range of baud rates)
•
Several error detection flags
•
Configurable frame length
•
Optional configurable CRC checksum
•
Optional noise immunity algorithm
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121
Theory of operation
STPM32, STPM33, STPM34
TX pin accesses this interface, which transmits data to the microcontroller, and RX pin,
which receives data from the microcontroller. A simple master/slave topology is
implemented on the UART interface where the STPM3x acts as the slave.
Transmission and reception are driven by a common baud rate generator; the clock for each
one is generated only when UART is enabled.
UART transmitting and receiving sections must have the same bit speed, frame length and
stop bits.
Chip selection in UART mode requires SCS bit is kept high.
Communication starts when the master sends slave a valid frame (the microcontroller). The
format of the frame is shown below.
Figure 51. UART frame
6WDUW
%LW
%LW
%LW
%LW
%LW
%LW
%LW
%LW
%LW
6WRS
%LW
1H[W
6WDUW
%LW
&ORFN
,GOH IUDPH
6WDUW
%LW
%UHDNIUDPH
([WUD
6WDUW
%LW
*,3*)65
As shown in Figure 51, each frame consists of 10 bits. Each bit is sent to a variable rate. All
frame data are sent LSBfirst.
If a BREAK frame is received, a break flag is set and the whole packet reception aborts.
The frame receiver can recognize an IDLE frame, but packet processing is not involved.
UART control register
US_REG1 and US_REG2 registers respectively contain all the configuration parameters of
SPI and UART interfaces of the STPM3x. Table 30 describes UART bits:
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Table 30. UART control register US_REG1
Row bit position
[23:16]
Name
Description
Default value
Timeout
Timeout threshold [ms]
0
9
Break on error
Enable/disable the operation to send break
frame in case of error
0
8
Noise detection
enable
Enable/disable error detection based on
noise immunity algorithm
0
[7:0]
CRCPolynomial
Polynomial used to validate transmitted and
received data
0x07
•
Timeout: any communication session should be completed within this configurable time
threshold (ms). If the timeout value is zero this threshold is disabled. If timeout expires,
the reception and the transmission processes stop and, if enabled, a BREAK character
is transmitted to warn the master about the error. Packet processing can resume only
after that BREAK transmission has been completed and an IDLE frame has been
received.
•
Break on error: if an error occurs (framing/noise/timeout/RX overrun) a BREAK
command is transmitted to the master.
•
Noise error detection. An oversampling technique is implemented to raise the noise
level immunity: received bit value is accomplished taking in account the value of three
samples, and applying to them the majority rule. This noise immunity algorithm is
automatically enabled: if "noise detection enable" bit is set, all samples must have the
same value to get a valid bit reception. In this case, when noise is detected within a
frame, a noise detection error is issued and the whole packet is discarded.
•
CRCPolynomial: default polynomial used is 0x07 (x8+x2+x+1).
CRC, in case of UART, has to be calculated on the reversed byte frame, because of the
internal structure of UART blocks.
For example, if the frame to transmit is 04_03_CD_AB, CRC should be calculated on the
frame:
20_C0_B3_D5 -> CRC = 0x16
The frame to send is: 04_03_CD_AB with the reversed CRC = 68
Note:
For UART peripheral, CRC byte is sent reversed only.
Table 31. UART control register US_REG2
Row bit position
Name
Description
[23:16]
Frame delay
[15:0]
Baud rate
TX frame-to-frame delay [bit periods]
Fractional baud rate generation
Default value
0
0x0683
•
Frame delay: delay (expressed as bit periods) in transmitted frames. The bit period
depends on the baud rate divider selection (see below).
•
Baud rate: set to 9600 default value, the communication baud rate can be programmed
in this configuration register. Theoretical values for configuration register can be
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121
Theory of operation
STPM32, STPM33, STPM34
calculated according to the following formulas, where a main clock frequency is 16
MHz, BR is the desired baud rate and BRDIV is the theoretical value of fractional
divider:
Equation 20
Equation 21
Equation 22
where BRRI are bits [15:4] and BRRF are bits [3:0] of the register.
According to the chosen baud rate divider the bit period is:
Equation 23
Table 32 summarizes the above calculation of the register value to select some typical baud
rates:
Table 32. Baud rate register examples
8.6.4
Baud rate
BRDIV
BRRI
BRRF
Register value
2400
416.666667
416 = 0x1A0
11 = 0xB
1A0B
9600
104.166667
104 = 0x68
3 = 0x3
683
19200
52.0833333
52 = 0x34
1 = 0x1
341
57600
17.3611111
17 = 0x11
6 = 0x6
116
115200
8.68055556
8 = 0x8
11 = 0xB
8B
230400
4.34027778
4 = 0x4
5 = 0x5
45
460800
2.17013889
2 = 0x2
3 = 0x3
23
UART/SPI status register and interrupt control register
At row 20, at read address 0x28, the register is responsible for holding the status of
UART/SPI peripherals of the STPM3x device. Setting the correspondent bit in IRQ CR the
interrupt mask raises an interrupt on both INT1, INT2 pins based on the peripheral status.
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Theory of operation
Table 33. UART/SPI status and interrupt control register
Register
Bit position
Description
Default value
Access
mode
30
SPI RX overrun
0
RW
29
SPI TX underrun
0
RW
28
SPI CRC error
0
RW
27
UART/SPI write address error
0
RW
26
UART/SPI read address error
0
RW
25
SPI TX empty
0
RO
24
SPI RX full
0
RO
22
UART TX overrun
0
RW
21
UART RX overrun
0
RW
20
UART noise error
0
RW
19
UART frame error
0
RW
18
UART timeout error
0
RW
17
UART CRC error
0
RW
16
UART break
0
RW
14
mask for SPI RX overrun error status bit
0
RW
13
mask for SPI TX underrun error status bit
0
RW
12
mask for SPI CRC error status bit
0
RW
11
mask for write address error status bit
0
RW
10
mask for read address error status bit
0
RW
6
mask for UART TX overrun
0
RW
5
mask for UART RX overrun
0
RW
4
mask for UART noise error
0
RW
3
mask for UART frame error
0
RW
2
mask for UART timeout error
0
RW
1
mask for UART CRC error
0
RW
SR
IRQ CR
•
SPI RX overrun: occurs when two consecutive write transactions are too fast and close
to each other
•
SPI TX underrun: occurs when a read-back operation (= write then read the same
register) or latch/read is too fast
•
SPI CRC error: CRC error detected
•
UART/SPI write address error: write address out of range (not write address not
writable)
•
UART/SPI read address error: read address out of range (not read address not
readable)
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121
Theory of operation
STPM32, STPM33, STPM34
•
SPI TX empty: transmission buffer empty (for SPI diagnostic, not recommended for
normal IRQ operations)
•
SPI RX full: reception buffer full (for SPI diagnostic, not recommended for normal IRQ
operations)
•
UART TX overrun: occurs when master and slave have different baud rates and master
transmits before reception has ended
•
UART RX overrun: active when received data have not been correctly processed
•
UART noise error: noisy bit detected
•
UART frame error: missing stop bit detected
•
UART timeout error: timeout counter expired
•
UART CRC error: CRC error detected
•
UART break: break frame (all zeros) received
Read-write status bits are set by the occurrence of the related event and are not reset when
the event ceases, on contrary master can only reset them transmitting a write sequence
addressed to memory location 0x28.
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DocID026142 Rev 3
STPM32, STPM33, STPM34
9
Application design and calibration
Application design and calibration
The choice of external components in the transduction section of the application is a crucial
point in the application design, affecting the precision and the resolution of the whole
system. A compromise has to be found among the following needs:
1.
Maximizing signal-to-noise ratio in the voltage and current channel
2.
Choosing current-to-voltage conversion ratio kS and the voltage divider ratio in a way
that calibration can be achieved for a given constant pulse CP
3.
Choosing kS to take advantage of the whole current dynamic range according to
desired maximum current and resolution
In this section, the rules for a good application design are described. After the design phase,
any tolerance of the real components from these values or device internal parameter drift
can be compensated through calibration.
Please refer to Section 8.4.6 and Section 8.4.7 for device basic calculations.
9.1
Application design
To reach CP target output constant pulse at default LPW value, the analog front end
component choice has to depend on:
–
value of R1 voltage divider resistor, given R2 and kS current sensor sensitivity
–
kS given R1 and R2 voltage divider resistors
Calculations for these two methods are developed below:
•
First method: constant kS
Given R2 (smaller voltage divider resistor), kS (current sensor sensitivity) and the target
meter constant pulse CP (pulses/kWh) as input of the calculations, the value of the voltage
divider resistor R1 comes from the following formula:
Equation 24
•
Second method: constant R1
Given R1, R2 (voltage divider resistors) and CP target meter constant pulse (pulses/kWh) as
input of the calculations, the value of kS current sensor comes from the following formula:
Equation 25
Note:
The resistor (the former) or the current channel sensor sensitivity (the latter) must be
chosen as closer as possible to the target; small tolerance is compensated by the
calibration, to reach the target constant pulse CP.
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121
Application design and calibration
STPM32, STPM33, STPM34
With the above external components, the maximum measurable values of RMS voltage and
current are:
Equation 26
Equation 27
These values are calculated leaving some available room for the input range with the peak
value and minimizing modulator distortions.
The current resolution value is equal to 4 times LSBIRMS:
Equation 28
V ref
I MIN = -------------------------------------------------------- [A]
15
cal I ⋅ A I ⋅ 2 ⋅ k S ⋅ k int
9.1.1
Example: current transformer case
This example shows the correct dimensioning of a meter using a current transformer having
the following specification:
Table 34. Example 1 design data
Parameter
Value
VN nominal voltage
230 VRMS
IN nominal current
5 ARMS
IMax maximum current
40 ARMS
CP constant pulses
1000 imp/kWh
The dimension of the voltage channel considers the voltage divider resistor values as 770
kΩ and 470 Ω.
Setting CP = 64000 pulses/kWh (at LPWx = 1 - device default value) and according to
calculation above the following values are:
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Application design and calibration
Table 35. Example 1 calculated data
Parameter
Value
Current sensor
sensitivity
V ref ⋅ C P ⋅ ( 1 + R 1 ⁄ R 2 )
k S = ------------------------------------------------------------------------------------ = 3.51mV ⁄ A
1800 ⋅ DClk ⋅ AV ⋅ A I ⋅ cal V ⋅ cal I
2
LED frequency at
PN
CP ⋅ VN ⋅ IN
LEDf = ----------------------------- = 20.44Hz
3600000
VMAX
IMAX
V ref
- = 5.97 mA
IMIN = -------------------------------------------------------15
cal I ⋅ A I ⋅ 2 ⋅ k S ⋅ k int
IMIN
2
LSBP
V ref ⋅ ( 1 + R 1 ⁄ R 2 )
LSB P = ------------------------------------------------------------------------------------ = 0.818mW ⁄ LSB
28
k int ⋅ A V ⋅ AI ⋅ k S ⋅ cal V ⋅ cal I ⋅ 2
LSBE
V ref ⋅ ( 1 + R 1 ⁄ R 2 )
= ------------------------------------------------------------------------------------------------------------------------= 0.214mWs ⁄ LSB
17
3600 ⋅ DClk ⋅ k int ⋅ A V ⋅ AI ⋅ k S ⋅ cal V ⋅ cal I ⋅ 2
2
LSBE
To set the desired LED pulse output, division factor LED_PWM can be set through
LPWx[3:0] bits in DSP_CR1 and DSP_CR2 configuration registers.
Table 36. LPWx bits, Cp, LED frequency relationships
LPWx
LED_PWM
CP [imp/kWh]
0000
0,0625
1024000
327,11
3,52
0001
0,125
512000
163,56
7,03
0010
0,25
256000
81,78
14,06
0011
0,5
128000
40,89
28,13
0100
1
64000
20,44
56,25
0101
2
32000
10,22
112,50
0110
4
16000
5,11
225
DocID026142 Rev 3
LED at PNom [Hz] Pulse value [Ws]
79/121
121
Application design and calibration
STPM32, STPM33, STPM34
Table 36. LPWx bits, Cp, LED frequency relationships (continued)
LPWx
LED_PWM
CP [imp/kWh]
LED at PNom [Hz] Pulse value [Ws]
0111
8
8000
2,56
450
1000
16
4000
1,28
900
1001
32
2000
0,64
1800
1010
64
1000
0,32
3600
1011
128
500
0,16
7200
1100
256
250
0,08
14400
1101
512
125
0,04
28800
1110
1024
62,5
0,02
57600
1111
2048
31,25
0,01
115200
The closer value to desired CP is given by setting LPWx divider to 1010.
Any tolerance producing small variation of CP from 1000 imp/kWh can be compensated by
calibration: setting CHV and CHC bits.
9.2
Application calibration
The meter has to be calibrated so to compensate external component tolerances and
internal VREF possible drift.
After the calibration, a meter using the STPM3x can reach IEC class 0.2 accuracy, taking
into account that the component choice follows the rules explained above, and the layout
and signal routing minimize the noise capture.
9.2.1
Voltage and current calibration (CHVx, CHCx bits)
Thanks to the device internal architecture and linearity, all calculated values (RMS, energies
and power) can be calibrated in a single point, just calibrating voltage and current streams.
For this purpose, a known nominal voltage VN and current IN must be applied to the meter
under calibration.
Referring to Section 9.1 and Section 5, having R1 or kS calculated as stated in the previous
section, the target values of voltage and current RMS registers, XV and XI respectively are
calculated as follows:
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Application design and calibration
Table 37. Calibration target values
Parameter
Value
15
V N ⋅ A V ⋅ cal V ⋅ 2
X V = -----------------------------------------------V ref ⋅ ( 1 + R 1 ⁄ R 2 )
Voltage register value at VN
17
IN ⋅ AI ⋅ cal I ⋅ k S ⋅ 2
X I = ----------------------------------------------------V ref
Current register value at IN
Note:
For the above calculation, the calculated value of the component kS or R1 (according to the
chosen design method) must be used; the difference of the real component is compensated
by calibration as a tolerance.
To start calibration, the device has to be programmed with the proper gain and current
sensor; moreover, to obtain the greatest correction dynamic, calibrators are initially set in
the middle of their range (0x800), thus obtaining a calibration range of ±12.5% per voltage
or current channel.
After applying VN and current IN to the meter, a certain number of voltage and current RMS
samples must be read and averaged (please, refer to averaged register values as VAV and
IAV) to calculate voltage and channel calibrators as follows:
Table 38. Calibrator calculation
Parameter
Calibrator value
Value
XV
CHV = 14336 ⋅ ---------- – 12288
V AV
XI
CHC = 14336 ⋅ -------- – 12288
I AV
Correction factor
The above procedure must be repeated for all voltage/current channels.
9.2.2
Phase calibration (PHVx, PHCx bits)
The STPM3x does not introduce any phase shift between voltage and current channels.
However, the voltage and current signals come from transducers, which could have inherent
phase errors. For example, a phase error of 0.1 ° to 0.3 ° is not uncommon for a current
transformer (CT). These phase errors can vary from part to part, and they must be corrected
in order to perform accurate power calculations. The errors associated with phase mismatch
are particularly noticeable at low power factors.
The phase compensation block provides a method of digital phase correction of the phase
shifting between voltage and current channels which can be introduced by the external
component intrinsic characteristics or by external component mismatch. The amount of
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121
Application design and calibration
STPM32, STPM33, STPM34
phase compensation can be set per each channel, and it is executed delaying the currents
and voltage samples using bits of the phase calibration configurators: PHCx[9:0] and
PHVx[1:0].
These registers act in the same way by delaying the desired waveform by a certain quantity
given from the equations below in degree:
Table 39. Phase-delay
Parameter
Value
Current shift
Voltage shift
f line
9
ϕ = ---------------- ⋅ ( PHCx [ 9:0 ] – PHVx [ 1:0 ] ⋅ 2 ) ⋅ 360°
SCLK
Global phase shift
A capacitive behavior is determined by the current leading the voltage waveform to a certain
angle. In this case, there is the compensation by delaying the current waveform by the same
angle through PHCx register. For a 50 Hz line the current channel waveform maximum
delayed is:
φC ≤ 4.6035° with step ΔφC =0.0045°
An inductive behavior has the opposite effect, so that current lags the voltage waveform. In
this case, PHV register delays the voltage waveform by the minimum angle to invert the
behavior to capacitive and then acting on PHCx register for the fine tuning of the current
waveform.
PHV impacts on the calculation of power and energies related to both current channels. For
a 50 Hz line, the voltage channel waveform maximum delayed is:
φV≤ 6.912 ° with step ΔφV = 2.304 °.
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DocID026142 Rev 3
STPM32, STPM33, STPM34
Application design and calibration
Figure 52. Phase shift error
9ROWDJH
&XUUHQWFDSDFLWLYH
&XUUHQWLQGXFWLYH
*,3*)65
The θ angle can be measured through the error on active power (from LED) averaged over
a certain number of samples (for example 50) at power factor PF = 0,5.
For example, if the error = e, the phase shift between voltage and current is:
Equation 29
1+e
θ = ar cos  ------------- – 60°
2
To compensate this error, PHC and PHV bits must be set as below, to introduce a correction
factor φ=-θ.
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121
Application design and calibration
STPM32, STPM33, STPM34
Table 40. Phase compensation
Parameter
Value
PHVx = 0x0
φ≥0
f line
9
– ---------------- ⋅ 2 ⋅ 360° ≤ ϕ < 0
SCLK
fline
f line
10
9
– ---------------- ⋅ 2 ⋅ 360° ≤ ϕ < – ---------------- ⋅ 2 ⋅ 360°
SCLK
SCLK
PHVx = 0x1
PHCx[9] = 0x0
9
ϕ ⋅ SCLK
PHCx [ 8:0 ] = PHVx ⋅ 2 + --------------------------360° ⋅ fline
PHVx = 0x2
PHCx[9] = 0
PHCx [ 8:0 ] = PHVx ⋅ 2
fline
f line
9
10
– ---------------- ⋅ 2 ⋅ 3 ⋅ 360° ≤ ϕ < – ---------------- ⋅ 2 ⋅ 360°
SCLK
SCLK
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DocID026142 Rev 3
10
ϕ ⋅ SCLK
+ --------------------------360° ⋅ f line
PHVx = 0x3
PHCx[9] = 0
9
ϕ ⋅ SCLK
PHCx [ 8:0 ] = PHVx ⋅ 2 + --------------------------360° ⋅ fline
STPM32, STPM33, STPM34
9.2.3
Application design and calibration
Power offset calibration (OFAx, OFAFx, OFRx, OFSx bits)
The device has the power offset compensation register for all measured powers (active,
active fundamental, reactive and apparent) to compensate, for each channel, the power
measured due to noise capture in the application.
Power registers are signed values, (MSB is the sign and negative values are two's
complemented); the power offset registers are also signed registers with LSB value equal to
4 times the power LSB:
Table 41. Power offset LSB
Parameter
Value
2
Power LSB value
LSB P
V ref ⋅ ( 1 + R 1 ⁄ R 2 )
w
- -----------= ------------------------------------------------------------------------------------28 LSB
Kint ⋅ A V ⋅ A I ⋅ k S ⋅ cal V ⋅ cal I ⋅ 2
2
Power offset LSB value
V ref ⋅ ( 1 + R 1 ⁄ R 2 )
2
2
w
LSB PO = LSB P ⋅ 2 = ------------------------------------------------------------------------------------- ⋅ 2 -----------28
LSB
K int ⋅ AV ⋅ A I ⋅ k S ⋅ cal V ⋅ cal I ⋅ 2
Power offset can be compensated by measuring the power value when the current I = 0, if
the average value is not null; the value is due to external influences, then an opposite value
should be applied to the power offset register.
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121
Register map
10
STPM32, STPM33, STPM34
Register map
There are three types of data register:
•
RW: read and written by application (in orange in the picture below)
•
RWL: the status bits, set from DSP, must be latched to read updated content, and must
be cleared by the application (in orange in the picture below)
•
RL: read registers only, they contain measured data and are continuously updated by
DSP, so they need to be latched before reading (in blue in the picture below)
The following nomenclature is used in the above registers:
86/121
•
A: active wideband
•
F: active fundamental
•
R: reactive
•
S: apparent
DocID026142 Rev 3
Register map graphical representation
Table 42. Register map
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_cr1
040000A0
dsp_cr2
240000A0
LSB [7:0]
11:8
7:4
STPM32, STPM33, STPM34
10.1
3:0
DSP control register #1
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
ENVREF1
ClearSS
TC1[2:0]
ROC1
BHPFC1
BHPFV1
APM1
AEM1
LPW1 [3:0]
RW
LPS1[1:0]
00
LCS1[1:0]
DocID026142 Rev 3
0
30
5
4
1
0
CLRSS_TO1[3:0]
31
DSP control register #2
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
ClearSS
ENVREF2
TC2[2:0]
ROC2
BHPFC2
BHPFV2
APM2
AEM2
LPW2 [3:0]
RW
LPS2[1:0]
02
LCS2[1:0]
1
30
3
2
1
0
87/121
Register map
CLRSS_TO2[3:0]
31
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_cr3
000004E0
dsp_cr4
00000000
LSB [7:0]
11:8
7:4
Register map
88/121
Table 42. Register map (continued)
3:0
DSP control register #3
DocID026142 Rev 3
06
RW
4
08
RW
5
0A
RW
6
0C
RW
7
0E
RW
8
10
RW
9
12
RW
26
25
24
23
22
21
20
19
SAG_THR1 [9:0]
18
17
16
15
14
13
12
11
10
ZCR
_SEL
[1:0]
PHC1[9:0]
9
8
7
6
5
4
3
2
1
0
SAG_TIME_THR[13:0]
PHC2[9:0]
SWV_THR1 [9:0]
CHV1 [11:0]
dsp_cr5
003FF800
SWC_THR1 [9:0]
CHC1 [11:0]
dsp_cr6
003FF800
SWV_THR2 [9:0]
CHV2 [11:0]
dsp_cr7
003FF800
SWC_THR2 [9:0]
CHC2 [11:0]
dsp_cr8
003FF800
OFAF1 [9:0]
OFA1 [9:0]
AH_UP1 [11:0]
dsp_cr9
00000FFF
OFS1 [9:0]
OFR1 [9:0]
AH_DOWN1 [11:0]
dsp_cr10
00000FFF
SAG_THR2 [9:0]
STPM32, STPM33, STPM34
3
27
PHV2[1:0]
RW
28
ZCR_EN
04
29
TMP_TOL[1:0]
2
30
REF_FREQ
EN_CUM
LED_OFF2
LED_OFF1
S/W Auto Latch
PHV1[1:0]
S/W latch2
S/W latch1
S/W reset
TMP_EN
31
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
LSB [7:0]
11:8
7:4
3:0
10
14
RW
OFAF2 [9:0]
OFA2 [9:0]
AH_UP2 [11:0]
dsp_cr11
00000FFF
11
16
RW
OFS2 [9:0]
OFR2 [9:0]
AH_DOWN2 [11:0]
dsp_cr12
00000FFF
dfe_cr1
0F270327
dfe_cr2
03270327
STPM32, STPM33, STPM34
Table 42. Register map (continued)
DFE Control Register 1 [31:0]
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
enC1
enV1
18
GAIN1[1:0]
DocID026142 Rev 3
31
12
DFE Control Register 2 [31:0]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
enV2
RW
enC2
1A
GAIN1[2:0]
13
Register map
89/121
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_irq1
00000000
dsp_irq2
00000000
LSB [7:0]
11:8
7:4
Register map
90/121
Table 42. Register map (continued)
3:0
DSP IRQ (Interrupt Control Mask) Register #1
14
1C
RW
31
30
29
28
27
26
25
24
23
22
21
20
19
C1 IRQ
CR[3:0]
V1 IRQ CR [7:0]
18
17
16
15
14
13
12
11
PH1 IRQ CR[7:0]
10
9
8
7
6
5
4
3
2
1
0
DocID026142 Rev 3
PH1+PH2
IRQ
CR[3:0]
PH2 IRQ CR [7:0]
DSP IRQ (interrupt control mask) register #2
15
1E
RW
31
30
29
28
27
26
25
V2 IRQ CR [7:0]
24
23
22
21
C2 IRQ
CR[3:0]
20
19
18
17
16
15
14
13
PH1 IRQ CR [7:0]
12
11
10
9
8
7
6
5
PH2 IRQ CR [7:0]
4
3
2
1
0
PH1+PH2
IRQ
CR[3:0]
STPM32, STPM33, STPM34
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_sr1
00000000
LSB [7:0]
11:8
7:4
3:0
DSP Status Register #1
29
28
27
26
20
RWL
24
23
22
21
20
19
18
17
16
C1
PH1 TAMPER
Swell End
Swell Start
Sag End
Sag Start
Per ERR
Signal Stuck
Swell End
Swell Start
Nah
Signal Stuck
DocID026142 Rev 3
16
TAMPER OR WRONG
V1
25
15
14
13
12
11
10
9
PH1
Energy
Overflow
7
6
5
4
PH2
Power Sign
S R F A S R F
8
A
Energy
Overflow
Power Sign
3
2
1
0
PH1+PH2
Power Sign
30
Energy Overflow
31
STPM32, STPM33, STPM34
Table 42. Register map (continued)
S R F A S R F A R A R A
Register map
91/121
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_sr2
00000000
us_reg1
00004007
LSB [7:0]
11:8
7:4
Register map
92/121
Table 42. Register map (continued)
3:0
DSP Status Register #2
29
28
27
26
25
24
23
22
RWL
21
20
19
18
17
16
C2
15
14
13
12
11
10
9
PH1
PH2 TAMPER
Swell End
Swell Start
Sag End
Sag Start
Per ERR
Signal Stuck
Swell End
Swell Start
Nah
Signal Stuck
Energy
Overflow
8
7
6
5
4
PH2
Power Sign
S R F A S R F
A
Energy
Overflow
3
2
1
0
PH1+PH2
Power Sign
S R F A S R F A R A R A
UART & SPI Control Register #1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
RW
Time Out [7:0] (ms)
13
12
11
10
9
8
Break on Err
Noise en
24
29
crcen
18
30
7
6
5
4
3
2
1
CRC Polynomial [7:0]
0
STPM32, STPM33, STPM34
31
lsbfirst
DocID026142 Rev 3
17
TAMPER OR WRONG
V2
22
Power Sign
30
Energy Overflow
31
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
us_reg2
00000683
us_reg3
00000000
LSB [7:0]
11:8
7:4
3:0
UART & SPI Control Register #2
19
26
RW
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
Frame Delay [7:0]
11
10
9
8
7
6
5
3
2
1
0
4
3
2
1
0
Baud rate (ufix16_en4)
UART & SPI IRQ Register
20
19
18
17
16
15
14
13
UART & SPI IRQ Status Register
12
11
10
9
8
7
6
5
UART & SPI IRQ Control Register
time-out err
crcerror
21
noise err
22
frame err
23
tx ovr
24
rx ovr
25
underrun
26
read error
27
crc error
RW
28
write error
28
29
overrun
20
30
tx ovr
rx ovr
noise err
frame err
time-out err
crc error
Break
31
overrun
underrun
crc error
write error
read error
tx empty
rx full
DocID026142 Rev 3
4
STPM32, STPM33, STPM34
Table 42. Register map (continued)
Register map
93/121
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_ev1
00000000
LSB [7:0]
11:8
7:4
Register map
94/121
Table 42. Register map (continued)
3:0
DSP live events #1
24
23
22
21
20
19
18
17
16
SWC1_EV[3:0]
RL
SWV1_EV[3:0]
2A
SAG1_EV[3:0]
DocID026142 Rev 3
21
14
13
12
11
10
C1
Per ERR
Signal stuck
ZCR
V1
15
9
8
7
6
5
PH1
4
3
2
1
0
PH1+PH2
Power Sign
25
Energy Overflow
26
Power Sign
27
Energy Overflow
28
ZCR
29
Signal Stuck
30
Nah
31
S R F A S R F A R A q A
STPM32, STPM33, STPM34
Index
MSW [31:16]
(R)ead
Row Address (W)rite
(L)atch
MSB [31:24]
31:28
LSW [15:0]
LSB [23:16]
27:24
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
dsp_ev2
00000000
dsp_reg1
00000000
LSB [7:0]
11:8
7:4
3:0
DSP live events #2
29
28
27
26
25
24
23
22
21
20
19
18
17
16
V2
14
13
12
11
10
C2
9
8
7
6
5
4
PH2
ZCR
Signal Stuck
Nah
SWC2_EV[3:0]
Per ERR
Signal Stuck
ZCR
RL
SWV2_EV[3:0]
2C
SAG2_EV[3:0]
DocID026142 Rev 3
22
15
Power Sign
Power Sign
3
2
1
0
PH1+PH2
Power Sign
30
Energy Overflow
31
STPM32, STPM33, STPM34
Table 42. Register map (continued)
S R F A S R F A R A R A
2E
RL
PH2 Period [11:0]
PH1 Period [11:0]
24
30
RL
Padding
V1 Data [23:0]
dsp_reg2
00000000
25
32
RL
Padding
C1 Data [23:0]
dsp_reg3
00000000
26
34
RL
Padding
V2 Data [23:0]
dsp_reg4
00000000
27
36
RL
Padding
C2 Data [23:0]
dsp_reg5
00000000
28
38
RL
Padding
V1 Fund [23:0]
dsp_reg6
00000000
Register map
95/121
23
Index
(R)ead
Row Address (W)rite
(L)atch
MSW [31:16]
MSB [31:24]
31:28
27:24
LSW [15:0]
LSB [23:16]
23:20
19:16
MSB [15:8]
15:12
Names
Default
values
LSB [7:0]
11:8
7:4
3:0
DocID026142 Rev 3
3A
RL
Padding
C1 Fund [23:0]
dsp_reg7
00000000
30
3C
RL
Padding
V2 Fund [23:0]
dsp_reg8
00000000
31
3E
RL
Padding
C2 Fund [23:0]
dsp_reg9
00000000
32
40
RL
dsp_reg10
00000000
33
42
RL
dsp_reg11
00000000
34
44
RL
dsp_reg12
00000000
35
46
RL
dsp_reg13
00000000
36
48
RL
C1 RMS Data [16:0]
V1 RMS Data [14:0]
dsp_reg14
00000000
37
4A
RL
C2 RMS Data [16:0]
V2 RMS Data [14:0]
dsp_reg15
00000000
38
4C
RL
SAG1_TIME [14:0]
SWV1_TIME [14:0]
dsp_reg16
00000000
39
4E
RL
SWC1_TIME [14:0]
dsp_reg17
00000000
40
50
RL
SWV2_TIME [14:0]
dsp_reg18
00000000
SAG2_TIME [14:0]
STPM32, STPM33, STPM34
29
C1_PHA[11:0]
Register map
96/121
Table 42. Register map (continued)
Index
(R)ead
Row Address (W)rite
(L)atch
MSW [31:16]
MSB [31:24]
31:28
27:24
LSW [15:0]
LSB [23:16]
23:20
MSB [15:8]
19:16
15:12
11:8
C2_PHA[11:0]
Names
Default
values
dsp_reg19
00000000
LSB [7:0]
7:4
SWC2_TIME [14:0]
3:0
DocID026142 Rev 3
52
RL
42
54
RL
PH1 Active Energy
ph1_reg1
00000000
43
56
RL
PH1 Fundamental Energy
ph1_reg2
00000000
44
58
RL
PH1 Reactive Energy
ph1_reg3
00000000
45
5A
RL
PH1 Apparent Energy
ph1_reg4
00000000
46
5C
RL
PH1 Active Power[28:0]
ph1_reg5
00000000
47
5E
RL
PH1 Fundamental Power[28:0]
ph1_reg6
00000000
48
60
RL
PH1 Reactive Power[28:0]
ph1_reg7
00000000
49
62
RL
PH1 Apparent RMS Power[28:0]
ph1_reg8
00000000
50
64
RL
PH1 Apparent Vectorial Power[28:0]
ph1_reg9
00000000
51
66
RL
PH1 Momentary Active Power[28:0]
ph1_reg10
00000000
52
68
RL
PH1 Momentary Fundamental Power[28:0]
ph1_reg11
00000000
53
6A
RL
ph1_reg12
00000000
PH1 AH_ACC
Register map
97/121
41
STPM32, STPM33, STPM34
Table 42. Register map (continued)
Index
(R)ead
Row Address (W)rite
(L)atch
MSW [31:16]
MSB [31:24]
31:28
27:24
LSW [15:0]
LSB [23:16]
23:20
MSB [15:8]
19:16
15:12
11:8
Names
Default
values
LSB [7:0]
7:4
Register map
98/121
Table 42. Register map (continued)
3:0
DocID026142 Rev 3
6C
RL
PH2 Active Energy
ph2_reg1
00000000
55
6E
RL
PH2 Fundamental Energy
ph2_reg2
00000000
56
70
RL
PH2 Reactive Energy
ph2_reg3
00000000
57
72
RL
PH2 Apparent RMS Energy
ph2_reg4
00000000
58
74
RL
PH2 Active Power[28:0]
ph2_reg5
00000000
59
76
RL
PH2 Fundamental Power[28:0]
ph2_reg6
00000000
60
78
RL
PH2 Reactive Power[28:0]
ph2_reg7
00000000
61
7A
RL
PH2 Apparent RMS Power[28:0]
ph2_reg8
00000000
62
7C
RL
PH2 Apparent Vectorial Power[28:0]
ph2_reg9
00000000
63
7E
RL
PH2 Momentary Active Power[28:0]
ph2_reg10
00000000
64
80
RL
PH2 Momentary Fundamental Power[28:0]
ph2_reg11
00000000
65
82
RL
PH2 AH_ACC
ph2_reg12
00000000
66
84
RL
Total Active Energy
tot_reg1
00000000
STPM32, STPM33, STPM34
54
Index
(R)ead
Row Address (W)rite
(L)atch
MSW [31:16]
MSB [31:24]
31:28
27:24
LSW [15:0]
LSB [23:16]
23:20
MSB [15:8]
19:16
15:12
Names
Default
values
LSB [7:0]
11:8
7:4
3:0
67
86
RL
Total Fundamental Energy
tot_reg2
00000000
68
88
RL
Total Reactive Energy
tot_reg3
00000000
69
8A
RL
Total Apparent Energy
tot_reg4
00000000
STPM32, STPM33, STPM34
Table 42. Register map (continued)
DocID026142 Rev 3
Table 43. Register map legend
Read/Write bit
RESERVED
Read
Active
Energy/Power
Fundamental
Energy/Power
Reactive
Energy/Power
Apparent
Energy/Power
A
F
R
S
Register map
99/121
Register map
10.2
STPM32, STPM33, STPM34
Configuration register
Table 44. Row 0, DSP control register 1 (DSP_CR1)
Bit
Internal signal
[3:0]
CLRSS_TO1
Set duration of primary channel signal to clear sag and swell
and avoid race condition on digital counters
0x0
4
ClearSS1
Clear sag and swell time register and history bits for primary
channel, auto-reset to '0'
0x0
5
ENVREF1
Enable internal voltage reference for primary channel:
0: reference disabled – external VREF required
1: reference enabled
0x1
[8:6]
TC1
Temperature compensation coefficient selection for primary
channel voltage reference VREF1 (see Table 9)
0x2
Reserved
0x0
AEM1
Apparent energy mode for primary channel:
0: use apparent RMS power
1: use apparent vectorial power
0x0
18
APM1
Apparent vectorial power mode for primary channel:
0: use fundamental power
1: use active power
0x0
19
BHPFV1
Bypass hi-pass filter for primary voltage channel:
0: HPF enabled
1: HPF bypassed
0x0
20
BHPFC1
Bypass hi-pass filter for primary current channel:
0: HPF enabled
1: HPF bypassed
0x0
Add Rogowski integrator to primary current channel filtering
pipeline:
0: integrator bypassed
1: integrator enabled
0x0
Reserved
0x0
[16:9]
17
21
ROC1
[23:22]
Default
[27:24]
LPW1
LED1 speed dividing factor: 0x0 = 2^(-4), 0xF = 2^11
Default 0x4 = 1
0x4
[29:28]
LPS1
LED1 pulse-out power selection:
LPS1 [1:0]: 00,01,10,11
LED1 output: active, fundamental, reactive, apparent
0x0
LCS1
LED1 pulse-out channel selection:
LCS1 [1:0]: 00,01,10,11
LED1: primary channels, secondary channels, cumulative,
sigma-delta bitstream
0x0
[31:30]
100/121
Description
DocID026142 Rev 3
STPM32, STPM33, STPM34
Register map
Table 45. Row 1, DSP control register 2 (DSP_CR2)
Bit
Internal signal
[3:0]
CLRSS_TO2
4
Description
Default
Set duration of secondary channel signal to clear sag and
swell and avoid race condition on digital counters
0x0
ClearSS2
Clear sag and swell time register and history bits for
secondary channel, auto-reset to 0
0x0
5
ENVREF2
Enable internal voltage reference for secondary channel:
0: reference disabled – external VREF required
1: reference enabled
0x1
[8:6]
TC2
Temperature compensation coefficient selection for
secondary channel voltage reference VREF2 (see Table 9)
0x2
Reserved
0x0
AEM2
Apparent energy mode for secondary channel:
0: use apparent RMS power
1: use apparent vectorial power
0x0
18
APM2
Apparent vectorial power mode for secondary channel:
0: use fundamental power
1: use active power
0x0
19
BHPFV2
Bypass hi-pass filter for secondary voltage channel:
0: HPF enabled
1: HPF bypassed
0x0
20
BHPFC2
Bypass hi-pass filter for secondary current channel:
0: HPF enabled
1: HPF bypassed
0x0
Add Rogowski integrator to secondary current channel
filtering pipeline:
0: integrator bypassed
1: integrator enabled
0x0
Reserved
0x0
[16:9]
17
21
ROC2
[23:22]
[27:24]
LPW2
LED2 speed dividing factor: 0x0 = 2^(-4), 0xF = 2^11
Default 0x4 = 1
0x4
[29:28]
LPS2
LED2 pulse-out power selection:
LPS2 [1:0]: 00,01,10,11
LED2: output, active, fundamental, reactive, apparent
0x2
[31:30]
LCS2
LED2 pulse-out channel selection:
LCS2 [1:0]: 00,01,10,11
LED2: secondary channels, algebraic, sigma-delta bitstream
0x0
DocID026142 Rev 3
101/121
121
Register map
STPM32, STPM33, STPM34
Table 46. Row 2, DSP control register 3 (DSP_CR3)
Bit
Internal signal
[13:0]
TIME_VALUE
Time counter threshold for voltage sag detection
Default
0x4E0
[15:14]
ZCR_SEL
Selection bit for ZCR/CLK pin, (output depends on ZCR/CLK
enable bit):
ZCR_SEL[1:0]: 00, 01, 10, 11
ZCR: V1, C1, V2, C2
CLK: 7.8125 kHz, 4 MHz, 4 MHz, 50% duty cycle, 16 MHz
16
ZCR_EN
ZCR/CLK pin output:
0: CLK
1: ZCR
0x0
[18:17]
TMP_TOL
Selection bits for tamper tolerance:
TMP_TOL[1:0]: 00, 01, 10, 11
Tolerance: 12.5%, 8.33%, 6.25%, 3.125%
0x0
19
TMP_EN
Enable tampering feature:
0: tamper disable
1: tamper enable
0x0
20
S/W reset
SW reset brings the configuration registers to default
This bit is set to zero after this action automatically
0
21
S/W latch1
Primary channel measurement register latch
This bit is set to zero after this action automatically
0
22
S/W latch2
Secondary channel measurement register latch
his bit is set to zero after this action automatically
0
23
S/W Auto Latch Automatic measurement register latch at 7.8125 kHz
0x0
0
LED1OFF
LED1 pin output disable
0: LED1 output on
1: LED1 output disabled
When the LED output is disabled the pin is set at low-state
0
LED2OFF
LED2 pin output disable
0: LED2 output on
1: LED2 output disabled
When the LED output is disabled the pin is set at low-state
0
26
EN_CUM
Cumulative energy calculation
0: cumulative is the sum of channel energies
1: total is the difference of energies
0
27
REF_FREQ
Reference line frequency:
0: 50 Hz
1: 60 Hz
0
Reserved
0
24
25
[31:28]
102/121
Description
DocID026142 Rev 3
STPM32, STPM33, STPM34
Register map
Table 47. Row 3, DSP control register 4 (DSP_CR4)
Bit
Internal signal
[9:0]
PHC2
Secondary current channel phase compensation
register
0x0
[11:10]
PHV2
Secondary voltage channel phase compensation
register
0x0
[21:12]
PHC1
Primary current channel phase compensation register
0x0
[23:22]
PHV1
Primary voltage channel phase compensation register
0x0
Reserved
0x0
[31:24]
Description
Default
Table 48. Row 4, DSP control register 5 (DSP_CR5)
Bit
Internal signal
[11:0]
CHV1
[21:12]
[31:22]
Description
Default
Calibration register of primary voltage channel
0x800
SWV_THR1
Swell threshold of primary voltage channel
8x3FF
SAG_THR1
Sag threshold of primary voltage channel
DocID026142 Rev 3
0x0
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121
Register map
STPM32, STPM33, STPM34
Table 49. Row 5, DSP control register 6 (DSP_CR6)
Bit
Internal signal
[11:0]
CHC1
[21:12]
SWC_THR1
[31:22]
Description
Default
Calibration register of primary current channel
0x800
Swell threshold of primary current channel
0x3FF
Reserved
0x0
Table 50. Row 6, DSP control register 7 (DSP_CR7)
Bit
Internal signal
[11:0]
CHV2
[21:12]
[31:22]
Description
Default
Calibration register of secondary voltage channel
0x800
SWV_THR2
Swell threshold of secondary voltage channel
0x3FF
SAG_THR2
Sag threshold of secondary voltage channel
0x0
Table 51. Row 7, DSP control register 8 (DSP_CR8)
Bit
Internal signal
[11:0]
CHC2
[21:12]
SWC_THR2
[31:22]
Description
Default
Calibration register of secondary current channel
0x800
Swell threshold of secondary current channel
0x3FF
Reserved
0x0
Table 52. Row 8, DSP control register 9 (DSP_CR9)
Bit
Internal signal
[11:0]
AH_UP1
[21:12]
OFA1
[31:22]
OFAF1
Description
Primary channel RMS upper threshold (for AH)
Default
0xFFF
Offset for primary channel active power
0x0
Offset for primary channel fundamental active power
0x0
Table 53. Row 9, DSP control register 10 (DSP_CR10)
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Bit
Internal signal
Description
[11:0]
AH_DOWN1
[21:12
OFR1
Offset for primary channel reactive power
0x0
[31:22]
OFS1
Offset for primary channel apparent power
0x0
Primary channel RMS lower threshold (for AH)
DocID026142 Rev 3
Default
0xFFF
STPM32, STPM33, STPM34
Register map
Table 54. Row 10, DSP control register 11 (DSP_CR11)
Bit
Internal signal
[11:0]
AH_UP2
[21:12]
OFA2
[31:22]
OFAF2
Description
Secondary channel RMS upper threshold (for AH)
Default
0xFFF
Offset for secondary channel active power
0x0
Offset for secondary channel fundamental active power
0x0
Table 55. Row 11, DSP control register 12 (DSP_CR12)
Bit
Internal signal
Description
[11:0]
AH_DOWN2
[21:12]
OFR2
Offset for secondary channel reactive power
0x0
[31:22]
OFS2
Offset for secondary channel apparent power
0x0
Secondary channel RMS lower threshold (for AH)
Default
0xFFF
Table 56. Row 12, digital front end control register 1 (DFE_CR1)
Bit
Internal signal
0
enV1
[15:1]
[16]
Description
Enable for primary voltage channel
Reserved
enC1
Default
0x1
0x193
Enable for primary current channel
0x1
[17:25]
Reserved
[27:26]
Gain selection of primary current channel:
GAIN1[1:0]: 00, 01, 10, 11
GAIN: x2, x4, x8, x16
0x3
Reserved
0x0
GAIN1
[31:28]
0x193
Table 57. Row 13, digital front end control register 2 (DFE_CR2)
Bit
Internal signal
0
enV2
[15:1]
[16]
Description
Enable for secondary voltage channel
Reserved
enC2
Enable for secondary current channel
Default
0x1
0x193
0x1
[17:25]
Reserved
[27:26]
Gain selection of secondary current channel:
GAIN2 [1:0]: 00, 01, 10, 11
GAIN: x2, x4, x8, x16
0x0
Reserved
0x0
[31:28]
GAIN2
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0x193
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121
Register map
STPM32, STPM33, STPM34
Table 58. Row 14, DSP interrupt control mask register 1 (DSP_IRQ1)
Bit
Internal signal
0
Description
Default
Sign total active power
0
Sign total reactive power
0
2
Overflow total active energy
0
3
Overflow total reactive energy
0
4
Sign secondary channel active power
0
5
Sign secondary channel active fundamental power
0
6
Sign secondary channel reactive power
0
Sign secondary channel apparent power
0
8
Overflow secondary channel active energy
0
9
Overflow secondary channel active fundamental energy
0
10
Overflow secondary channel reactive energy
0
11
Overflow secondary channel apparent energy
0
12
Sign primary channel active power
0
13
Sign primary channel active fundamental power
0
14
Sign primary channel reactive power
0
Sign primary channel apparent power
0
16
Overflow primary channel active energy
0
17
Overflow primary channel active fundamental energy
0
18
Overflow primary channel reactive energy
0
19
Overflow primary channel apparent energy
0
20
Primary current sigma-delta bitstream stuck
0
AH1 - accumulation of primary channel current
0
22
Primary current swell detected
0
23
Primary current swell end
0
24
Primary voltage sigma-delta bitstream stuck
0
25
Primary voltage period error
0
Primary voltage sag detected
0
27
Primary voltage sag end
0
28
Primary voltage swell detected
0
29
Primary voltage swell end
0
Tamper on primary
0
Tamper or wrong connection
0
1
PH1+PH2 IRQ CR
7
PH2 IRQ CR
15
PH1 IRQ CR
21
C1 IRQ CR
26
V1 IRQ CR
30
Tamper
31
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Register map
Table 59. Row 15, DSP interrupt control mask register 2 (DSP_IRQ2)
Bit
Internal signal
0
Description
Default
Sign total active power
0
Sign total reactive power
0
2
Overflow total active energy
0
3
Overflow total reactive energy
0
4
Sign secondary channel active power
0
5
Sign secondary channel active fundamental power
0
6
Sign secondary channel reactive power
0
Sign secondary channel apparent power
0
8
Overflow secondary channel active energy
0
9
Overflow secondary channel active fundamental energy
0
10
Overflow secondary channel reactive energy
0
11
Overflow secondary channel apparent energy
0
12
Sign primary channel active power
0
13
Sign primary channel active fundamental power
0
14
Sign primary channel reactive power
0
Sign primary channel apparent power
0
16
Overflow primary channel active energy
0
17
Overflow primary channel active fundamental energy
0
18
Overflow primary channel reactive energy
0
19
Overflow primary channel apparent energy
0
20
Secondary current sigma-delta bitstream stuck
0
AH1 - accumulation of secondary channel current
0
22
Secondary current swell detected
0
23
Secondary current swell end
0
24
Secondary voltage sigma-delta bitstream stuck
0
25
Secondary voltage period error
0
Secondary voltage sag detected
0
27
Secondary voltage sag end
0
28
Secondary voltage swell detected
0
29
Secondary voltage swell end
0
Tamper on secondary
0
Tamper or wrong connection
0
1
PH1+PH2 IRQ CR
7
PH2 IRQ CR
15
PH1 IRQ CR
21
C2 IRQ CR
26
V2 IRQ CR
30
Tamper
31
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Register map
STPM32, STPM33, STPM34
Table 60. Row 16, DSP status register 1 (DSP_SR1)
Bit
Internal signal
0
Description
Default
Sign total active power
0
Sign total reactive power
0
2
Overflow total active energy
0
3
Overflow total reactive energy
0
4
Sign secondary channel active power
0
5
Sign secondary channel active fundamental power
0
6
Sign secondary channel reactive power
0
Sign secondary channel apparent power
0
8
Overflow secondary channel active energy
0
9
Overflow secondary channel active fundamental energy
0
10
Overflow secondary channel reactive energy
0
11
Overflow secondary channel apparent energy
0
12
Sign primary channel active power
0
13
Sign primary channel active fundamental power
0
14
Sign primary channel reactive power
0
Sign primary channel apparent power
0
16
Overflow primary channel active energy
0
17
Overflow primary channel active fundamental energy
0
18
Overflow primary channel reactive energy
0
19
Overflow primary channel apparent energy
0
20
Secondary current sigma-delta bitstream stuck
0
AH1 - accumulation of secondary channel current
0
22
Secondary current swell detected
0
23
Secondary current swell end
0
24
Secondary voltage sigma-delta bitstream stuck
0
25
Secondary voltage period error
0
Secondary voltage sag detected
0
27
Secondary voltage sag end
0
28
Secondary voltage swell detected
0
29
Secondary voltage swell end
0
Tamper on secondary
0
Tamper or wrong connection
0
1
PH1+PH2 status
7
PH2 IRQ status
15
PH1 IRQ status
21
C1 IRQ status
26
V1 IRQ status
30
Tamper
31
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Register map
Table 61. Row 17, DSP status register 2 (DSP_SR2)
Bit
Internal signal
0
Description
Default
Sign total active power
0
Sign total reactive power
0
2
Overflow total active energy
0
3
Overflow total reactive energy
0
4
Sign secondary channel active power
0
5
Sign secondary channel active fundamental power
0
6
Sign secondary channel reactive power
0
Sign secondary channel apparent power
0
8
Overflow secondary channel active energy
0
9
Overflow secondary channel active fundamental energy
0
10
Overflow secondary channel reactive energy
0
11
Overflow secondary channel apparent energy
0
12
Sign primary channel active power
0
13
Sign primary channel active fundamental power
0
14
Sign primary channel reactive power
0
Sign primary channel apparent power
0
16
Overflow primary channel active energy
0
17
Overflow primary channel active fundamental energy
0
18
Overflow primary channel reactive energy
0
19
Overflow primary channel apparent energy
0
20
Secondary current sigma-delta bitstream stuck
0
AH1 - accumulation of secondary channel current
0
22
Secondary current swell detected
0
23
Secondary current swell end
0
24
Secondary voltage sigma-delta bitstream stuck
0
25
Secondary voltage period error
0
Secondary voltage sag detected
0
27
Secondary voltage sag end
0
28
Secondary voltage swell detected
0
29
Secondary voltage swell end
0
Tamper on secondary
0
Tamper or wrong connection
0
1
PH1+PH2 status
7
PH2 status
15
PH1 status
21
C2 status
26
V2 status
30
Tamper
31
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Register map
10.3
STPM32, STPM33, STPM34
UART/SPI registers
Table 62. Row 18, UART/SPI control register 1 (US_REG1)
Bit
Internal signal
Description
Default
[7:0]
CRCpolynomial
UART/SPI polynomial for CRC calculus (SMBus default polynomial
used: x8+x2+x+1)
0x07
8
Noise detection
enable
UART noise immunity feature enabled
0x0
9
Break on error
UART break feature enabled
0x0
Reserved
0x0
[13:10]
th
14
CRCenable
8-bit CRC enable (5 packet required in each transmission)
0x1
15
LSBfirst
0: big-endian, 1: little-endian
0x0
[23:16]
Time out
Time out (ms)
0x0
Reserved
0x0
[31:24]
Table 63. Row 19, UART/SPI control register 2 (US_REG2)
Bit
[15:0]
Internal signal
Baud rate
Description
Defaulted to 9600 baud
Default
0x683
[23:16] Frame delay
Frame delay
0x0
[31:24]
Reserved
0x0
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Register map
Table 64. Row 20, UART/SPI control register 3 (US_REG3)
Bit
Internal signal
Description
Default
0
-
Reserved
0
1
UART CRC error
Activate IRQ on both INT1, INT2 for selected signals
0
2
UART timeout error Activate IRQ on both INT1, INT2 for selected signals
0
3
UART framing error Activate IRQ on both INT1, INT2 for selected signals
0
4
UART noise error
Activate IRQ on both INT1, INT2 for selected signals
0
5
UART RX overrun
Activate IRQ on both INT1, INT2 for selected signals
0
6
UART TX overrun
Activate IRQ on both INT1, INT2 for selected signals
0
Reserved
1
[9:7]
10
UART/SPI read
error
Activate IRQ on both INT1, INT2 for selected signals
0
11
UART/SPI write
error
Activate IRQ on both INT1, INT2 for selected signals
0
12
SPI CRC error
Activate IRQ on both INT1, INT2 for selected signals
0
13
SPI TX underrun
Activate IRQ on both INT1, INT2 for selected signals
0
14
SPI RX overrun
Activate IRQ on both INT1, INT2 for selected signals
0
Reserved
0
15
16
UART break
Break frame (all zeros) received
0
17
UART CRC error
CRC error detected
0
18
UART timeout error Timeout counter expired
0
19
UART framing error Missing stop bit detected
0
20
UART noise error
Noisy bit detected
0
21
UART RX overrun
Active when received data have not been correctly
processed
0
22
UART TX overrun
Occurs when master and slave have different baud rates
and master transmits before reception has ended
0
Reserved
0
23
24
SPI RX full
Reception buffer full (for SPI diagnostic, not recommended
for normal IRQ operations)
0
25
SPI TX empty
Transmission buffer empty (for SPI diagnostic, not
recommended for normal IRQ operations)
0
26
UART/SPI read
address error
Read address out of range
0
27
UART/SPI write
address error
Write address out of range
0
28
SPI CRC error
CRC error detected
0
29
SPI TX underrun
Occurs when a read-back operation (= write then read the
same register) or latch + read is too fast
0
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121
Register map
STPM32, STPM33, STPM34
Table 64. Row 20, UART/SPI control register 3 (US_REG3) (continued)
Bit
30
31
112/121
Internal signal
SPI RX overrun
Description
Default
Occurs when two consecutive write transactions are too fast
and close to each other
0
Reserved
0
DocID026142 Rev 3
STPM32, STPM33, STPM34
10.4
Register map
Data registers
Table 65. Row 21, DSP live event 1 (DSP_EV1)
Bit
Internal signal
0
Description
Default
Sign total active power
0
Sign total reactive power
0
2
Overflow total active energy
0
3
Overflow total reactive energy
0
4
Sign primary channel active power
0
5
Sign primary channel active fundamental power
0
6
Sign primary channel reactive power
0
Sign primary channel apparent power
0
8
Overflow primary channel active energy
0
9
Overflow primary channel active fundamental energy
0
10
Overflow primary channel reactive energy
0
11
Overflow primary channel apparent energy
0
12
Primary current zero-crossing
0
13
Primary current sigma-delta bitstream stuck
0
14
Primary current AH accumulation
0
1
PH1+PH2 events
7
PH1 events
15
0
C1 events
16
0
Primary current swell event history
17
0
18
0
19
Primary voltage zero-crossing
0
20
Primary voltage sigma-delta bitstream stuck
0
21
Primary voltage period error (out of range)
0
0
22
23
0
Primary voltage swell event history
24
0
V1 events
25
0
26
0
27
0
Primary voltage sag event history
28
0
29
0
30
Reserved
0
31
Reserved
0
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121
Register map
STPM32, STPM33, STPM34
Table 66. Row 22, DSP live event 2 (DSP_EV2)
Bit
Internal signal
0
Description
Default
Sign total active power
0
Sign total reactive power
0
2
Overflow active energy total
0
3
Overflow reactive energy total
0
4
Sign secondary channel active power
0
5
Sign secondary channel active fundamental power
0
6
Sign secondary channel reactive power
0
Sign secondary channel apparent power
0
8
Overflow secondary channel active energy
0
9
Overflow secondary channel active fundamental energy
0
10
Overflow secondary channel reactive energy
0
11
Overflow secondary channel apparent energy
0
12
Secondary current zero-crossing
0
13
Secondary current sigma-delta bitstream stuck
0
14
Secondary current AH accumulation
0
1
PH1+PH2 events
7
PH2 events
15
0
C2 events
16
0
Secondary current swell event history
17
0
18
0
19
Secondary voltage zero-crossing
0
20
Secondary voltage sigma-delta bitstream stuck
0
21
Secondary voltage period error (out of range)
0
22
0
23
0
Secondary voltage swell event history
24
0
V2 events
25
0
26
0
27
0
Secondary voltage sag event history
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28
0
29
0
30
Reserved
0
31
Reserved
0
DocID026142 Rev 3
STPM32, STPM33, STPM34
11
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:www.st.com.
ECOPACK® is an ST trademark.
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Package information
11.1
STPM32, STPM33, STPM34
QFN24L 4x4x1 mm 0.5 pitch package information
Figure 53. QFN24L 4x4x1 mm 0.5 pitch outline
B(
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STPM32, STPM33, STPM34
Package information
Table 67. QFN24L 4x4x1 mm 0.5 pitch package mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.02
0.05
b
0.18
0.25
0.30
D
3.90
4.00
4.10
D2
2.30
2.45
2.55
E
3.90
4.00
4.10
E2
2.30
2.45
2.55
e
0.45
0.50
0.55
K
0.20
L
0.30
0.40
0.50
Figure 54. QFN24L 4x4x1 mm 0.5 pitch recommended footprint
4)1[BIRRWSULQW
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Package information
11.2
STPM32, STPM33, STPM34
QFN32L 5x5x1 mm 0.5 pitch package information
Figure 55. QFN32L 5x5x1 mm 0.5 pitch outline
B2
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Package information
Table 68. QFN32L 5x5x1 mm 0.5 pitch package mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
A3
0.20
b
0.18
0.25
0.30
D
4.85
5.00
5.15
D2
3.40
3.45
3.50
E
4.85
5.00
5.15
E2
3.40
3.45
3.50
e
0.45
0.50
0.55
L
0.30
0.40
0.50
Ddd
0.08
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Revision history
12
STPM32, STPM33, STPM34
Revision history
Table 69. Revision history
Date
Revision
31-Mar-2014
1
Initial release.
2
Updated Features.
Updated Table 2, from Table 14, to Table 18, from Table 21, to
Table 23; updated Table 33, Table 35, Table 36, Table 40, Table 41
and from Table 44 to Table 66.
Changed title of Figure 15.
Updated Figure 22, Figure 31.
Updated Section 8.2.1, Section 8.2.3, Section 8.3.1, Section 8.4.12,
Section 8.6.3.
Minor text changes.
3
Updated Features.
Updated Section 8.2.1, Section 8.3.3, Section 8.3.6, Section 8.4,
Section 8.4.3, Section 8.4.4, Section 8.4.12, Section 8.4.13, Period
measurement, Sag and swell threshold calculation.
Added note to Interrupt control mask register.
Updated Table 5, Table 22, Table 42, Table 44, Table 45,
Table 56,Table 57, Table 58, Table 59, Table 60, Table 61.
Updated equations in Table 14, Table 15, Table 16, Table 17,
Table 18, Table 20, Table 35, Table 37, Table 39, Table 40.
Updated Equation 29.
Added Figure 8, Figure 9, Figure 10 and Figure 29.
Updated Figure 26, Figure 27, Figure 28, Figure 31, Figure 32,
Figure 35, Figure 36, Figure 45.
Changed Figure 46.
16-Oct-2014
01-Oct-2015
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Changes
DocID026142 Rev 3
STPM32, STPM33, STPM34
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