Supertex inc. HV7620 40MHz, 32-Channel Serial to Parallel Converter with Push-Pull Outputs General Description Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► HVCMOS® technology 5.0V logic and 12V supply rail Output voltage up to +200V Low power level shifting Source/sink current minimum 50mA 40MHz equivalent data rate Latched data outputs Forward and reverse shifting options (DIR pin) Chip select Polarity function The HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. The device has 4 parallel 8-bit shift registers permitting data rates four times the speed of one. The data is clocked in simultaneously on all four data inputs with a single clock. Data is shifted in on a low to high transition of the clock. The latches and control logic perform the output enable function. The DIR pin causes clockwise (CW) shifting of the data when connected to VDD1, and counterclockwise (CCW) shifting when connected to LVGND. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. Data is stored in the latches when LE is low. The current source on the logic inputs provides active pull up when the input pins are open. Functional Block Diagram LE DINA DOUTA CLK 8-Bit Shift Register QA1 8 DINB DOUTB DIR 8-Bit Latches ≈ ≈ POL ≈ 8-Bit Shift Register QB1 8 8-Bit Latches ≈ ≈ HVOUTA1 HVOUTB1 HVOUTC1 QA8 HVOUTD1 BLB DINC DOUTC ≈ QB8 BLC 8-Bit Shift Register QC1 8 8-Bit Latches ≈ ≈ BLD 8-Bit Shift Register QD1 8 ≈ QC8 DIND DOUTD Doc.# DSFP-HV7620 C112213 BLA CS 8-Bit Latches QD8 ≈ ≈ HVOUTA8 HVOUTB8 HVOUTC8 HVOUTD8 Supertex inc. www.supertex.com HV7620 Pin Configuration Ordering Information / Availability Part Number Package Option Packing HV7620PG-G 64-Lead PQFP (3-sided) 66/tray 64 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings 1 Parameter 64-Lead PQFP (3-sided) Value Supply voltage, VDD1 -0.5V to +14V Supply voltage, VDD2 -0.5V to +14V Supply voltage, VPP -0.5V to +225V Product Marking Top Marking -2.0V to VDD1 + 2.0V Logic input levels Continuous total power dissipation (top view) Storage temperature range LLLLLLLLLL YYWW CCCCCCCC AAA 1200mW 1 Operating temperature range HV7 6 2 0 PG -40°C to +85°C L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging Package may or may not include the following marks: Si or -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 64-Lead PQFP (3-sided) Typical Thermal Resistance Notes: 1. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. Package θja 64-Lead PQFP 41OC/W Recommended Operating Conditions Sym Parameter Min Max Units VDD1 Logic supply voltage 4.5 VDD2 V VDD2 12V supply voltage 10.8 13.2 V VPP High voltage supply voltage 50 200 V VIH High-level input voltage VDD1 -0.5V VDD1 V VIL Low-level input voltage 0 0.5 V fCLK Clock frequency VDD1 = 5.0V - 10 MHz VDD1 = 12V - 5 MHz TA Operating temperature range -40 +85 °C IOD Allowable pulsed current through output diodes1 - 500 mA IGND(VPP) Allowable pulsed VPP or HVGND current1 - 16 A VPP(SLEW) Slew rate of VPP - 340 V/µs Notes: 1. The current pulse width = 500ns, duty cycle = 5%. Doc.# DSFP-HV7620 C112213 2 Supertex inc. www.supertex.com HV7620 DC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted, VDD1 = 5.0V, VDD2 = 12V, VPP = 200V and Tj = 25°C) Sym Parameter Min Max Units Conditions IDD1 VDD1 supply current - 5.0 mA fCLK = 10MHz IDD2 VDD2 supply current - 20 mA VDD2 = 13.2V, fCLK = 10MHz IPP High voltage supply current - 2.0 mA All outputs high or low IDD1Q Quiescent VDD1 supply current - 100 µA All input = VDD1 IDD2Q Quiescent VDD2 supply current - 100 µA All input = VDD1 VOH High-level output HVOUT 185 - Data OUT VDD -1 - VOL Low-level output HVOUT - 20 Data OUT - 1.0 IIH High-level logic input current - 1.0 µA VIN = VDD1 IIL Low-level logic input current - -10 µA VIN = 0V -1.0 1.0 V --- VGG HVGND to LVGND voltage difference V V IO = -50mA IO = -100µA IO = +50mA IO = +100µA AC Electrical Characteristics (Logic signal inputs and data inputs have tr, tf ≤ 5ns. VDD1 = 5.0V or 12V, VDD2 = 12V, VPP = 200V and Tj = 25°C) Sym Min Max VDD1 = 5.0V - 10 VDD1 = 12V - 5.0 Clock width high or low 40 - ns --- tSU Data set-up time before clock rises 20 - ns --- tH Data hold time after clock rises 20 - ns --- tON, tOFF Time from latch enable to HVOUT - 275 ns CL = 15pF fCLK tWL, tWH Parameter Clock frequency Units Conditions MHz Per register, CL = 15pF tWLE LE pulse width 25 - ns --- tDLE Delay time clock to LE low to high 50 - ns --- tSLE LE set-up time before clock rises 20 - ns --- tDLF, tDLN BL or CS low to high to HVOUT - 250 ns --- tCOF, tCON Clock to HVOUT - 275 ns --- ns CL = 15pF ns CL = 15pF tDLH Delay time clock to data low to high VDD1 = 5.0V - 250 VDD1 = 12V - 100 tDHL Delay time clock to data high to low VDD1 = 5.0V - 250 VDD1 = 12V - 100 Doc.# DSFP-HV7620 C112213 3 Supertex inc. www.supertex.com HV7620 Input and Output Equivalent Circuits VDD2 VDD1 VDD1 VPP INPUT DATA OUT LVGND HVGND LVGND Logic Inputs HVOUT Logic Data Output High Voltage Outputs Switching Waveforms VIH 50% Data Input CLK 50% Data Valid tSU 50% tH tf 90% 50% 50% tWL VIL tr 10% 10% tWH 90% 50% VIH VIL VOH tDLH 50% VOL Data Output VOH 50% tDHL VIH 50% 50% LE VOL VIL tDLE tWLE tCOF HVOUT 90% tOFF tSLE VOH VOL VOH 10% HVOUT tON VOL tCON BLA, BLB, BLC, BLD, or CS VIH 50% VIL tDLF 90% 10% HVOUT tDLN Doc.# DSFP-HV7620 C112213 4 VOH VOL Supertex inc. www.supertex.com HV7620 Function Table Inputs Function HVOUT DINA DINB DINC DIND CLK LE DIR BLA BLB BLC BLD CS POL A B C D All O/P High X X X X X X X X X X X L L H H H H All O/P Low X X X X X X X X X X X L H L L L L “A” Outputs Low X X X X X X X L X X X X H L * * * Normal Polarity X X X X X X X H H H H H H No Inversion Outputs Inverted X X X X X X X H H H H H L Inversion Transparent Mode H L L L ↑ H X H H H H H H Data Stored X X X X X L X H H H H H H Shift CWA X X X X ↑ H H H H H H H X AN → AN+1 BN → BN+1 CN → CN+1 DN → DN+1 Shift CCWB X X X X ↑ H L H H H H H X AN → AN-1 BN → BN-1 CN → CN-1 DN → DN-1 † H L L L Stored data Notes: H = High level, L = Low level, X = Irrelevant, ↑ = Low to high transition. * = Dependent on previous stage’s state before the last CLK ↑ for last LE high. † = BLB, BLC and BLD will have similar effect on their respective output. Power-up sequence: 1. GND (HV, LV) 2. VDD1 3. VDD2 4. VPP 5. Logic Input Signals To power down reverse the sequence above. Doc.# DSFP-HV7620 C112213 5 Supertex inc. www.supertex.com HV7620 Pin Function Pin # Function Pin # Function Pin # Function Pin # Function 1 HVGND 17 HVOUTB5 33 CS 49 HVOUTB4 2 VPP 18 HVOUTA5 34 DOUTB 50 HVOUTA4 3 HVOUTD8 19 VPP 35 DINB 51 HVOUTD3 4 HVOUTC8 20 HVGND 36 DINA 52 HVOUTC3 5 HVOUTB8 21 HVGND 37 DOUTA 53 HVOUTB3 6 HVOUTA8 22 VDD2 38 CLK 54 HVOUTA3 7 HVOUTD7 23 BLC 39 BLA 55 HVOUTD2 8 HVOUTC7 24 BLD 40 BLB 56 HVOUTC2 9 HVOUTB7 25 LE 41 VDD1 57 HVOUTB2 10 HVOUTA7 26 DOUTD 42 LVGND 58 HVOUTA2 11 HVOUTD6 27 DIND 43 N/C 59 HVOUTD1 12 HVOUTC6 28 DINC 44 HVGND 60 HVOUTC1 13 HVOUTB6 29 DOUTC 45 HVGND 61 HVOUTB1 14 HVOUTA6 30 POL 46 VPP 62 HVOUTA1 15 HVOUTD5 31 LVGND 47 HVOUTD4 63 VPP 16 HVOUTC5 32 DIR 48 HVOUTC4 64 HVGND Doc.# DSFP-HV7620 C112213 6 Supertex inc. www.supertex.com HV7620 64-Lead PQFP (3-Sided) Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint D L3 D1 64 E1 E Note 1 (Index Area D1/4 x E1/4) 1 Note 2 e b θ1 Top View View B A A2 Seating Plane A1 L L1 L2 Gauge Plane θ Seating Plane View B Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The leads on this side are trimmed. Symbol Dimension (mm) A A1 A2 b MIN 2.80 0.25 2.55 0.30 NOM - - 2.80 - MAX 3.40 0.50 3.05 0.45 D D1 E E1 22.25 19.80 17.65 13.80 e L L1 L2 L3 θ 0.73 0O 0.80 1.95 0.25 0.55 22.50 20.00 17.90 14.00 0.88 3.5O BSC REF BSC REF 22.75 20.20 18.15 14.20 1.03 7O θ1 5O 16O Drawings not to scale. Supertex Doc. #: DSPD-64PQFPPG, Version A080812. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV7620 C112213 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com