Supertex inc. HV7224 40-Channel Symmetric Row Driver Features ►► HVCMOS technology ►► Symmetric row drive (reduces latent imaging in ACTFEL displays) ►► Output voltage up to +240V ►► Low power level shifting ►► Source/sink current minimum 70mA ►► Shift register speed 3.0MHz ►► Pin-programmable shift direction (DIR, SHIFT) ® General Description The HV7224 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. When the data reset pin (DRIOA/DRIOB) is at logic high, it will reset all the outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DRIOA/ DRIOB can be triggered at any time. The DIR and SHIFT pins control the direction of data shift through the device. When DIR is at logic high, DRIOA is the input and DRIOB is the output. When DIR is grounded, DRIOB is the input and the DRIOA is the output. See the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is loaded on the low to high transition of the clock. A logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. All outputs will be in High-Z state if OE is at logic high. Data output buffers are provided for cascading devices. Functional Block Diagram VPP OE POL VDD P Level Translator DRIOA HVOUT1 N SHIFT P CLK S/R Level Translator DIR N P DRIOB Level Translator GND Doc.# DSFP-HV7224 C072413 HVOUT2 HVOUT40 N Supertex inc. www.supertex.com HV7224 Pin Configuration Ordering Information Part Number Package Packing HV7224PG-G 64-Lead PQFP 66/Tray 64 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.0V Supply voltage , VPP -0.5V to +260V Logic input levels 1 64-Lead PQFP (3-sided) (top view) -0.5V to VDD + 0.5V Continuous total power dissipation1 Operating temperature range Storage temperature range Product Marking 1200mW Top Marking -40°C to +85°C H V 7224P G LLLLLLLLLL YYWW CCCCCCCC AAA -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging Package may or may not include the following marks: Si or 64-Lead PQFP (3-sided) Note: 1. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. Typical Thermal Resistance Package θja 44-Lead PLCC 37OC/W Recommended Operating Conditions Sym Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP High voltage supply1 0 240 V VIH High-level input voltage 0.7 VDD VDD V VIL Low-level input voltage 0 0.2VDD V fCLK Clock frequency - 3.0 MHz TA Operating free-air temperature -40 +85 °C IO High voltage output current - ±70 mA IOD Allowable pulsed current through output diode - ±300 mA Note: 1. Output will not switch at VPP = 0V. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Doc.# DSFP-HV7224 C072413 2 Supertex inc. www.supertex.com HV7224 DC Electrical Characteristics (over recommended operating conditions of VDD = 5.0V, VPP = 240V, and TA = 25°C unless noted) Sym Parameter Min Max Units Conditions - 10 mA fCLK = 3.0MHz, VDD = 5.5V - 2.0 mA All outputs low or High-Z - 4.0 mA One output high1 - 100 µA All VIN = GND or VDD HVOUT 190 - V IO = -70mA DATA OUT 4.5 - V IO = -100µA HVOUT - 50 V IO = +70mA DATA OUT - 0.5 V IO = +100µA IDD VDD supply current IPP VPP supply current IDDQ Quiescent VDD supply current VOH High-level output VOL Low-level output IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V P-channel -80 - mA --- N-channel 75 - mA --- Min Max Units Conditions - 3.0 MHz Per register, CL = 15pF Clock width high or low 150 - ns --- tSUD Data set-up time before clock rises 50 - ns --- tHD Data hold time after clock rises 50 - ns --- tSUC HVOUT delay from clock rises (Hi-Z to H or L) - 1.0 µs CL = 330pF // RL = 10kΩ tSUE HVOUT delay from Output Enable falls - 600 ns CL = 330pF // RL = 10kΩ tHC HVOUT delay from clock rises (H or L to Hi-Z) - 2.0 µs CL = 330pF // RL = 10kΩ tHE HVOUT delay from Output Enable rises - 600 ns CL = 330pF // RL = 10kΩ tDHL Delay time clock to data output falls* - 250 ns CL = 15pF tDLH Delay time clock to data output rises* - 250 ns CL = 15pF tONF HVOUT fall time - 2.0 µs CL = 330pF // RL = 10kΩ tONR HVOUT rise time - 2.0 µs CL = 330pF // RL = 10kΩ tPOW POL pulse width 3.0 - µs --- tOEW Output Enable pulse width 3.0 - µs --- SR Slew rate, VPP - 45 V/µs ISAT HVOUT saturation current Note: 1. Only one output can be turned on at a time. AC Electrical Characteristics (VDD = 5.0V and TA = 25°C) Sym fCLK tWH, tWL Parameter Clock frequency One active output driving 4.7nF load Note: * The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is equal to tWH. Doc.# DSFP-HV7224 C072413 3 Supertex inc. www.supertex.com HV7224 Input and Output Equivalent Circuits VDD VPP VDD DATA OUT GND (Logic) GND (Logic) Logic Inputs GND (Power) Logic Data Output Switching Waveforms HVOUT High Voltage Outputs 1/fCLK tWL tWH VIH CLK Data Reset Input (DRIOA/DRIOB) 50% tSUD tHD 50% Data Valid 50% 50% 50% VIH Data Valid 50% tDLH Data Reset Output (DRIOA/DRIOB) HVOUT (POL = H) VIL tDHL 50% 50% tSUC VIL VOL tHC tONR 90% 90% VOH VOH 10% High Impedance High Impedance 90% HVOUT (POL = L) 10% tONF tSUC 10% VOL tHC tPOW 50% POL VIH 50% VIL tOEW OE 50% 50% tSUE tHE VIH VIL tONR 10% High Impedance HVOUT High Impedance 90% 10% tSUE 10% VOL tHE tONF Doc.# DSFP-HV7224 C072413 VOH 90% 90% HVOUT 4 Supertex inc. www.supertex.com HV7224 Function Table I/O Relations Inputs HV Outputs CLK DIR S/R DATA POL OE O/P HIGH X X H H L H O/P OFF X X L X L HIGH-Z O/P LOW X X H L L L O/P OFF X X X X H All O/P HIGH-Z Notes: H = logic high level, L = logic low level, X = irrelevant Data input (DRIO) loaded on the low-to-high transition of the clock. Only one active output can be set at a time. Output Sequence Operation Table DIR SHIFT Data Reset In Data Reset Out HVOUT # Sequence L L DRIOB DRIOA1 40 → 1 H L DRIOA DRIOB2 1 → 40 L H DRIOB DRIOA1 20 → 1 → 40 → 21 H H DRIOA DRIOB2 21 → 40 → 1 → 20 Direction* Notes: * Reference to package outline or chip layout drawing. 1. DRIOA is DRIOB delayed by 40 clock pulses. 2. DRIOB is DRIOA delayed by 40 clock pulses. Doc.# DSFP-HV7224 C072413 5 Supertex inc. www.supertex.com HV7224 Pin Description - 64-Lead PQFP (3-sided) (PG) Option A Pin # Function Pin # Function Pin # Function Pin # Function 1 HVOUT1/40 17 HVOUT17/24 33 N/C 49 HVOUT25/16 2 HVOUT2/39 18 HVOUT18/23 34 DRIOB 50 HVOUT26/15 3 HVOUT3/38 19 HVOUT19/22 35 OE 51 HVOUT27/14 4 HVOUT4/37 20 HVOUT20/21 36 N/C 52 HVOUT28/13 5 HVOUT5/36 21 VPP 37 POL 53 HVOUT29/12 6 HVOUT6/35 22 N/C 38 N/C 54 HVOUT30/11 7 HVOUT7/34 23 GND (Power) 39 VDD 55 HVOUT31/10 8 HVOUT8/33 24 GND (Logic) 40 N/C 56 HVOUT32/9 9 HVOUT9/32 25 DIR 41 GND (Logic) 57 HVOUT33/8 10 HVOUT10/31 26 VDD 42 GND (Power) 58 HVOUT34/7 11 HVOUT11/30 27 CLK 43 N/C 59 HVOUT35/6 12 HVOUT12/29 28 N/C 44 VPP 60 HVOUT36/5 13 HVOUT13/28 29 SHIFT 45 HVOUT21/20 61 HVOUT37/4 14 HVOUT14/27 30 N/C 46 HVOUT22/19 62 HVOUT38/3 15 HVOUT15/26 31 DRIOA 47 HVOUT23/18 63 HVOUT39/2 16 HVOUT16/25 32 N/C 48 HVOUT24/17 64 HVOUT40/1 Note: Pin designation for DIR H/L, Shift = L Example: For DIR = H, pin 1 is HVOUT1 For DIR = L, pin 1 is HVOUT40 Pin Description - 64-Lead PQFP (3-sided) (PG) Option B Pin # Function Pin # Function Pin # Function Pin # Function 1 HVOUT20/21 17 HVOUT4/37 33 N/C 49 HVOUT36/5 2 HVOUT19/22 18 HVOUT3/38 34 DRIOB 50 HVOUT35/6 3 HVOUT18/23 19 HVOUT2/39 35 OE 51 HVOUT34/7 4 HVOUT17/24 20 HVOUT1/40 36 N/C 52 HVOUT33/8 5 HVOUT16/25 21 VPP 37 POL 53 HVOUT32/9 6 HVOUT15/26 22 N/C 38 N/C 54 HVOUT31/10 7 HVOUT14/27 23 GND (Power) 39 VDD 55 HVOUT30/11 8 HVOUT13/28 24 GND (Logic) 40 N/C 56 HVOUT29/12 9 HVOUT12/29 25 DIR 41 GND (Logic) 57 HVOUT28/13 10 HVOUT11/30 26 VDD 42 GND (Power) 58 HVOUT27/14 11 HVOUT10/31 27 CLK 43 N/C 59 HVOUT26/15 12 HVOUT9/32 28 N/C 44 VPP 60 HVOUT25/16 13 HVOUT8/33 29 SHIFT 45 HVOUT40/1 61 HVOUT24/17 14 HVOUT7/34 30 N/C 46 HVOUT39/2 62 HVOUT23/18 15 HVOUT6/35 31 DRIOA 47 HVOUT38/3 63 HVOUT22/19 16 HVOUT5/36 32 N/C 48 HVOUT37/4 64 HVOUT21/20 Note: Pin designation for DIR H/L, Shift = H Example: For DIR = H, pin 1 is HVOUT20 For DIR = L, pin 1 is HVOUT21 Doc.# DSFP-HV7224 C072413 6 Supertex inc. www.supertex.com HV7224 64-Lead PQFP (3-sided) Package Outline (PG) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint D L3 D1 64 E1 E Note 1 (Index Area D1/4 x E1/4) 1 Note 2 e b θ1 Top View View B A A2 Seating Plane A1 L L1 L2 Gauge Plane θ Seating Plane View B Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 Identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The leads on this side are trimmed. Symbol Dimension (mm) A A1 A2 b MIN 2.80 0.25 2.55 0.30 NOM - - 2.80 - MAX 3.40 0.50 3.05 0.45 D D1 E E1 22.25 19.80 17.65 13.80 e L L1 L2 L3 θ 0.73 0O 0.80 1.95 0.25 0.55 22.50 20.00 17.90 14.00 0.88 3.5O BSC REF BSC REF 22.75 20.20 18.15 14.20 1.03 7O θ1 5O 16O Drawings not to scale. Supertex Doc. #: DSPD-64PQFPPG, Version NR090608. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV7224 C072413 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com