SUPERTEX HV623PG

HV623
32-Channel 128-Level Amplitude Gray-Shade
Display Column Driver
Ordering Information
Package Option
Device
64-Lead 3-sided Plastic Gullwing
HV623
HV623PG
General Description
Features
The HV623 is a 32-channel driver IC for gray shade display use.
It is designed to produce varying output voltages between 3 and
80 volts. This amplitude modulation at the output is facilitated by
an external ramp voltage VR. See Theory of Operation for detailed
explanation.
5V CMOS inputs
Up to 80V modulation voltage
Capable of 128 levels of gray shading
20MHz data throughput rate
This device consists of a dual 16-bit shift registers, 32 data latches
and comparators, and control logic to preform 128 levels of gray
shading. There are 7 bits of data inputs. Data is shifted through the
shift registers at both edges of the clock, resulting a data transfer
rate of twice of the shift clock frequency. When the DIR pin is high,
CSI/CSO is the input/output for the chip select pulse. When DIR
is low, CSI/CSO is the output/input for the chip select pulse. The
DIR = HIGH also allows the HV623 to shift data in the counterclockwise direction when viewed from the top of the package.
When the DIR pin is low, data is shifted in the clockwise direction.
32 outputs per device (can be cascaded)
Pin-programmable shift direction (DIR)
D/A conversion cycle time is 32µs
Diodes in output structure allow usage
in energy recovery systems
Integrated HVCMOS® technology
Available in 3-sided 64-lead gullwing package
The output circuitry allows the energy which is stored in the output
capacitance to be returned to VPP through the body diode of the
output transistor.
Absolute Maximum Ratings
Supply voltage, VDD1
-0.5V to +7.5V
VPP1
-0.5V to +90V
Supply voltage,
Logic input
levels1
Ground current 2
-0.5 to VDD + 0.5V
1.5A
Continuous total power dissipation3
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
1W
-40°C to +70°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 70°C at 22.2mW/°C.
12-122
HV623
Electrical Characteristics (at TA = 25°C, over operating conditions unless otherwise specified)
Low-Voltage DC Characteristics (Digital)
Symbol
Parameter
Min
Typ1
Max
Units
12
20
mA
fSC = 10MHz
fCC = 8MHz
100
µA
All VIN = 0V, VDD = max
Conditions
IDD
VDD supply current
IDDQ
Quiescent VDD supply current
IIH
High-level input current
1.0
50
µA
VIH = VDD
IIL
Low-level input current
-1.0
-50
µA
VIL = 0V
CIN2
Input capacitance (data, LC, SC, CC)
15
pF
VIN = 0V, f = 1MHz
IOH
High-level output current
-2
mA
VDD = 4.5V
IOL
Low-level output current
2
mA
VDD = 4.5V
Notes
1. All typical values are at VDD = 5.0V.
2. Guaranteed by design.
Low-Voltage DC Characteristics (Analog)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
IDD
VDD supply current
100
µA
fSC =10MHz
fCC = 8MHz
IDDQ
Quiescent VDD supply current
100
µA
All VIN = 0V, VDD = max
Max
Units
High-Voltage Bias Circuit for Output Variation Control
Symbol
IPP
Parameter
Min
VPP supply current for bias circuit
Typ
2
mA
Conditions
Depending on external
bias circuit, see Table 1.
High-Voltage DC Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Conditions
IAOH
High-voltage analog output source current
See Performance Curves
mA
VPP = 80V
See test circuit
IAOL
High-voltage analog output sink current
See Performance Curves
mA
VPP = 80V, VDD = 4.5V
VAO = 2V
∆VO
Maximum delta voltage between high voltage outputs
of the same level
±0.2
V
At all gray levels
Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
4.5
5.0
5.5
V
4.5
5.0
VDD
Low-voltage digital supply voltage
VDD
Low-voltage analog supply voltage
5.5
V
VIH
High-level input voltage (analog and digital)
VDD -1
VDD
V
VIL
Low-level input voltage (analog and digital)
0
1
V
VBIAS
IPP control circuit bias voltage
-2
VCTL
IPP control circuit control voltage
2
V
VPP
High-voltage supply
VR
Ramp voltage
fSC
Shift clock operating frequency (at VDD = 5.5V)
TA
Operating free-air temperature
0
0
-0.3
80
V
0
VPP -2
V
10.2
MHz
70
°C
-40
Notes:
Power-up sequence should be the following:
1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
Power-down sequence should be the reverse of the above.
12-123
V
4. Apply VPP.
HV623
Electrical Characteristics
AC Characteristics (VDD = 5.5V, TA = 25°C)
Logic Timing
Symbol
Parameter
Min
Typ
Max
Units
fSC
Shift clock operating frequency
10.2
MHz
fDIN
Data-in frequency
20.4
MHz
tSS
CSI/CSO pulse to shift clock setup time
40
ns
tHS
CSI/CSO pulse to shift clock hold time
0
ns
tWA
CSI pulse width
49
ns
tDS
Data to shift clock setup time
20
ns
tDH
Data to shift clock hold time
0
ns
tWD
Data-in pulse width
24
ns
tWLC
Load count pulse width
98
ns
tDLCR
Load count to ramp delay
1
µs
tDRCC1
Ramp to count clock delay
0.47
µs
tDSL
Shift clock to load count delay time
tCSC
Shift clock cycle time
98
ns
tWSC
Shift clock pulse width
49
ns
tCCC
Count clock cycle time
98
ns
tWCC
Count clock pulse width
49
ns
98
Conditions
ns
Note 1: Count clock starts counting after 0.47µs min. This is equivalent to a time duration for a linear ramp VR to ramp from 0 to 3V, assuming the minimum value of TRR,
ramp size time of 12µs for VR = 80V.
VRAMP Timing
Symbol
Parameter
Min
Typ
Max
Units
tCR
Cycle time of ramp signal
15
µs
tRR
Ramp rise time
12
µs
tHR2
Ramp hold time
2
15
µs
tFR
Ramp fall time
TBD
3
µs
Conditions
Note 2: The maximum ramp hold time may be longer than 15 µs, but the output voltage HVOUT will droop due to leakage.
Table 1:
Schemes to control IPP bias current, typical IPP
Option 1
VCTL
Option 2
VBIAS
VCTL
RCTL
IPP
VBIAS
VCTL
RCTL
IPP
(V)
(V)
(Ω)
(mA)
(V)
(V)
(Ω)
(mA)
0
0.1
56K
2
-1.0
0
56K
4
0
1.0
56K
7
-2.0
0
56K
5.5
HV623
VCTL
+-
RCTL
RCTL
+-
12-124
VBIAS
HV623
Pin Definitions
Pin #
Name
Function
30-36
D1-D7
Inputs for binary-format parallel data.
26
SC (Shift Clock)
22
CSI (Chip
Select Input)
Input pin for the chip select pulse (when DIR is high).
Output pin for the chip select pulse (when DIR is low).
43
CSO (Chip
Select Output)
Input pin for the chip select pulse (when DIR is low).
Output pin for the chip select pulse (when DIR is high).
40
LC
(Load Count)
Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,
and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).
Also, the HVOUT will clear to zero after the load count is initiated.
42
Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock
rate (data rate = 20MHz max if clock rate = 10MHz max).
CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.
18, 47
VR
High-voltage ramp input for charging the output stage hold capacitors (CH).
This input can be linear or non-linear as desired.
28
DIR
When this pin is connected to VDD, input data is shifted in ascending order,
i.e., corresponding to HVOUT1 to HVOUT32. When connected to LVGND, input data is shifted
in descending order, i.e., corresponding to HVOUT32 to HVOUT1.
27, 38
LVGND
This is ground for the logic section.
HVGND and LVGND should be connected together externally.
17, 48
HVGND
This is ground for the high-voltage (output) section.
HVGND and LVGND should be connected together externally.
19, 45
VPP
1-16
49-64
HVOUT1HVOUT32
This input biases the output source followers.
High-voltage outputs.
21
VDD (Analog)
Low-voltage analog supply voltage.
29
VDD (Digital)
Low-voltage digital supply voltage.
24
VCTL
Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (VCTL = 2V for a
particular panel). The combination of VCTL and RCTL will reduce the output voltage variation to less than
±0.2V of delta voltage between high voltage outputs of the same level at all gray levels.
25
RCTL
Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs
(RCTL = 56KΩ for a particular panel). See VCTL function above.
Input and Output Equivalent Circuits
VDD
VDD
Data Out
Input
GND
(Logic)
GND
(Logic)
Logic Data Output
Logic Inputs
12-125
HV623
Output Stage Detail
Test Circuit
High-voltage Analog Output Source Current (IAOH)
For gray shade #1 (000 0000)
VPP = 80V
VR
VR
VPP
HV623
+
–
CH
70V
Q1
VCTL
Internal
Logic
&
Bias
Circuit
RCTL
HVOUT
+
Output
Stage
Logic
0V
1KΩ Vtst
-
HVOUT
10KΩ
LVGND
Q2
1.
2.
3.
4.
5.
HVGND
Set HVOUT = Low.
Apply VPP = 80V.
Apply a step voltage of 70V at VR (slew rate = 4.1V/µs).
Measure voltage across the 1KΩ resistor.
V
Output source current can be calculated by using tst .
1K
Functional Block Diagram
See Output Stage Detail
GND
VR VPP
L/E
Data
Latches
L/E
Data
Latches
L/E
Data
Latches
L/E
Data
Latches
1
2
7
7
7
RS
F/F
Output
Stage
HVOUT 1
RS
F/F
Output
Stage
HVOUT 2
7
RS
F/F
Output
Stage
HVOUT 31
Latches and 7
Comparators
RS
F/F
Output
Stage
HVOUT 32
Latches and
Comparators
Latches and
Comparators
7
RCTL
Load
Dual
16-bit
Shift Registers
Count
VCTL
31
32
7
7
Latches and
Comparators
Clear
7
Count
SC
SC
Reset
Counter
Load
DIR
I/O
Buffers
I/O
Buffers
Shift
Clock
Buffer
CSI
CSO
SC
SC = Shift Clock
CSI = Chip Select Input
LC = Load Count
CSO = Chip Select Output
CC = Count Clock
*Strobe = twice the SC frequency
Data In
Buffers
D7
Clear
Pulse
Generator
D1
12-126
CC
Counter
Load
Count
Buffer
Count
Clock
Buffer
LC
CC
HV623
Typical Panel Connections
Data Bus
(7)
DIR = LOW
VR, VPP
LVGND, HVGND,
SC, LC, CC, CSO
32
1
32
1
32
1
1
32
Display Panel
(Example)
1
VR, VPP
LVGND, HVGND,
SC, LC, CC, CSI
32
1
32
DIR = HIGH
Data Bus
(7)
Gray Scale Voltage
Gray Shade Decoding Scheme
D7
D6
D5
D4
D3
D2
D1
128
1
1
1
1
1
1
1
127
1
1
1
1
1
1
0
126
1
1
1
1
1
0
1
125
1
1
1
1
1
0
0
124
1
1
1
1
0
1
1
123
1
1
1
1
0
1
0
122
1
1
1
1
0
0
1
121
1
1
1
1
0
0
0
(000 0000)
HVOUT
(111 1111)
01 2
7
0
0
0
0
1
1
0
6
0
0
0
0
1
0
1
5
0
0
0
0
1
0
0
4
0
0
0
0
0
1
1
3
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
VR
HVOUT
HVOUT
HVOUT
• • •
Clock Cycle
12-127
127
HVOUT
Gray Scale Voltage
Shade Number
HV623
Function Table
Sequence
Function
DIR
Data-In
(D1 - D7)
1
Shift Data
from HVOUT1 to 32
H
H
L
2
Shift Data
from HVOUT32 to 1
L
H
L
3
Load Shift Register
X
X
4
Load Counter
X
X
5
Counting/Voltage
Conversion
X
X
CSI
CSO
Shift
Clock
Output
Output
Pre-define by 1 or 2
Load
Count
Count
Clock
VR
HVOUT
L
L
L
L
H
L
L
L
L
H
L
L
L
-
L
L
-
Initiates
VRAMP
-
L
L
L
Timing Diagrams
(a) Basic System Timing
t CR
t RR
VR
Chip Select
Input (CSI)
Load
Last
Device
Load
Second
Device
Load
First
Device
t FR
t HR
Chip Select
Output (CSO)
Shift Clock
(SC)
↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓
Data In
(D1 - D7)
↑ ↓
↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓
Data from Data Bus (See Detailed Timing)
t DLCR
Load Count*
(LC)
Count Clock
(CC)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
2
3
4
5
128
1
2
3
4
5
128
HV OUT
*HVOUT will clear to zero with load count.
12-128
HV623
(b) Detailed Device Timing
LOADING LAST DEVICE
NEXT LOADING CYCLE
t WA
Chip Select
Input (CSI)
t HS
t SS
t CSC
Shift Clock
(SC)
SC 2
SC 1
Data
(D1-D7)
DATA
SET 1
DATA
SET 2
SC 16
DATA
SET 3
t DH
DATA
SET 31
SC 1
DATA
SET 32
t WD
SC 16
DATA
SET 31
DATA
SET 1
t DSL
t DS
t WLC
Load Count
(LC)
t WCC
t CCC
Count Clock
(CC)
Count
Clock 1
Count
Clock 128
t DRCC
t DLCR
VR
3V
0V
Typical Performance Curves
Sink Output Characteristics
15
12
12
IO (milliamperes)
IO (milliamperes)
Source Output Characteristics
15
9
6
3
9
6
3
1
0
0
1
2
3
4
5
6
7
8
0
VGS Volts
1
2
3
4
5
VGS Volts
12-129
6
7
8
80V
HV623
Pin Configuration
64-Pin PG Package
Pin Function
1
HVOUT 1
2
HVOUT 2
3
HVOUT 3
4
HVOUT 4
5
HVOUT 5
6
HVOUT 6
7
HVOUT 7
8
HVOUT 8
9
HVOUT 9
10
HVOUT 10
11
HVOUT 11
12
HVOUT 12
13
HVOUT 13
14
HVOUT 14
15
HVOUT 15
16
HVOUT 16
17
HVGND
18
VR
19
VPP
20
N/C
21
VDD (Analog)*
22
CSI
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin
Function
45
N/C
46
VCTL
47
RCTL
SC (Shift Clock) 48
LVGND
49
DIR
50
VDD (Digital)*
51
D7
52
53
D6
54
D5
55
D4
56
D3
57
D2
58
D1
59
N/C
LVGND
60
N/C
61
LC (Load Count) 62
N/C
63
CC (Count Clock) 64
CSO
N/C
Package Outlines
Function
VPP
N/C
VR
HVGND
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
1
64
Index
top view
24
41
25
40
3-Sided Plastic QFP 64-pin Gullwing Package
* Analog VDD and digital VDD may be connected
separately for better noise immunity.
Theory of Operation
Loading Data from Data Bus
The HV623 has two primary functions:
Here is the full data-entry sequence:
1) Loading data from the data bus and,
1) The microcontroller puts data on the bus (7 bits)
2) Gray-shade conversion
(converting latched data to output voltages).
2) To enter the data into the 32 sets of 7 latches on the first chip,
the shift clock rises. This positive transition is combined with
the CSI pulse and is generated only once to strobe the data into
the first set of latches. (These latches eventually send data to
the HVOUT1). The data on the bus then changes, the shift clock
falls, and this negative transition is combined with the CSI
pulse, which is now propagated internally, to strobe the new
data into the next set of 7 latches (which will end up as
HVOUT2). This internal CSI pulse therefore runs at twice the
shift clock rate.
Since the device was developed initially for flat panel displays, the
operation will be described in terms that pertain to that technology. As shown by the Typical Drive Scheme, several HV623
packages are mounted at the top and bottom of a display panel.
Data exists on a 7-bit bus (adjacent PC board traces) at top and
bottom. The D1 through D7 inputs of each chip take data from the
bus when either a CSI or CSO pulse is present at the chip. These
pulses therefore act as a combination CHIP SELECT and LOCATION STROBE. Because of the way the chip HVOUT pins are
sequenced, data on the bus at the bottom of the display panel will
be entered into the left-most chip as HVOUT1, HVOUT2, etc. up to
HVOUT32. The CSI pulse will accomplish this with DIR = High.
3) When the last set of 7 latches in the first chip has been loaded
(HVOUT32), the CSI pulse leaves chip 1 and enters chip 2. The
exit pin is called CSO and the chip 2 entry pin is CSI . For chips
at the top of the panel things are reversed: DIR is low, entry pins
are CSO and exit pins are CSI , because the data-into-latches
sequence is in descending order, HVOUT32 down to HVOUT1.
4) The buses may of course be separate, and data can be strobed
in on an interleaved basis, etc., but those complications will be
left to systems designers.
12-130
HV623
Output Voltage Variation
When data has been loaded into all 32 outputs of all chips (top and
bottom of the display panel), the load count pin is pulsed. On its
rising transition, all output levels are reset to zero and all the data
in the input latches is transferred to a like number of comparator
latches, (thus leaving the data latches ready to receive new data
during the following operations). After the transfer, the load count
pin is brought low. This transition begins the events that convert
the binary data into a gray-shade level.
The output voltage of the HV623 is determined by the logic and
the ramp voltage VR. It is possible that the output voltage may be
coupled to an unacceptable level due to its adjacent outputs
through the panel. In order to solve this problem, internal logic
(refer to Output Stage Detail) is integrated in the IC to minimize
the effect.
Two external pins VCTL and RCTL allow the feasibility to control the
current flowing through Q2. The VCTL pin is connected to a voltage
source and the RCTL pin is connected to ground through a resistor
(2V and 56KΩ are used for a particular panel). The internal bias
circuit will drive the resistor to a voltage level that is equal to the
VCTL voltage at steady state through an operational amplifier. The
current flowing through Q1 and Q2 will be limited to VCTRL/RCTRL.
This combination of VCTL and RCTL will reduce the output voltage
variation to less than ±0.2V of delta voltage for each gray shade,
independent of its adjacent output voltages.
Gray-shade Conversion
1) The COUNT CLOCK is started. An external signal is applied
to the COUNT CLOCK pin, causing the counter on each chip
to increment from binary 000 0000 to 111 1111 (0 to 127).
2) At the same time, the VR voltage is applied to all chips, via
charging transistors, causing the HOLD CAPACITOR (CH) on
each output to experience a rise in voltage.
3) The logic control compares the count in the comparator latch
to the count clock. The gate voltage of Q1 and the output
voltage HVOUT will ramp up at the same rate as VR.
4) Once VR has reached the maximum voltage, then all the pixels
will be at the final value. (See Output Gray Scale Voltage.)
12-131