CY24272
Rambus® XDR™ Clock Generator
with Zero SDA Hold Time
Rambus® XDR™ Clock Generator with Zero SDA Hold Time
Features
■
Device Comparison
Meets Rambus® Extended Data Rate (XDR™) clocking
requirements
CY24271
CY24272
■
25 ps typical cycle-to-cycle jitter
❐ –135 dBc/Hz typical phase noise at 20 MHz offset
SDA hold time = 300 ns
(SMBus compliant)
SDA hold time = 0 ns
(I2C compliant)
■
100 or 133 MHz differential clock input
■
300–667 MHz high speed clock support
RRC = 200 typical
(Rambus standard drive)
RRC = 295 minimum
(Reduced output drive)
■
Quad (open drain) differential output drivers
■
Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
■
Spread Aware™
■
2.5 V operation
■
28-pin TSSOP package
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
/BYPASS
EN
EN
RegA
CLK0
CLK0B
EN
RegB
CLK1
Bypass
MUX
CLK1B
EN
RegC
PLL
REFCLK,REFCLKB
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
Cypress Semiconductor Corporation
Document Number: 001-42414 Rev. *D
•
SDA
ID0
ID1
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 7, 2016
CY24272
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
PLL Multiplier ............................................................... 4
Input Clock Signal ....................................................... 4
Modes of Operation ..................................................... 5
Device ID and SMBus Device Address ....................... 6
SMBus Protocol ........................................................... 6
SMBus Data Byte Definitions ...................................... 6
Absolute Maximum Conditions ....................................... 8
DC Operating Conditions ................................................. 9
DC Electrical Specifications .......................................... 10
Thermal Resistance ........................................................ 10
AC Operating Conditions ............................................... 11
AC Electrical Specifications .......................................... 12
SMBus Timing Specification ......................................... 13
Document Number: 001-42414 Rev. *D
Test and Measurement Setup ........................................ 14
Signal Waveforms .......................................................... 15
Jitter ................................................................................. 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Drawing and Dimension ................................. 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC®Solutions ....................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Page 2 of 21
CY24272
Pin Configuration
Figure 1. 28-pin TSSOP pinout
VDDP
VSSP
ISET
VSS
REFCLK
VDDC
VSSC
SCL
SDA
EN
ID0
ID1
/BYPASS
CY24272
REFCLKB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
VSS
CLK2
CLK2B
VSS
CLK3
CLK3B
VDD
Pin Definitions
28-pin TSSOP
Pin No.
Name
I/O
1
VDDP
PWR
Description
2
VSSP
GND
3
ISET
I
4
VSS
GND
5
REFCLK
I
6
REFCLKB
I
7
VDDC
PWR
2.5 V power supply for core
8
VSSC
GND
Ground
9
SCL
I
10
SDA
I
SMBus data (connect to SMBus)
11
EN
I
Output Enable (CMOS signal)
12
ID0
I
Device ID (CMOS signal)
13
ID1
I
Device ID (CMOS signal)
14
/BYPASS
I
REFCLK bypassing PLL (CMOS signal)
15
VDD
PWR
Power supply for outputs
16
CLK3B
O
Complement clock output
17
CLK3
O
Clock output
18
VSS
GND
19
CLK2B
O
20
CLK2
O
21
VSS
GND
22
VDD
PWR
Power supply for outputs
23
CLK1B
O
Complement clock output
24
CLK1
O
25
VSS
GND
2.5 V power supply for phased lock loop (PLL)
Ground
Set clock driver current (external resistor)
Ground
Reference clock input (connect to clock source)
Complement of reference clock (connect to clock source)
SMBus clock (connect to SMBus)
Ground
Complement clock output
Clock output
Ground
Clock output
Ground
Document Number: 001-42414 Rev. *D
Page 3 of 21
CY24272
Pin Definitions (continued)
28-pin TSSOP
Pin No.
Name
I/O
Description
26
CLK0B
O
Complement clock output
27
CLK0
O
Clock output
28
VDD
PWR
Power supply for outputs
Functional Overview
PLL Multiplier
Table 1 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.
Default multiplier at power up is 4.
Table 1. PLL Multiplier Selection
Register
MULT2
MULT1
MULT0
0
0
0
Frequency Multiplier
Output Frequency (MHz)
REFCLK = 100 MHz [1], REFSEL = 0
REFCLK = 133 MHz [1], REFSEL = 1
300
400
3
0
0
1
4
0
1
0
5
500
0
1
1
6
600
–
1
0
0
Reserved
–
–
1
0
1
9/2
450
600
1
1
0
Reserved
–
–
1
1
1
15/4
375
500
Input Clock Signal
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions on page 9 and AC Operating
Conditions on page 11.
400
[2]
–
667
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in Figure 2, provide a reference
voltage VTH at the REFCLKB pin. This determines the proper trip
point of REFCLK. For the range of VTH specified in DC Operating
Conditions on page 9, the outputs also meet the DC and AC
Operating Conditions tables.
Figure 2. Differential and Single-Ended Clock Inputs
Supply Voltage
REFCLKB
VTH
Input
REFCLK
Input
REFCLK
XDR Clock Generator
Differential Input
XDR Clock Generator
Single-ended Input
Notes
1. Output frequencies shown in Table 1 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.
2. Default PLL multiplier at power up.
Document Number: 001-42414 Rev. *D
Page 4 of 21
CY24272
Modes of Operation
Mode (EN = high, /BYPASS = low). There is an option reserved
for vendor test. Disabled outputs are set to High Z.
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 3 on page 6 shows selection from one to all four of the
outputs, the Outputs Disabled Mode (EN = low), and Bypass
At power up, the SMBus registers default to the last entry in Table
4 on page 7. The value at RegTest is 0. The values at RegA,
RegB, RegC, and RegD are all ‘1’. Thus, all outputs are
controlled by the logic applied to EN and /BYPASS.
Table 2. SMBus Device Addresses for CY24272
XCG
Device
0
1
2
3
Operation
Write
Five Most Significant Bits
D8
Read
D9
Write
DA
Read
DB
Write
DC
Read
DD
Write
DE
Read
DF
Document Number: 001-42414 Rev. *D
8-bit SMBus Device Address Including Operation
Hex Address
1
1
0
1
ID1
ID0
0
0
0
1
1
0
1
1
1
WR# / RD
0
1
0
1
0
1
0
1
Page 5 of 21
CY24272
Table 3. Modes of Operation for CY24272
EN
/BYPASS RegTest
X
RegA
RegB
RegC
RegD
CLK0/CLK0B
CLK1/CLK1B
CLK2/CLK2B
CLK3/CLK3B
X
X
X
X
High Z
High Z
High Z
High Z
X
REFCLK/
REFCLKB[3]
REFCLK/
REFCLKB
REFCLK/
REFCLKB
REFCLK/
REFCLKB
0
0
High Z
High Z
High Z
High Z
0
0
1
High Z
High Z
High Z
CLK/CLKB
0
1
0
High Z
High Z
CLK/CLKB
High Z
L
X
H
X
1
X
X
X
X
H
L
0
X
X
X
H
H
0
0
0
H
H
0
0
H
H
0
0
Reserved for Vendor Test
H
H
0
0
0
1
1
High Z
High Z
CLK/CLKB
CLK/CLKB
H
H
0
0
1
0
0
High Z
CLK/CLKB
High Z
High Z
H
H
0
0
1
0
1
High Z
CLK/CLKB
High Z
CLK/CLKB
H
H
0
0
1
1
0
High Z
CLK/CLKB
CLK/CLKB
High Z
H
H
0
0
1
1
1
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
H
0
1
0
0
0
CLK/CLKB
High Z
High Z
High Z
H
H
0
1
0
0
1
CLK/CLKB
High Z
High Z
CLK/CLKB
H
H
0
1
0
1
0
CLK/CLKB
High Z
CLK/CLKB
High Z
H
H
0
1
0
1
1
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
H
H
0
1
1
0
0
CLK/CLKB
CLK/CLKB
High Z
High Z
H
H
0
1
1
0
1
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
H
H
0
1
1
1
0
CLK/CLKB
CLK/CLKB
CLK/CLKB
High Z
H
0[4]
1[4]
1[4]
1[4]
1[4]
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
Device ID and SMBus Device Address
SMBus Data Byte Definitions
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation. Table 2 on page 5 shows the addresses
for four CY24272 devices on the same SMBus.
Three data bytes are defined for the CY24272. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
SMBus Protocol
The CY24272 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
The definition of Byte 2 is shown in Table 4 on page 7, Table 5
on page 7, and Table 6 on page 7. The upper five bits are the
revision numbers of the device and the lower three bits are the
ID numbers assigned to the vendor by Rambus.
DC specifications are modified to Rambus standard to support
1.8, 2.5, and 3.3 volt devices. Time out detection and packet
error protocol SMBus features are not supported.
Hold time for SDA is reduced relative to the CY24271, so that it
is compatible with I2C.
Notes
3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
4. Default mode of operation is at power up.
Document Number: 001-42414 Rev. *D
Page 6 of 21
CY24272
Table 4. Command Code 80h [5]
Bit
Register
POD
Type
Description
7
Reserved
0
RW
Reserved (no internal function)
6
MULT2
0
RW
PLL Multiplier Select (reference Table 1 on page 4)
5
MULT1
0
RW
4
MULT0
1
RW
3
RegA
1
RW
Clock 0 Output Select
2
RegB
1
RW
Clock 1 Output Select
1
RegC
1
RW
Clock 2 Output Select
0
RegD
1
RW
Clock 3 Output Select
Table 5. Command Code 81h [5]
Bit
Register
POD
Type
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
1
RW
Description
Reserved (no internal function)
Reserved (must be set to ‘1’ for proper operation)
2
REFSEL
0
RW
Reference Frequency Select (reference Table 1 on page 4)
1
Reserved
0
RW
Reserved (must be set to ‘0’ for proper operation)
0
RegTest
0
RW
Reserved (must be set to ‘0’ for proper operation)
Table 6. Command Code 82h [5]
Bit
Register
POD
7
Device
Revision
Number
?
RO
?
RO
?
RO
?
RO
?
RO
0
RO
1
1
RO
0
0
RO
6
5
4
3
2
Vendor ID
Type
Description
Contact factory for Device Revision Number information.
Rambus assigned Vendor ID Code
Note
5. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 1 on page 4 for PLL multipliers and Table 3 on page 6 for clock output selections.
Document Number: 001-42414 Rev. *D
Page 7 of 21
CY24272
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.6
V
Core Supply Voltage
–0.5
4.6
V
PLL Supply Voltage
–0.5
4.6
V
VDD
Clock Buffer Supply Voltage
VDDC
VDDP
VIN
Input Voltage (SCL and SDA)
Relative to VSS
–0.5
4.6
V
Input Voltage
(REFCLK/REFCLKB)
Relative to VSS
–0.5
VDD + 1.0
V
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
V
Non-functional
–65
150
°C
0
70
°C
–
150
°C
2000
–
V
TS
Temperature, Storage
TA
Temperature, Operating Ambient Functional
TJ
Temperature, Junction
Functional
ESDHBM
ESD Protection (Human Body
Model)
MIL-STD-883, Method 3015
Document Number: 001-42414 Rev. *D
Page 8 of 21
CY24272
DC Operating Conditions
Parameter
Description
Condition
Min
Max
Unit
VDDP
Supply Voltage for PLL
2.5 V ± 5%
2.375
2.625
V
VDDC
Supply Voltage for Core
2.5 V ± 5%
2.375
2.625
V
VDD
Supply Voltage for Clock Buffers 2.5 V ± 5%
2.375
2.625
V
VIHCLK
Input High Voltage,
REFCLK/REFCLKB
0.6
0.95
V
VILCLK
Input Low Voltage,
REFCLK/REFCLKB
–0.15
+0.15
V
VIXCLK[6]
Crossing Point Voltage,
REFCLK/REFCLKB
200
550
mV
VIXCLK[6]
Difference in Crossing Point
Voltage, REFCLK/REFCLKB
–
150
mV
VIH
Input Signal High Voltage at ID0,
ID1, EN, and /BYPASS
1.4
2.625
V
VIL
Input Signal Low Voltage at ID0,
ID1, EN, and /BYPASS
–0.15
0.8
V
VIH,SM
Input Signal High Voltage at SCL
and SDA[7]
1.4
3.465
V
VIL,SM
Input Signal Low Voltage at SCL
and SDA
–0.15
0.8
V
VTH[8]
Input Threshold Voltage for
single-ended REFCLK
0.35
0.5 × VDD
V
VIH,SE
Input Signal High Voltage for
single-ended REFCLK
VTH + 0.3
2.625
V
VIL,SE
Input Signal Low Voltage for
single-ended REFCLK
–0.15
VTH – 0.3
V
TA
Ambient Operating Temperature
0
70
°C
Notes
6. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
7. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3 V, 2.5 V, or 1.8 V SMBus voltages.
8. Single-ended operation guaranteed only when 0.8 < (VIH,SE – VTH)/(VTH – VIL,SE) < 1.2.
Document Number: 001-42414 Rev. *D
Page 9 of 21
CY24272
DC Electrical Specifications
Parameter
Description
Min
Typ
Max
Unit
–
1.08
–
V
–
400
–
mV
0.85
–
–
V
0.98
1.0
1.02
V
–
–
85
mA
–
–
125
mA
6.8
7.0
7.2
25
–
–
mA
SDA output low voltage at test condition of
SDA output low current = 4 mA
–
–
0.4
V
IOL,SDA
SDA output low voltage at test condition of SDA voltage = 0.8 V
6
–
–
mA
IOZ
Current during High Z per pin at CLK[3:0], CLK[3:0]B
–
–
10
A
ZOUT
Output dynamic impedance when clock output signal is
at VOL = 0.9 V [16]
1000
–
–
[10]
VOX[9]
VCOS[9]
Differential output crossing point voltage
VOL,ABS
Absolute output low voltage at CLK[3:0], CLK[3:0]B[12]
VISET
Reference voltage for swing controlled current, IREF
IDD[13]
IDD[13]
Power Supply Current at 2.625V, fref = 100 MHz, and fout = 300 MHz
IOL/IREF
Ratio of output low current to reference current[14]
IOL,ABS
Minimum current at VOL,ABS[15]
VOL,SDA
Output voltage swing (peak-to-peak single-ended)
[11]
Power Supply Current at 2.625V, fref = 133 MHz, and fout = 667 MHz
Thermal Resistance
Parameter [17]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
28-pin TSSOP Unit
78
°C/W
17
°C/W
Notes
9. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
10. VOX is measured on external divider network.
11. VCOS = (clock output high voltage – clock output low voltage), measured on the external divider network.
12. VOL_ABS is measured at the clock output pins of the package.
13. This range of SCL and SDA input high voltage enables the CY24272 for use with 3.3 V, 2.5 V, or 1.8 V SMBus voltages.
14. IREF is equal to VISET/RRC.
15. Minimum IOL,ABS is measured at the clock output pin with RRC = 266 ohms or less.
16. ZOUT is defined at the output pins as (0.94 V – 0.90 V)/(I0.94 – I0.90) under conditions specified for IOL, ABS.
17. These parameters are guaranteed by design and are not tested.
Document Number: 001-42414 Rev. *D
Page 10 of 21
CY24272
AC Operating Conditions
The AC operating conditions follow. [18]
Parameter
tCYCLE,IN
Description
Condition
REFCLK, REFCLKB input cycle REFSEL = 0, /BYPASS = High
time
REFSEL = 1, /BYPASS = High
/BYPASS = Low
[19]
Min
Max
Unit
9
11
ns
7
8
ns
4
–
ns
–
185
ps
tJIT,IN(cc)
Input Cycle to Cycle Jitter
tDCIN[20]
Input Duty Cycle
Over 10,000 cycles
40%
60%
tCYCLE
tRIN / tFIN
Rise and Fall Times
Measured at 20%–80% of input voltage for
REFCLK and REFCLKB inputs
175
700
ps
tRIN / tFIN
Rise and Fall Times Difference
–
150
ps
Modulation Index for triangular
modulation
–
0.6
%
Modulation Index for
non-triangular modulation
–
0.5[22]
%
fMIN[21]
Input Frequency Modulation
30
33
kHz
tSR,IN
Input Slew Rate (measured at
20%–80% of input voltage) for
REFCLK
1
4
V/ns
CIN,REF
Capacitance at REFCLK inputs
–
7
pF
CIN,CMOS
Capacitance at CMOS inputs
–
10
pF
fSCL
SMBus clock frequency input in
SCL pin
DC
100
kHz
pMIN
[21]
Notes
18. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
19. Jitter measured at crossing points and is the absolute value of the worst case deviation.
20. Measured at crossing points.
21. If input modulation is used; input modulation is allowed but not required.
22. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Document Number: 001-42414 Rev. *D
Page 11 of 21
CY24272
AC Electrical Specifications
The AC Electrical specifications follow. [23]
Parameter
tCYCLE
tJIT(cc)
Description
Clock Cycle time[24]
Jitter over 1-6 clock cycles at 400–635 MHz
[25]
Min
Typ
Max
Unit
1.25
–
3.34
ns
–
25
40
ps
Jitter over 1-6 clock cycles at 638–667 MHz
–
25
30
ps
L20
Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz
(In addition, device must not exceed
L(f) = 10log[1+(50×106/f)2.4] –138 for f = 1 MHz to 100 MHz except
for the region near f = REFCLK/Q where Q is the value of the internal
reference divider.)
–
–135
–128
dBC/Hz
tJIT(hper,cc)
Cycle-to-cycle duty cycle error at 400–635 MHz
–
25
40
ps
Cycle-to-cycle duty cycle error at 636–667 MHz
–
25
30
ps
tSKEW
Drift in tSKEW when ambient temperature varies between 0 °C and
70 °C and supply voltage varies between 2.375 V and 2.625 V.[26]
–
–
15
ps
DC
Long term average output duty cycle
45%
50
55%
tCYCLE
tEER,SCC
PLL output phase error when tracking SSC
–100
–
100
ps
tCR,tCF
Output rise and fall times at 400–667 MHz (measured at 20%–80%
of output voltage)
–
150
–
ps
tCR,CF
Difference between output rise and fall times on the same pin
of the single device (20%–80%) of 400–667 MHz[27]
–
–
100
ps
Notes
23. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
24. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 667 MHz, respectively. For spread spectrum modulated differential or
single-ended REFCLK, the output clock tracks the modulation of the input.
25. Output short term jitter spec is the absolute value of the worst case deviation.
26. tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. tSKEW is the change in tSKEW when the
operating temperature and supply voltage change.
27. tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.
Document Number: 001-42414 Rev. *D
Page 12 of 21
CY24272
SMBus Timing Specification
Parameter
Description
Min
Max
Units
FSMB
SMBus Operating Frequency
10
100
kHz
TBUF
Bus free time between Stop and Start Condition
4.7
–
s
THD:STA
Hold time after (Repeated) Start Condition.
After this period, the first clock is generated.
4.0
–
s
TSU:STA
Repeated Start Condition setup time
4.7
–
s
TSU:STO
Stop Condition setup time
4.0
–
s
THD:DAT
Data Hold time
0
–
ns
TSU:DAT
Data Setup time
250
–
ns
TTIMEOUT
Detect clock low timeout
–
–
Not
supported
TLOW
Clock low period
4.7
–
s
THIGH
Clock high period
4.0
50
s
TLOW:SEXT
Cumulative clock low extend time (slave device)
–
25
ms
CY24272
doesn’t
extend
TLOW:MEXT
Cumulative clock low extend time (master device)
–
10
ms
TF
Clock/Data Fall Time
–
300
ns
TR
Clock/Data Rise Time
–
1000
ns
TPOR
Time in which a device must be operational after power on reset
–
500
ms
Document Number: 001-42414 Rev. *D
Page 13 of 21
CY24272
Test and Measurement Setup
Figure 3. Clock Outputs
Measurement
Point
VTS
R1
CLK
Swing Current
Control
R2
R T1
Z CH
R3 C
VT
R T2
S
Differential Driver
ISET
Measurement
Point
VTS
R RC
R1
CLKB
R2
Z CH
R3 C
VT
R T1
R T2
S
Table 7. Example External Resistor Values
and Termination Voltages for a 50 Channel (continued)
Table 7. Example External Resistor Values
and Termination Voltages for a 50 Channel
Parameter
Value
Unit
301
Parameter
Value
Unit
RT2
R1
33.0
CS
2700
pF
R2
18.0
RRC
432
R3
17.0
VTS
2.5
V
VT
1.2
V
RT1
60.4
Document Number: 001-42414 Rev. *D
Page 14 of 21
CY24272
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in Figure 4 on page 15. Both rise and fall times are defined
between the 20% and 80% points of the voltage swing, with the
swing defined as VH–VL.
Figure 5 on page 15 shows the definition of the output crossing
point. The nominal crossing point between the complementary
outputs is defined as the 50% point of the DC voltage levels.
There are two crossing points defined: Vx+ at the rising edge of
CLK and Vx– at the falling edge of CLK. For some waveforms,
both Vx+ and Vx– are below Vx,nom (for example, if tCR is larger
than tCF).
Figure 4. Input and Output Waveforms
VH
80%
V (t)
20%
VL
tF
tR
Figure 5. Crossing Point Voltage
CLK
Vx+
Vx.nom
Vx-
CLKB
Document Number: 001-42414 Rev. *D
Page 15 of 21
CY24272
Jitter
requirements apply rising edges of the CLK signal. Figure 7 on
page 16 shows the definition of cycle-to-cycle duty cycle error
(tDC,ERR). Cycle-to-cycle duty cycle is defined as the difference
between tPW+ (high times) of adjacent differential clock cycles.
Equal requirements apply to tPW-, low times of the differential
click cycles.
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms. Figure 6
on page 16 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle jitter
is the difference between cycle times of adjacent cycles. Equal
Figure 6. Cycle-to-cycle Jitter
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles
Figure 7. Cycle-to-cycle Duty-cycle Error
CLK
CLKB
tPW-(i)
tCYCLE,(i)
tPW+(i)
tPW-(i+1)
tPW+(i+1)
tCYCLE,(i+1)
tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)
Document Number: 001-42414 Rev. *D
Page 16 of 21
CY24272
Ordering Information
Part Number
Package Type
Product Flow
Pb-free
CY24272ZXC
28-pin TSSOP
Commercial, 0 °C to 70 °C
CY24272ZXCT
28-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
Ordering Code Definitions
CY 24272 ZX
C
T
T = Tape and Reel
Temperature Range:
C = Commercial
Package Type:
ZX = 28-pin TSSOP (Pb-free)
Base Device Part Number
Company ID: CY = Cypress
Document Number: 001-42414 Rev. *D
Page 17 of 21
CY24272
Package Drawing and Dimension
Figure 8. 28-pin TSSOP (4.40 mm Body) Z28.173/ZZ28.173 Package Outline, 51-85120
51-85120 *D
Document Number: 001-42414 Rev. *D
Page 18 of 21
CY24272
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
ESD
Electrostatic Discharge
°C
degree Celsius
PLL
Phase Locked Loop
Hz
hertz
TSSOP
Thin Shrunk Small Outline Package
kHz
kilohertz
XDR
Extended Data Rate
MHz
megahertz
Document Number: 001-42414 Rev. *D
Symbol
Unit of Measure
µs
microsecond
µA
microampere
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 19 of 21
CY24272
Document History Page
Document Title: CY24272, Rambus® XDR™ Clock Generator with Zero SDA Hold Time
Document Number: 001-42414
Rev.
ECN No.
Issue Date
Orig. of
Change
**
1749003
See ECN
KVM /
AESA
New data sheet.
*A
3175899
02/17/2011
BASH
Added Ordering Code Definitions under Ordering Information.
Updated Package Drawing and Dimension.
Added Acronyms and Units of Measure.
Updated to new template.
*B
4299246
03/05/2014
CINM
Updated Package Drawing and Dimension:
spec 51-85120 – Changed revision from *B to *C.
Updated to new template.
Completing Sunset Review.
*C
4581659
11/28/2014
AJU
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Drawing and Dimension:
spec 51-85120 – Changed revision from *C to *D.
*D
5279278
06/07/2016
PSR
Updated Absolute Maximum Conditions:
Removed ØJA parameter and its details.
Added Thermal Resistance.
Updated to new template.
Document Number: 001-42414 Rev. *D
Description of Change
Page 20 of 21
CY24272
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-42414 Rev. *D
Rambus is a registered trademark, and XDR is a trademark, of Rambus Inc.
Revised June 7, 2016
Page 21 of 21