CY8C29466, CY8C29666:Automotive - Extended Temperature PSoC® Programmable System-on-Chip

CY8C29466, CY8C29666
Automotive – Extended Temperature
PSoC® Programmable System-on-Chip
Features
■
AEC qualified
■
Powerful Harvard-Architecture processor
❐ M8C processor speeds up to 12 MHz
❐ Two 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 4.75 V to 5.25 V
❐ Extended temperature range: –40 °C to +125 °C
■
■
■
■
■
Additional system resources
2
❐ I C™ master, slave, or multi-master operation up to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full featured in-circuit emulator (ICE) and
programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128 K bytes trace memory
❐ Complex events
❐ C Compilers, assembler, and linker
Advanced peripherals (PSoC® blocks)
❐ 12 Rail-to-Rail analog PSoC blocks provide:
• Up to 14-Bit analog-to-digital converters (ADCs)
• Up to 9-Bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGA)
• Programmable filters and comparators
❐ 16 digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Up to four full-duplex or eight half-duplex UARTs
• Multiple SPI masters or slaves
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
Precision, programmable clocking
❐ Internal ±4% 24 MHz oscillator
❐ High accuracy 24 MHz with optional 32.768 kHz crystal
and phase locked loop (PLL)
❐ Optional external oscillator, up to 24 MHz
❐ Internal low speed, low power oscillator for Watchdog and
Sleep functionality
Logic Block Diagram
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
SROM
Global Analog Interconnect
Flash 32K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Flexible on-chip memory
❐ 32K bytes flash program storage,
100 erase/write cycles
❐ 2K bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block Array
Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull up, pull down, high Z, strong, or open drain drive modes
on all GPIO
[1]
❐ Up to 12 analog inputs on GPIO
❐ Four 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIOs
Analog
Block Array
Analog
Input
Muxing
Digital
Clocks
Two
Multiply
Accums.
POR and LVD
Decimator
I2C
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Note
1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the
PSoC Technical Reference Manual for more details
Cypress Semiconductor Corporation
Document Number: 38-12026 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 16, 2015
CY8C29466, CY8C29666
Contents
PSoC Functional Overview .............................................. 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
28-pin Part Pinout ........................................................ 9
48-pin Part Pinout ...................................................... 10
Registers ......................................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Document Number: 38-12026 Rev. *N
Operating Temperature ............................................. 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 22
Packaging Information ................................................... 29
Thermal Impedances ................................................. 30
Capacitance on Crystal Pins ..................................... 30
Solder Reflow Specifications ..................................... 30
Development Tool Selection ......................................... 31
Software .................................................................... 31
Development Kits ...................................................... 31
Evaluation Tools ........................................................ 31
Device Programmers ................................................. 31
Accessories (Emulation and Programming) .............. 32
Ordering Information ...................................................... 32
Ordering Code Definitions ......................................... 32
Reference Information ................................................... 33
Acronyms Used ......................................................... 33
Units of Measure ....................................................... 33
Numeric Naming ........................................................ 33
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC® Solutions ...................................................... 35
Cypress Developer Community ................................. 35
Technical Support ..................................................... 35
Page 2 of 35
CY8C29466, CY8C29666
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU utilizes an interrupt controller with 25
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep Timer and Watch Dog Timer (WDT).
■
PWMs with Dead Band (8- and 16-bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
Full or Half-Duplex 8-bit UART with selectable parity (up to 4
Full-Duplex or 8 Half-Duplex)
■
SPI master and slave (up to 8 total)
■
I2C master, slave, or multi-master
■
Cyclical Redundancy Checker/Generator (16 bit)
■
IrDA (up to 4)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
Figure 1. Digital System Block Diagram
Port 5
DIGITAL SYSTEM
Row Input
Configuration
Digital PSoC Block Array
Row 0
DBB00
DCB02
DCB03
4
8
8
8
Row 1
DBB10
DBB11
DCB12
4
DCB13
4
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
DBB30
DBB31
DCB32
4
DCB33
4
GIE[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
Row 3
GIO[7:0]
Document Number: 38-12026 Rev. *N
DBB01
4
Row Output
Configuration
The Digital System is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations include
those listed here.
To Analog
System
Row Output
Configuration
The Digital System
Port 0
Row Output
Configuration
PSoC GPIOs provide connection to the CPU, digital resources,
and analog resources of the device. Each pin’s drive mode may
be selected from eight options, allowing great flexibility in
external interfacing. Every pin also has the capability to generate
a system interrupt.
Port 1
Port 2
To System Bus
Digital Clocks
From Core
Memory includes 32K of Flash for program storage and 2K of
SRAM for data storage. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±4% over temperature and voltage. A low power 32 kHz internal
low speed oscillator (ILO) is provided for the Sleep Timer and
WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate
24 MHz system clock using a PLL. The clocks, together with
programmable clock dividers (as a System Resource), provide
the flexibility to integrate almost any timing requirement into the
PSoC device.
Port 3
Port 4
Row Input
Configuration
The PSoC architecture, as illustrated in the Logic Block Diagram
on page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global buses allow all the device resources to be combined into
a complete custom system. The PSoC CY8C29x66 family can
have up to six I/O ports that connect to the global digital and
analog interconnects, providing access to 16 digital blocks and
12 analog blocks.
PWMs (8- and 16-bit)
Row Input
Configuration
The PSoC programmable system-on-chip family consists of
many devices with on-chip controllers. These devices are
designed to replace multiple traditional microcontroller unit
(MCU)-based system components with one, low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, as well as programmable
interconnects. This architecture enables the user to create
customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
■
Row Input
Configuration
PSoC Functional Overview
GOE[7:0]
GOO[7:0]
Page 3 of 35
CY8C29466, CY8C29666
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are as follows:
■
ADCs (up to 4, with 6- to 14-bit resolution, selectable as
Incremental, Delta-Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain up to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain up to
93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 30 mA drive as a PSoC
Core resource)
■
1.3 V reference (as a System Resource)
■
DTMF Dialer
■
Correlators
■
Peak Detectors
■
Many other topologies possible
Analog blocks are provided in columns of three, which includes
one Continuous Time (CT) and two Switched Capacitor (SC)
blocks, as shown in Figure 2.
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The Analog System
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12026 Rev. *N
Page 4 of 35
CY8C29466, CY8C29666
Additional System Resources
■
System Resources, some of which have been previously listed,
provide additional capability useful for complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are given below:
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multiplier
with 32-bit accumulate to assist in both general math as well
as digital filters.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR (Power On Reset) circuit
eliminates the need for a system supervisor.
■
An internal 1.3 V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog
blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet
is highlighted in Table 1.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
CY8C29x66[2]
up to 64
4
16
12
4
4
CY8C27x43
up to 44
2
8
12
4
4
CY8C24x94
64
1
4
48
2
2
CY8C24x23A[2]
CY8C23x33
CY8C21x34[2]
SRAM
Size
Flash
Size
12
2K
32K
12
256 Bytes
16K
6
1K
16K
up to 24
1
4
12
2
2
6
256 Bytes
4K
up to
1
4
12
2
2
4
256 Bytes
8K
up to 28
1
4
28
0
2
4[3]
512 Bytes
8K
256 Bytes
4K
512 Bytes
8K
CY8C21x23
16
1
4
8
0
2
4[3]
CY8C20x34
up to 28
0
0
28
0
0
3[3, 4]
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense.
Document Number: 38-12026 Rev. *N
Page 5 of 35
CY8C29466, CY8C29666
Getting Started
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
covers a wide variety of topics and skill levels to assist you in
your designs.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
CYPros Consultants
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
Document Number: 38-12026 Rev. *N
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Page 6 of 35
CY8C29466, CY8C29666
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
■
Built-in debugger
Online Help System
■
In-circuit emulation
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this allows you to use more than 100 percent of PSoC's
resources for an application.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
Code Generation Tools
1. Select User Modules.
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
2. Configure User Modules.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
Select User Modules
Document Number: 38-12026 Rev. *N
3. Organize and Connect.
4. Generate, Verify, and Debug.
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Page 7 of 35
CY8C29466, CY8C29666
Configure User Modules
Generate, Verify, and Debug
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information you may need to
successfully implement your design.
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Document Number: 38-12026 Rev. *N
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events. These include
monitoring address and data bus values, memory locations, and
external signals.
Page 8 of 35
CY8C29466, CY8C29666
Pinouts
The automotive CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
28-pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Type
Digital Analog
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
Power
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1[2]
P1[4]
P1[6]
XRES
Input
I
I
I
I/O
I/O
I
Power
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
I/O
16
17
18
19
Pin
Name
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[5].
Ground connection.
Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA[5].
Figure 3. CY8C29466 28-pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VRef).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
Note
5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12026 Rev. *N
Page 9 of 35
CY8C29466, CY8C29666
48-pin Part Pinout
Table 3. 48-pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Type
Digital Analog
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
Pin
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
VSS
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Power
VSS
25
I/O
P1[0]
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
I
I
I
I/O
I/O
I
Description
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output
Analog column mux input
Figure 4. CY8C29666 48-pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
Direct switched capacitor block input
Direct switched capacitor block input
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
Ground connection
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C serial clock (SCL)
I2C serial data (SDA)
Crystal input (XTALin), I2C serial clock (SCL),
ISSP-SCLK[6]
Ground connection
I2C SDA, P1[5]
P1[3]
XTALin, I2C SCL, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VREF
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], I2C SDA, XTALout
Crystal output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA[6]
Optional external clock (EXTCLK) input
Active high external reset with internal
pull-down
Direct switched capacitor block input
Direct switched capacitor block input
External analog ground (AGND)
External voltage reference (VREF)
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output
Analog column mux input
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
Note
6. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12026 Rev. *N
Page 10 of 35
CY8C29466, CY8C29666
Registers
Register Conventions
Register Mapping Tables
This section lists the the registers of the automotive CY8C29x66
PSoC device. For detailed register information, reference the
PSoC Technical Reference Manual.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
The register conventions specific to this section are listed in the
following table.
Table 4. Abbreviations
Convention
R
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 38-12026 Rev. *N
Page 11 of 35
CY8C29466, CY8C29666
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
Addr (0, Hex) Access
Name
00
RW
DBB20DR0
01
RW
DBB20DR1
02
RW
DBB20DR2
03
RW
DBB20CR0
04
RW
DBB21DR0
05
RW
DBB21DR1
06
RW
DBB21DR2
07
RW
DBB21CR0
08
RW
DCB22DR0
09
RW
DCB22DR1
0A
RW
DCB22DR2
0B
RW
DCB22CR0
0C
RW
DCB23DR0
0D
RW
DCB23DR1
0E
RW
DCB23DR2
0F
RW
DCB23CR0
10
RW
DBB30DR0
11
RW
DBB30DR1
12
RW
DBB30DR2
13
RW
DBB30CR0
14
RW
DBB31DR0
15
RW
DBB31DR1
16
RW
DBB31DR2
17
RW
DBB31CR0
18
DCB32DR0
19
DCB32DR1
1A
DCB32DR2
1B
DCB32CR0
1C
DCB33DR0
1D
DCB33DR1
1E
DCB33DR2
1F
DCB33CR0
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
DBB10DR0
30
#
ACB00CR3
DBB10DR1
31
W
ACB00CR0
DBB10DR2
32
RW
ACB00CR1
DBB10CR0
33
#
ACB00CR2
DBB11DR0
34
#
ACB01CR3
DBB11DR1
35
W
ACB01CR0
DBB11DR2
36
RW
ACB01CR1
DBB11CR0
37
#
ACB01CR2
DCB12DR0
38
#
ACB02CR3
DCB12DR1
39
W
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 38-12026 Rev. *N
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 12 of 35
CY8C29466, CY8C29666
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
Addr (1,Hex) Access
Name
00
RW
DBB20FN
01
RW
DBB20IN
02
RW
DBB20OU
03
RW
04
RW
DBB21FN
05
RW
DBB21IN
06
RW
DBB21OU
07
RW
08
RW
DCB22FN
09
RW
DCB22IN
0A
RW
DCB22OU
0B
RW
0C
RW
DCB23FN
0D
RW
DCB23IN
0E
RW
DCB23OU
0F
RW
10
RW
DBB30FN
11
RW
DBB30IN
12
RW
DBB30OU
13
RW
14
RW
DBB31FN
15
RW
DBB31IN
16
RW
DBB31OU
17
RW
18
DCB32FN
19
DCB32IN
1A
DCB32OU
1B
1C
DCB33FN
1D
DCB33IN
1E
DCB33OU
1F
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
ALT_CR1
DCB02IN
29
RW
CLK_CR2
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
DBB10FN
30
RW
ACB00CR3
DBB10IN
31
RW
ACB00CR0
DBB10OU
32
RW
ACB00CR1
33
ACB00CR2
DBB11FN
34
RW
ACB01CR3
DBB11IN
35
RW
ACB01CR0
DBB11OU
36
RW
ACB01CR1
37
ACB01CR2
DCB12FN
38
RW
ACB02CR3
DCB12IN
39
RW
ACB02CR0
DCB12OU
3A
RW
ACB02CR1
3B
ACB02CR2
DCB13FN
3C
RW
ACB03CR3
DCB13IN
3D
RW
ACB03CR0
DCB13OU
3E
RW
ACB03CR1
3F
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 38-12026 Rev. *N
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
RDI3RI
C8
RDI3SYN
C9
RDI3IS
CA
RDI3LT0
CB
RDI3LT1
CC
RDI3RO0
CD
RDI3RO1
CE
CF
GDI_O_IN
D0
GDI_E_IN
D1
GDI_O_OU
D2
GDI_E_OU
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
OSC_GO_EN
DD
OSC_CR4
DE
OSC_CR3
DF
OSC_CR0
E0
OSC_CR1
E1
OSC_CR2
E2
VLT_CR
E3
VLT_CMP
E4
E5
E6
E7
IMO_TR
E8
ILO_TR
E9
BDG_TR
EA
ECO_TR
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
CPU_F
F7
F8
F9
FLS_PR1
FA
FB
FC
FD
CPU_SCR1
FE
CPU_SCR0
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RL
RW
#
#
Page 13 of 35
CY8C29466, CY8C29666
Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C29x66 PSoC device. For the most up to date
electrical specifications, confirm that you have the most recent data sheet by visiting http://www.cypress.com.
Specifications are valid for –40 C  TA  125C and TJ  135C, except where noted.
Figure 5. Voltage versus CPU Frequency
5.25
lid ing
Va rat n
e io
Op eg
R
4.75
Vdd Voltage (V)
0
93 kHz
12 MHz
24 MHz
CPU Frequency
(nominal setting)
Document Number: 38-12026 Rev. *N
Page 14 of 35
CY8C29466, CY8C29666
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
TBAKETEMP
Bake Temperature
TBAKETIME
Bake Time
TA
Vdd
VIO
VIOZ
IMIO
ESD
LU
Min
–55
Typ
+25
–
125
See
package
label
Ambient Temperature with Power Applied
–40
Supply Voltage on Vdd Relative to Vss
–0.5
DC Input Voltage
Vss – 0.5
DC Voltage Applied to Tri-state
Vss – 0.5
Maximum Current into any Port Pin
–25
Electro Static Discharge Voltage
2000
Latch up Current
–
Max
+125
Units
Notes
°C Higher
storage
temperatures
reduce data retention time.
Recommended
storage
temperature is +25 °C ± 25 °C.
Storage temperatures above 65C
degrade
reliability.
Maximum
combined storage and operational
time at +125 °C is 7000 hours.
°C
–
See
package
label
72
Hours
–
–
–
–
–
–
–
+125
+6.0
Vdd + 0.5
Vdd + 0.5
+25
–
200
Typ
–
–
Max
+125
+135
°C
V
V
V
mA
V
mA
Human Body Model ESD.
Operating Temperature
Table 8. Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Document Number: 38-12026 Rev. *N
Min
–40
–40
Units
Notes
°C
°C The temperature rise from ambient
to junction is package specific. See
Thermal Impedances on page 30.
The user must limit the power
consumption to comply with this
requirement.
Page 15 of 35
CY8C29466, CY8C29666
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 9. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD
Supply Current
Min
4.75
–
Typ
–
8
Max
5.25
15
Units
V
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.[7]
–
6
16
A
ISBH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature[7]
–
6
100
A
ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal.[7]
–
8
18
A
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.[7]
Reference Voltage (Bandgap)
–
8
100
A
1.25
1.3
1.35
V
VREF
Notes
Conditions are –40 °C  TA  125 °C,
CPU=3 MHz, 48 MHz disabled.
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 0.366 kHz. Analog power = off.
Conditions are with internal low speed
oscillator active, –40 °C  TA  55 °C.
Analog power = off.
Conditions are with internal low speed
oscillator active, 55 °C < TA  125 °C.
Analog power = off.
Conditions are with properly loaded,
1 W max, 32.768 kHz crystal. –40 °C
 TA  55 °C. Analog power = off.
Conditions are with properly loaded, 1
W max, 32.768 kHz crystal. 55 °C <
TA  125 °C. Analog power = off.
Note
7. Standby current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 38-12026 Rev. *N
Page 16 of 35
CY8C29466, CY8C29666
DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 10. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull up Resistor
Pull down Resistor
High Output Level
Min
4
4
3.5
Typ
5.6
5.6
–
Max
8
8
–
Units
k
k
V
VOL
Low Output Level
–
–
0.75
V
IOH
High Level Source Current
10
–
–
mA
IOL
Low Level Sink Current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Document Number: 38-12026 Rev. *N
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25 V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]),
maximum 40 mA on odd port pins
(for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25 V
(maximum 100 mA on even port
pins (for example, P0[2], P1[4]),
maximum 100 mA on odd port pins
(for example, P0[3], P1[5])). 150
mA maximum combined IOL
budget.
VOH  Vdd–1.0 V, see the limitations of
the total current in the note for VOH
VOL  0.75 V, see the limitations of the
total current in the note for VOL
Gross tested to 1 A.
Package and pin dependent.
Temp = 25 °C.
Package and pin dependent.
Temp = 25 °C.
Page 17 of 35
CY8C29466, CY8C29666
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitors
(SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time (CT) PSoC blocks.
Table 11. DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value) Low Power
Input Offset Voltage (absolute value) Mid Power
Input Offset Voltage (absolute value) High Power
TCVOSOA Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
IEBOA
Input Capacitance (Port 0 Analog Pins)
CINOA
Min
–
–
–
–
–
–
Typ
1.6
1.3
1.2
7.0
200
4.5
Max
11
9
9
35.0
–
9.5
VCMOA
0.0
0.5
–
–
Vdd
Vdd –
0.5
80
–
–
–
–
–
–
–
V
V
V
–
–
–
0.2
0.2
0.5
V
V
V
150
300
600
1200
2400
4600
80
200
400
800
1600
3200
6400
–
A
A
A
A
A
A
dB
Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
GOLOA
Open Loop Gain
–
VOHIGHOA High Output Voltage Swing (worst case internal load)
Power = Low
Vdd – 0.2
Power = Medium
Vdd – 0.2
Power = High
Vdd – 0.5
VOLOWOA Low Output Voltage Swing (worst case internal load)
Power = Low
–
Power = Medium
–
Power = High
–
ISOA
Supply Current (including associated AGND buffer)
–
Power = Low, Opamp Bias = Low
–
Power = Low, Opamp Bias = High
–
Power = Medium, Opamp Bias = Low
–
Power = Medium, Opamp Bias = High
–
Power = High, Opamp Bias = Low
–
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
–
Document Number: 38-12026 Rev. *N
Units
Notes
mV
mV
mV
V/C
pA Gross tested to 1 A
pF
Package and pin
dependent. Temp = 25 °C.
V
The common-mode input
–
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the
characteristics of the
analog output buffer.
dB
Vss VIN (Vdd - 2.25) or
(Vdd – 1.25 V) VIN  Vdd
Page 18 of 35
CY8C29466, CY8C29666
DC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 12. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference voltage
range
LPC supply current
LPC voltage offset
Min
0.2
Typ
–
Max
Vdd – 1
Units
V
–
–
10
2.5
40
30
A
mV
Notes
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 13. DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
Description
Input Offset Voltage (Absolute Value)
Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
High Output Voltage Swing (Load = 32 to Vdd/2)
VOLOWOB
Low Output Voltage Swing (Load = 32 to Vdd/2)
ISOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
PSRROB
Document Number: 38-12026 Rev. *N
Min
–
–
0.5
–
0.5 x Vdd +
1.1
–
Typ
3
+6
–
1
–
Max
18
–
Vdd – 1.0
–
–
Units
mV
V/°C
V
W
V
–
0.5 x Vdd –
1.3
V
–
–
–
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Notes
Page 19 of 35
CY8C29466, CY8C29666
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
The guaranteed specifications for RefHI and RefLO are measured through the analog continuous time PSoC blocks. The power levels
for RefHI and RefLO refer to the analog reference control register. AGND is measured at P2[4] in AGND bypass mode. Each analog
continuous time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local
AGND buffer. Reference control power can be set to medium or high unless otherwise noted.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 14. DC Analog Reference Specifications
Symbol
VBG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Min
Bandgap Voltage Reference
1.25
AGND = Vdd/2[8]
Vdd/2 – 0.02
AGND = 2 x BandGap[8]
2.4
AGND = P2[4] (P2[4] = Vdd/2)[8]
P2[4] – 0.02
AGND = BandGap[8]
1.23
[8]
AGND = 1.6 x BandGap
1.98
AGND Column to Column Variation
(AGND=Vdd/2)[8]
0.035
[9]
RefHi = Vdd/2 + BandGap
Vdd/2 + 1.15
RefHi = 3 x BandGap[9]
3.65
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3 V)[9]
P2[6] + 2.4
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[9]
P2[4] + 1.24
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = P2[4] + P2[6] – 0.1
1.3 V)[9]
RefHi = 2 x BandGap[9]
2.4
[9]
RefHi = 3.2 x BandGap
3.9
RefLo = Vdd/2 - BandGap[9]
Vdd/2 – 1.45
RefLo = BandGap[9]
1.15
RefLo = 2 x BandGap – P2[6] (P2[6] = 1.3 V)[9]
2.4 – P2[6]
RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[9]
P2[4] – 1.45
RefLo = P2[4] – P2[6] (P2[4] = Vdd/2,
P2[4] – P2[6] – 0.1
P2[6] = 1.3 V)[9]
Typ
1.30
Vdd/2
2.6
P2[4]
1.3
2.08
Max
1.35
Vdd/2 + 0.02
2.8
P2[4] + 0.02
1.37
2.14
Units
V
V
V
V
V
V
0.000
Vdd/2 + 1.30
3.9
P2[6] + 2.6
P2[4] + 1.30
P2[4] + P2[6]
0.035
Vdd/2 + 1.45
4.15
P2[6] + 2.8
P2[4] + 1.36
P2[4] + P2[6] + 0.1
V
V
V
V
V
2.6
4.16
Vdd/2 – 1.3
1.30
2.6 – P2[6]
P2[4] – 1.3
P2[4] – P2[6]
2.8
4.42
Vdd/2 – 1.15
1.45
2.8 – P2[6]
P2[4] – 1.15
P2[4] – P2[6] + 0.1
V
V
V
V
V
V
V
V
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 15. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Min
–
–
Typ
12.24
80
Max
–
–
Units
k
fF
Notes
Notes
8. This specification is only valid when CT Block Power = High. AGND tolerance includes the offsets of the local buffer in the PSoC block.
9. This specification is only valid when Ref Control Power = High.
Document Number: 38-12026 Rev. *N
Page 20 of 35
CY8C29466, CY8C29666
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 16. DC POR and LVD Specifications
Symbol
Description
VPPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 10b
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
4.55
4.70
V
4.62
4.710
4.73
4.814
4.83
4.950
V
V
Notes
Vdd must be greater than or equal
to 2.5 V during startup, reset from
the XRES pin, or reset from
watchdog.
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 17. DC Programming Specifications
Symbol
Description
IDDP
Supply Current During Programming or Verify
VILP
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying VILP to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying VIHP to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)[10]
FlashENT Flash Endurance (total)[10, 11]
FlashDR
Flash Data Retention[12]
Min
–
–
Typ
15
–
Max
30
0.8
Units
mA
V
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
0.75
V
3.5
–
Vdd
V
100
51,200
15
–
–
–
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
Erase/write cycles per block.
Erase/write cycles.
Notes
10. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
11. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
12. Flash data retention based on the use condition of  7000 hours at TA  125 °C and the remaining time at TA  65 °C.
Document Number: 38-12026 Rev. *N
Page 21 of 35
CY8C29466, CY8C29666
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 18. AC Chip-Level Specifications
Symbol
FIMO24
FCPU1
F24M
F32K1
Description
Internal Main Oscillator Frequency for
24 MHz
CPU Frequency (5 V Vdd Nominal)
Digital PSoC Block Frequency
Internal Low Speed Oscillator
Frequency
Min
23.04[13]
Typ
24
Max
24.96[13]
0.09[13]
0
15
12
24
32
12.48[13]
24.96[14, 13]
64
Units
Notes
MHz Trimmed. Utilizing factory trim
values.
MHz
MHz
kHz This specification applies
when the ILO has been
trimmed.
kHz After a reset and before the
M8C processor starts to
execute, the ILO is not
trimmed.
kHz Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
MHz Is a multiple (x732) of crystal
frequency.
ps
ms
Refer to Figure 6 on page 23.
ms
Refer to Figure 7 on page 23.
ms
Refer to Figure 8 on page 23.
ms
F32KU
Internal Low Speed Oscillator (ILO)
Untrimmed Frequency
5
–
–
F32K2
External Crystal Oscillator
–
32.768
–
FPLL
PLL Frequency
–
23.986
–
Jitter24M2
TPLLSLEW
TPLLSLEWSLOW
TOS
TOSACC
24 MHz Period Jitter (PLL)
PLL Lock Time
PLL Lock Time for Low Gain Setting
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 200
ppm
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
Internal Low Speed Oscillator (ILO) Duty
Cycle
24 MHz Trim Step Size
24 MHz Period Jitter (IMO)
Peak-to-Peak
24 MHz Period Jitter (IMO) Root Mean
Squared
Maximum frequency of signal on row
input or row output.
Power Supply Slew Rate
–
0.5
0.5
–
–
–
–
–
1700
2800
800
10
50
2620
3800
–
10
40
20
100
–
50
50
–
–
60
80
ns
s
%
%
–
–
50
600
–
–
kHz
ps
Refer to Figure 9 on page 23.
–
–
600
ps
Refer to Figure 9 on page 23.
–
–
12.48[13]
MHz
–
–
250
V/ms
–
16
100
ms
Jitter32k
TXRST
DC24M
DCILO
Step24M
Jitter24M1P
Jitter24M1R
FMAX
SRPOWERUP
TPOWERUP
Time between end of POR state and
CPU code execution
Refer to Figure 10 on page 23.
Vdd slew rate during power
up.
Power up from 0 V.
Notes
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12026 Rev. *N
Page 22 of 35
CY8C29466, CY8C29666
Figure 6. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 7. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 8. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1P
Jitter24M1R
F 24M
Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F32K2
Document Number: 38-12026 Rev. *N
Page 23 of 35
CY8C29466, CY8C29666
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 19. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
2
2
9
9
Typ
–
–
–
27
22
Max
12.48[13]
22
22
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
10% - 90%
10% - 90%
10% - 90%
10% - 90%
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 20. AC Operational Amplifier Specifications
Symbol
SRROA
SRFOA
BWOA
Description
Rising Slew Rate (20% to 80%) of a 1 V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Falling Slew Rate (80% to 20%) of a 1 V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
Document Number: 38-12026 Rev. *N
Min
Typ
Max
Units
0.15
0.15
0.15
1.7
1.7
6.5
–
–
–
–
–
–
–
–
–
–
–
–
V/s
V/s
V/s
V/s
V/s
V/s
0.01
0.01
0.01
0.5
0.5
4.0
–
–
–
–
–
–
–
–
–
–
–
–
V/s
V/s
V/s
V/s
V/s
V/s
0.75
0.75
0.75
3.1
3.1
5.4
–
–
–
–
–
–
–
–
–
–
–
–
MHz
MHz
MHz
MHz
MHz
MHz
Notes
Page 24 of 35
CY8C29466, CY8C29666
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 38-12026 Rev. *N
0.01
0.1
Freq (kHz)
1
10
100
Page 25 of 35
CY8C29466, CY8C29666
AC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 21. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
s
Notes
 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 22. AC Digital Block Specifications
Function
Description
All
Functions
Maximum Block Clocking Frequency
Timer
Capture Pulse Width
Min
Typ
Max
Units
–
–
24.96[13]
MHz
50[15]
–
–
ns
MHz
MHz
Notes
Maximum Frequency, No Capture
–
–
24.96[13]
Maximum Frequency, With Capture
–
–
24.96[13]
50[15]
–
–
ns
Maximum Frequency, No Enable Input
–
–
24.96[13]
MHz
Maximum Frequency, Enable Input
–
–
24.96[13]
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[15]
–
–
ns
Disable Mode
50[15]
–
–
ns
Maximum Frequency
–
–
24.96[13]
MHz
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
24.96[13]
MHz
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
24.96[13]
MHz
SPIM
Maximum Input Clock Frequency
–
–
4.16[13]
MHz
SPIS
Maximum Input Clock Frequency
–
–
2.08[13]
MHz
Width of SS_ Negated Between
Transmissions
50[15]
–
–
ns
Transmitter
Maximum Input Clock Frequency
–
–
8.32[13]
MHz
Maximum baud rate at
1.04 Mbaud due to
8 × over clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.96[13]
MHz
Maximum baud rate at
3.12 Mbaud due to
8 × over clocking.
Counter
Dead Band
Enable Pulse Width
Kill Pulse Width:
Maximum data rate is
2.08 Mbps due to
2 × over clocking.
Note
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12026 Rev. *N
Page 26 of 35
CY8C29466, CY8C29666
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 23. AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1 V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1 V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1 V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1 V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1 Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
3
3
s
s
–
–
–
–
3
3
s
s
0.6
0.6
–
–
–
–
V/s
V/s
0.6
0.6
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 24. AC External Clock Specifications
Symbol
FOSCEXT
–
–
–
Description
Frequency
High Period
Low Period
Power Up IMO to Switch
Min
0.093
20.6
20.6
150
Typ
–
–
–
–
Max
24.24
–
–
–
Units
MHz
ns
ns
s
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 25. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TPRGH
TPRGC
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Total Flash Block Program Time (TERASEB + TWRITE),
Hot
Total Flash Block Program Time (TERASEB + TWRITE),
Cold
Document Number: 38-12026 Rev. *N
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
10
40
–
–
Max
20
20
–
–
8
40[10]
160[10]
50
100[10]
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ms
Notes
TJ  0 °C
–
–
200[10]
ms
TJ  0 °C
Page 27 of 35
CY8C29466, CY8C29666
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  TA  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 26. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Description
SCL Clock Frequency
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set Up Time for a Repeated START
Condition
Data Hold Time
Data Set Up Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and
START Condition
Pulse Width of spikes are suppressed by
the input filter.
Standard Mode
Min
Max
0
100[16]
4.0
–
Fast Mode
Min
Max
0
400[16]
0.6
–
Units
Notes
kHz
s
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
s
s
s
0
250
4.0
4.7
–
–
–
–
0
100[17]
0.6
1.3
–
–
–
–
s
ns
s
s
–
–
0
50
ns
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Notes
16. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly.
17. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C  250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12026 Rev. *N
Page 28 of 35
CY8C29466, CY8C29666
Packaging Information
This section illustrates the packaging specifications for the automotive CY8C29x66 PSoC device, along with the thermal impedances
and solder reflow for each package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Figure 15. 28-pin SSOP (210 Mils)
51-85079 *F
Document Number: 38-12026 Rev. *N
Page 29 of 35
CY8C29466, CY8C29666
Figure 16. 48-pin SSOP (300 Mils)
51-85061 *F
Thermal Impedances
Capacitance on Crystal Pins
Table 27. Thermal Impedances per Package
Typical JA
Package
Table 28. Typical Package Capacitance on Crystal Pins
[18]
Package
Package Capacitance
28-pin SSOP
94 °C/W
28-pin SSOP
2.8 pF
48-pin SSOP
69 °C/W
48-pin SSOP
3.3 pF
Solder Reflow Specifications
Table 29 shows the solder reflow temperature limits that must not be exceeded.
Table 29. Solder Reflow Specifications
Package
Maximum Peak Temperature
(TC)
Maximum Time above TC – 5 °C
28-pin SSOP
260 °C
30 seconds
48-pin SSOP
260 °C
30 seconds
Note
18. TJ = TA + Power × JA .
Document Number: 38-12026 Rev. *N
Page 30 of 35
CY8C29466, CY8C29666
Development Tool Selection
This section presents the development tools available for the
CY8C29x66 family.
Software
PSoC Designer
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for years. PSoC
Designer is available free of charge at http://www.cypress.com.
PSoC Designer comes with a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up to date information
on kit contents, descriptions, and availability.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store. The online store also has the most up to date information
on kit contents, descriptions, and availability.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3210-29X66 Evaluation Pod (EvalPod)
PSoC EvalPods are pods that connect to the ICE In-Circuit
Emulator (CY3215-DK kit) to allow debugging capability. They
can also function as a standalone device without debugging
capability. The EvalPod has a 28-pin DIP footprint on the bottom
for easy connection to development kits or other hardware. The
top of the EvalPod has prototyping headers for easy connection
to the device's pins. CY3210-29X66 provides evaluation of the
CY8C29x66 PSoC device family.
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
■
ICE-Cube Unit
■
28-pin PDIP Emulation Pod for CY8C29466-24PXI
■
28-pin CY8C29466-24PXI PDIP PSoC Device Samples (two)
■
PSoC Designer Software CD
■
ISSP Cable
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniEval Socket Programming and Evaluation board
■
MiniProg Programming Unit
■
Backward Compatibility Cable (for connecting to legacy Pods)
■
MiniEval Socket Programming and Evaluation Board
■
Universal 110/220 Power Supply (12 V)
■
28-pin CY8C29466-24PXI PDIP PSoC Device Sample
■
European Plug Adapter
■
PSoC Designer Software CD
■
USB 2.0 Cable
■
Getting Started Guide
■
Getting Started Guide
■
USB 2.0 Cable
■
Development Kit Registration form
Document Number: 38-12026 Rev. *N
CY3210-MiniProg1
Page 31 of 35
CY8C29466, CY8C29666
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. This software is free and
can be downloaded from http://www.cypress.com. The kit
includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 30. Emulation and Programming Accessories
Part Number
Pod Kit[19]
Pin Package
Foot Kit[20]
CY8C29466-12PVXE
28-pin SSOP
CY3250-29X66
CY3250-28SSOP-FK
CY8C29666-12PVXE
48-pin SSOP
CY3250-29X66
CY3250-48SSOP-FK
Adapter[21]
Adapters can be found at
http://www.emulation.com.
Ordering Information
The following table lists the automotive CY8C29x66 PSoC device’s key package features and ordering codes.
Flash
(Bytes)
RAM
(Bytes)
Temperature
Range
Digital PSoC
Blocks
Analog PSoC
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8C29466-12PVXE
CY8C29466-12PVXET
32 K
32 K
2K
2K
–40 °C to +125 °C
–40 °C to +125 °C
16
16
12
12
24
24
12[1]
12[1]
4
4
Yes
Yes
CY8C29666-12PVXE
32 K
2K
–40 °C to +125 °C
16
12
44
12[1]
4
Yes
Package
Ordering
Code
Table 31. CY8C29x66 Automotive PSoC Key Features and Ordering Information
28-pin (210 Mil) SSOP
28-pin (210 Mil) SSOP
(Tape and Reel)
48-pin (300-Mil) SSOP
Ordering Code Definitions
CY 8 C 29 xxx-SPxx
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LTX = QFN Pb-free
AX = TQFP Pb-free
Thermal Rating:
A = Automotive –40 °C to +85 °C
C = Commercial
E = Automotive Extended –40 °C to +125 °C
I = Industrial
CPU Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Notes
19. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
20. Foot kit includes surface mount feet that can be soldered to the target PCB.
21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 38-12026 Rev. *N
Page 32 of 35
CY8C29466, CY8C29666
Reference Information
Acronyms Used
The following table lists the acronyms that are used in this document.
Table 32. Acronyms
Acronym
Description
Acronym
Description
AC
alternating current
IMO
internal main oscillator
ADC
analog-to-digital converter
I/O
input/output
API
application programming interface
IPOR
imprecise power on reset
CPU
central processing unit
LSb
least-significant bit
CT
continuous time
LVD
low voltage detect
DAC
digital-to-analog converter
MSb
most-significant bit
DC
direct current
PC
program counter
ECO
external crystal oscillator
PLL
phase-locked loop
EEPROM electrically erasable programmable read-only memory POR
power on reset
FSR
full scale range
PPOR
precision power on reset
GPIO
general purpose IO
PSoC
Programmable System-on-Chip
GUI
graphical user interface
PWM
pulse width modulator
HBM
human body model
SC
switched capacitor
ICE
in-circuit emulator
SRAM
static random access memory
ILO
internal low speed oscillator
Units of Measure
The following table lists the units of measure that are used in this section.
Table 33. Units of Measure
Symbol
C
dB
fF
Hz
KB
Kbit
kHz
k
Mbaud
Mbps
MHz
M
A
F
H
s
V
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megabaud
megabits per second
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolt
Symbol
Vrms
W
mA
ms
mV
nA
ns
nV

pA
pF
pp
ppm
ps
sps

V
Unit of Measure
microvolts root-mean-square
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volt
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal.
Document Number: 38-12026 Rev. *N
Page 33 of 35
CY8C29466, CY8C29666
Document History Page
Document Title: CY8C29466, CY8C29666, Automotive – Extended Temperature PSoC® Programmable System-on-Chip
Document Number: 38-12026
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
228771
06/01/2004
SFV
First release of the CY8C29x66 automotive PSoC device data sheet.
*A
271452
See ECN
HMT
Update per SFV memo. Input changes from MWR, including removing SMP.
*B
288029
See ECN
HMT
Add Reflow Peak Temp. table. Update PSoC Characteristics table. Update
characterization data.
*C
473829
See ECN
HMT
Update PSoC Characteristics table. Update characterization data. Update
Storage Temperature for extended temperature devices. Fix error in Register
Bank 0/1. Update CY color, logo and copyright.
*D
602219
See ECN
HMT
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add
CY8C20x34 to PSoC Device Characteristics table. Update Technical Training
Modules paragraph. Add ISSP note to pinout tables.
*E
2101387
See ECN
AESA
Post to www.cypress.com
*F
2545030
07/29/08
YARA
Added note to DC Analog Reference Specification table and Ordering Information
*G
2663861
02/24/09
PRKA /
AESA
*H
2756235
08/26/09
BTK/AESA Changed title. Updated Features section. Updated text of PSoC Functional
Overview section. Updated Getting Started section. Made corrections and minor
text edits to Pinouts section. Changed the name of some sections for added
clarity. Improved formatting of the register tables. Added clarifying comments to
some electrical specifications. Changed TRAMP specification per MASJ input.
Fixed all AC specifications to conform to a ±4% IMO accuracy. Made other
miscellaneous minor text edits. Deleted some non-applicable or redundant information. Added a footnote to clarify that 8 of the 12 analog inputs are regular and
the other 4 are direct SC block connections. Added Development Tool Selection
section. Improved the bookmark structure. Changed the TROB, TSOB, VIHP,
VOHIGHOB, VOSOB, VOSOA, CINOA, VOHIGHOA, VOLOWOA, ISOA, Jitter24M1P,
TRiseF, and DC POR and LVD specifications according to MASJ directives.
*I
2822792 12/07/2009
BTK/AESA Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the text of footnote 10. Added maximum values and updated
typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP
electrical specification with SRPOWERUP electrical specification. Added
“Contents” on page 2. This revision fixes CDT 63984.
*J
2888007
03/30/2010
*K
3440253
11/16/2011
*L
3537225
02/28/2011
Document Number: 38-12026 Rev. *N
NJF
Updated template
Removed CY8C29666-12PVXE and CY8C29666-12PVXET and related
package information
Updated PSoC Designer and Getting Started sections
Updated Cypress website links.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
Updated Packaging Information.
Updated Development Kits and Evaluation Tools.
Removed Third Party Tools and Build a PSoC Emulator into your Board.
Updated Ordering Code Definitions.
Updated links in Sales, Solutions, and Legal Information.
MYKT_UKR Added part number CY8C29666-12PVXE to the Ordering Information table.
Added 48-pin part information to Pinouts, Thermal Impedances, and Capacitance on Crystal Pins sections.
Updated Accessories (Emulation and Programming) section.
Updated Solder Reflow Specifications section.
Included 48-Pin (300-Mil) SSOP spec to Packaging Information section.
VIVG
No technical updates.
Page 34 of 35
CY8C29466, CY8C29666
Document Title: CY8C29466, CY8C29666, Automotive – Extended Temperature PSoC® Programmable System-on-Chip
Document Number: 38-12026
*M
3726340
08/28/2012
tess_ukr/
LURE
*N
4689330
03/16/2015
KUK
Updated the following sections: Getting Started, Development Tools, and
Designing with PSoC Designer as all the System level designs have been
de-emphasized.
Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC Analog Reference Specifications:
Updated description.
Updated Packaging Information:
spec 51-85079 – Changed revision from *E to *F.
spec 51-85061 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
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© Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12026 Rev. *N
Revised March 16, 2015
All products and company names mentioned in this document may be the trademarks of their respective holders.
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