CY8C21x34B ® PSoC Programmable System-on-Chip™ CapSense Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity ® Features ■ Advanced CapSense® block with SmartSense™ Auto-Tuning ❐ Patented CSD sensing algorithm ❐ SmartSense_EMC Auto-Tuning • Sets and maintains optimal sensor performance during run time • Eliminates system tuning during development and production • Compensates for variations in manufacturing process ■ Driven shield ❐ Delivers best-in class water tolerant designs ❐ Robust proximity sensing in the presence of metal objects ❐ Supports longer trace lengths ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ Low power at high speed ❐ Operating voltage: 2.4 V to 5.25 V ❐ Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) ❐ Industrial temperature range: -40 °C to 85 °C ■ Advanced peripherals (PSoC® blocks) ❐ Four analog Type E PSoC blocks provide: • Two comparators with digital-to-analog converter (DAC) references • Single or dual 10-bit 28 channel analog-to-digital converters (ADC) ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers, counters, and pulse width modulators (PWMs) • Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules • Full-duplex universal asynchronous receiver transmitter (UART), serial peripheral interface (SPI) master or slave • Connectable to all general purpose I/O (GPIO) pins ❐ Implement a combination up to 21 buttons or 4 sliders using 4 analog blocks and 3 digital blocks ❐ Complex peripherals by combining blocks ■ Flexible on-chip memory ❐ 8-KB Flash /512-B SRAM ❐ 50,000 erase/write cycles ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash ■ Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full-featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128-KB trace memory ■ Precision, programmable clocking [1] ❐ Internal ±2.5% 24- / 48-MHz main oscillator ❐ Internal oscillator for watchdog and sleep ■ Programmable pin configurations ❐ 25-mA sink, 10-mA source on all GPIOs ❐ Pull-up, pull-down, high-Z, strong, or open-drain drive modes on all GPIOs ❐ Up to eight analog inputs on GPIOs ❐ Configurable interrupt on all GPIOs ■ Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations ❐ Capacitive sensing application capability ■ Additional system resources 2 [2] master, slave, and multi-master to 400 kHz ❐I C ❐ Watchdog and sleep timers ❐ User-configurable low-voltage detection (LVD) ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ■ Package options ❐ 16-pin SOIC ❐ 20-pin, 28-pin, 56-pin SSOP ❐ 32-pin QFN Errata: For information on silicon errata, see “Errata” on page 48. Details include trigger conditions, devices affected, and proposed workaround. Notes 1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%. 2. Errata:The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep mode. Cypress Semiconductor Corporation Document Number: 001-67345 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 25, 2015 CY8C21x34B Logic Block Diagram Document Number: 001-67345 Rev. *F Page 2 of 52 CY8C21x34B More Information Note: For CY8C21x34B devices related Development Kits please click here. Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article “How to Design with PSoC® 1, PowerPSoC®, and PLC – KBA88292”. Following is an abbreviated list for PSoC 1: The MiniProg1 and MiniProg3 devices provide interfaces for flash programming and debug. ■ Overview: PSoC Portfolio, PSoC Roadmap ■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP ■ In addition, PSoC Designer includes a device selection tool. ■ Application notes: Cypress offers a large number of PSoC application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 1 are: ® ❐ Getting Started with PSoC 1 – AN75320. ® ❐ PSoC 1 - Getting Started with GPIO – AN2094. ® ❐ PSoC 1 Analog Structure and Configuration – AN74170. ® ❐ PSoC 1 Switched Capacitor Analog Blocks – AN2041. ❐ Selecting Analog Ground and Reference – AN2219. Note: For CY8C21x34B devices related Application note please click here. ■ Development Kits: ❐ CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array families, including automotive, except CY8C25/26xxx devices. The kit includes an LCD module, potentiometer, LEDs, and breadboarding space. ❐ CY3214-PSoCEvalUSB features a development board for the CY8C24x94 PSoC device. Special features of the board include USB and CapSense development and debugging support. PSoC Designer PSoC Designer is a free Windows-based Integrated Design Environment (IDE). Develop your applications using a library of pre-characterized analog and digital peripherals in a drag-and-drop design environment. Then, customize your design leveraging the dynamically generated API libraries of code. Figure 1 shows PSoC Designer windows. Note: This is not the default view. 1. Global Resources – all device hardware settings. 2. Parameters – the parameters of the currently selected User Modules. 3. Pinout – information related to device pins. 4. Chip-Level Editor – a diagram of the resources available on the selected chip. 5. Datasheet – the datasheet for the currently selected UM 6. User Modules – all available User Modules for the selected device. 7. Device Resource Meter – device resource usage for the current project configuration. 8. Workspace – a tree level diagram of files associated with the project. 9. Output – output from project build and debug operations. Note: For detailed information on PSoC Designer, go to PSoC® Designer > Help > Documentation > Designer Specific Documents > IDE User Guide. Figure 1. PSoC Designer Layout Document Number: 001-67345 Rev. *F Page 3 of 52 CY8C21x34B Contents PSoC Functional Overview.............................................. 5 The PSoC Core ........................................................... 5 The Digital System ...................................................... 5 The Analog System ..................................................... 6 Additional System Resources ..................................... 6 PSoC Device Characteristics ...................................... 7 Development Tools .......................................................... 8 PSoC Designer Software Subsystems........................ 8 Designing with PSoC Designer ....................................... 9 Select User Modules ................................................... 9 Configure User Modules.............................................. 9 Organize and Connect ................................................ 9 Generate, Verify, and Debug....................................... 9 SmartSense................................................................. 9 Pin Information ............................................................... 10 16-Pin Part Pinout ..................................................... 10 20-Pin Part Pinout ..................................................... 11 28-Pin Part Pinout ..................................................... 12 32-Pin Part Pinout ..................................................... 13 56-Pin Part Pinout ..................................................... 15 Register Reference......................................................... 17 Register Conventions ................................................ 17 Register Mapping Tables .......................................... 17 Electrical Specifications ................................................ 20 Absolute Maximum Ratings....................................... 20 Operating Temperature ............................................. 21 DC Electrical Characteristics..................................... 21 AC Electrical Characteristics ..................................... 27 Packaging Information................................................... 35 Document Number: 001-67345 Rev. *F Thermal Impedances................................................. Solder Reflow Peak Temperature ............................. Development Tool Selection ......................................... Software .................................................................... Development Kits ...................................................... Evaluation Tools........................................................ Device Programmers................................................. Accessories (Emulation and Programming) .............. Ordering Information...................................................... Ordering Code Definitions ......................................... Acronyms ........................................................................ Reference Documents.................................................... Document Conventions ................................................. Units of Measure ....................................................... Numeric Conventions ................................................ Glossary .......................................................................... Errata ............................................................................... Part Numbers Affected .............................................. CY8C21X34 Qualification Status .............................. CY8C21X34 Errata Summary ................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 38 38 39 39 39 39 40 40 41 41 42 42 43 43 43 43 48 48 48 49 50 52 52 52 52 52 52 Page 4 of 52 CY8C21x34B PSoC Functional Overview The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture, shown in Figure 2, consists of four main areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow combining all of the device resources into a complete custom system. Each CY8C21x34B PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects. The PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (IMO) and internal low speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. The Digital System The digital system consists of four digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include: ■ PWMs (8- to 32-bit) ■ PWMs with dead band (8- to 32-bit) ■ Counters (8- to 32-bit) ■ Timers (8- to 32-bit) ■ UART 8- with selectable parity ■ Serial peripheral interface (SPI) master and slave ■ I2C slave and multi-master ■ CRC/generator (8-bit) ■ IrDA ■ PRS generators (8-bit to 32-bit) The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. System resources provide these additional capabilities: Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 7. ■ Digital clocks for increased flexibility Figure 2. Digital System Block Diagram ■ I2C functionality to implement an I2C master and slave An internal voltage reference, multi-master, that provides an absolute value of 1.3 V to a number of PSoC subsystems ■ A SMP that generates normal operating voltages from a single battery cell ■ Various system resets supported by the M8C To Analog System DIGITAL SYSTEM Row Input Configuration Digital PSoC Block Array 4 Row 0 DBB00 DBB01 DCB02 DCB03 4 8 8 8 8 GIE[7:0] GIO[7:0] Document Number: 001-67345 Rev. *F Port 0 Digital Clocks To System Bus From Core The digital system consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIOs through a series of global buses. These buses can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. The analog system consists of four analog PSoC blocks, supporting comparators, and analog-to-digital conversion up to 10 bits of precision. Port 1 Port 2 Row Output Configuration ■ Port 3 Global Digital Interconnect GOE[7:0] GOO[7:0] Page 5 of 52 CY8C21x34B The Analog System The Analog Multiplexer System The analog system consists of four configurable blocks that allow for the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are: The analog mux bus can connect to every GPIO pin. Pins may be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. ■ ADCs (single or dual, with 8-bit or 10-bit resolution) ■ Pin-to-pin comparator ■ Single-ended comparators (up to two) with absolute (1.3 V) reference or 8-bit DAC reference Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ Track pad, finger sensing 1.3-V reference (as a system resource) ■ Chip-wide mux that allows analog input from any I/O pin ■ Crosspoint connection between any I/O pin combinations ■ In most PSoC devices, analog blocks are provided in columns of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks. The CY8C21x34B devices provide limited functionality Type E analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Technical Reference Manual for detailed information on the CY8C21x34B’s Type E analog blocks. Figure 3. Analog System Block Diagram Array Input Configuration ACI0[1:0] ACI1[1:0] Additional System Resources System resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a switch-mode pump, low-voltage detection, and power-on-reset (POR). ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. ■ The I2C module provides 100- and 400-kHz communication over two wires. Slave, master, and multi-master modes are all supported. ■ LVD interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. ■ An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs. ■ An integrated switch-mode pump generates normal operating voltages from a single 1.2-V battery cell, providing a low cost boost converter. ■ Versatile analog multiplexer system. All I/O X X X ACOL1MUX X Analog Mux Bus X Array ACE00 ACE01 ASE10 ASE11 Document Number: 001-67345 Rev. *F Page 6 of 52 CY8C21x34B PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in Table 1. Table 1. PSoC Device Characteristics PSoC Part Number Digital I/O CY8C29x66 up to 64 CY8C28xxx up to 44 CY8C27x43 up to 44 CY8C24x94 up to 56 CY8C24x23A Digital Rows Digital Blocks Analog Inputs Analog Outputs 4 16 up to 12 4 up to 3 up to 12 up to 44 up to 4 2 8 up to 12 4 1 4 up to 48 2 up to 24 1 4 up to 12 CY8C23x33 up to 26 1 4 CY8C22x45 up to 38 2 8 CY8C21x45 up to 24 1 CY8C21x34 up to 28 CY8C21x34B up to 28 Analog Columns Analog Blocks SRAM Size Flash Size SmartSense Enabled 4 12 2K 32 K – up to 6 up to 12 + 4[3] 1K 16 K – 4 12 256 16 K – 2 6 1K 16 K – 2 2 6 256 4K – up to 12 2 2 4 256 8K – up to 38 0 4 6[3] 1K 16 K – 4 up to 24 0 4 6[3] 512 8K – 1 4 up to 28 0 2 4[3] 512 8K – 1 4 up to 28 0 2 4[3] 512 8K Y [3] – CY8C21x23 up to 16 1 4 up to 8 0 2 256 4K CY8C20x34 up to 28 0 0 up to 28 0 0 3[3,4] 4 512 8K – CY8C20xx6A up to 36 0 0 up to 36 0 0 3[3,4] up to 2K up to 32 K Y Notes 3. Limited analog functionality. 4. Two analog blocks and one CapSense®. Document Number: 001-67345 Rev. *F Page 7 of 52 CY8C21x34B Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. ■ Integrated source-code editor (C and assembly) Debugger ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. ■ Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are ADCs, DACs, amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-67345 Rev. *F Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 8 of 52 CY8C21x34B Designing with PSoC Designer Generate, Verify, and Debug The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. 1. Select User Modules. 2. Configure User Modules. 3. Organize and Connect. 4. Generate, Verify, and Debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. These include monitoring address and data bus values, memory locations, and external signals. SmartSense A key differentiation between the current offering of CY8C21x34 and CY8C21x34B, is the addition of the SmartSense user module in the ‘B’ version. SmartSense is an innovative solution from Cypress that eliminates the manual tuning process from CapSense applications. This solution is easy to use and provides robust noise immunity. It is the only auto-tuning solution that establishes, monitors and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Document Number: 001-67345 Rev. *F Page 9 of 52 CY8C21x34B Pin Information The CY8C21x34B PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 16-Pin Part Pinout Figure 4. CY8C21234B 16-Pin PSoC Device A, I, M, P0[7] 1 16 VDD A, I, M, P0[5] 2 15 P0[6], A, I, M A, I, M, P0[3] 3 14 P0[4], A, I, M A, I, M, P0[1] 4 13 P0[2], A, I, M SMP 5 12 P0[0], A, I, M VSS 6 11 P1[4], EXTCLK, M M, I2C SCL, P1[1] 7 10 P1[2], M VSS 8 9 SOIC P1[0], I2C SDA, M Table 2. Pin Definitions – CY8C21234B 16-Pin (SOIC) Pin No. Type Digital Name Analog Description 1 I/O I, M P0[7] Analog column mux input 2 I/O I, M P0[5] Analog column mux input 3 I/O I, M P0[3] Analog column mux input, integrating input 4 I/O I, M P0[1] Analog column mux input, integrating input 5 Power SMP Switch-mode pump (SMP) connection to required external components 6 Power VSS Ground connection 7 I/O P1[1] I2C serial clock (SCL), ISSP-SCLK[5] 8 Power VSS Ground connection 9 I/O M P1[0] I2C serial data (SDA), ISSP-SDATA[5] 10 I/O M P1[2] 11 I/O M P1[4] Optional external clock input (EXTCLK) 12 I/O I, M P0[0] Analog column mux input 13 I/O I, M P0[2] Analog column mux input 14 I/O I, M P0[4] Analog column mux input 15 I/O I, M P0[6] Analog column mux input 16 Power VDD Supply voltage M LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 5. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *F Page 10 of 52 CY8C21x34B 20-Pin Part Pinout Figure 5. CY8C21334B 20-Pin PSoC Device A, I, M, P0[7] 1 20 VDD A, I, M, P0[5] 2 19 P0[6], A, I, M A, I, M, P0[3] 3 18 P0[4], A, I, M A, I, M, P0[1] 4 17 P0[2], A, I, M VSS 5 16 P0[0], A, I, M M, I2C SCL, P1[7] 6 15 XRES M, I2C SDA, P1[5] 7 14 P1[6], M M, P1[3] 8 13 P1[4], EXTCLK, M M, I2C SCL, P1[1] 9 12 P1[2], M VSS 10 11 P1[0], I2C SDA, M SSOP Table 3. Pin Definitions – CY8C21334B 20-Pin (SSOP) Pin No. Type Digital Analog Name Description 1 I/O I, M P0[7] Analog column mux input 2 I/O I, M P0[5] Analog column mux input 3 I/O I, M P0[3] Analog column mux input, integrating input 4 I/O I, M P0[1] Analog column mux input, integrating input 5 Power VSS Ground connection 6 I/O M P1[7] I2C SCL 7 I/O M P1[5] I2C SDA 8 I/O M P1[3] 9 I/O M P1[1] I2C SCL, ISSP-SCLK[6] 10 Power VSS Ground connection. 11 I/O M P1[0] I2C SDA, ISSP-SDATA[6] 12 I/O M P1[2] 13 I/O M P1[4] 14 I/O M P1[6] 15 Input 16 I/O 17 I/O 18 19 20 Power Optional external clock input (EXTCLK) XRES Active high external reset with internal pull-down I, M P0[0] Analog column mux input I, M P0[2] Analog column mux input I/O I, M P0[4] Analog column mux input I/O I, M P0[6] Analog column mux input VDD Supply voltage LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 6. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *F Page 11 of 52 CY8C21x34B 28-Pin Part Pinout Figure 6. CY8C21534B 28-Pin PSoC Device A, I, M, P0[7] 1 28 VDD A, I, M, P0[5] 2 27 P0[6], A, I, M A, I, M, P0[3] 3 26 P0[4], A, I, M A, I, M, P0[1] 4 25 P0[2], A, I, M M, P2[7] 5 24 P0[0], A, I, M M, P2[5] 6 23 P2[6], M M, P2[3] 7 22 P2[4], M M, P2[1] 8 21 P2[2], M VSS 9 20 P2[0], M M, I2C SCL, P1[7] 10 19 XRES M, I2C SDA, P1[5] 11 18 P1[6], M M, P1[3] 12 17 P1[4], EXTCLK, M M, I2C SCL, P1[1] 13 16 P1[2], M VSS 14 15 P1[0], I2C SDA, M SSOP Table 4. Pin Definitions – CY8C21534B 28-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power Analog I, M I, M I, M I, M M M I, M I, M M M M M M M M M I, M I, M M M I, M I, M I, M I, M Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description Analog column mux input Analog column mux input and column output Analog column mux input and column output, integrating input Analog column mux input, integrating input Direct switched capacitor block input Direct switched capacitor block input Ground connection I2C SCL I2C SDA I2C SCL, ISSP-SCLK[7] Ground connection I2C SDA, ISSP-SDATA[7] Optional external clock input (EXTCLK) Active high external reset with internal pull-down Direct switched capacitor block input Direct switched capacitor block input Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. Note 7. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *F Page 12 of 52 CY8C21x34B 32-Pin Part Pinout Figure 7. CY8C21434B 32-Pin PSoC Device Figure 9. CY8C21634B 32-Pin Sawn PSoC Device Sawn M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] Document Number: 001-67345 Rev. *F A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 QFN (Top View) 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] QFN (Top View) 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, I2C SCL, P1[7] Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M Figure 8. CY8C21434B 32-Pin Sawn PSoC Device Sawn Figure 7. CY8C21634B 32-Pin PSoC Device Page 13 of 52 CY8C21x34B Table 5. Pin Definitions - CY8C21434B/CY8C21634B 32-Pin (QFN)[8] Pin No. 1 2 3 4 5 6 6 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Digital I/O I/O I/O I/O I/O I/O Power I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O Power Type Analog I, M M M M M M M M M M M M M M M M M M M M M I, M I, M I, M I, M I, M I, M I, M Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] SMP P3[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS Description Analog column mux input, integrating input In CY8C21434B part SMP connection to required external components in CY8C21634B part In CY8C21434B part Ground connection in CY8C21634B part I2C SCL I2C SDA I2C SCL, ISSP-SCLK[9] Ground connection I2C SDA, ISSP-SDATA[9] Optional external clock input (EXTCLK) Active high external reset with internal pull-down Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Analog column mux input Analog column mux input Analog column mux input, integrating input Ground connection LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Notes 8. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 9. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *F Page 14 of 52 CY8C21x34B 56-Pin Part Pinout The 56-Pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 10. CY8C21001 56-Pin PSoC Device V ss P 0[7] P 0[5] P 0[3] P 0[1] P 2[7] P 2[5] P 2[3] P 2[1] NC NC NC NC OCDE OCDO SMP V ss V ss P 3[3] P 3[1] NC NC I2C S C L, P 1[7] I2C S D A , P 1[5] NC P 1[3] S C LK , I2C S C L, P 1[1] V ss A I, A I, A I, A I, 1 2 56 55 3 4 5 6 7 8 9 10 54 53 52 51 18 19 20 21 22 23 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 24 25 33 32 26 27 28 31 30 11 12 13 14 15 16 17 S SO P 29 V dd P 0[6], P 0[4], P 0[2], P 0[0], P 2[6] AI AI AI AI P 2[4] P 2[2] P 2[0] NC NC P 3[2] P 3[0] C C LK H C LK XR E S NC NC NC NC NC NC P 1[6] P 1[4], E XTC LK P 1[2] P 1[0], I2C S D A , S D A TA NC NC Table 6. Pin Definitions – CY8C21001 56-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Type Digital Power I/O I/O I/O I/O I/O I/O I/O I/O OCD OCD Power Power Power I/O Analog I I I I I I Pin Name VSS P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC NC NC OCDE OCDO SMP VSS VSS P3[3] Document Number: 001-67345 Rev. *F Description Ground connection Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Direct switched capacitor block input Direct switched capacitor block input No connection No connection No connection No connection OCD even data I/O OCD odd data output SMP connection to required external components Ground connection Ground connection Page 15 of 52 CY8C21x34B Table 6. Pin Definitions – CY8C21001 56-Pin (SSOP) (continued) Type Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Digital Analog I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Input OCD OCD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I I I I I Pin Name P3[1] NC NC P1[7] P1[5] NC P1[3] P1[1] VSS NC NC P1[0] P1[2] P1[4] P1[6] NC NC NC NC NC NC XRES HCLK CCLK P3[0] P3[2] NC NC P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description No connection No connection I2C SCL I2C SDA No connection IFMTEST I2C SCL, ISSP-SCLK[10] Ground connection No connection No connection I2C SDA, ISSP-SDATA[10] VFMTEST Optional external clock input (EXTCLK) No connection No connection No connection No connection No connection No connection Active high external reset with internal pull-down OCD high-speed clock output OCD CPU clock output No connection No connection Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. Note 10. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *F Page 16 of 52 CY8C21x34B Register Reference This chapter lists the registers of the CY8C21x34B PSoC device. For detailed register information, see the PSoC Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 7. Table 7. Register Conventions Convention R Description Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set to 1, the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed. Document Number: 001-67345 Rev. *F Page 17 of 52 CY8C21x34B Table 8. Register Map 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 Addr (0,Hex) Access Name 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00DR0 20 # AMX_IN DBB00DR1 21 W AMUXCFG DBB00DR2 22 RW PWM_CR DBB00CR0 23 # DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # ADC0_CR DCB02DR1 29 W ADC1_CR DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 30 31 32 ACE00CR1 33 ACE00CR2 34 35 36 ACE01CR1 37 ACE01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are reserved and must not be accessed. Document Number: 001-67345 Rev. *F Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW # RW # # RW RW RW RW RW RW RW RW Name ASE10CR0 Addr (0,Hex) 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW Name RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_CR0 DEC_CR1 RW RW RW RW RW RW RW CPU_F DAC_D CPU_SCR1 CPU_SCR0 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW # RW # RW RW RW RW RW RW RC W RW RW RL RW # # Page 18 of 52 CY8C21x34B Table 9. Register Map 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 Addr (1,Hex) Access Name 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW CMP_GO_EN DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW DCB02IN 29 RW DCB02OU 2A RW 2B CLK_CR3 DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 30 31 32 ACE00CR1 33 ACE00CR2 34 35 36 ACE01CR1 37 ACE01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are reserved and must not be accessed. Document Number: 001-67345 Rev. *F Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASE10CR0 Addr (1,Hex) 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW Name RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IMO_TR ILO_TR BDG_TR ECO_TR RW RW RW RW RW RW RW CPU_F FLS_PR1 DAC_CR CPU_SCR1 CPU_SCR0 Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW W W RW W RL RW RW # # Page 19 of 52 CY8C21x34B Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34B PSoC device. For up-to-date electrical specifications, visit the Cypress web site at http://www.cypress.com. Specifications are valid for –40 C TA 85 C and TJ 100 C as specified, except where noted. Refer to Table 21 on page 27 for the electrical specifications for the IMO using SLIMO mode. Figure 14. IMO Frequency Trim Options Figure 11. Voltage versus CPU Frequency Vdd Voltage lid ng Va ati er ion Op eg R 4.75 SLIMO Mode = 0 5.25 Vdd Voltage 5.25 4.75 3.60 3.00 3.00 2.40 2.40 93 kHz 12 MHz 3 MHz 24 MHz 93 kHz SLIMO Mode=1 SLIMO Mode=0 SLIMO Mode=1 SLIMO Mode=0 SLIMO Mode=1 SLIMO Mode=1 6 MHz 12 MHz 24 MHz IMO Frequency CPU Frequency Absolute Maximum Ratings Symbol TSTG Description Storage temperature TBAKETEMP Bake temperature tBAKETIME Bake time TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electrostatic discharge voltage Latch-up current Document Number: 001-67345 Rev. *F Min –55 Typ 25 Max +100 Units °C – 125 °C See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – See package label 72 Hours – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C V V V mA V mA Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 65 °C degrade reliability. Human body model ESD. Page 20 of 52 CY8C21x34B Operating Temperature Symbol Description TA Ambient temperature TJ Junction temperature Min –40 –40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Table 34 on page 38. You must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 10. DC Chip-level Specifications Symbol Description VDD Supply voltage IDD Supply current, IMO = 24 MHz Min 2.40 – Typ – 3 Max 5.25 4 Units V mA Notes See Table 18 on page 25 Conditions are VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz Conditions are VDD = 2.55 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz VDD = 2.55 V, 0 °C TA 40 °C IDD3 Supply current, IMO = 6 MHz using SLIMO mode. – 1.2 2 mA IDD27 Supply current, IMO = 6 MHz using SLIMO mode. – 1.1 1.5 mA ISB27 – 2.6 4 µA – 2.8 5 µA VDD = 3.3 V, –40 °C TA 85 °C VREF Sleep (mode) current with POR, LVD, sleep timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (mode) current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference voltage (Bandgap) 1.28 1.30 1.32 V VREF27 Reference voltage (Bandgap) 1.16 1.30 1.33 V Trimmed for appropriate VDD VDD = 3.0 V to 5.25 V Trimmed for appropriate VDD VDD = 2.4 V to 3.0 V AGND Analog ground VREF – 0.003 VREF VREF + 0.003 V ISB Document Number: 001-67345 Rev. *F Page 21 of 52 CY8C21x34B DC General-Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 11. 5-V and 3.3-V DC GPIO Specifications Symbol Description Pull-up resistor RPU Pull-down resistor RPD High output level VOH Min 4 4 VDD – 1.0 Typ 5.6 5.6 – Max 8 8 – Units k k V VOL Low output level – – 0.75 V IOH High level source current 10 – – mA IOL Low level sink current 25 – – mA VIL VIH VH IIL CIN Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input – 2.1 – – – – – 60 1 3.5 0.8 – – 10 V V mV nA pF COUT Capacitive load on pins as output – 3.5 10 pF Min 4 4 VDD – 0.4 Typ 5.6 5.6 – Max 8 8 – Units k k V – – 0.75 V Notes IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]) IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])) VOH = VDD – 1.0 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 3.0 to 5.25 VDD = 3.0 to 5.25 Gross tested to 1 µA Package and pin dependent Temp = 25 °C Package and pin dependent Temp = 25 °C Table 12. 2.7-V DC GPIO Specifications Symbol Description RPU Pull-up resistor RPD Pull-down resistor VOH High output level VOL Low output level IOH High level source current 2.5 – – mA IOL Low level sink current 10 – – mA VIL VIH VH IIL CIN Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input – 2.0 – – – – – 90 1 3.5 0.75 – – – 10 V V mV nA pF COUT Capacitive load on pins as output – 3.5 10 pF Document Number: 001-67345 Rev. *F Notes IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to 3.0 V (16 mA maximum, 50 mA Typ combined IOH budget) IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA maximum combined IOL budget) VOH = VDD – 0.4 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 2.4 to 3.0 VDD = 2.4 to 3.0 Gross tested to 1 µA Package and pin dependent Temp = 25 °C Package and pin dependent Temp = 25 °C Page 22 of 52 CY8C21x34B DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 13. 5-V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA IEBOA00 CINOA Description Input offset voltage (absolute value) Average input offset voltage drift Input leakage current (Port 0 analog pins 7-to-1) Input leakage current (Port 0, Pin 0 analog pin) Input capacitance (Port 0 analog pins) Min – – – – – Typ 2.5 10 200 50 4.5 Max 15 – – – 9.5 Units mV µV/°C pA nA pF VCMOA Common mode voltage range 0.0 – VDD – 1.0 V GOLOA ISOA Open loop gain Amplifier supply current – – 80 10 – 30 dB µA Min Typ Max Units Notes Gross tested to 1 µA Gross tested to 1 µA Package and pin dependent. Temp = 25 °C Table 14. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Notes – 2.5 15 mV TCVOSOA Average input offset voltage drift – 10 – µV/°C IEBOA Input leakage current (Port 0 analog pins) – 200 – pA Gross tested to 1 µA IEBOA00 Input leakage current (Port 0, Pin 0 analog pin) – 50 – nA Gross tested to 1 µA CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25 °C VCMOA Common mode voltage range 0 – VDD – 1.0 V GOLOA Open loop gain – 80 – dB ISOA Amplifier supply current – 10 30 µA Min Typ Max Units Table 15. 2.7-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Notes – 2.5 15 mV TCVOSOA Average input offset voltage drift – 10 – µV/°C IEBOA Input leakage current (Port 0 analog pins) – 200 – pA Gross tested to 1 µA IEBOA00 Input leakage current (Port 0, Pin 0 analog pin) – 50 – nA Gross tested to 1 µA CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25 °C VCMOA Common mode voltage range 0 – VDD – 1.0 V GOLOA Open loop gain – 80 – dB ISOA Amplifier supply current – 10 30 µA Document Number: 001-67345 Rev. *F Page 23 of 52 CY8C21x34B DC Switch Mode Pump Specifications Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Figure 12. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT + SMP Battery C1 PSoC Vss Table 16. DC Switch Mode Pump (SMP) Specifications Min Typ Max Units VPUMP5V Symbol 5 V output voltage from pump Description 4.75 5.0 5.25 V Configured as in Note 11 Average, neglecting ripple SMP trip voltage is set to 5.0 V VPUMP3V 3.3 V output voltage from pump 3.00 3.25 3.60 V Configured as in Note 11 Average, neglecting ripple. SMP trip voltage is set to 3.25 V VPUMP2V 2.6 V output voltage from pump 2.45 2.55 2.80 V Configured as in Note 11 Average, neglecting ripple. SMP trip voltage is set to 2.55 V IPUMP Available output current VBAT = 1.8 V, VPUMP = 5.0 V VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.3 V, VPUMP = 2.55 V 5 8 8 – – – – – – mA mA mA VBAT5V Input voltage range from battery 1.8 – 5.0 V Configured as in Note 11 SMP trip voltage is set to 5.0 V VBAT3V Input voltage range from battery 1.0 – 3.3 V Configured as in Note 11 SMP trip voltage is set to 3.25 V VBAT2V Input voltage range from battery 1.0 – 2.8 V Configured as in Note 11 SMP trip voltage is set to 2.55 V VBATSTART Minimum input voltage from battery to start pump 1.2 – – V Configured as in Note 11 0 C TA 100. 1.25 V at TA = –40 °C VPUMP_Line Line regulation (over Vi range) – 5 – %VO Configured as in Note 11 VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 18 on page 25 VPUMP_Load Load regulation – 5 – %VO Configured as in Note 11 VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 18 on page 25 VPUMP_Ripple Output voltage ripple (depends on cap/load) – 100 – mVpp Configured as in Note 11 Load is 5 mA E3 Efficiency 35 50 – % Notes Configured as in Note 11 SMP trip voltage is set to 5.0 V SMP trip voltage is set to 3.25 V SMP trip voltage is set to 2.55 V Configured as in Note 11 Load is 5 mA. SMP trip voltage is set to 3.25 V Note 11. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 12. Document Number: 001-67345 Rev. *F Page 24 of 52 CY8C21x34B Table 16. DC Switch Mode Pump (SMP) Specifications (continued) Symbol Description Min Typ Max Units Notes For I load = 1mA, VPUMP = 2.55 V, VBAT = 1.3 V, 10 µH inductor, 1 µF capacitor, and Schottky diode E2 Efficiency 35 80 – % FPUMP Switching frequency – 1.3 – MHz DCPUMP Switching duty cycle – 50 – % DC Analog Mux Bus Specifications Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 17. DC Analog Mux Bus Specifications Symbol RSW Description Switch resistance to common analog bus Min – Typ – RVDD Resistance of initialization switch to VDD – – Max 400 800 800 Units Notes VDD 2.7 V 2.4 V VDD 2.7 V DC POR and LVD Specifications Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 18. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes – – – 2.36 2.82 4.55 2.40 2.95 4.70 V V V VDD must be greater than or equal to 2.5 V during startup, the reset from the XRES pin, or reset from watchdog VPPOR0 VPPOR1 VPPOR2 VDD value for PPOR trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51[12] 2.99[13] 3.09 3.20 4.55 4.75 4.83 4.95 V V V V V V V V VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VDD value for pump trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62[14] 3.09 3.16 3.32[15] 4.74 4.83 4.92 5.12 V V V V V V V V Notes 12. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 13. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 14. Always greater than 50 mV above VLVD0. 15. Always greater than 50 mV above VLVD3. Document Number: 001-67345 Rev. *F Page 25 of 52 CY8C21x34B DC Programming Specifications Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 19. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.5 Units V VDDLV Low VDD for verify 2.4 2.5 2.6 V VDDHV High VDD for verify 5.1 5.2 5.3 V VDDIWRITE Supply voltage for flash write operation 2.7 5.25 V IDDP VILP VIHP Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block) Flash endurance (total)[17] Flash data retention – – 2.2 5 – – 25 0.8 – mA V V – – 0.2 mA Driving internal pull-down resistor – – 1.5 mA Driving internal pull-down resistor – – VSS + 0.75 V VDD – 1.0 – VDD V 50,000[16] 1,800,000 10 – – – – – – – – Years IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Notes This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to this device when it is executing internal flash writes Erase/write cycles per block Erase/write cycles DC I2C Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 20. DC I2C Specifications[18] Symbol VILI2C Input low level Description VIHI2C Input high level Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 2.4 V VDD 3.6 V 4.75 V VDD 5.25 V 2.4 V VDD 5.25 V Notes 16. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V, and 4.75 V to 5.25 V. 17. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36×2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no single block ever sees more than 50,000 cycles). For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC® Flash) for more information. 18. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 001-67345 Rev. *F Page 26 of 52 CY8C21x34B AC Electrical Characteristics AC Chip-Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 21. 5-V and 3.3-V AC Chip-Level Specifications Symbol FIMO24 Description IMO frequency for 24 MHz Min 23.4 Typ 24 Max 24.6[19,20] Units MHz FIMO6 IMO frequency for 6 MHz 5.5 6 6.5[19,20] MHz FCPU1 CPU frequency (5 V nominal) 0.091 24 24.6[19] MHz FCPU2 FBLK5 CPU frequency (3.3 V nominal) Digital PSoC block frequency0(5 V nominal) 0.091 0 12 48 12.3[20] 49.2[19,21] MHz MHz FBLK33 F32K1 F32K_U Digital PSoC block frequency (3.3 V nominal) ILO frequency ILO untrimmed frequency 0 15 5 24 32 – 24.6[21] 64 100 MHz kHz kHz tXRST DC24M DCILO Step24M Fout48M External reset pulse width 24 MHz duty cycle ILO duty cycle 24 MHz trim step size 48 MHz output frequency 10 40 20 – 46.8 – 50 50 50 48.0 – 60 80 – 49.2[19,20] s % % kHz MHz FMAX – – 12.3 MHz SRPOWER_UP Maximum frequency of signal on row input or row output. Power supply slew rate – – 250 V/ms tPOWERUP Time from end of POR to CPU executing code – 16 100 ms tjit_IMO 24-MHz IMO cycle-to-cycle jitter (RMS)[22] 24-MHz IMO long term N cycle-to-cycle jitter (RMS)[22] 24-MHz IMO period jitter (RMS)[22] – – 200 300 700 900 ps ps – 100 400 ps Notes Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 14 on page 20. SLIMO mode = 0 Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 14 on page 20. SLIMO mode = 1 24 MHz only for SLIMO mode = 0 SLIMO mode = 0 Refer to AC Digital Block Specifications on page 30 After a reset and before the M8C starts to run, the ILO is not trimmed. See the system resets section of the PSoC Technical Reference Manual for details on this timing Trimmed. Using factory trim values VDD slew rate during power-up Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual N = 32 Notes 19. 4.75 V < VDD < 5.25 V. 20. 3.0 V < VDD < 3.6 V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3 V. 21. See the individual user module datasheets for information on maximum frequencies for user modules. 22. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at www.cypress.com under Application Notes for more information. Document Number: 001-67345 Rev. *F Page 27 of 52 CY8C21x34B Table 22. 2.7-V AC Chip-Level Specifications Symbol FIMO12 Description IMO frequency for 12 MHz Min 11.5 Typ 120 Max 12.7[23,24] Units MHz FIMO6 IMO frequency for 6 MHz 5.5 6 6.5[23,24] MHz FCPU1 CPU frequency (2.7 V nominal) 0.093 3 3.15[23] MHz FBLK27 Digital PSoC block frequency (2.7 V nominal) 0 12 12.5[23,24] MHz F32K1 F32K_U ILO frequency ILO untrimmed frequency 8 5 32 – 96 100 kHz kHz tXRST DCILO FMAX 10 20 – – 50 – – 80 12.3 µs % MHz SRPOWER_UP External reset pulse width IILO duty cycle Maximum frequency of signal on row input or row output. Power supply slew rate – – 250 V/ms tPOWERUP Time from end of POR to CPU executing code – 16 100 ms tjit_IMO 12 MHz IMO cycle-to-cycle jitter (RMS)[25] 12 MHz IMO long term N cycle-to-cycle jitter (RMS)[25] 12 MHz IMO period jitter (RMS)[25] – – 400 600 1000 1300 ps ps – 100 500 ps Notes Trimmed for 2.7 V operation using factory trim values. See Figure 14 on page 20. SLIMO mode = 1 Trimmed for 2.7 V operation using factory trim values. See Figure 14 on page 20. SLIMO mode = 1 12 MHz only for SLIMO mode = 0 Refer to AC Digital Block Specifications on page 30 After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing VDD slew rate during power-up Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. N = 32 Note 23. 2.4 V < VDD < 3.0 V. 24. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” available at http://www.cypress.com for information on maximum frequency for user modules. 25. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at www.cypress.com under Application Notes for more information. Document Number: 001-67345 Rev. *F Page 28 of 52 CY8C21x34B AC General Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 23. 5-V and 3.3-V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 7 7 Typ – – – 27 22 Max 12 18 18 – – Units MHz ns ns ns ns Notes Normal strong mode VDD = 4.5 to 5.25 V, 10% to 90% VDD = 4.5 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% Min 0 6 6 18 18 Typ – – – 40 40 Max 3 50 50 120 120 Units MHz ns ns ns ns Notes Normal strong mode VDD = 2.4 to 3.0 V, 10% to 90% VDD = 2.4 to 3.0 V, 10% to 90% VDD = 2.4 to 3.0 V, 10% to 90% VDD = 2.4 to 3.0 V, 10% to 90% Table 24. 2.7 V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Figure 13. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 25. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator mode response time, 50 mV overdrive Document Number: 001-67345 Rev. *F Min – Typ – Max 100 200 Units ns ns Notes VDD 3.0 V 2.4 V < VDD <3.0 V Page 29 of 52 CY8C21x34B AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 26. 5-V and 3.3-V AC Digital Block Specifications Function All functions Timer Description Min Typ Max Unit VDD 4.75 V – – 49.2 MHz VDD < 4.75 V – – 24.6 MHz No capture, VDD 4.75 V – – 49.2 MHz No capture, VDD < 4.75 V – – 24.6 MHz – – 24.6 MHz 50[26] – – ns Input clock frequency With capture Capture pulse width Counter Input clock frequency No enable input, VDD 4.75 V – – 49.2 MHz No enable input, VDD < 4.75 V – – 24.6 MHz – – 24.6 MHz 50[26] – – ns With enable input Enable input pulse width Dead Band Notes Block input clock frequency Kill pulse width Asynchronous restart mode 20 – – ns Synchronous restart mode 50[26] – – ns Disable mode 50[26] – – ns VDD 4.75 V – – 49.2 MHz VDD < 4.75 V – – 24.6 MHz – – 49.2 MHz Input clock frequency CRCPRS (PRS Mode) Input clock frequency – – 24.6 MHz CRCPRS (CRC Mode) Input clock frequency – – 24.6 MHz SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode. VDD 4.75 V VDD < 4.75 V SPIS Transmitter Input clock (SCLK) frequency – – 4.1 MHz Width of SS_negated between transmissions 50[26] – – ns – – 49.2 MHz Input clock frequency VDD 4.75 V, 2 stop bits Receiver VDD 4.75 V, 1 stop bit – – 24.6 MHz VDD < 4.75 V – – 24.6 MHz Input clock frequency The baud rate is equal to the input clock frequency divided by 8. The baud rate is equal to the input clock frequency divided by 8. VDD 4.75 V, 2 stop bits – – 49.2 MHz VDD 4.75 V, 1 stop bit – – 24.6 MHz VDD < 4.75 V – – 24.6 MHz Note 26. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-67345 Rev. *F Page 30 of 52 CY8C21x34B Table 27. 2.7-V AC Digital Block Specifications Function Description All functions Block input clock frequency Timer Capture pulse width Input clock frequency, with or without capture Counter Typ Max Units Notes – – 12.7 MHz 2.4 V < VDD < 3.0 V 100[27] – – ns – – 12.7 MHz 100 – – ns Input clock frequency, no enable input – – 12.7 MHz Input clock frequency, enable input – – 12.7 MHz Asynchronous restart mode 20 – – ns Synchronous restart mode 100 – – ns Disable mode 100 – – ns Input clock frequency – – 12.7 MHz CRCPRS (PRS Mode) Input clock frequency – – 12.7 MHz CRCPRS (CRC Mode) Input clock frequency – – 12.7 MHz SPIM Input clock frequency – – 6.35 MHz SPIS Input clock (SCLK) frequency – – 4.1 MHz Dead Band Enable input pulse width Min Kill pulse width: Width of SS_ Negated between transmissions The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. 100 – – ns Transmitter Input clock frequency – – 12.7 MHz The baud rate is equal to the input clock frequency divided by 8. Receiver Input clock frequency – – 12.7 MHz The baud rate is equal to the input clock frequency divided by 8. AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 28. 5-V AC External Clock Specifications Min Typ Max Units FOSCEXT Symbol Frequency Description 0.093 – 24.6 MHz – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power-up IMO to switch 150 – – µs Notes Note 27. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 001-67345 Rev. *F Page 31 of 52 CY8C21x34B Table 29. 3.3-V AC External Clock Specifications Min Typ Max Units Notes FOSCEXT Symbol Frequency with CPU clock divide by 1 Description 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements FOSCEXT Frequency with CPU clock divide by 2 or greater 0.186 – 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met – High period with CPU clock divide by 1 41.7 – 5300 ns – Low period with CPU clock divide by 1 41.7 – – ns – Power-up IMO to switch 150 – – µs Min Typ Max Units Notes 0 Table 30. 2.7-V AC External Clock Specifications Symbol Description FOSCEXT Frequency with CPU clock divide by 1 0.093 – 3.08 MHz Maximum CPU frequency is 3 MHz at 2.7 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements FOSCEXT Frequency with CPU clock divide by 2 or greater 0.186 – 6.35 MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met – High period with CPU clock divide by 1 160 – 5300 ns – Low period with CPU clock divide by 1 160 – – ns – Power-up IMO to switch 150 – – µs Document Number: 001-67345 Rev. *F Page 32 of 52 CY8C21x34B AC Programming Specifications Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 31. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 TERASEALL Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Flash erase time (Bulk) Min 1 1 40 40 0 – – – – – – Typ – – – – – 10 40 – – – 20 Max 20 20 – – 8 – – 45 50 70 – Units ns ns ns ns MHz ms ms ns ns ns ms TPROGRAM_HOT TPROGRAM_COLD Flash block erase + flash block write time Flash block erase + flash block write time – – – – 100[28] 200[28] ms ms Notes 3.6 VDD 3.0 VDD 3.6 2.4 VDD 3.0 Erase all blocks and protection fields at once 0 °C Tj 100 °C –40 °C Tj 0 °C AC I2C Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated Low period of the SCL clock High period of the SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition Bus free time between a stop and start condition Pulse width of spikes suppressed by the input filter. Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – Fast Mode Min Max 0 400 0.6 – 1.3 0.6 0.6 0 100[29] 0.6 1.3 0 – – – – – – – 50 Units kHz µs µs µs µs µs ns µs µs ns Notes 28. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC® Flash) for more information. 29. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but it must meet the requirement TSU;DAT 250 ns. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line Trmax + TSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-67345 Rev. *F Page 33 of 52 CY8C21x34B Table 33. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated. Low period of the SCL clock High period of the SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition Bus free time between a stop and start condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100 4.0 – Fast Mode Min – – Max – – Units kHz µs 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – – – – – – – – – – – – – µs µs µs µs ns µs µs – – – – ns Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C TSPI2C THDDATI2CTSUSTAI2C TBUFI2C I2C_SCL THIGHI2C TLOWI2C S START Condition Document Number: 001-67345 Rev. *F TSUSTOI2C Sr Repeated START Condition P S STOP Condition Page 34 of 52 CY8C21x34B Packaging Information This section shows the packaging specifications for the CY8C21x34B PSoC device with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 15. 16-Pin (150-Mil) SOIC 51-85068 *E Figure 16. 20-Pin (210-Mil) SSOP 51-85077 *E Document Number: 001-67345 Rev. *F Page 35 of 52 CY8C21x34B Figure 17. 28-Pin (210-Mil) SSOP 51-85079 *E Figure 18. 32-Pin QFN ( 5 X 5 X 1.0 MM) LT32B (3.5 X 3.5) EPAD (SAWN) 001-30999 *D Document Number: 001-67345 Rev. *F Page 36 of 52 CY8C21x34B Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) 1.3 × 2.7 E-Pad (Sawn Type) Package Outline 001-48913 *D Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note, Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at http://www.cypress.com. Figure 20. 56-Pin (300-Mil) SSOP 51-85062 *F Document Number: 001-67345 Rev. *F Page 37 of 52 CY8C21x34B Thermal Impedances Table 34. Thermal Impedances per Package Typical JA [30] 123 °C/W 117 °C/W 96 °C/W 27 °C/W 22 °C/W 48 °C/W Package 16-pin SOIC 20-pin SSOP 28-pin SSOP 32-pin QFN[31] 5 × 5 mm 0.60 Max 32-pin QFN[31] 5 × 5 mm 0.93 Max 56-pin SSOP Typical JC 55 °C/W 41 °C/W 39 °C/W 15 °C/W 12 °C/W 24 °C/W Solder Reflow Peak Temperature Table 35 lists the maximum solder reflow peak temperatures to achieve good solderability. Thermal ramp rate during preheat should be 3 °C/s or lower. Table 35. Solder Reflow Peak Temperature Package Maximum Peak Temperature Time at Maximum Temperature 16-pin SOIC 260 °C 30 s 20-pin SSOP 260 °C 30 s 28-pin SSOP 260 °C 30 s 32-pin QFN 260 °C 30 s 56-pin SSOP 260 °C 30 s Notes 30. TJ = TA + Power × JA 31. To achieve the thermal impedance specified for the QFN package, refer to Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at http://www.cypress.com. 32. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-67345 Rev. *F Page 38 of 52 CY8C21x34B Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C21x34B family. Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of cost at http://www.cypress.com and includes a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. Development Kits All development kits can be purchased from the Cypress Online Store. CY3280-BK1 Universal CapSense Controller - Basic Kit 1 The CY3280-BK1 Universal CapSense Controller Kit is designed for easy prototyping and debug of CapSense designs with pre-defined control circuitry and plug-in hardware. The kit comes with controller boards for the CY8C20x34 and CY8C21x34 PSoC devices as well as a breadboard module and a button(5) / slider module. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation, and the software interface allows you to run, halt, and single step the processor, and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: ■ PSoC Designer software CD ■ ICE-Cube in-circuit emulator ■ ICE Flex-Pod for CY8C29x66 family ■ Cat-5 adapter ■ Mini-Eval programming board ■ 110 ~ 240 V power supply, Euro-Plug adapter ■ iMAGEcraft C compiler ■ ISSP cable ■ USB 2.0 cable and Blue Cat-5 cable ■ Two CY8C29466-24PXI 28-PDIP chip samples Document Number: 001-67345 Rev. *F Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows you to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: ■ MiniProg programming unit ■ MiniEval socket programming and evaluation board ■ 28-Pin CY8C29466-24PXI PDIP PSoC device sample ■ 28-Pin CY8C27443-24PXI PDIP PSoC device sample ■ PSoC Designer software CD ■ Getting Started guide ■ USB 2.0 cable CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ Evaluation board with LCD module ■ MiniProg programming unit ■ Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples ■ PSoC Designer software CD ■ Getting Started guide ■ USB 2.0 cable CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. The board includes both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ PSoCEvalUSB board ■ LCD module ■ MIniProg programming unit ■ Mini USB cable ■ PSoC Designer and example projects CD ■ Getting Started guide ■ Wire pack Page 39 of 52 CY8C21x34B Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer ■ MiniProg programming unit The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ PSoC Designer software CD ■ Getting Started guide ■ USB 2.0 cable ■ Modular programmer base ■ Three programming module cards Accessories (Emulation and Programming) Table 36. Emulation and Programming Accessories Part Number Pin Package Flex-Pod Kit[33] Foot Kit[34] CY8C21234B-24SXI 16-Pin SOIC CY3250-21X34 CY3250-16SOIC-FK CY8C21334B-24PVXI 20-Pin SSOP CY3250-21X34 CY3250-20SSOP-FK CY8C21534B-24PVXI 28-Pin SSOP CY3250-21X34 CY3250-28SSOP-FK Adapter Adapters can be found at http://www.emulation.com. Notes 33. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 34. Foot kit includes surface mount feet that can be soldered to the target PCB. Document Number: 001-67345 Rev. *F Page 40 of 52 CY8C21x34B SRAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 16-Pin (150-Mil) SOIC CY8C21234B-24SXI 8K 512 Yes –40 °C to +85 °C 4 4 12 12[35] 0 No 16-Pin (150-Mil) SOIC (Tape and Reel) CY8C21234B-24SXIT 8K 512 Yes –40 °C to +85 °C 4 4 12 12[35] 0 No 20-Pin (210-Mil) SSOP CY8C21334B-24PVXI 8K 512 No –40 °C to +85 °C 4 4 16 16[35] 0 Yes [35] 0 Yes Package Ordering Code Flash (Bytes) Ordering Information 20-Pin (210-Mil) SSOP (Tape and Reel) CY8C21334B-24PVXIT 8K 512 No –40 °C to +85 °C 4 4 16 16 28-Pin (210-Mil) SSOP CY8C21534B-24PVXI 8K 512 No –40 °C to +85 °C 4 4 24 24[35] 0 Yes [35] 0 Yes 28-Pin (210-Mil) SSOP (Tape and Reel) CY8C21534B-24PVXIT 8K 512 No –40 °C to +85 °C 4 4 24 24 32-Pin (5 × 5 mm 1.00 max) Sawn QFN CY8C21434B-24LTXI 8K 512 No –40 °C to +85 °C 4 4 28 28[35] 0 Yes 32-Pin (5 × 5 mm 1.00 max) CY8C21434B-24LTXIT Sawn QFN [36] (Tape and Reel) 8K 512 No –40 °C to +85 °C 4 4 28 28[35] 0 Yes 32-Pin (5 × 5 mm 0.60 max) Thin Sawn QFN CY8C21434B-24LQXI 8K 512 No –40 °C to +85 °C 4 4 28 28[35] 0 Yes 32-Pin (5 × 5 mm 0.60 max) Thin Sawn QFN (Tape and Reel) CY8C21434B-24LQXIT 8K 512 No –40 °C to +85 °C 4 4 28 28[35] 0 Yes 56-Pin OCD SSOP CY8C21001-24PVXI 8K 512 Yes –40 °C to +85 °C 4 4 26 26[35] 0 Yes Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 21 xxxx-24 xx Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LKX/LTX/LQX = QFN Pb-free Thermal Rating: C = Commercial I = Industrial E = Extended Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Notes 35. All Digital I/O Pins also connect to the common analog mux. 36. Refer to the section 32-Pin Part Pinout on page 13 for pin differences. Document Number: 001-67345 Rev. *F Page 41 of 52 CY8C21x34B Acronyms Table 37 lists the acronyms that are used in this document. Table 37. Acronyms Used in this Datasheet Acronym AC Description Acronym Description alternating current MIPS million instructions per second ADC analog-to-digital converter OCD on-chip debug API application programming interface PCB printed circuit board CMOS complementary metal oxide semiconductor PDIP plastic dual-in-line package CPU central processing unit PGA programmable gain amplifier CRC cyclic redundancy check PLL phase-locked loop continuous time POR power on reset CT DAC DC digital-to-analog converter direct current PPOR PRS precision power on reset pseudo-random sequence DTMF dual-tone multi-frequency PSoC® ECO external crystal oscillator PWM pulse width modulator electrically erasable programmable read-only memory QFN quad flat no leads general purpose I/O RTC real time clock in-circuit emulator SAR successive approximation EEPROM GPIO ICE IDE integrated development environment ILO internal low speed oscillator SC SLIMO Programmable System-on-Chip switched capacitor slow IMO IMO internal main oscillator SMP switch-mode pump I/O input/output SOIC small-outline integrated circuit IrDA infrared data association SPITM serial peripheral interface ISSP in-system serial programming SRAM static random access memory LCD liquid crystal display SROM supervisory read only memory LED light-emitting diode SSOP shrink small-outline package LPC low power comparator UART LVD low voltage detect MAC MCU universal asynchronous receiver / transmitter USB universal serial bus multiply-accumulate WDT watchdog timer microcontroller unit XRES external reset Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34B, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash - AN2015 (001-40459) Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397) Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 available at http://www.cypress.com. Document Number: 001-67345 Rev. *F Page 42 of 52 CY8C21x34B Document Conventions Units of Measure Table 38 lists the units of measures. Table 38. Units of Measure Symbol Unit of Measure Symbol µH Unit of Measure kB 1024 bytes microhenry dB decibels µs microsecond °C degree Celsius ms millisecond µF microfarad ns nanosecond fF femto farad ps picosecond pF picofarad µV microvolts kHz kilohertz mV millivolts MHz megahertz mVpp rt-Hz root hertz nV nanovolts V volts k kilohm ohm millivolts peak-to-peak µW microwatts W watt µA microampere mA milliampere mm nA nanoampere ppm pA pikoampere % mH millihenry millimeter parts per million percent Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. Application programming interface (API) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. Document Number: 001-67345 Rev. *F Page 43 of 52 CY8C21x34B Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation. Document Number: 001-67345 Rev. *F Page 44 of 52 CY8C21x34B Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. External Reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. Flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low-voltage detect A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. Document Number: 001-67345 Rev. *F Page 45 of 52 CY8C21x34B Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). Phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. Power on reset (POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurement modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. Document Number: 001-67345 Rev. *F Page 46 of 52 CY8C21x34B Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. VDD A name for a power net meaning ‘voltage drain’. The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning ‘voltage source’. The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-67345 Rev. *F Page 47 of 52 CY8C21x34B Errata This section describes the errata for the PSoC® Programmable System-on-Chip CY8C21X34. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number CY8C21X34 Ordering Information CY8C21234-24SXI CY8C21234-24SXIT CY8C21334-24PVXI CY8C21334-24PVXIT CY8C21534-24PVXI CY8C21534-24PVXIT CY8C21434-24LFXI CY8C21434-24LFXIT CY8C21434-24LKXI CY8C21434-24LKXIT CY8C21634-24LFXI CY8C21634-24LFXIT CY8C21434-24LTXI CY8C21434-24LTXIT CY8C21434-24LQXI CY8C21434-24LQXIT CY8C21634-24LTXI CY8C21634-24LTXIT CY8C21001-24PVXI CY8C21X34 Qualification Status Product Status: Production Document Number: 001-67345 Rev. *F Page 48 of 52 CY8C21x34B CY8C21X34 Errata Summary The following table defines the errata applicability to available CY8C21X34 family devices. An "X" indicates that the errata pertains to the selected device. Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description. Items Part Number Silicon Revision Fix Status [1.]. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes CY8C21X34 A No fix is currently planned. [2]. I2C Errors CY8C21X34 A No fix is currently planned. 1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes ■ Problem Definition Asynchronous Digital Communications Interfaces may fail framing beyond 0 °C to 70 °C. This problem does not affect end-product usage between 0 °C and 70 °C. ■ Parameters Affected The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%. ■ Trigger Condition(S) The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the datasheet limit of ±2.5% when operated beyond the temperature range of 0 °C to +70 °C. ■ Scope of Impact This problem may affect UART, IrDA, and FSK implementations. ■ Workaround Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface. ■ Fix Status No fix is currently planned. 2. I2C Errors ■ Problem Definition The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep mode. ■ Parameters Affected Affects reliability of I2C communication to device, between I2C master, and third party I2C slaves. ■ Trigger Condition(S) Triggered by transitions into and out of the device's sleep mode. ■ Scope of Impact This problem may affect UART, IrDA, and FSK implementations. ■ Workaround Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I2C block from the bus prior to going to sleep modes. I2C transactions during sleep are supported by a protocol in which the master wakes the device prior to the I2C transaction ■ Fix Status Will not be fixed. Document Number: 001-67345 Rev. *F Page 49 of 52 CY8C21x34B Document History Page Document Title: CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity Document Number: 001-67345 Revision ECN Orig. of Change Submission Date Description of Change ** 3169205 YVA 02/16/2011 New data sheet. *A 3247292 YVA 05/11/2011 Updated Packaging Information. Post to Web. *B 3846480 SRLI 12/19/2012 Updated Features. Updated Packaging Information: spec 51-85062 – Changed Revision from *D to *F. spec 001-48913 – Changed Revision from *B to *C. spec 001-44368 – Changed Revision from *B to *C. spec 001-30999 – Changed Revision from *C to *D. spec 51-85068 – Changed Revision from *D to *E. Updated Ordering Information (Updated part numbers). *C 3894458 SRLI 02/09/2013 Updated Document Title to read as “CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity”. Updated Packaging Information (Updated Solder Reflow Peak Temperature (Changed Time at Maximum Temperature from 20 s to 30 s in Table 35)). *D 4297481 DCHE 03/04/2014 Updated Development Tools: Added hyperlink for “PSoC Designer™”. Updated PSoC Designer Software Subsystems: Updated In-Circuit Emulator: Added hyperlink for “in-circuit emulator” in description. Updated Development Tool Selection: Updated Software: Updated PSoC Designer: Updated hyperlinks in description. Updated PSoC Programmer: Updated hyperlinks in description. Updated Development Kits: Updated description. Updated Evaluation Tools: Updated CY3210-MiniProg1: Updated hyperlinks in description. Updated CY3214-PSoCEvalUSB: Updated hyperlinks in description. Updated Device Programmers: Updated CY3216 Modular Programmer: Updated hyperlinks in description. Updated Packaging Information: spec 001-44368 – Changed Revision from *C to *D. spec 001-48913 – Changed Revision from *C to *D. Updated in new template. Completing Sunset Review. Document Number: 001-67345 Rev. *F Page 50 of 52 CY8C21x34B Document History Page (continued) Document Title: CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity Document Number: 001-67345 Revision ECN Orig. of Change Submission Date Description of Change *E 4476297 DCHE / ASRI 08/28/2014 Replaced references of “Application Notes for Surface Mount Assembly of Amkor’s MicroLeadFrame (MLF) Packages” with “Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845” in all instances across the document. Added More Information. Added PSoC Designer. Removed “Getting Started”. Updated Electrical Specifications: Updated AC Electrical Characteristics: Updated AC Operational Amplifier Specifications: Updated Table 25: Replaced VCC with VDD. Updated Packaging Information: Removed spec 001-44368 *D. Updated Development Tool Selection: Updated Device Programmers: Removed “CY3207ISSP In-System Serial Programmer (ISSP)”. Updated Ordering Information (Updated part numbers). *F 4670626 DCHE Document Number: 001-67345 Rev. *F 02/25/2015 Added Errata and references to errata items on page 1. Page 51 of 52 CY8C21x34B Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/memory PSoC Touch Sensing psoc.cypress.com/solutions Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-67345 Rev. *F Revised February 25, 2015 ® ® Page 52 of 52 PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.