Keystone Advanced Debug Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family Debug Architecture Features • Advanced Event Triggering – Hardware Breakpoints/Watchpoints – Event Monitoring/Counting – Core Trace Control • DSP Core Trace – Export Program, Timing, Data, Event Info • System Trace – Export Bus Statistics and Events – Export Software Messages • Cross Triggering Trace Data Capture Mechanisms • DSP Core Trace – Debug Port EMU pins for export to an external receiver* – Dedicated TI Embedded Trace Buffer (TETB) • 4Kb on each core • System Trace – Debug Port EMU pins for export to an external receiver* – System Level TI Embedded Trace Buffer (TETB) • 16Kb per device * XDS560v2 Pro (In Beta) = 2GB Embedded Trace Buffer (TETB) • Can be optionally drained “on the fly” to L2, shared, or external memories • Can trigger event on ½ full status or full status • Advantages – Virtually extends the limited ETB size – Data can be streamed from the device via Ethernet or any other transport Debug Subsystem Debug Subsystem System Trace TETB System Trace C66x CorePac C66x CorePac C66x CorePac C66x CorePac DSP Core DSP Core AET Trace DSP Core AET Trace DSP Core AET Trace AET Trace TETB TETB TETB TETB Debug Port External Trace Receiver Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family Advanced Event Triggering (AET) • Logic that can monitor – Program Bus Activity – Data Memory Bus Activity – System Events • Non-Intrusive / Real Time • Programmable at load or run time Advanced Event Triggering Inputs • Input Logic – 6 Dual Range Address Comparators • 4 Program/Data Address w/ Value Qualify • 2 Program Address Only – 4 Auxiliary Event Generators – 4 State Sequencer – 2 Timers/Counters • With Min/Max Watermark Capabilities – …. Advanced Event Triggering Outputs (Triggers) • Output Logic (Triggers) – CPU Halt Request* – Interrupt – Counter Inc/Dec/Reset – Timer Start/Stop – Store Trace Sample (7 Streams) – Start Trace (7 Streams) – State Sequencer Transition – …. *Halt Request ignored when debugger not connected Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family DSP Core Trace • Core Trace (aka XDS560 Trace, CPU Trace) – Allows real-time, non intrusive, cycle accurate logging of PC (PC Trace) and Data (Data Trace) activity on the DSP Memory Buses. – Captured Trace data is compressed by on-chip hardware, passed either to the ETB or an external receiver, and then decoded on the host (with CCS or a stand alone decoder) • Event Trace – Event Trace is similar to PC trace, but allows selection of a subset of events that are tagged within the Trace Output. Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family System Trace • Allows System Level monitoring of Application Events and Resources • Two Options – Software Messages – Hardware Messages – Common Platform Tracer (CPTracer) Software Messaging • Enabled By System Trace Library (STMLib) • Advantages over Standard Printf – Real-time – System Level Cycle aligned • Up to 240 User Defined Channels • Reduced capability library build (compact) also provided (< 1K ) STMLib is a component of the CToolsLib Family of libraries Download free via Gforge: https://gforge.ti.com/gf/project/ctoolslib/frs/ Common Platform Tracer (CPTracer) • CPT Modules - Provide data for slave buses. – Profiling: Periodically export STM Messages for statistics counters • Throughput Counter 0,1 – Bytes of slave acknowledged accesses • Wait Counter – Number of cycles a master access must wait for slave acknowledge • Access Counter – Number of unique transactions – Event Logging • New Request • Last Read • Last Write KeyStone CP Tracer Modules Legend Bridge S Wireless Apps Only Media Apps Only VUSR TPCC 16ch QDMA S M3_DDR CPU/2 256b TeraNet SCR CP Tracer M VUSR CPT TC0 M TC1 M EDMA_0 M MSMC_SS S M3_SL2 S for EMIF_DDR3 (36b) CPT CPT CPT CPT 4 CPTs for SRAM (36b) CONFIG XMC X 4/ x 8 DDR3 M x5 x8 S S CP Tracer (x5) S CP Tracer (x8) x7 x4 for Wireless x8 for Media SRIO M M PA/SA M TC2 M TPCC M TC6 TPCC TC3 64ch TC4 M 64ch TC5TC7 QDMA M TC8 QDMA TC9 EDMA_1,2 S RAC_BE0,1 M FFTC / DMA M AIF / DMA M QMSS M PCIe M M M M Bridge 14 CPU/3 128b TeraNet SCR CPT S TCP3e_W/R CPT S CPU / 3 128b SCR MPU TCP3d CPU/3 32b TeraNet SCR CPT S x2 x2 SCR CPU / 3 x4 SCR CPU / 3 x4 S S S S S S TPCC TPTC TPCC TPTC S TSIP S AIF2 S VCP2 S TCP3D S TCP3E S FFTC TPCC TPTC S MPU CPT S Semaphore MPU CPT S QMSS PA/SA DebugSS S SEC_CTL QMSS S PLL_CTL PCIe S Bootcfg S Timer S GPIO S I2C S STM TETB CPU/3 CPU / 6 32b CP Tracer (x5) M 32b TeraNet SBoot ROM CP Tracer (x8) M Write-only TeraNet SCR SCR CP Tracer (x7) M Preliminary Information S SPI under NDA - subject to change SEMIF16 DebugSS STM S STETB CPU/6 32b TeraNet SCR X8 / x16 S INTC S UART … CPU / 3 32b TeraNet SCR CPU/3 32b TeraNet SCR SCR CPU /2 x4 S CP Tracer (x7) S S VCP2 (x4) S M M x2 MPU CPT x2 DAP (DebugSS) M TSIP0,1 SRIO Bridge 13 Monitors transactions from AIF, TCs M S TETB Bridge 12 Monitors transactions from AIF,SRIO, Core, TCs TAC_FE S CorePac M SRIO Global Timestamp Configuration • CCS Breakpoint Manager • CPTracer Library (CPTLib) – Use Case based APIs – Enable/Disable functions allow isolation of Trace Data generation CPTLibis a component of the CToolsLib Family of libraries Download free via Gforge: https://gforge.ti.com/gf/project/ctoolslib/frs/ CPTracer Sample Ouput http://processors.wiki.ti.com/index.php/CorePac_1_L2_CPT_-_CCS_setup_XDS560v2_System_Trace_Example Cross Triggering • Provides a means to propagate debug events from one processor to another. • Other processors can generate actions upon cross trigger • Sample Debug Events – Processor Entering Debug State – Watch Point Match – ETB Full • Sample Debug Actions – Restart – Interrupt Request – Start Trace Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family Application Embedded Debug Support • CToolsLib – A suite of libraries that can be used for embedding debug elements into an application – AETLib – ETBLib – CPTLib – DSPTraceLib – STMLib Available Free Via GForge: https://gforge.ti.com/gf/project/ctoolslib/frs/ AETLib • Provides programmatic access to the Advanced Event Triggering logic • Advantages – Reuse of limited AET resources (task stack monitoring) – More granularity for enabling/disabling AET/Trace at specific points of the application – Capture of Trace data from fielded devices ETBLib • Provides application access to configuration of the embedded trace buffer • Advantages – ETB can be configured without Debugger connection – Dynamic draining of ETB is supported • Events generated on half full and full • Data can be moved from ETB into internal memory and passed off via any transport (Ethernet, Srio, etc) • Virtually extend the size of the ETB System Trace Libraries • STMLib – Application Interface to System Trace Software Messages – Advantages • Small function overhead • Real-Time • System Level Time Stamp • CPTLib – Application Interface to Common Platform Tracer Configuration Agenda • • • • • • Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore System Analyzer (MCSA) Indicates features that are new on the Keystone generation of the C6000 Family Multicore System Analyzer(MCSA) • Suite of tools providing real-time visibility into performance and behavior of an application. – Information collected in various ways • Advanced Tooling Features: – Real-time event monitoring – Multicore event correlation – Correlation of software events, hardware events and CPU trace – Real-time profiling and benchmarking – Real-time debugging http://processors.wiki.ti.com/index.php/Multicore_System_Analyzer Analysis Features • Benchmarking: Finding out how long it takes some action to complete. Includes 'context aware' benchmarking for multi-threaded analysis • CPU and Task Load Monitoring: real-time visibility into how busy your system really is • O/S Execution Monitoring: monitoring task switches and the state of kernel objects such as semaphores • Filtering events • Multicore Event Correlation Current/Future Features Current • • • • • • • • • Ethernet Transport JTAG Stop-Mode JTAG Run-Mode Execution Graph CPU Load Task Load Benchmark/Duration Context Aware Profile Statistics / Count Analysis MCSA User’s Guide Future • ETB Draining • CPU Trace, STM, UIA Correlation • Logging on Linux • Realtime Config & Software Instrumentation Control • USB Transport • STM Transport • Remote Debug • Back Trace System Analyzer 1.0 System Analyzer 1.1